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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_mbist_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_mbist_ctl ( | |
36 | mcu_mbist_run, | |
37 | mcu_mbist_addr, | |
38 | mcu_mbist_sel_bank0or1, | |
39 | mcu_mbist_sel_hiorlo_72bits, | |
40 | mcu_mbist_wdata, | |
41 | mcu_mbist_wdqrf00_wr_en, | |
42 | mcu_mbist_wdqrf00_rd_en, | |
43 | mcu_mbist_wdqrf01_wr_en, | |
44 | mcu_mbist_wdqrf01_rd_en, | |
45 | mcu_mbist_wdqrf10_wr_en, | |
46 | mcu_mbist_wdqrf10_rd_en, | |
47 | mcu_mbist_wdqrf11_wr_en, | |
48 | mcu_mbist_wdqrf11_rd_en, | |
49 | scan_out, | |
50 | mcu_mbist_done, | |
51 | mcu_mbist_fail, | |
52 | l2clk, | |
53 | scan_in, | |
54 | tcu_pce_ov, | |
55 | tcu_aclk, | |
56 | tcu_bclk, | |
57 | tcu_scan_en, | |
58 | mcu_mbist_start, | |
59 | mcu_mbist_bisi_mode, | |
60 | mcu_mbist_user_mode, | |
61 | read_data); | |
62 | wire pce_ov; | |
63 | wire siclk; | |
64 | wire soclk; | |
65 | wire se; | |
66 | wire l1clk; | |
67 | wire config_reg_scanin; | |
68 | wire config_reg_scanout; | |
69 | wire [7:0] config_in; | |
70 | wire [7:0] config_out; | |
71 | wire start_transition; | |
72 | wire reset_engine; | |
73 | wire mbist_user_loop_mode; | |
74 | wire mbist_done; | |
75 | wire run; | |
76 | wire bisi; | |
77 | wire user_mode; | |
78 | wire user_data_mode; | |
79 | wire user_addr_mode; | |
80 | wire user_loop_mode; | |
81 | wire ten_n_mode; | |
82 | wire mbist_user_data_mode; | |
83 | wire mbist_user_addr_mode; | |
84 | wire mbist_ten_n_mode; | |
85 | wire user_data_reg_scanin; | |
86 | wire user_data_reg_scanout; | |
87 | wire [7:0] user_data_in; | |
88 | wire [7:0] user_data_out; | |
89 | wire user_start_addr_reg_scanin; | |
90 | wire user_start_addr_reg_scanout; | |
91 | wire [4:0] user_start_addr_in; | |
92 | wire [4:0] user_start_addr; | |
93 | wire user_stop_addr_reg_scanin; | |
94 | wire user_stop_addr_reg_scanout; | |
95 | wire [4:0] user_stop_addr_in; | |
96 | wire [4:0] user_stop_addr; | |
97 | wire user_incr_addr_reg_scanin; | |
98 | wire user_incr_addr_reg_scanout; | |
99 | wire [4:0] user_incr_addr_in; | |
100 | wire [4:0] user_incr_addr; | |
101 | wire user_array_sel_reg_scanin; | |
102 | wire user_array_sel_reg_scanout; | |
103 | wire [1:0] user_array_sel_in; | |
104 | wire [1:0] user_array_sel; | |
105 | wire user_bisi_wr_reg_scanin; | |
106 | wire user_bisi_wr_reg_scanout; | |
107 | wire user_bisi_wr_mode_in; | |
108 | wire user_bisi_wr_mode; | |
109 | wire user_bisi_rd_reg_scanin; | |
110 | wire user_bisi_rd_reg_scanout; | |
111 | wire user_bisi_rd_mode_in; | |
112 | wire user_bisi_rd_mode; | |
113 | wire mbist_user_bisi_wr_mode; | |
114 | wire mbist_user_bisi_wr_rd_mode; | |
115 | wire start_transition_reg_scanin; | |
116 | wire start_transition_reg_scanout; | |
117 | wire start_transition_piped; | |
118 | wire run_reg_scanin; | |
119 | wire run_reg_scanout; | |
120 | wire counter_reg_scanin; | |
121 | wire counter_reg_scanout; | |
122 | wire [3:0] counter_in; | |
123 | wire [3:0] counter_out; | |
124 | wire cycle16; | |
125 | wire run_piped16; | |
126 | wire msb; | |
127 | wire addr_reg_scanin; | |
128 | wire addr_reg_scanout; | |
129 | wire [4:0] mbist_address; | |
130 | wire wdata_reg_scanin; | |
131 | wire wdata_reg_scanout; | |
132 | wire [7:0] mbist_wdata; | |
133 | wire wdqrf00_wr_rd_reg_scanin; | |
134 | wire wdqrf00_wr_rd_reg_scanout; | |
135 | wire mbist_wdqrf00_wr_en; | |
136 | wire mbist_wdqrf00_rd_en; | |
137 | wire wdqrf01_wr_rd_reg_scanin; | |
138 | wire wdqrf01_wr_rd_reg_scanout; | |
139 | wire mbist_wdqrf01_wr_en; | |
140 | wire mbist_wdqrf01_rd_en; | |
141 | wire wdqrf10_wr_rd_reg_scanin; | |
142 | wire wdqrf10_wr_rd_reg_scanout; | |
143 | wire mbist_wdqrf10_wr_en; | |
144 | wire mbist_wdqrf10_rd_en; | |
145 | wire wdqrf11_wr_rd_reg_scanin; | |
146 | wire wdqrf11_wr_rd_reg_scanout; | |
147 | wire mbist_wdqrf11_wr_en; | |
148 | wire mbist_wdqrf11_rd_en; | |
149 | wire done_reg_scanin; | |
150 | wire done_reg_scanout; | |
151 | wire mbist_fail_reg_scanin; | |
152 | wire mbist_fail_reg_scanout; | |
153 | wire fail; | |
154 | wire read_data_reg_scanin; | |
155 | wire read_data_reg_scanout; | |
156 | wire [71:0] read_data_pipe; | |
157 | wire control_reg_scanin; | |
158 | wire control_reg_scanout; | |
159 | wire [18:0] control_in; | |
160 | wire [18:0] control_out; | |
161 | wire bisi_wr_rd; | |
162 | wire [1:0] array_sel; | |
163 | wire [1:0] data_control; | |
164 | wire address_mix; | |
165 | wire [3:0] march_element; | |
166 | wire [4:0] array_address; | |
167 | wire upaddress_march; | |
168 | wire [2:0] read_write_control; | |
169 | wire five_cycle_march; | |
170 | wire one_cycle_march; | |
171 | wire increment_addr; | |
172 | wire [4:0] start_addr; | |
173 | wire [4:0] next_array_address; | |
174 | wire next_upaddr_march; | |
175 | wire next_downaddr_march; | |
176 | wire [4:0] stop_addr; | |
177 | wire [5:0] overflow_addr; | |
178 | wire [4:0] incr_addr; | |
179 | wire overflow; | |
180 | wire [5:0] compare_addr; | |
181 | wire [4:0] add; | |
182 | wire [4:0] adj_address; | |
183 | wire increment_march_elem; | |
184 | wire [1:0] next_array_sel; | |
185 | wire [1:0] next_data_control; | |
186 | wire next_address_mix; | |
187 | wire [3:0] next_march_element; | |
188 | wire array_write; | |
189 | wire array_read; | |
190 | wire true_data; | |
191 | wire [7:0] data_pattern; | |
192 | wire done_counter_reg_scanin; | |
193 | wire done_counter_reg_scanout; | |
194 | wire [2:0] done_counter_in; | |
195 | wire [2:0] done_counter_out; | |
196 | wire wdqrf00_sel; | |
197 | wire wdqrf01_sel; | |
198 | wire wdqrf10_sel; | |
199 | wire wdqrf11_sel; | |
200 | wire sel_bank0or1; | |
201 | wire sel_hiorlo_72bits; | |
202 | wire data_pipe_reg1_scanin; | |
203 | wire data_pipe_reg1_scanout; | |
204 | wire [7:0] data_pipe_reg1_in; | |
205 | wire [7:0] data_pipe_out1; | |
206 | wire data_pipe_reg2_scanin; | |
207 | wire data_pipe_reg2_scanout; | |
208 | wire [7:0] data_pipe_reg2_in; | |
209 | wire [7:0] data_pipe_out2; | |
210 | wire data_pipe_reg3_scanin; | |
211 | wire data_pipe_reg3_scanout; | |
212 | wire [7:0] data_pipe_reg3_in; | |
213 | wire [7:0] data_pipe_out3; | |
214 | wire data_pipe_reg4_scanin; | |
215 | wire data_pipe_reg4_scanout; | |
216 | wire [7:0] data_pipe_reg4_in; | |
217 | wire [7:0] data_pipe_out4; | |
218 | wire [7:0] mbist_piped_wdata; | |
219 | wire ren_pipe_reg1_scanin; | |
220 | wire ren_pipe_reg1_scanout; | |
221 | wire ren_pipe_reg1_in; | |
222 | wire ren_pipe_out1; | |
223 | wire ren_pipe_reg2_scanin; | |
224 | wire ren_pipe_reg2_scanout; | |
225 | wire ren_pipe_reg2_in; | |
226 | wire ren_pipe_out2; | |
227 | wire ren_pipe_reg3_scanin; | |
228 | wire ren_pipe_reg3_scanout; | |
229 | wire ren_pipe_reg3_in; | |
230 | wire ren_pipe_out3; | |
231 | wire ren_pipe_reg4_scanin; | |
232 | wire ren_pipe_reg4_scanout; | |
233 | wire ren_pipe_reg4_in; | |
234 | wire ren_pipe_out4; | |
235 | wire ren_pipe_reg5_scanin; | |
236 | wire ren_pipe_reg5_scanout; | |
237 | wire ren_pipe_reg5_in; | |
238 | wire ren_pipe_out5; | |
239 | wire mbist_piped_ren; | |
240 | wire sel_pipe_reg1_scanin; | |
241 | wire sel_pipe_reg1_scanout; | |
242 | wire [1:0] sel_pipe_reg1_in; | |
243 | wire [1:0] sel_pipe_out1; | |
244 | wire sel_pipe_reg2_scanin; | |
245 | wire sel_pipe_reg2_scanout; | |
246 | wire [1:0] sel_pipe_reg2_in; | |
247 | wire [1:0] sel_pipe_out2; | |
248 | wire sel_pipe_reg3_scanin; | |
249 | wire sel_pipe_reg3_scanout; | |
250 | wire [1:0] sel_pipe_reg3_in; | |
251 | wire [1:0] sel_pipe_out3; | |
252 | wire sel_pipe_reg4_scanin; | |
253 | wire sel_pipe_reg4_scanout; | |
254 | wire [1:0] sel_pipe_reg4_in; | |
255 | wire [1:0] sel_pipe_out4; | |
256 | wire sel_pipe_reg5_scanin; | |
257 | wire sel_pipe_reg5_scanout; | |
258 | wire [1:0] sel_pipe_reg5_in; | |
259 | wire [1:0] sel_pipe_out5; | |
260 | wire piped_sel_hiorlo_72bits; | |
261 | wire piped_sel_bank0or1; | |
262 | wire wdqrf00_sel_piped; | |
263 | wire wdqrf01_sel_piped; | |
264 | wire wdqrf10_sel_piped; | |
265 | wire wdqrf11_sel_piped; | |
266 | wire fail_reg_scanin; | |
267 | wire fail_reg_scanout; | |
268 | wire [3:0] fail_reg_in; | |
269 | wire [3:0] fail_reg_out; | |
270 | wire qual_sio_wdqrf11_fail; | |
271 | wire qual_sio_wdqrf10_fail; | |
272 | wire qual_sio_wdqrf01_fail; | |
273 | wire qual_sio_wdqrf00_fail; | |
274 | wire fail_detect; | |
275 | wire spares_scanin; | |
276 | wire spares_scanout; | |
277 | ||
278 | ||
279 | ||
280 | // ///////////////////////////////////////////////////////////////////////////// | |
281 | // Outputs | |
282 | // ///////////////////////////////////////////////////////////////////////////// | |
283 | ||
284 | output mcu_mbist_run; | |
285 | ||
286 | output [4:0] mcu_mbist_addr; | |
287 | ||
288 | //Select the 144 bits from wdqrf00 and 01 (when 0) OR wdqrf10 and 11 (when 1) | |
289 | output mcu_mbist_sel_bank0or1; | |
290 | ||
291 | //Select the 72 bits from wdqrf00 over 01 OR wdqrf10 over 11 (when 0) | |
292 | //Assumed wdqrf00 and wdqrf10 provide the lower 72 bits! | |
293 | output mcu_mbist_sel_hiorlo_72bits; | |
294 | ||
295 | output [7:0] mcu_mbist_wdata; | |
296 | ||
297 | output mcu_mbist_wdqrf00_wr_en; | |
298 | output mcu_mbist_wdqrf00_rd_en; | |
299 | ||
300 | output mcu_mbist_wdqrf01_wr_en; | |
301 | output mcu_mbist_wdqrf01_rd_en; | |
302 | ||
303 | output mcu_mbist_wdqrf10_wr_en; | |
304 | output mcu_mbist_wdqrf10_rd_en; | |
305 | ||
306 | output mcu_mbist_wdqrf11_wr_en; | |
307 | output mcu_mbist_wdqrf11_rd_en; | |
308 | ||
309 | output scan_out; | |
310 | ||
311 | ||
312 | output mcu_mbist_done; | |
313 | output mcu_mbist_fail; | |
314 | ||
315 | ||
316 | // ///////////////////////////////////////////////////////////////////////////// | |
317 | // Inputs | |
318 | // ///////////////////////////////////////////////////////////////////////////// | |
319 | ||
320 | input l2clk; | |
321 | input scan_in; | |
322 | input tcu_pce_ov; // scan signals | |
323 | input tcu_aclk; | |
324 | input tcu_bclk; | |
325 | input tcu_scan_en; | |
326 | ||
327 | ||
328 | input mcu_mbist_start; | |
329 | input mcu_mbist_bisi_mode; | |
330 | input mcu_mbist_user_mode; | |
331 | ||
332 | input [71:0] read_data; | |
333 | ||
334 | ||
335 | ||
336 | // ///////////////////////////////////////////////////////////////////////////// | |
337 | // Scan Renames | |
338 | // ///////////////////////////////////////////////////////////////////////////// | |
339 | ||
340 | assign pce_ov = tcu_pce_ov; | |
341 | assign siclk = tcu_aclk; | |
342 | assign soclk = tcu_bclk; | |
343 | assign se = tcu_scan_en; | |
344 | ||
345 | ||
346 | ||
347 | //////////////////////////////////////////////////////////////////////////////// | |
348 | // Clock header | |
349 | ||
350 | mcu_mbist_ctl_l1clkhdr_ctl_macro clkgen ( | |
351 | .l2clk (l2clk ), | |
352 | .l1en (1'b1 ), | |
353 | .stop (1'b0 ), | |
354 | .l1clk (l1clk ), | |
355 | .pce_ov(pce_ov), | |
356 | .se(se) | |
357 | ); | |
358 | ||
359 | ||
360 | ||
361 | // ///////////////////////////////////////////////////////////////////////////// | |
362 | // | |
363 | // MBIST Config Register | |
364 | // | |
365 | // ///////////////////////////////////////////////////////////////////////////// | |
366 | // | |
367 | // A low to high transition on mbist_start will reset and start the engine. | |
368 | // mbist_start must remain active high for the duration of MBIST. | |
369 | // If mbist_start deasserts the engine will stop but not reset. | |
370 | // Once MBIST has completed mbist_done will assert and the fail status | |
371 | // signals will be valid. | |
372 | // To run MBIST again the mbist_start signal must transition low then high. | |
373 | // | |
374 | // Loop on Address will disable the address mix function. | |
375 | // | |
376 | // ///////////////////////////////////////////////////////////////////////////// | |
377 | ||
378 | ||
379 | mcu_mbist_ctl_msff_ctl_macro__width_8 config_reg ( | |
380 | .scan_in(config_reg_scanin), | |
381 | .scan_out(config_reg_scanout), | |
382 | .din ( config_in[7:0] ), | |
383 | .dout ( config_out[7:0] ), | |
384 | .l1clk(l1clk), | |
385 | .siclk(siclk), | |
386 | .soclk(soclk)); | |
387 | ||
388 | ||
389 | ||
390 | assign config_in[0] = mcu_mbist_start; | |
391 | assign config_in[1] = config_out[0]; | |
392 | assign start_transition = config_out[0] & ~config_out[1]; | |
393 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
394 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); | |
395 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
396 | ||
397 | assign config_in[2] = start_transition ? mcu_mbist_bisi_mode: config_out[2]; | |
398 | assign bisi = config_out[2]; | |
399 | ||
400 | assign config_in[3] = start_transition ? mcu_mbist_user_mode: config_out[3]; | |
401 | assign user_mode = config_out[3]; | |
402 | ||
403 | assign config_in[4] = config_out[4]; | |
404 | assign user_data_mode = config_out[4]; | |
405 | ||
406 | assign config_in[5] = config_out[5]; | |
407 | assign user_addr_mode = config_out[5]; | |
408 | ||
409 | assign config_in[6] = config_out[6]; | |
410 | assign user_loop_mode = config_out[6]; | |
411 | ||
412 | assign config_in[7] = config_out[7]; | |
413 | assign ten_n_mode = config_out[7]; | |
414 | ||
415 | ||
416 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
417 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
418 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
419 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
420 | ||
421 | ||
422 | mcu_mbist_ctl_msff_ctl_macro__width_8 user_data_reg ( | |
423 | .scan_in(user_data_reg_scanin), | |
424 | .scan_out(user_data_reg_scanout), | |
425 | .din ( user_data_in[7:0] ), | |
426 | .dout ( user_data_out[7:0] ), | |
427 | .l1clk(l1clk), | |
428 | .siclk(siclk), | |
429 | .soclk(soclk)); | |
430 | ||
431 | ||
432 | assign user_data_in[7:0] = user_data_out[7:0]; | |
433 | ||
434 | ||
435 | // Defining User start, stop, and increment addresses. | |
436 | ||
437 | mcu_mbist_ctl_msff_ctl_macro__width_5 user_start_addr_reg ( | |
438 | .scan_in(user_start_addr_reg_scanin), | |
439 | .scan_out(user_start_addr_reg_scanout), | |
440 | .din ( user_start_addr_in[4:0] ), | |
441 | .dout ( user_start_addr[4:0] ), | |
442 | .l1clk(l1clk), | |
443 | .siclk(siclk), | |
444 | .soclk(soclk)); | |
445 | ||
446 | assign user_start_addr_in[4:0] = user_start_addr[4:0]; | |
447 | ||
448 | mcu_mbist_ctl_msff_ctl_macro__width_5 user_stop_addr_reg ( | |
449 | .scan_in(user_stop_addr_reg_scanin), | |
450 | .scan_out(user_stop_addr_reg_scanout), | |
451 | .din ( user_stop_addr_in[4:0] ), | |
452 | .dout ( user_stop_addr[4:0] ), | |
453 | .l1clk(l1clk), | |
454 | .siclk(siclk), | |
455 | .soclk(soclk)); | |
456 | ||
457 | assign user_stop_addr_in[4:0] = user_stop_addr[4:0]; | |
458 | ||
459 | ||
460 | mcu_mbist_ctl_msff_ctl_macro__width_5 user_incr_addr_reg ( | |
461 | .scan_in(user_incr_addr_reg_scanin), | |
462 | .scan_out(user_incr_addr_reg_scanout), | |
463 | .din ( user_incr_addr_in[4:0] ), | |
464 | .dout ( user_incr_addr[4:0] ), | |
465 | .l1clk(l1clk), | |
466 | .siclk(siclk), | |
467 | .soclk(soclk)); | |
468 | ||
469 | assign user_incr_addr_in[4:0] = user_incr_addr[4:0]; | |
470 | ||
471 | // Defining User array_sel. | |
472 | ||
473 | mcu_mbist_ctl_msff_ctl_macro__width_2 user_array_sel_reg ( | |
474 | .scan_in(user_array_sel_reg_scanin), | |
475 | .scan_out(user_array_sel_reg_scanout), | |
476 | .din ( user_array_sel_in[1:0] ), | |
477 | .dout ( user_array_sel[1:0] ), | |
478 | .l1clk(l1clk), | |
479 | .siclk(siclk), | |
480 | .soclk(soclk)); | |
481 | ||
482 | assign user_array_sel_in[1:0] = user_array_sel[1:0]; | |
483 | ||
484 | // Defining user_bisi write and read registers | |
485 | ||
486 | mcu_mbist_ctl_msff_ctl_macro__width_1 user_bisi_wr_reg ( | |
487 | .scan_in(user_bisi_wr_reg_scanin), | |
488 | .scan_out(user_bisi_wr_reg_scanout), | |
489 | .din ( user_bisi_wr_mode_in ), | |
490 | .dout ( user_bisi_wr_mode ), | |
491 | .l1clk(l1clk), | |
492 | .siclk(siclk), | |
493 | .soclk(soclk)); | |
494 | ||
495 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
496 | ||
497 | mcu_mbist_ctl_msff_ctl_macro__width_1 user_bisi_rd_reg ( | |
498 | .scan_in(user_bisi_rd_reg_scanin), | |
499 | .scan_out(user_bisi_rd_reg_scanout), | |
500 | .din ( user_bisi_rd_mode_in ), | |
501 | .dout ( user_bisi_rd_mode ), | |
502 | .l1clk(l1clk), | |
503 | .siclk(siclk), | |
504 | .soclk(soclk)); | |
505 | ||
506 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
507 | ||
508 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
509 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
510 | ||
511 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
512 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
513 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
514 | ||
515 | //////////////////////////////////////////////////////////////////////////////// | |
516 | // Piping start_transition | |
517 | //////////////////////////////////////////////////////////////////////////////// | |
518 | ||
519 | mcu_mbist_ctl_msff_ctl_macro__width_1 start_transition_reg ( | |
520 | .scan_in(start_transition_reg_scanin), | |
521 | .scan_out(start_transition_reg_scanout), | |
522 | .din ( start_transition ), | |
523 | .dout ( start_transition_piped ), | |
524 | .l1clk(l1clk), | |
525 | .siclk(siclk), | |
526 | .soclk(soclk)); | |
527 | ||
528 | ||
529 | //////////////////////////////////////////////////////////////////////////////// | |
530 | // Staging run for 16 cycles for mbist engines supporting async FIFO's | |
531 | //////////////////////////////////////////////////////////////////////////////// | |
532 | ||
533 | mcu_mbist_ctl_msff_ctl_macro__width_1 run_reg ( | |
534 | .scan_in(run_reg_scanin), | |
535 | .scan_out(run_reg_scanout), | |
536 | .din ( run ), | |
537 | .dout ( mcu_mbist_run ), | |
538 | .l1clk(l1clk), | |
539 | .siclk(siclk), | |
540 | .soclk(soclk) ); | |
541 | ||
542 | mcu_mbist_ctl_msff_ctl_macro__width_4 counter_reg ( | |
543 | .scan_in(counter_reg_scanin), | |
544 | .scan_out(counter_reg_scanout), | |
545 | .din ( counter_in[3:0] ), | |
546 | .dout ( counter_out[3:0] ), | |
547 | .l1clk(l1clk), | |
548 | .siclk(siclk), | |
549 | .soclk(soclk)); | |
550 | ||
551 | assign cycle16 = (&counter_out[3:0] == 1'b1); | |
552 | assign counter_in[3:0] = reset_engine ? 4'b0: | |
553 | run & ~cycle16 ? counter_out[3:0] + 4'b0001: | |
554 | counter_out[3:0]; | |
555 | ||
556 | assign run_piped16 = config_out[0] & cycle16 & ~msb; // As soon as run goes low, mbist operation is done! | |
557 | ||
558 | //////////////////////////////////////////////////////////////////////////////// | |
559 | // | |
560 | // Creating the flop boundary around the mbist controller | |
561 | // | |
562 | //////////////////////////////////////////////////////////////////////////////// | |
563 | ||
564 | mcu_mbist_ctl_msff_ctl_macro__width_5 addr_reg ( | |
565 | .scan_in(addr_reg_scanin), | |
566 | .scan_out(addr_reg_scanout), | |
567 | .din ( mbist_address[4:0] ), | |
568 | .dout ( mcu_mbist_addr[4:0] ), | |
569 | .l1clk(l1clk), | |
570 | .siclk(siclk), | |
571 | .soclk(soclk)); | |
572 | ||
573 | mcu_mbist_ctl_msff_ctl_macro__width_8 wdata_reg ( | |
574 | .scan_in(wdata_reg_scanin), | |
575 | .scan_out(wdata_reg_scanout), | |
576 | .din ( mbist_wdata[7:0] ), | |
577 | .dout ( mcu_mbist_wdata[7:0] ), | |
578 | .l1clk(l1clk), | |
579 | .siclk(siclk), | |
580 | .soclk(soclk)); | |
581 | ||
582 | mcu_mbist_ctl_msff_ctl_macro__width_2 wdqrf00_wr_rd_reg ( | |
583 | .scan_in(wdqrf00_wr_rd_reg_scanin), | |
584 | .scan_out(wdqrf00_wr_rd_reg_scanout), | |
585 | .din ( {mbist_wdqrf00_wr_en, mbist_wdqrf00_rd_en} ), | |
586 | .dout ( {mcu_mbist_wdqrf00_wr_en, mcu_mbist_wdqrf00_rd_en} ), | |
587 | .l1clk(l1clk), | |
588 | .siclk(siclk), | |
589 | .soclk(soclk)); | |
590 | ||
591 | mcu_mbist_ctl_msff_ctl_macro__width_2 wdqrf01_wr_rd_reg ( | |
592 | .scan_in(wdqrf01_wr_rd_reg_scanin), | |
593 | .scan_out(wdqrf01_wr_rd_reg_scanout), | |
594 | .din ( {mbist_wdqrf01_wr_en, mbist_wdqrf01_rd_en} ), | |
595 | .dout ( {mcu_mbist_wdqrf01_wr_en, mcu_mbist_wdqrf01_rd_en} ), | |
596 | .l1clk(l1clk), | |
597 | .siclk(siclk), | |
598 | .soclk(soclk)); | |
599 | ||
600 | mcu_mbist_ctl_msff_ctl_macro__width_2 wdqrf10_wr_rd_reg ( | |
601 | .scan_in(wdqrf10_wr_rd_reg_scanin), | |
602 | .scan_out(wdqrf10_wr_rd_reg_scanout), | |
603 | .din ( {mbist_wdqrf10_wr_en, mbist_wdqrf10_rd_en} ), | |
604 | .dout ( {mcu_mbist_wdqrf10_wr_en, mcu_mbist_wdqrf10_rd_en} ), | |
605 | .l1clk(l1clk), | |
606 | .siclk(siclk), | |
607 | .soclk(soclk)); | |
608 | ||
609 | mcu_mbist_ctl_msff_ctl_macro__width_2 wdqrf11_wr_rd_reg ( | |
610 | .scan_in(wdqrf11_wr_rd_reg_scanin), | |
611 | .scan_out(wdqrf11_wr_rd_reg_scanout), | |
612 | .din ( {mbist_wdqrf11_wr_en, mbist_wdqrf11_rd_en} ), | |
613 | .dout ( {mcu_mbist_wdqrf11_wr_en, mcu_mbist_wdqrf11_rd_en} ), | |
614 | .l1clk(l1clk), | |
615 | .siclk(siclk), | |
616 | .soclk(soclk)); | |
617 | ||
618 | mcu_mbist_ctl_msff_ctl_macro__width_1 done_reg ( | |
619 | .scan_in(done_reg_scanin), | |
620 | .scan_out(done_reg_scanout), | |
621 | .din ( mbist_done ), | |
622 | .dout ( mcu_mbist_done ), | |
623 | .l1clk(l1clk), | |
624 | .siclk(siclk), | |
625 | .soclk(soclk) ); | |
626 | ||
627 | ||
628 | mcu_mbist_ctl_msff_ctl_macro__width_1 mbist_fail_reg ( | |
629 | .scan_in(mbist_fail_reg_scanin), | |
630 | .scan_out(mbist_fail_reg_scanout), | |
631 | .din ( fail ), | |
632 | .dout ( mcu_mbist_fail ), | |
633 | .l1clk(l1clk), | |
634 | .siclk(siclk), | |
635 | .soclk(soclk) ); | |
636 | ||
637 | // | |
638 | mcu_mbist_ctl_msff_ctl_macro__width_72 read_data_reg ( | |
639 | .scan_in(read_data_reg_scanin), | |
640 | .scan_out(read_data_reg_scanout), | |
641 | .din ( read_data[71:0] ), | |
642 | .dout ( read_data_pipe[71:0] ), | |
643 | .l1clk(l1clk), | |
644 | .siclk(siclk), | |
645 | .soclk(soclk)); | |
646 | ||
647 | ||
648 | // ///////////////////////////////////////////////////////////////////////////// | |
649 | // | |
650 | // MBIST Control Register | |
651 | // | |
652 | // ///////////////////////////////////////////////////////////////////////////// | |
653 | // Remove Address mix disable before delivery | |
654 | // ///////////////////////////////////////////////////////////////////////////// | |
655 | ||
656 | mcu_mbist_ctl_msff_ctl_macro__width_19 control_reg ( | |
657 | .scan_in(control_reg_scanin), | |
658 | .scan_out(control_reg_scanout), | |
659 | .din ( control_in[18:0] ), | |
660 | .dout ( control_out[18:0] ), | |
661 | .l1clk(l1clk), | |
662 | .siclk(siclk), | |
663 | .soclk(soclk)); | |
664 | ||
665 | assign msb = control_out[18]; | |
666 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[17] : 1'b1; | |
667 | assign array_sel[1:0] = user_mode ? user_array_sel[1:0] : control_out[16:15]; | |
668 | assign data_control[1:0] = control_out[14:13]; | |
669 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[12]; | |
670 | assign march_element[3:0] = control_out[11:8]; | |
671 | assign array_address[4:0] = upaddress_march ? control_out[7:3] : ~control_out[7:3]; | |
672 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
673 | control_out[2:0]; | |
674 | ||
675 | ||
676 | assign control_in[2:0] = reset_engine ? 3'b0: | |
677 | ~run_piped16 ? control_out[2:0]: | |
678 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
679 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: | |
680 | control_out[2:0] + 3'b001; | |
681 | ||
682 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
683 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || | |
684 | (read_write_control[2:0] == 3'b111); | |
685 | ||
686 | // start_transition_piped was added to have the correct start_addr at the start | |
687 | // of mbist during user_addr_mode | |
688 | assign control_in[7:3] = start_transition_piped || reset_engine ? start_addr[4:0]: | |
689 | ~run_piped16 || ~increment_addr ? control_out[7:3]: | |
690 | next_array_address[4:0]; | |
691 | ||
692 | assign next_array_address[4:0] = next_upaddr_march ? start_addr[4:0]: | |
693 | next_downaddr_march ? ~stop_addr[4:0]: | |
694 | (overflow_addr[4:0]); // array_addr + incr_addr | |
695 | ||
696 | assign start_addr[4:0] = mbist_user_addr_mode ? user_start_addr[4:0] : 5'b00000; | |
697 | assign stop_addr[4:0] = mbist_user_addr_mode ? user_stop_addr[4:0] : 5'b11111; | |
698 | assign incr_addr[4:0] = mbist_user_addr_mode ? user_incr_addr[4:0] : 5'b00001; | |
699 | ||
700 | assign overflow_addr[5:0] = {1'b0,control_out[7:3]} + {1'b0,incr_addr[4:0]}; | |
701 | assign overflow = compare_addr[5:0] < overflow_addr[5:0]; | |
702 | ||
703 | assign compare_addr[5:0] = upaddress_march ? {1'b0, stop_addr[4:0]} : | |
704 | {1'b0, ~start_addr[4:0]}; | |
705 | ||
706 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
707 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
708 | (march_element[3:0] == 4'h8) ) && overflow; | |
709 | ||
710 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
711 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
712 | overflow; | |
713 | ||
714 | ||
715 | ||
716 | assign add[4:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
717 | (read_write_control[2:0] == 3'h3)) ? | |
718 | adj_address[4:0]: array_address[4:0]; | |
719 | ||
720 | assign adj_address[4:0] = { array_address[4:2], ~array_address[1], array_address[0] }; // In case it is 2 blks of 16 rows! | |
721 | ||
722 | assign mbist_address[4:0] = address_mix ? {add[0],add[4],add[3],add[2],add[1]}: | |
723 | add[4:0]; | |
724 | ||
725 | // Definition of the rest of the control register | |
726 | assign increment_march_elem = increment_addr && overflow; | |
727 | ||
728 | assign control_in[18:8] = reset_engine ? 11'b0: | |
729 | ~run_piped16 ? control_out[18:8]: | |
730 | {msb, bisi_wr_rd, next_array_sel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} | |
731 | + {10'b0, increment_march_elem}; | |
732 | ||
733 | assign next_array_sel[1:0] = user_mode ? 2'b11: control_out[16:15]; | |
734 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
735 | data_control[1:0]; | |
736 | ||
737 | assign next_address_mix = bisi | mbist_user_addr_mode ? 1'b1 : address_mix; | |
738 | ||
739 | // Modified next_march_element to remove a possible long path. | |
740 | // Incorporated ten_n_mode! | |
741 | assign next_march_element[3:0] = ( bisi || | |
742 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
743 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
744 | && overflow ? 4'b1111: march_element[3:0]; | |
745 | ||
746 | ||
747 | assign array_write = ~run_piped16 ? 1'b0: | |
748 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
749 | (read_write_control[2:0] == 3'h1) || | |
750 | (read_write_control[2:0] == 3'h4): | |
751 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: | |
752 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); | |
753 | ||
754 | assign array_read = ~array_write && run_piped16; // && ~initialize; | |
755 | // assign mbist_done = msb; | |
756 | ||
757 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
758 | ||
759 | ||
760 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
761 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
762 | (march_element[3:0] == 4'h7); | |
763 | ||
764 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
765 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
766 | (march_element[3:0] == 4'h7); | |
767 | ||
768 | // assign true_data = read_write_control[1] ^ ~march_element[0]; | |
769 | ||
770 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
771 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
772 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
773 | ((read_write_control[2:0] == 3'h1) || | |
774 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
775 | one_cycle_march ? (march_element[3:0] == 4'h7): | |
776 | ~(read_write_control[0] ^ march_element[0]); | |
777 | ||
778 | ||
779 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
780 | mbist_user_data_mode ? user_data_out[7:0]: | |
781 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
782 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
783 | (data_control[1:0] == 2'h1) ? 8'h99: | |
784 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
785 | 8'h00; | |
786 | ||
787 | ///////////////////////////////////////////////////////////////////////// | |
788 | // Creating the mbist_done signal | |
789 | ///////////////////////////////////////////////////////////////////////// | |
790 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
791 | // a generic solution for done going high after the last fail has come back! | |
792 | ||
793 | mcu_mbist_ctl_msff_ctl_macro__width_3 done_counter_reg ( | |
794 | .scan_in(done_counter_reg_scanin), | |
795 | .scan_out(done_counter_reg_scanout), | |
796 | .din ( done_counter_in[2:0] ), | |
797 | .dout ( done_counter_out[2:0] ), | |
798 | .l1clk(l1clk), | |
799 | .siclk(siclk), | |
800 | .soclk(soclk)); | |
801 | ||
802 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
803 | // goes low. | |
804 | ||
805 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
806 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
807 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
808 | done_counter_out[2:0]; | |
809 | ||
810 | ||
811 | // ///////////////////////////////////////////////////////////////////////////// | |
812 | // Memory Select Definitions | |
813 | // ///////////////////////////////////////////////////////////////////////////// | |
814 | ||
815 | assign wdqrf00_sel = ~array_sel[1] & ~array_sel[0]; | |
816 | assign wdqrf01_sel = ~array_sel[1] & array_sel[0]; | |
817 | ||
818 | assign wdqrf10_sel = array_sel[1] & ~array_sel[0]; | |
819 | assign wdqrf11_sel = array_sel[1] & array_sel[0]; | |
820 | ||
821 | assign sel_bank0or1 = array_sel[1]; // 1: wdqrf10 or 11 | |
822 | assign sel_hiorlo_72bits = array_sel[0]; // 1: wdqrf01 or 11 | |
823 | ||
824 | assign mbist_wdqrf00_rd_en = wdqrf00_sel && array_read; | |
825 | assign mbist_wdqrf00_wr_en = wdqrf00_sel && array_write; | |
826 | ||
827 | assign mbist_wdqrf01_rd_en = wdqrf01_sel && array_read; | |
828 | assign mbist_wdqrf01_wr_en = wdqrf01_sel && array_write; | |
829 | ||
830 | assign mbist_wdqrf10_rd_en = wdqrf10_sel && array_read; | |
831 | assign mbist_wdqrf10_wr_en = wdqrf10_sel && array_write; | |
832 | ||
833 | assign mbist_wdqrf11_rd_en = wdqrf11_sel && array_read; | |
834 | assign mbist_wdqrf11_wr_en = wdqrf11_sel && array_write; | |
835 | ||
836 | ||
837 | // ///////////////////////////////////////////////////////////////////////////// | |
838 | // Pipeline for wdata, read_en, and select lines | |
839 | // ///////////////////////////////////////////////////////////////////////////// | |
840 | ||
841 | // 3 stages to account for memory + flop after 1st output mux and flop on | |
842 | // read_data in mbist engine. | |
843 | // 5/27/05: Added one more stage to account for additional memory input muxing | |
844 | // in RTL. | |
845 | ||
846 | mcu_mbist_ctl_msff_ctl_macro__width_8 data_pipe_reg1 ( | |
847 | .scan_in(data_pipe_reg1_scanin), | |
848 | .scan_out(data_pipe_reg1_scanout), | |
849 | .din ( data_pipe_reg1_in[7:0] ), | |
850 | .dout ( data_pipe_out1[7:0] ), | |
851 | .l1clk(l1clk), | |
852 | .siclk(siclk), | |
853 | .soclk(soclk)); | |
854 | ||
855 | mcu_mbist_ctl_msff_ctl_macro__width_8 data_pipe_reg2 ( | |
856 | .scan_in(data_pipe_reg2_scanin), | |
857 | .scan_out(data_pipe_reg2_scanout), | |
858 | .din ( data_pipe_reg2_in[7:0] ), | |
859 | .dout ( data_pipe_out2[7:0] ), | |
860 | .l1clk(l1clk), | |
861 | .siclk(siclk), | |
862 | .soclk(soclk)); | |
863 | ||
864 | mcu_mbist_ctl_msff_ctl_macro__width_8 data_pipe_reg3 ( | |
865 | .scan_in(data_pipe_reg3_scanin), | |
866 | .scan_out(data_pipe_reg3_scanout), | |
867 | .din ( data_pipe_reg3_in[7:0] ), | |
868 | .dout ( data_pipe_out3[7:0] ), | |
869 | .l1clk(l1clk), | |
870 | .siclk(siclk), | |
871 | .soclk(soclk)); | |
872 | ||
873 | mcu_mbist_ctl_msff_ctl_macro__width_8 data_pipe_reg4 ( | |
874 | .scan_in(data_pipe_reg4_scanin), | |
875 | .scan_out(data_pipe_reg4_scanout), | |
876 | .din ( data_pipe_reg4_in[7:0] ), | |
877 | .dout ( data_pipe_out4[7:0] ), | |
878 | .l1clk(l1clk), | |
879 | .siclk(siclk), | |
880 | .soclk(soclk)); | |
881 | ||
882 | ||
883 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: mcu_mbist_wdata[7:0]; | |
884 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
885 | assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
886 | assign data_pipe_reg4_in[7:0] = reset_engine ? 8'h00: data_pipe_out3[7:0]; | |
887 | ||
888 | assign mbist_piped_wdata[7:0] = data_pipe_out4[7:0]; | |
889 | ||
890 | // 4 stages to account from array_read | |
891 | mcu_mbist_ctl_msff_ctl_macro__width_1 ren_pipe_reg1 ( | |
892 | .scan_in(ren_pipe_reg1_scanin), | |
893 | .scan_out(ren_pipe_reg1_scanout), | |
894 | .din ( ren_pipe_reg1_in ), | |
895 | .dout ( ren_pipe_out1 ), | |
896 | .l1clk(l1clk), | |
897 | .siclk(siclk), | |
898 | .soclk(soclk)); | |
899 | ||
900 | mcu_mbist_ctl_msff_ctl_macro__width_1 ren_pipe_reg2 ( | |
901 | .scan_in(ren_pipe_reg2_scanin), | |
902 | .scan_out(ren_pipe_reg2_scanout), | |
903 | .din ( ren_pipe_reg2_in ), | |
904 | .dout ( ren_pipe_out2 ), | |
905 | .l1clk(l1clk), | |
906 | .siclk(siclk), | |
907 | .soclk(soclk)); | |
908 | ||
909 | mcu_mbist_ctl_msff_ctl_macro__width_1 ren_pipe_reg3 ( | |
910 | .scan_in(ren_pipe_reg3_scanin), | |
911 | .scan_out(ren_pipe_reg3_scanout), | |
912 | .din ( ren_pipe_reg3_in ), | |
913 | .dout ( ren_pipe_out3 ), | |
914 | .l1clk(l1clk), | |
915 | .siclk(siclk), | |
916 | .soclk(soclk)); | |
917 | ||
918 | mcu_mbist_ctl_msff_ctl_macro__width_1 ren_pipe_reg4 ( | |
919 | .scan_in(ren_pipe_reg4_scanin), | |
920 | .scan_out(ren_pipe_reg4_scanout), | |
921 | .din ( ren_pipe_reg4_in ), | |
922 | .dout ( ren_pipe_out4 ), | |
923 | .l1clk(l1clk), | |
924 | .siclk(siclk), | |
925 | .soclk(soclk)); | |
926 | ||
927 | mcu_mbist_ctl_msff_ctl_macro__width_1 ren_pipe_reg5 ( | |
928 | .scan_in(ren_pipe_reg5_scanin), | |
929 | .scan_out(ren_pipe_reg5_scanout), | |
930 | .din ( ren_pipe_reg5_in ), | |
931 | .dout ( ren_pipe_out5 ), | |
932 | .l1clk(l1clk), | |
933 | .siclk(siclk), | |
934 | .soclk(soclk)); | |
935 | ||
936 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; | |
937 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; | |
938 | assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; | |
939 | assign ren_pipe_reg4_in = reset_engine ? 1'b0: ren_pipe_out3; | |
940 | assign ren_pipe_reg5_in = reset_engine ? 1'b0: ren_pipe_out4; | |
941 | assign mbist_piped_ren = ren_pipe_out5; | |
942 | ||
943 | // sel_hiorlo_72bits and sel_bank0or1 | |
944 | mcu_mbist_ctl_msff_ctl_macro__width_2 sel_pipe_reg1 ( | |
945 | .scan_in(sel_pipe_reg1_scanin), | |
946 | .scan_out(sel_pipe_reg1_scanout), | |
947 | .din ( sel_pipe_reg1_in[1:0] ), | |
948 | .dout ( sel_pipe_out1[1:0] ), | |
949 | .l1clk(l1clk), | |
950 | .siclk(siclk), | |
951 | .soclk(soclk)); | |
952 | ||
953 | mcu_mbist_ctl_msff_ctl_macro__width_2 sel_pipe_reg2 ( | |
954 | .scan_in(sel_pipe_reg2_scanin), | |
955 | .scan_out(sel_pipe_reg2_scanout), | |
956 | .din ( sel_pipe_reg2_in[1:0] ), | |
957 | .dout ( sel_pipe_out2[1:0] ), | |
958 | .l1clk(l1clk), | |
959 | .siclk(siclk), | |
960 | .soclk(soclk)); | |
961 | ||
962 | mcu_mbist_ctl_msff_ctl_macro__width_2 sel_pipe_reg3 ( | |
963 | .scan_in(sel_pipe_reg3_scanin), | |
964 | .scan_out(sel_pipe_reg3_scanout), | |
965 | .din ( sel_pipe_reg3_in[1:0] ), | |
966 | .dout ( sel_pipe_out3[1:0] ), | |
967 | .l1clk(l1clk), | |
968 | .siclk(siclk), | |
969 | .soclk(soclk)); | |
970 | ||
971 | mcu_mbist_ctl_msff_ctl_macro__width_2 sel_pipe_reg4 ( | |
972 | .scan_in(sel_pipe_reg4_scanin), | |
973 | .scan_out(sel_pipe_reg4_scanout), | |
974 | .din ( sel_pipe_reg4_in[1:0] ), | |
975 | .dout ( sel_pipe_out4[1:0] ), | |
976 | .l1clk(l1clk), | |
977 | .siclk(siclk), | |
978 | .soclk(soclk)); | |
979 | ||
980 | mcu_mbist_ctl_msff_ctl_macro__width_2 sel_pipe_reg5 ( | |
981 | .scan_in(sel_pipe_reg5_scanin), | |
982 | .scan_out(sel_pipe_reg5_scanout), | |
983 | .din ( sel_pipe_reg5_in[1:0] ), | |
984 | .dout ( sel_pipe_out5[1:0] ), | |
985 | .l1clk(l1clk), | |
986 | .siclk(siclk), | |
987 | .soclk(soclk)); | |
988 | ||
989 | ||
990 | assign sel_pipe_reg1_in[1:0] = reset_engine ? 2'h0: {sel_bank0or1, sel_hiorlo_72bits}; | |
991 | assign sel_pipe_reg2_in[1:0] = reset_engine ? 2'h0: sel_pipe_out1[1:0]; | |
992 | assign sel_pipe_reg3_in[1:0] = reset_engine ? 2'h0: sel_pipe_out2[1:0]; | |
993 | assign sel_pipe_reg4_in[1:0] = reset_engine ? 2'h0: sel_pipe_out3[1:0]; | |
994 | assign sel_pipe_reg5_in[1:0] = reset_engine ? 2'h0: sel_pipe_out4[1:0]; | |
995 | assign mcu_mbist_sel_hiorlo_72bits = sel_pipe_out3[0]; // After mux for bank0 or 1, there is a flop | |
996 | assign mcu_mbist_sel_bank0or1 = sel_pipe_out3[1]; // therefore, one more stage for hiorlo_72bits! | |
997 | ||
998 | assign piped_sel_hiorlo_72bits = sel_pipe_out5[0]; | |
999 | assign piped_sel_bank0or1 = sel_pipe_out5[1]; | |
1000 | ||
1001 | assign wdqrf00_sel_piped = ~piped_sel_bank0or1 & ~piped_sel_hiorlo_72bits; | |
1002 | assign wdqrf01_sel_piped = ~piped_sel_bank0or1 & piped_sel_hiorlo_72bits; | |
1003 | ||
1004 | assign wdqrf10_sel_piped = piped_sel_bank0or1 & ~piped_sel_hiorlo_72bits; | |
1005 | assign wdqrf11_sel_piped = piped_sel_bank0or1 & piped_sel_hiorlo_72bits; | |
1006 | ||
1007 | ||
1008 | // ///////////////////////////////////////////////////////////////////////////// | |
1009 | // Shared Fail Detection | |
1010 | // ///////////////////////////////////////////////////////////////////////////// | |
1011 | // Updated to meet these new features: | |
1012 | // 1.When mbist_done signal is asserted when it completes all the | |
1013 | // tests, it also need to assert static membist fail signal if | |
1014 | // there were any failures during the tests. | |
1015 | // 2.The mbist_fail signal won't be sticky bit from membist | |
1016 | // engine. The TCU will make it sticky fail bit as needed. | |
1017 | ||
1018 | ||
1019 | mcu_mbist_ctl_msff_ctl_macro__width_4 fail_reg ( | |
1020 | .scan_in(fail_reg_scanin), | |
1021 | .scan_out(fail_reg_scanout), | |
1022 | .din ( fail_reg_in[3:0] ), | |
1023 | .dout ( fail_reg_out[3:0] ), | |
1024 | .l1clk(l1clk), | |
1025 | .siclk(siclk), | |
1026 | .soclk(soclk)); | |
1027 | ||
1028 | ||
1029 | assign fail_reg_in[3:0] = reset_engine ? 4'b0: {qual_sio_wdqrf11_fail,qual_sio_wdqrf10_fail,qual_sio_wdqrf01_fail,qual_sio_wdqrf00_fail} | fail_reg_out[3:0]; | |
1030 | ||
1031 | ||
1032 | assign qual_sio_wdqrf00_fail = fail_detect && wdqrf00_sel_piped; | |
1033 | assign qual_sio_wdqrf01_fail = fail_detect && wdqrf01_sel_piped; | |
1034 | assign qual_sio_wdqrf10_fail = fail_detect && wdqrf10_sel_piped; | |
1035 | assign qual_sio_wdqrf11_fail = fail_detect && wdqrf11_sel_piped; | |
1036 | ||
1037 | assign fail = mbist_done ? |fail_reg_out[3:0]: | |
1038 | qual_sio_wdqrf00_fail | qual_sio_wdqrf01_fail | | |
1039 | qual_sio_wdqrf10_fail | qual_sio_wdqrf11_fail; | |
1040 | ||
1041 | ||
1042 | assign fail_detect = (({9{mbist_piped_wdata[7:0]}} != read_data_pipe[71:0]) && mbist_piped_ren); | |
1043 | ||
1044 | supply0 vss; // <- port for ground | |
1045 | supply1 vdd; // <- port for power | |
1046 | // ///////////////////////////////////////////////////////////////////////////// | |
1047 | ||
1048 | // spare gates | |
1049 | mcu_mbist_ctl_spare_ctl_macro__num_2 spares ( | |
1050 | .scan_in(spares_scanin), | |
1051 | .scan_out(spares_scanout), | |
1052 | .l1clk(l1clk), | |
1053 | .siclk(siclk), | |
1054 | .soclk(soclk) | |
1055 | ); | |
1056 | ||
1057 | // fixscan start: | |
1058 | assign config_reg_scanin = scan_in ; | |
1059 | assign user_data_reg_scanin = config_reg_scanout ; | |
1060 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
1061 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
1062 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
1063 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; | |
1064 | assign user_bisi_wr_reg_scanin = user_array_sel_reg_scanout; | |
1065 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
1066 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
1067 | assign run_reg_scanin = start_transition_reg_scanout; | |
1068 | assign counter_reg_scanin = run_reg_scanout ; | |
1069 | assign addr_reg_scanin = counter_reg_scanout ; | |
1070 | assign wdata_reg_scanin = addr_reg_scanout ; | |
1071 | assign wdqrf00_wr_rd_reg_scanin = wdata_reg_scanout ; | |
1072 | assign wdqrf01_wr_rd_reg_scanin = wdqrf00_wr_rd_reg_scanout; | |
1073 | assign wdqrf10_wr_rd_reg_scanin = wdqrf01_wr_rd_reg_scanout; | |
1074 | assign wdqrf11_wr_rd_reg_scanin = wdqrf10_wr_rd_reg_scanout; | |
1075 | assign done_reg_scanin = wdqrf11_wr_rd_reg_scanout; | |
1076 | assign mbist_fail_reg_scanin = done_reg_scanout ; | |
1077 | assign read_data_reg_scanin = mbist_fail_reg_scanout ; | |
1078 | assign control_reg_scanin = read_data_reg_scanout ; | |
1079 | assign done_counter_reg_scanin = control_reg_scanout ; | |
1080 | assign data_pipe_reg1_scanin = done_counter_reg_scanout ; | |
1081 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
1082 | assign data_pipe_reg3_scanin = data_pipe_reg2_scanout ; | |
1083 | assign data_pipe_reg4_scanin = data_pipe_reg3_scanout ; | |
1084 | assign ren_pipe_reg1_scanin = data_pipe_reg4_scanout ; | |
1085 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; | |
1086 | assign ren_pipe_reg3_scanin = ren_pipe_reg2_scanout ; | |
1087 | assign ren_pipe_reg4_scanin = ren_pipe_reg3_scanout ; | |
1088 | assign ren_pipe_reg5_scanin = ren_pipe_reg4_scanout ; | |
1089 | assign sel_pipe_reg1_scanin = ren_pipe_reg5_scanout ; | |
1090 | assign sel_pipe_reg2_scanin = sel_pipe_reg1_scanout ; | |
1091 | assign sel_pipe_reg3_scanin = sel_pipe_reg2_scanout ; | |
1092 | assign sel_pipe_reg4_scanin = sel_pipe_reg3_scanout ; | |
1093 | assign sel_pipe_reg5_scanin = sel_pipe_reg4_scanout ; | |
1094 | assign fail_reg_scanin = sel_pipe_reg5_scanout ; | |
1095 | assign spares_scanin = fail_reg_scanout ; | |
1096 | assign scan_out = spares_scanout ; | |
1097 | // fixscan end: | |
1098 | endmodule | |
1099 | // ///////////////////////////////////////////////////////////////////////////// | |
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | ||
1105 | ||
1106 | // any PARAMS parms go into naming of macro | |
1107 | ||
1108 | module mcu_mbist_ctl_l1clkhdr_ctl_macro ( | |
1109 | l2clk, | |
1110 | l1en, | |
1111 | pce_ov, | |
1112 | stop, | |
1113 | se, | |
1114 | l1clk); | |
1115 | ||
1116 | ||
1117 | input l2clk; | |
1118 | input l1en; | |
1119 | input pce_ov; | |
1120 | input stop; | |
1121 | input se; | |
1122 | output l1clk; | |
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | cl_sc1_l1hdr_8x c_0 ( | |
1129 | ||
1130 | ||
1131 | .l2clk(l2clk), | |
1132 | .pce(l1en), | |
1133 | .l1clk(l1clk), | |
1134 | .se(se), | |
1135 | .pce_ov(pce_ov), | |
1136 | .stop(stop) | |
1137 | ); | |
1138 | ||
1139 | ||
1140 | ||
1141 | endmodule | |
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | // any PARAMS parms go into naming of macro | |
1156 | ||
1157 | module mcu_mbist_ctl_msff_ctl_macro__width_8 ( | |
1158 | din, | |
1159 | l1clk, | |
1160 | scan_in, | |
1161 | siclk, | |
1162 | soclk, | |
1163 | dout, | |
1164 | scan_out); | |
1165 | wire [7:0] fdin; | |
1166 | wire [6:0] so; | |
1167 | ||
1168 | input [7:0] din; | |
1169 | input l1clk; | |
1170 | input scan_in; | |
1171 | ||
1172 | ||
1173 | input siclk; | |
1174 | input soclk; | |
1175 | ||
1176 | output [7:0] dout; | |
1177 | output scan_out; | |
1178 | assign fdin[7:0] = din[7:0]; | |
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | dff #(8) d0_0 ( | |
1186 | .l1clk(l1clk), | |
1187 | .siclk(siclk), | |
1188 | .soclk(soclk), | |
1189 | .d(fdin[7:0]), | |
1190 | .si({scan_in,so[6:0]}), | |
1191 | .so({so[6:0],scan_out}), | |
1192 | .q(dout[7:0]) | |
1193 | ); | |
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | endmodule | |
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | // any PARAMS parms go into naming of macro | |
1221 | ||
1222 | module mcu_mbist_ctl_msff_ctl_macro__width_5 ( | |
1223 | din, | |
1224 | l1clk, | |
1225 | scan_in, | |
1226 | siclk, | |
1227 | soclk, | |
1228 | dout, | |
1229 | scan_out); | |
1230 | wire [4:0] fdin; | |
1231 | wire [3:0] so; | |
1232 | ||
1233 | input [4:0] din; | |
1234 | input l1clk; | |
1235 | input scan_in; | |
1236 | ||
1237 | ||
1238 | input siclk; | |
1239 | input soclk; | |
1240 | ||
1241 | output [4:0] dout; | |
1242 | output scan_out; | |
1243 | assign fdin[4:0] = din[4:0]; | |
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | dff #(5) d0_0 ( | |
1251 | .l1clk(l1clk), | |
1252 | .siclk(siclk), | |
1253 | .soclk(soclk), | |
1254 | .d(fdin[4:0]), | |
1255 | .si({scan_in,so[3:0]}), | |
1256 | .so({so[3:0],scan_out}), | |
1257 | .q(dout[4:0]) | |
1258 | ); | |
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | endmodule | |
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | // any PARAMS parms go into naming of macro | |
1286 | ||
1287 | module mcu_mbist_ctl_msff_ctl_macro__width_2 ( | |
1288 | din, | |
1289 | l1clk, | |
1290 | scan_in, | |
1291 | siclk, | |
1292 | soclk, | |
1293 | dout, | |
1294 | scan_out); | |
1295 | wire [1:0] fdin; | |
1296 | wire [0:0] so; | |
1297 | ||
1298 | input [1:0] din; | |
1299 | input l1clk; | |
1300 | input scan_in; | |
1301 | ||
1302 | ||
1303 | input siclk; | |
1304 | input soclk; | |
1305 | ||
1306 | output [1:0] dout; | |
1307 | output scan_out; | |
1308 | assign fdin[1:0] = din[1:0]; | |
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | dff #(2) d0_0 ( | |
1316 | .l1clk(l1clk), | |
1317 | .siclk(siclk), | |
1318 | .soclk(soclk), | |
1319 | .d(fdin[1:0]), | |
1320 | .si({scan_in,so[0:0]}), | |
1321 | .so({so[0:0],scan_out}), | |
1322 | .q(dout[1:0]) | |
1323 | ); | |
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | endmodule | |
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | ||
1350 | // any PARAMS parms go into naming of macro | |
1351 | ||
1352 | module mcu_mbist_ctl_msff_ctl_macro__width_1 ( | |
1353 | din, | |
1354 | l1clk, | |
1355 | scan_in, | |
1356 | siclk, | |
1357 | soclk, | |
1358 | dout, | |
1359 | scan_out); | |
1360 | wire [0:0] fdin; | |
1361 | ||
1362 | input [0:0] din; | |
1363 | input l1clk; | |
1364 | input scan_in; | |
1365 | ||
1366 | ||
1367 | input siclk; | |
1368 | input soclk; | |
1369 | ||
1370 | output [0:0] dout; | |
1371 | output scan_out; | |
1372 | assign fdin[0:0] = din[0:0]; | |
1373 | ||
1374 | ||
1375 | ||
1376 | ||
1377 | ||
1378 | ||
1379 | dff #(1) d0_0 ( | |
1380 | .l1clk(l1clk), | |
1381 | .siclk(siclk), | |
1382 | .soclk(soclk), | |
1383 | .d(fdin[0:0]), | |
1384 | .si(scan_in), | |
1385 | .so(scan_out), | |
1386 | .q(dout[0:0]) | |
1387 | ); | |
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | endmodule | |
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | // any PARAMS parms go into naming of macro | |
1415 | ||
1416 | module mcu_mbist_ctl_msff_ctl_macro__width_4 ( | |
1417 | din, | |
1418 | l1clk, | |
1419 | scan_in, | |
1420 | siclk, | |
1421 | soclk, | |
1422 | dout, | |
1423 | scan_out); | |
1424 | wire [3:0] fdin; | |
1425 | wire [2:0] so; | |
1426 | ||
1427 | input [3:0] din; | |
1428 | input l1clk; | |
1429 | input scan_in; | |
1430 | ||
1431 | ||
1432 | input siclk; | |
1433 | input soclk; | |
1434 | ||
1435 | output [3:0] dout; | |
1436 | output scan_out; | |
1437 | assign fdin[3:0] = din[3:0]; | |
1438 | ||
1439 | ||
1440 | ||
1441 | ||
1442 | ||
1443 | ||
1444 | dff #(4) d0_0 ( | |
1445 | .l1clk(l1clk), | |
1446 | .siclk(siclk), | |
1447 | .soclk(soclk), | |
1448 | .d(fdin[3:0]), | |
1449 | .si({scan_in,so[2:0]}), | |
1450 | .so({so[2:0],scan_out}), | |
1451 | .q(dout[3:0]) | |
1452 | ); | |
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | endmodule | |
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | // any PARAMS parms go into naming of macro | |
1480 | ||
1481 | module mcu_mbist_ctl_msff_ctl_macro__width_72 ( | |
1482 | din, | |
1483 | l1clk, | |
1484 | scan_in, | |
1485 | siclk, | |
1486 | soclk, | |
1487 | dout, | |
1488 | scan_out); | |
1489 | wire [71:0] fdin; | |
1490 | wire [70:0] so; | |
1491 | ||
1492 | input [71:0] din; | |
1493 | input l1clk; | |
1494 | input scan_in; | |
1495 | ||
1496 | ||
1497 | input siclk; | |
1498 | input soclk; | |
1499 | ||
1500 | output [71:0] dout; | |
1501 | output scan_out; | |
1502 | assign fdin[71:0] = din[71:0]; | |
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | dff #(72) d0_0 ( | |
1510 | .l1clk(l1clk), | |
1511 | .siclk(siclk), | |
1512 | .soclk(soclk), | |
1513 | .d(fdin[71:0]), | |
1514 | .si({scan_in,so[70:0]}), | |
1515 | .so({so[70:0],scan_out}), | |
1516 | .q(dout[71:0]) | |
1517 | ); | |
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | endmodule | |
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | // any PARAMS parms go into naming of macro | |
1545 | ||
1546 | module mcu_mbist_ctl_msff_ctl_macro__width_19 ( | |
1547 | din, | |
1548 | l1clk, | |
1549 | scan_in, | |
1550 | siclk, | |
1551 | soclk, | |
1552 | dout, | |
1553 | scan_out); | |
1554 | wire [18:0] fdin; | |
1555 | wire [17:0] so; | |
1556 | ||
1557 | input [18:0] din; | |
1558 | input l1clk; | |
1559 | input scan_in; | |
1560 | ||
1561 | ||
1562 | input siclk; | |
1563 | input soclk; | |
1564 | ||
1565 | output [18:0] dout; | |
1566 | output scan_out; | |
1567 | assign fdin[18:0] = din[18:0]; | |
1568 | ||
1569 | ||
1570 | ||
1571 | ||
1572 | ||
1573 | ||
1574 | dff #(19) d0_0 ( | |
1575 | .l1clk(l1clk), | |
1576 | .siclk(siclk), | |
1577 | .soclk(soclk), | |
1578 | .d(fdin[18:0]), | |
1579 | .si({scan_in,so[17:0]}), | |
1580 | .so({so[17:0],scan_out}), | |
1581 | .q(dout[18:0]) | |
1582 | ); | |
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | endmodule | |
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | // any PARAMS parms go into naming of macro | |
1610 | ||
1611 | module mcu_mbist_ctl_msff_ctl_macro__width_3 ( | |
1612 | din, | |
1613 | l1clk, | |
1614 | scan_in, | |
1615 | siclk, | |
1616 | soclk, | |
1617 | dout, | |
1618 | scan_out); | |
1619 | wire [2:0] fdin; | |
1620 | wire [1:0] so; | |
1621 | ||
1622 | input [2:0] din; | |
1623 | input l1clk; | |
1624 | input scan_in; | |
1625 | ||
1626 | ||
1627 | input siclk; | |
1628 | input soclk; | |
1629 | ||
1630 | output [2:0] dout; | |
1631 | output scan_out; | |
1632 | assign fdin[2:0] = din[2:0]; | |
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | dff #(3) d0_0 ( | |
1640 | .l1clk(l1clk), | |
1641 | .siclk(siclk), | |
1642 | .soclk(soclk), | |
1643 | .d(fdin[2:0]), | |
1644 | .si({scan_in,so[1:0]}), | |
1645 | .so({so[1:0],scan_out}), | |
1646 | .q(dout[2:0]) | |
1647 | ); | |
1648 | ||
1649 | ||
1650 | ||
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | ||
1660 | endmodule | |
1661 | ||
1662 | ||
1663 | ||
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | ||
1670 | // Description: Spare gate macro for control blocks | |
1671 | // | |
1672 | // Param num controls the number of times the macro is added | |
1673 | // flops=0 can be used to use only combination spare logic | |
1674 | ||
1675 | ||
1676 | module mcu_mbist_ctl_spare_ctl_macro__num_2 ( | |
1677 | l1clk, | |
1678 | scan_in, | |
1679 | siclk, | |
1680 | soclk, | |
1681 | scan_out); | |
1682 | wire si_0; | |
1683 | wire so_0; | |
1684 | wire spare0_flop_unused; | |
1685 | wire spare0_buf_32x_unused; | |
1686 | wire spare0_nand3_8x_unused; | |
1687 | wire spare0_inv_8x_unused; | |
1688 | wire spare0_aoi22_4x_unused; | |
1689 | wire spare0_buf_8x_unused; | |
1690 | wire spare0_oai22_4x_unused; | |
1691 | wire spare0_inv_16x_unused; | |
1692 | wire spare0_nand2_16x_unused; | |
1693 | wire spare0_nor3_4x_unused; | |
1694 | wire spare0_nand2_8x_unused; | |
1695 | wire spare0_buf_16x_unused; | |
1696 | wire spare0_nor2_16x_unused; | |
1697 | wire spare0_inv_32x_unused; | |
1698 | wire si_1; | |
1699 | wire so_1; | |
1700 | wire spare1_flop_unused; | |
1701 | wire spare1_buf_32x_unused; | |
1702 | wire spare1_nand3_8x_unused; | |
1703 | wire spare1_inv_8x_unused; | |
1704 | wire spare1_aoi22_4x_unused; | |
1705 | wire spare1_buf_8x_unused; | |
1706 | wire spare1_oai22_4x_unused; | |
1707 | wire spare1_inv_16x_unused; | |
1708 | wire spare1_nand2_16x_unused; | |
1709 | wire spare1_nor3_4x_unused; | |
1710 | wire spare1_nand2_8x_unused; | |
1711 | wire spare1_buf_16x_unused; | |
1712 | wire spare1_nor2_16x_unused; | |
1713 | wire spare1_inv_32x_unused; | |
1714 | ||
1715 | ||
1716 | input l1clk; | |
1717 | input scan_in; | |
1718 | input siclk; | |
1719 | input soclk; | |
1720 | output scan_out; | |
1721 | ||
1722 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1723 | .siclk(siclk), | |
1724 | .soclk(soclk), | |
1725 | .si(si_0), | |
1726 | .so(so_0), | |
1727 | .d(1'b0), | |
1728 | .q(spare0_flop_unused)); | |
1729 | assign si_0 = scan_in; | |
1730 | ||
1731 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1732 | .out(spare0_buf_32x_unused)); | |
1733 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1734 | .in1(1'b1), | |
1735 | .in2(1'b1), | |
1736 | .out(spare0_nand3_8x_unused)); | |
1737 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1738 | .out(spare0_inv_8x_unused)); | |
1739 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1740 | .in01(1'b1), | |
1741 | .in10(1'b1), | |
1742 | .in11(1'b1), | |
1743 | .out(spare0_aoi22_4x_unused)); | |
1744 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1745 | .out(spare0_buf_8x_unused)); | |
1746 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1747 | .in01(1'b1), | |
1748 | .in10(1'b1), | |
1749 | .in11(1'b1), | |
1750 | .out(spare0_oai22_4x_unused)); | |
1751 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1752 | .out(spare0_inv_16x_unused)); | |
1753 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1754 | .in1(1'b1), | |
1755 | .out(spare0_nand2_16x_unused)); | |
1756 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1757 | .in1(1'b0), | |
1758 | .in2(1'b0), | |
1759 | .out(spare0_nor3_4x_unused)); | |
1760 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1761 | .in1(1'b1), | |
1762 | .out(spare0_nand2_8x_unused)); | |
1763 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1764 | .out(spare0_buf_16x_unused)); | |
1765 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1766 | .in1(1'b0), | |
1767 | .out(spare0_nor2_16x_unused)); | |
1768 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1769 | .out(spare0_inv_32x_unused)); | |
1770 | ||
1771 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1772 | .siclk(siclk), | |
1773 | .soclk(soclk), | |
1774 | .si(si_1), | |
1775 | .so(so_1), | |
1776 | .d(1'b0), | |
1777 | .q(spare1_flop_unused)); | |
1778 | assign si_1 = so_0; | |
1779 | ||
1780 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1781 | .out(spare1_buf_32x_unused)); | |
1782 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1783 | .in1(1'b1), | |
1784 | .in2(1'b1), | |
1785 | .out(spare1_nand3_8x_unused)); | |
1786 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1787 | .out(spare1_inv_8x_unused)); | |
1788 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1789 | .in01(1'b1), | |
1790 | .in10(1'b1), | |
1791 | .in11(1'b1), | |
1792 | .out(spare1_aoi22_4x_unused)); | |
1793 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1794 | .out(spare1_buf_8x_unused)); | |
1795 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1796 | .in01(1'b1), | |
1797 | .in10(1'b1), | |
1798 | .in11(1'b1), | |
1799 | .out(spare1_oai22_4x_unused)); | |
1800 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1801 | .out(spare1_inv_16x_unused)); | |
1802 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1803 | .in1(1'b1), | |
1804 | .out(spare1_nand2_16x_unused)); | |
1805 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1806 | .in1(1'b0), | |
1807 | .in2(1'b0), | |
1808 | .out(spare1_nor3_4x_unused)); | |
1809 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1810 | .in1(1'b1), | |
1811 | .out(spare1_nand2_8x_unused)); | |
1812 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1813 | .out(spare1_buf_16x_unused)); | |
1814 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1815 | .in1(1'b0), | |
1816 | .out(spare1_nor2_16x_unused)); | |
1817 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1818 | .out(spare1_inv_32x_unused)); | |
1819 | assign scan_out = so_1; | |
1820 | ||
1821 | ||
1822 | ||
1823 | endmodule | |
1824 |