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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_reqq_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_reqq_ctl ( | |
36 | woq_entry0, | |
37 | woq_entry1, | |
38 | woq_entry_valid, | |
39 | woq_entry0_val, | |
40 | woq_entry1_val, | |
41 | woq_wr_bank_val, | |
42 | woq_wdq_radr, | |
43 | woq_io_wdata_sel, | |
44 | woq1_wr_picked, | |
45 | woq_wr_addr_picked, | |
46 | woq_wr1_addr_picked, | |
47 | woq_wr2_addr_picked, | |
48 | woq_wr_index_picked, | |
49 | woq_wr1_index_picked, | |
50 | woq_wr2_index_picked, | |
51 | woq_wr_wdq_index_picked, | |
52 | woq_wr1_wdq_index_picked, | |
53 | woq_wr2_wdq_index_picked, | |
54 | woq_wr_adr_queue_sel, | |
55 | woq_wr1_adr_queue_sel, | |
56 | woq_wr2_adr_queue_sel, | |
57 | woq_wadr_parity, | |
58 | woq_wdata_wsn, | |
59 | woq_err_st_wait_free, | |
60 | woq_err_fifo_empty, | |
61 | woq_wr_req_out, | |
62 | woq_pd_mode_wr_decr, | |
63 | woq_owr_empty, | |
64 | woq_empty, | |
65 | woq_wr_error_mode, | |
66 | woq_wdata_send, | |
67 | drq0_rd_adr_queue7_en, | |
68 | drq0_rd_adr_queue6_en, | |
69 | drq0_rd_adr_queue5_en, | |
70 | drq0_rd_adr_queue4_en, | |
71 | drq0_rd_adr_queue3_en, | |
72 | drq0_rd_adr_queue2_en, | |
73 | drq0_rd_adr_queue1_en, | |
74 | drq0_rd_adr_queue0_en, | |
75 | drq0_rd_adr_queue_sel, | |
76 | drq0_wr_adr_queue7_en, | |
77 | drq0_wr_adr_queue6_en, | |
78 | drq0_wr_adr_queue5_en, | |
79 | drq0_wr_adr_queue4_en, | |
80 | drq0_wr_adr_queue3_en, | |
81 | drq0_wr_adr_queue2_en, | |
82 | drq0_wr_adr_queue1_en, | |
83 | drq0_wr_adr_queue0_en, | |
84 | drq0_req_rdwr_addr_sel, | |
85 | drq0_rdbuf_valids, | |
86 | drq0_wrbuf_valids, | |
87 | drq0_pending_wr_req, | |
88 | drq0_read_queue_cnt, | |
89 | drq0_write_queue_cnt, | |
90 | drq0_rd_entry0_val, | |
91 | drq0_rd_entry1_val, | |
92 | drq0_rd_entry2_val, | |
93 | drq0_rd_entry3_val, | |
94 | drq0_rd_entry4_val, | |
95 | drq0_rd_entry5_val, | |
96 | drq0_rd_entry6_val, | |
97 | drq0_rd_entry7_val, | |
98 | drq0_rd_bank_val, | |
99 | drq0_rd_entry0_rank, | |
100 | drq0_rd_entry1_rank, | |
101 | drq0_rd_entry2_rank, | |
102 | drq0_rd_entry3_rank, | |
103 | drq0_rd_entry4_rank, | |
104 | drq0_rd_entry5_rank, | |
105 | drq0_rd_entry6_rank, | |
106 | drq0_rd_entry7_rank, | |
107 | drq0_wr_entry0_rank, | |
108 | drq0_wr_entry1_rank, | |
109 | drq0_wr_entry2_rank, | |
110 | drq0_wr_entry3_rank, | |
111 | drq0_wr_entry4_rank, | |
112 | drq0_wr_entry5_rank, | |
113 | drq0_wr_entry6_rank, | |
114 | drq0_wr_entry7_rank, | |
115 | drq0_rd_entry0_dimm, | |
116 | drq0_rd_entry1_dimm, | |
117 | drq0_rd_entry2_dimm, | |
118 | drq0_rd_entry3_dimm, | |
119 | drq0_rd_entry4_dimm, | |
120 | drq0_rd_entry5_dimm, | |
121 | drq0_rd_entry6_dimm, | |
122 | drq0_rd_entry7_dimm, | |
123 | drq0_wr_entry0_dimm, | |
124 | drq0_wr_entry1_dimm, | |
125 | drq0_wr_entry2_dimm, | |
126 | drq0_wr_entry3_dimm, | |
127 | drq0_wr_entry4_dimm, | |
128 | drq0_wr_entry5_dimm, | |
129 | drq0_wr_entry6_dimm, | |
130 | drq0_wr_entry7_dimm, | |
131 | drq0_rd_addr_picked, | |
132 | drq0_rdq_free, | |
133 | drq0_rdq_full, | |
134 | drq0_empty, | |
135 | drq0_rd_index_picked, | |
136 | drq0_wr_index_picked, | |
137 | drq0_wr_id_picked, | |
138 | drq0_pd_mode_rd_incr, | |
139 | drq0_pd_mode_rd_decr, | |
140 | drq0_pd_mode_wr_incr, | |
141 | woq0_wdq_rd, | |
142 | woq0_wdq_entry_free, | |
143 | drq0_rd_req, | |
144 | drq0_wr_req, | |
145 | drif0_raw_hazard, | |
146 | l2if0_rd_req, | |
147 | l2if0_wr_req, | |
148 | drif0_cpu_wr_addr, | |
149 | l2if0_wdq_in_cntr, | |
150 | l2b0_rd_rank_adr, | |
151 | l2b0_rd_dimm_adr, | |
152 | l2b0_rd_bank_adr, | |
153 | l2b0_rd_addr_err, | |
154 | l2b0_rd_addr_par, | |
155 | l2b0_wr_rank_adr, | |
156 | l2b0_wr_dimm_adr, | |
157 | l2b0_wr_bank_adr, | |
158 | l2b0_wr_addr_err, | |
159 | l2b0_wr_addr_par, | |
160 | rdpctl_drq0_clear_ent, | |
161 | drif_drq0_clear_ent, | |
162 | drif0_rd_entry_picked, | |
163 | drq1_rd_adr_queue7_en, | |
164 | drq1_rd_adr_queue6_en, | |
165 | drq1_rd_adr_queue5_en, | |
166 | drq1_rd_adr_queue4_en, | |
167 | drq1_rd_adr_queue3_en, | |
168 | drq1_rd_adr_queue2_en, | |
169 | drq1_rd_adr_queue1_en, | |
170 | drq1_rd_adr_queue0_en, | |
171 | drq1_rd_adr_queue_sel, | |
172 | drq1_wr_adr_queue7_en, | |
173 | drq1_wr_adr_queue6_en, | |
174 | drq1_wr_adr_queue5_en, | |
175 | drq1_wr_adr_queue4_en, | |
176 | drq1_wr_adr_queue3_en, | |
177 | drq1_wr_adr_queue2_en, | |
178 | drq1_wr_adr_queue1_en, | |
179 | drq1_wr_adr_queue0_en, | |
180 | drq1_req_rdwr_addr_sel, | |
181 | drq1_rdbuf_valids, | |
182 | drq1_wrbuf_valids, | |
183 | drq1_pending_wr_req, | |
184 | drq1_read_queue_cnt, | |
185 | drq1_write_queue_cnt, | |
186 | drq1_rd_entry0_val, | |
187 | drq1_rd_entry1_val, | |
188 | drq1_rd_entry2_val, | |
189 | drq1_rd_entry3_val, | |
190 | drq1_rd_entry4_val, | |
191 | drq1_rd_entry5_val, | |
192 | drq1_rd_entry6_val, | |
193 | drq1_rd_entry7_val, | |
194 | drq1_rd_bank_val, | |
195 | drq1_rd_entry0_rank, | |
196 | drq1_rd_entry1_rank, | |
197 | drq1_rd_entry2_rank, | |
198 | drq1_rd_entry3_rank, | |
199 | drq1_rd_entry4_rank, | |
200 | drq1_rd_entry5_rank, | |
201 | drq1_rd_entry6_rank, | |
202 | drq1_rd_entry7_rank, | |
203 | drq1_wr_entry0_rank, | |
204 | drq1_wr_entry1_rank, | |
205 | drq1_wr_entry2_rank, | |
206 | drq1_wr_entry3_rank, | |
207 | drq1_wr_entry4_rank, | |
208 | drq1_wr_entry5_rank, | |
209 | drq1_wr_entry6_rank, | |
210 | drq1_wr_entry7_rank, | |
211 | drq1_rd_entry0_dimm, | |
212 | drq1_rd_entry1_dimm, | |
213 | drq1_rd_entry2_dimm, | |
214 | drq1_rd_entry3_dimm, | |
215 | drq1_rd_entry4_dimm, | |
216 | drq1_rd_entry5_dimm, | |
217 | drq1_rd_entry6_dimm, | |
218 | drq1_rd_entry7_dimm, | |
219 | drq1_wr_entry0_dimm, | |
220 | drq1_wr_entry1_dimm, | |
221 | drq1_wr_entry2_dimm, | |
222 | drq1_wr_entry3_dimm, | |
223 | drq1_wr_entry4_dimm, | |
224 | drq1_wr_entry5_dimm, | |
225 | drq1_wr_entry6_dimm, | |
226 | drq1_wr_entry7_dimm, | |
227 | drq1_rd_addr_picked, | |
228 | drq1_rdq_free, | |
229 | woq1_wdq_entry_free, | |
230 | drq1_rdq_full, | |
231 | drq1_empty, | |
232 | drq1_rd_index_picked, | |
233 | drq1_wr_index_picked, | |
234 | drq1_wr_id_picked, | |
235 | drq1_pd_mode_rd_incr, | |
236 | drq1_pd_mode_rd_decr, | |
237 | drq1_pd_mode_wr_incr, | |
238 | woq1_wdq_rd, | |
239 | drq1_rd_req, | |
240 | drq1_wr_req, | |
241 | woq_err_pdm_wr_incr, | |
242 | woq_err_pdm_wr_decr, | |
243 | drif1_raw_hazard, | |
244 | l2if1_rd_req, | |
245 | l2if1_wr_req, | |
246 | drif1_cpu_wr_addr, | |
247 | l2if1_wdq_in_cntr, | |
248 | l2b1_rd_rank_adr, | |
249 | l2b1_rd_dimm_adr, | |
250 | l2b1_rd_bank_adr, | |
251 | l2b1_rd_addr_err, | |
252 | l2b1_rd_addr_par, | |
253 | l2b1_wr_rank_adr, | |
254 | l2b1_wr_dimm_adr, | |
255 | l2b1_wr_bank_adr, | |
256 | l2b1_wr_addr_err, | |
257 | l2b1_wr_addr_par, | |
258 | rdpctl_drq1_clear_ent, | |
259 | drif_drq1_clear_ent, | |
260 | drif1_rd_entry_picked, | |
261 | drif_wr_entry_picked, | |
262 | drif_mcu_state_1, | |
263 | drif_mcu_state_2, | |
264 | drif_mcu_state_3, | |
265 | drif_mcu_state_4, | |
266 | drif_mcu_state_5, | |
267 | drif_mcu_state_6, | |
268 | drif_init, | |
269 | drif_init_mcu_done, | |
270 | drif_cmd_picked, | |
271 | drif_blk_new_openbank, | |
272 | drif_refresh_rank, | |
273 | drif_rd_picked, | |
274 | drif_wr_picked, | |
275 | drif_eight_bank_mode, | |
276 | drif_stacked_dimm, | |
277 | drif_sync_frame_req_l, | |
278 | drif_sync_frame_req_early3_l, | |
279 | drif_single_channel_mode, | |
280 | drif_pd_mode_pending, | |
281 | drif_err_fifo_empty, | |
282 | pdmc_rank_avail, | |
283 | drif_dimm_rd_available, | |
284 | drif_dimm_wr_available, | |
285 | drif_wr_bc_stall, | |
286 | drif_hw_selfrsh, | |
287 | fbdic_l0_state, | |
288 | fbdic_chnl_reset_error_mode, | |
289 | drif_woq_free, | |
290 | fbdic_clear_wrq_ent, | |
291 | fbdic_scr_frame_req_d4, | |
292 | fbdic_error_mode, | |
293 | l1clk, | |
294 | scan_in, | |
295 | scan_out, | |
296 | tcu_aclk, | |
297 | tcu_bclk, | |
298 | tcu_scan_en); | |
299 | wire drq0_scanin; | |
300 | wire drq0_scanout; | |
301 | wire [7:0] woq0_wrq_clear_ent; | |
302 | wire [14:0] drq0_wr_queue_ent0; | |
303 | wire [14:0] drq0_wr_queue_ent1; | |
304 | wire [14:0] drq0_wr_queue_ent2; | |
305 | wire [14:0] drq0_wr_queue_ent3; | |
306 | wire [14:0] drq0_wr_queue_ent4; | |
307 | wire [14:0] drq0_wr_queue_ent5; | |
308 | wire [14:0] drq0_wr_queue_ent6; | |
309 | wire [14:0] drq0_wr_queue_ent7; | |
310 | wire [7:0] drq0_wdq_valid; | |
311 | wire [7:0] woq0_wr_queue_clear; | |
312 | wire [7:0] woq0_wr_entry_picked; | |
313 | wire drq1_scanin; | |
314 | wire drq1_scanout; | |
315 | wire [7:0] woq1_wrq_clear_ent; | |
316 | wire [14:0] drq1_wr_queue_ent0; | |
317 | wire [14:0] drq1_wr_queue_ent1; | |
318 | wire [14:0] drq1_wr_queue_ent2; | |
319 | wire [14:0] drq1_wr_queue_ent3; | |
320 | wire [14:0] drq1_wr_queue_ent4; | |
321 | wire [14:0] drq1_wr_queue_ent5; | |
322 | wire [14:0] drq1_wr_queue_ent6; | |
323 | wire [14:0] drq1_wr_queue_ent7; | |
324 | wire [7:0] drq1_wdq_valid; | |
325 | wire [7:0] woq1_wr_queue_clear; | |
326 | wire [7:0] woq1_wr_entry_picked; | |
327 | wire woq_scanin; | |
328 | wire woq_scanout; | |
329 | ||
330 | ||
331 | output [15:0] woq_entry0; | |
332 | output [15:0] woq_entry1; | |
333 | output [2:0] woq_entry_valid; | |
334 | ||
335 | output [15:0] woq_entry0_val; | |
336 | output [15:0] woq_entry1_val; | |
337 | ||
338 | output [15:0] woq_wr_bank_val; | |
339 | ||
340 | output [4:0] woq_wdq_radr; | |
341 | output [1:0] woq_io_wdata_sel; | |
342 | ||
343 | output [2:0] woq1_wr_picked; | |
344 | ||
345 | output [9:0] woq_wr_addr_picked; | |
346 | output [9:0] woq_wr1_addr_picked; | |
347 | output [9:0] woq_wr2_addr_picked; | |
348 | ||
349 | output [2:0] woq_wr_index_picked; | |
350 | output [2:0] woq_wr1_index_picked; | |
351 | output [2:0] woq_wr2_index_picked; | |
352 | ||
353 | output [2:0] woq_wr_wdq_index_picked; | |
354 | output [2:0] woq_wr1_wdq_index_picked; | |
355 | output [2:0] woq_wr2_wdq_index_picked; | |
356 | ||
357 | output [7:0] woq_wr_adr_queue_sel; | |
358 | output [7:0] woq_wr1_adr_queue_sel; | |
359 | output [7:0] woq_wr2_adr_queue_sel; | |
360 | output woq_wadr_parity; | |
361 | ||
362 | output woq_wdata_wsn; | |
363 | output woq_err_st_wait_free; | |
364 | output woq_err_fifo_empty; | |
365 | output [1:0] woq_wr_req_out; | |
366 | output [15:0] woq_pd_mode_wr_decr; | |
367 | output woq_owr_empty; | |
368 | output woq_empty; | |
369 | output woq_wr_error_mode; | |
370 | output woq_wdata_send; | |
371 | ||
372 | output drq0_rd_adr_queue7_en; | |
373 | output drq0_rd_adr_queue6_en; | |
374 | output drq0_rd_adr_queue5_en; | |
375 | output drq0_rd_adr_queue4_en; | |
376 | output drq0_rd_adr_queue3_en; | |
377 | output drq0_rd_adr_queue2_en; | |
378 | output drq0_rd_adr_queue1_en; | |
379 | output drq0_rd_adr_queue0_en; | |
380 | output [7:0] drq0_rd_adr_queue_sel; | |
381 | output drq0_wr_adr_queue7_en; | |
382 | output drq0_wr_adr_queue6_en; | |
383 | output drq0_wr_adr_queue5_en; | |
384 | output drq0_wr_adr_queue4_en; | |
385 | output drq0_wr_adr_queue3_en; | |
386 | output drq0_wr_adr_queue2_en; | |
387 | output drq0_wr_adr_queue1_en; | |
388 | output drq0_wr_adr_queue0_en; | |
389 | output drq0_req_rdwr_addr_sel; | |
390 | output [7:0] drq0_rdbuf_valids; | |
391 | output [7:0] drq0_wrbuf_valids; | |
392 | output [7:0] drq0_pending_wr_req; | |
393 | output [3:0] drq0_read_queue_cnt; | |
394 | output [3:0] drq0_write_queue_cnt; | |
395 | output [15:0] drq0_rd_entry0_val; | |
396 | output [15:0] drq0_rd_entry1_val; | |
397 | output [15:0] drq0_rd_entry2_val; | |
398 | output [15:0] drq0_rd_entry3_val; | |
399 | output [15:0] drq0_rd_entry4_val; | |
400 | output [15:0] drq0_rd_entry5_val; | |
401 | output [15:0] drq0_rd_entry6_val; | |
402 | output [15:0] drq0_rd_entry7_val; | |
403 | output [15:0] drq0_rd_bank_val; | |
404 | output drq0_rd_entry0_rank; | |
405 | output drq0_rd_entry1_rank; | |
406 | output drq0_rd_entry2_rank; | |
407 | output drq0_rd_entry3_rank; | |
408 | output drq0_rd_entry4_rank; | |
409 | output drq0_rd_entry5_rank; | |
410 | output drq0_rd_entry6_rank; | |
411 | output drq0_rd_entry7_rank; | |
412 | output drq0_wr_entry0_rank; | |
413 | output drq0_wr_entry1_rank; | |
414 | output drq0_wr_entry2_rank; | |
415 | output drq0_wr_entry3_rank; | |
416 | output drq0_wr_entry4_rank; | |
417 | output drq0_wr_entry5_rank; | |
418 | output drq0_wr_entry6_rank; | |
419 | output drq0_wr_entry7_rank; | |
420 | output [2:0] drq0_rd_entry0_dimm; | |
421 | output [2:0] drq0_rd_entry1_dimm; | |
422 | output [2:0] drq0_rd_entry2_dimm; | |
423 | output [2:0] drq0_rd_entry3_dimm; | |
424 | output [2:0] drq0_rd_entry4_dimm; | |
425 | output [2:0] drq0_rd_entry5_dimm; | |
426 | output [2:0] drq0_rd_entry6_dimm; | |
427 | output [2:0] drq0_rd_entry7_dimm; | |
428 | output [2:0] drq0_wr_entry0_dimm; | |
429 | output [2:0] drq0_wr_entry1_dimm; | |
430 | output [2:0] drq0_wr_entry2_dimm; | |
431 | output [2:0] drq0_wr_entry3_dimm; | |
432 | output [2:0] drq0_wr_entry4_dimm; | |
433 | output [2:0] drq0_wr_entry5_dimm; | |
434 | output [2:0] drq0_wr_entry6_dimm; | |
435 | output [2:0] drq0_wr_entry7_dimm; | |
436 | output [9:0] drq0_rd_addr_picked; | |
437 | output drq0_rdq_free; | |
438 | output drq0_rdq_full; | |
439 | output drq0_empty; | |
440 | output [2:0] drq0_rd_index_picked; | |
441 | output [2:0] drq0_wr_index_picked; | |
442 | output [2:0] drq0_wr_id_picked; | |
443 | output [15:0] drq0_pd_mode_rd_incr; | |
444 | output [15:0] drq0_pd_mode_rd_decr; | |
445 | output [15:0] drq0_pd_mode_wr_incr; | |
446 | output woq0_wdq_rd; | |
447 | output [7:0] woq0_wdq_entry_free; | |
448 | output drq0_rd_req; | |
449 | output drq0_wr_req; | |
450 | input drif0_raw_hazard; | |
451 | input l2if0_rd_req; | |
452 | input l2if0_wr_req; | |
453 | input [2:0] drif0_cpu_wr_addr; | |
454 | input [3:0] l2if0_wdq_in_cntr; // incremented by l2if when all data for a write is in wdq | |
455 | input l2b0_rd_rank_adr; | |
456 | input [2:0] l2b0_rd_dimm_adr; | |
457 | input [2:0] l2b0_rd_bank_adr; | |
458 | input l2b0_rd_addr_err; | |
459 | input l2b0_rd_addr_par; | |
460 | input l2b0_wr_rank_adr; | |
461 | input [2:0] l2b0_wr_dimm_adr; | |
462 | input [2:0] l2b0_wr_bank_adr; | |
463 | input l2b0_wr_addr_err; | |
464 | input l2b0_wr_addr_par; | |
465 | input [7:0] rdpctl_drq0_clear_ent; | |
466 | input [7:0] drif_drq0_clear_ent; | |
467 | input [7:0] drif0_rd_entry_picked; | |
468 | ||
469 | output drq1_rd_adr_queue7_en; | |
470 | output drq1_rd_adr_queue6_en; | |
471 | output drq1_rd_adr_queue5_en; | |
472 | output drq1_rd_adr_queue4_en; | |
473 | output drq1_rd_adr_queue3_en; | |
474 | output drq1_rd_adr_queue2_en; | |
475 | output drq1_rd_adr_queue1_en; | |
476 | output drq1_rd_adr_queue0_en; | |
477 | output [7:0] drq1_rd_adr_queue_sel; | |
478 | output drq1_wr_adr_queue7_en; | |
479 | output drq1_wr_adr_queue6_en; | |
480 | output drq1_wr_adr_queue5_en; | |
481 | output drq1_wr_adr_queue4_en; | |
482 | output drq1_wr_adr_queue3_en; | |
483 | output drq1_wr_adr_queue2_en; | |
484 | output drq1_wr_adr_queue1_en; | |
485 | output drq1_wr_adr_queue0_en; | |
486 | output drq1_req_rdwr_addr_sel; | |
487 | output [7:0] drq1_rdbuf_valids; | |
488 | output [7:0] drq1_wrbuf_valids; | |
489 | output [7:0] drq1_pending_wr_req; | |
490 | output [3:0] drq1_read_queue_cnt; | |
491 | output [3:0] drq1_write_queue_cnt; | |
492 | output [15:0] drq1_rd_entry0_val; | |
493 | output [15:0] drq1_rd_entry1_val; | |
494 | output [15:0] drq1_rd_entry2_val; | |
495 | output [15:0] drq1_rd_entry3_val; | |
496 | output [15:0] drq1_rd_entry4_val; | |
497 | output [15:0] drq1_rd_entry5_val; | |
498 | output [15:0] drq1_rd_entry6_val; | |
499 | output [15:0] drq1_rd_entry7_val; | |
500 | output [15:0] drq1_rd_bank_val; | |
501 | output drq1_rd_entry0_rank; | |
502 | output drq1_rd_entry1_rank; | |
503 | output drq1_rd_entry2_rank; | |
504 | output drq1_rd_entry3_rank; | |
505 | output drq1_rd_entry4_rank; | |
506 | output drq1_rd_entry5_rank; | |
507 | output drq1_rd_entry6_rank; | |
508 | output drq1_rd_entry7_rank; | |
509 | output drq1_wr_entry0_rank; | |
510 | output drq1_wr_entry1_rank; | |
511 | output drq1_wr_entry2_rank; | |
512 | output drq1_wr_entry3_rank; | |
513 | output drq1_wr_entry4_rank; | |
514 | output drq1_wr_entry5_rank; | |
515 | output drq1_wr_entry6_rank; | |
516 | output drq1_wr_entry7_rank; | |
517 | output [2:0] drq1_rd_entry0_dimm; | |
518 | output [2:0] drq1_rd_entry1_dimm; | |
519 | output [2:0] drq1_rd_entry2_dimm; | |
520 | output [2:0] drq1_rd_entry3_dimm; | |
521 | output [2:0] drq1_rd_entry4_dimm; | |
522 | output [2:0] drq1_rd_entry5_dimm; | |
523 | output [2:0] drq1_rd_entry6_dimm; | |
524 | output [2:0] drq1_rd_entry7_dimm; | |
525 | output [2:0] drq1_wr_entry0_dimm; | |
526 | output [2:0] drq1_wr_entry1_dimm; | |
527 | output [2:0] drq1_wr_entry2_dimm; | |
528 | output [2:0] drq1_wr_entry3_dimm; | |
529 | output [2:0] drq1_wr_entry4_dimm; | |
530 | output [2:0] drq1_wr_entry5_dimm; | |
531 | output [2:0] drq1_wr_entry6_dimm; | |
532 | output [2:0] drq1_wr_entry7_dimm; | |
533 | output [9:0] drq1_rd_addr_picked; | |
534 | output drq1_rdq_free; | |
535 | output [7:0] woq1_wdq_entry_free; | |
536 | output drq1_rdq_full; | |
537 | output drq1_empty; | |
538 | output [2:0] drq1_rd_index_picked; | |
539 | output [2:0] drq1_wr_index_picked; | |
540 | output [2:0] drq1_wr_id_picked; | |
541 | output [15:0] drq1_pd_mode_rd_incr; | |
542 | output [15:0] drq1_pd_mode_rd_decr; | |
543 | output [15:0] drq1_pd_mode_wr_incr; | |
544 | output woq1_wdq_rd; | |
545 | output drq1_rd_req; | |
546 | output drq1_wr_req; | |
547 | ||
548 | output [15:0] woq_err_pdm_wr_incr; | |
549 | output [15:0] woq_err_pdm_wr_decr; | |
550 | ||
551 | input drif1_raw_hazard; | |
552 | input l2if1_rd_req; | |
553 | input l2if1_wr_req; | |
554 | input [2:0] drif1_cpu_wr_addr; | |
555 | input [3:0] l2if1_wdq_in_cntr; // incremented by l2if when all data for a write is in wdq | |
556 | input l2b1_rd_rank_adr; | |
557 | input [2:0] l2b1_rd_dimm_adr; | |
558 | input [2:0] l2b1_rd_bank_adr; | |
559 | input l2b1_rd_addr_err; | |
560 | input l2b1_rd_addr_par; | |
561 | input l2b1_wr_rank_adr; | |
562 | input [2:0] l2b1_wr_dimm_adr; | |
563 | input [2:0] l2b1_wr_bank_adr; | |
564 | input l2b1_wr_addr_err; | |
565 | input l2b1_wr_addr_par; | |
566 | input [7:0] rdpctl_drq1_clear_ent; | |
567 | input [7:0] drif_drq1_clear_ent; | |
568 | input [7:0] drif1_rd_entry_picked; | |
569 | ||
570 | input [2:0] drif_wr_entry_picked; | |
571 | input drif_mcu_state_1; | |
572 | input drif_mcu_state_2; | |
573 | input drif_mcu_state_3; | |
574 | input drif_mcu_state_4; | |
575 | input drif_mcu_state_5; | |
576 | input drif_mcu_state_6; | |
577 | input drif_init; | |
578 | input drif_init_mcu_done; | |
579 | input drif_cmd_picked; | |
580 | input drif_blk_new_openbank; | |
581 | input [3:0] drif_refresh_rank; | |
582 | input drif_rd_picked; | |
583 | input drif_wr_picked; | |
584 | input drif_eight_bank_mode; | |
585 | input drif_stacked_dimm; | |
586 | input drif_sync_frame_req_l; | |
587 | input drif_sync_frame_req_early3_l; | |
588 | input drif_single_channel_mode; | |
589 | input drif_pd_mode_pending; | |
590 | input drif_err_fifo_empty; | |
591 | input [15:0] pdmc_rank_avail; | |
592 | input [7:0] drif_dimm_rd_available; | |
593 | input [7:0] drif_dimm_wr_available; | |
594 | input drif_wr_bc_stall; | |
595 | input drif_hw_selfrsh; | |
596 | ||
597 | input fbdic_l0_state; | |
598 | input fbdic_chnl_reset_error_mode; | |
599 | input [1:0] drif_woq_free; | |
600 | input fbdic_clear_wrq_ent; | |
601 | input fbdic_scr_frame_req_d4; | |
602 | input fbdic_error_mode; | |
603 | ||
604 | input l1clk; | |
605 | input scan_in; | |
606 | output scan_out; | |
607 | input tcu_aclk; | |
608 | input tcu_bclk; | |
609 | input tcu_scan_en; | |
610 | ||
611 | mcu_drq_ctl drq0 ( | |
612 | .scan_in(drq0_scanin), | |
613 | .scan_out(drq0_scanout), | |
614 | .l1clk(l1clk), | |
615 | .l2if_rd_req(l2if0_rd_req), | |
616 | .l2if_wr_req(l2if0_wr_req), | |
617 | .drq_cpu_wr_addr(drif0_cpu_wr_addr[2:0]), | |
618 | .l2if_wdq_in_cntr(l2if0_wdq_in_cntr[3:0]), | |
619 | .l2b_rank_rd_adr(l2b0_rd_rank_adr), | |
620 | .l2b_dimm_rd_adr(l2b0_rd_dimm_adr[2:0]), | |
621 | .l2b_bank_rd_adr(l2b0_rd_bank_adr[2:0]), | |
622 | .l2b_addr_rd_err(l2b0_rd_addr_err), | |
623 | .l2b_addr_rd_par(l2b0_rd_addr_par), | |
624 | .l2b_rank_wr_adr(l2b0_wr_rank_adr), | |
625 | .l2b_dimm_wr_adr(l2b0_wr_dimm_adr[2:0]), | |
626 | .l2b_bank_wr_adr(l2b0_wr_bank_adr[2:0]), | |
627 | .l2b_addr_wr_err(l2b0_wr_addr_err), | |
628 | .l2b_addr_wr_par(l2b0_wr_addr_par), | |
629 | .rdpctl_drq_clear_ent(rdpctl_drq0_clear_ent[7:0]), | |
630 | .woq_wrq_clear_ent(woq0_wrq_clear_ent[7:0]), | |
631 | .drif_drq_clear_ent(drif_drq0_clear_ent[7:0]), | |
632 | .drq_rd_adr_queue7_en(drq0_rd_adr_queue7_en), | |
633 | .drq_rd_adr_queue6_en(drq0_rd_adr_queue6_en), | |
634 | .drq_rd_adr_queue5_en(drq0_rd_adr_queue5_en), | |
635 | .drq_rd_adr_queue4_en(drq0_rd_adr_queue4_en), | |
636 | .drq_rd_adr_queue3_en(drq0_rd_adr_queue3_en), | |
637 | .drq_rd_adr_queue2_en(drq0_rd_adr_queue2_en), | |
638 | .drq_rd_adr_queue1_en(drq0_rd_adr_queue1_en), | |
639 | .drq_rd_adr_queue0_en(drq0_rd_adr_queue0_en), | |
640 | .drq_rd_adr_queue_sel(drq0_rd_adr_queue_sel[7:0]), | |
641 | .drq_wr_adr_queue7_en(drq0_wr_adr_queue7_en), | |
642 | .drq_wr_adr_queue6_en(drq0_wr_adr_queue6_en), | |
643 | .drq_wr_adr_queue5_en(drq0_wr_adr_queue5_en), | |
644 | .drq_wr_adr_queue4_en(drq0_wr_adr_queue4_en), | |
645 | .drq_wr_adr_queue3_en(drq0_wr_adr_queue3_en), | |
646 | .drq_wr_adr_queue2_en(drq0_wr_adr_queue2_en), | |
647 | .drq_wr_adr_queue1_en(drq0_wr_adr_queue1_en), | |
648 | .drq_wr_adr_queue0_en(drq0_wr_adr_queue0_en), | |
649 | .drq_req_rdwr_addr_sel(drq0_req_rdwr_addr_sel), | |
650 | .drif_rd_entry_picked(drif0_rd_entry_picked[7:0]), | |
651 | .drif_wr_entry_picked(8'h0), | |
652 | .drq_rdbuf_valids(drq0_rdbuf_valids[7:0]), | |
653 | .drq_wrbuf_valids(drq0_wrbuf_valids[7:0]), | |
654 | .drq_pending_wr_req(drq0_pending_wr_req[7:0]), | |
655 | .drq_read_queue_cnt(drq0_read_queue_cnt[3:0]), | |
656 | .drq_write_queue_cnt(drq0_write_queue_cnt[3:0]), | |
657 | .drq_rd_entry0_val(drq0_rd_entry0_val[15:0]), | |
658 | .drq_rd_entry1_val(drq0_rd_entry1_val[15:0]), | |
659 | .drq_rd_entry2_val(drq0_rd_entry2_val[15:0]), | |
660 | .drq_rd_entry3_val(drq0_rd_entry3_val[15:0]), | |
661 | .drq_rd_entry4_val(drq0_rd_entry4_val[15:0]), | |
662 | .drq_rd_entry5_val(drq0_rd_entry5_val[15:0]), | |
663 | .drq_rd_entry6_val(drq0_rd_entry6_val[15:0]), | |
664 | .drq_rd_entry7_val(drq0_rd_entry7_val[15:0]), | |
665 | .drq_rd_bank_val(drq0_rd_bank_val[15:0]), | |
666 | .drq_rd_entry0_rank(drq0_rd_entry0_rank), | |
667 | .drq_rd_entry1_rank(drq0_rd_entry1_rank), | |
668 | .drq_rd_entry2_rank(drq0_rd_entry2_rank), | |
669 | .drq_rd_entry3_rank(drq0_rd_entry3_rank), | |
670 | .drq_rd_entry4_rank(drq0_rd_entry4_rank), | |
671 | .drq_rd_entry5_rank(drq0_rd_entry5_rank), | |
672 | .drq_rd_entry6_rank(drq0_rd_entry6_rank), | |
673 | .drq_rd_entry7_rank(drq0_rd_entry7_rank), | |
674 | .drq_wr_entry0_rank(drq0_wr_entry0_rank), | |
675 | .drq_wr_entry1_rank(drq0_wr_entry1_rank), | |
676 | .drq_wr_entry2_rank(drq0_wr_entry2_rank), | |
677 | .drq_wr_entry3_rank(drq0_wr_entry3_rank), | |
678 | .drq_wr_entry4_rank(drq0_wr_entry4_rank), | |
679 | .drq_wr_entry5_rank(drq0_wr_entry5_rank), | |
680 | .drq_wr_entry6_rank(drq0_wr_entry6_rank), | |
681 | .drq_wr_entry7_rank(drq0_wr_entry7_rank), | |
682 | .drq_rd_entry0_dimm(drq0_rd_entry0_dimm[2:0]), | |
683 | .drq_rd_entry1_dimm(drq0_rd_entry1_dimm[2:0]), | |
684 | .drq_rd_entry2_dimm(drq0_rd_entry2_dimm[2:0]), | |
685 | .drq_rd_entry3_dimm(drq0_rd_entry3_dimm[2:0]), | |
686 | .drq_rd_entry4_dimm(drq0_rd_entry4_dimm[2:0]), | |
687 | .drq_rd_entry5_dimm(drq0_rd_entry5_dimm[2:0]), | |
688 | .drq_rd_entry6_dimm(drq0_rd_entry6_dimm[2:0]), | |
689 | .drq_rd_entry7_dimm(drq0_rd_entry7_dimm[2:0]), | |
690 | .drq_wr_entry0_dimm(drq0_wr_entry0_dimm[2:0]), | |
691 | .drq_wr_entry1_dimm(drq0_wr_entry1_dimm[2:0]), | |
692 | .drq_wr_entry2_dimm(drq0_wr_entry2_dimm[2:0]), | |
693 | .drq_wr_entry3_dimm(drq0_wr_entry3_dimm[2:0]), | |
694 | .drq_wr_entry4_dimm(drq0_wr_entry4_dimm[2:0]), | |
695 | .drq_wr_entry5_dimm(drq0_wr_entry5_dimm[2:0]), | |
696 | .drq_wr_entry6_dimm(drq0_wr_entry6_dimm[2:0]), | |
697 | .drq_wr_entry7_dimm(drq0_wr_entry7_dimm[2:0]), | |
698 | .drq_wr_queue_ent0(drq0_wr_queue_ent0[14:0]), | |
699 | .drq_wr_queue_ent1(drq0_wr_queue_ent1[14:0]), | |
700 | .drq_wr_queue_ent2(drq0_wr_queue_ent2[14:0]), | |
701 | .drq_wr_queue_ent3(drq0_wr_queue_ent3[14:0]), | |
702 | .drq_wr_queue_ent4(drq0_wr_queue_ent4[14:0]), | |
703 | .drq_wr_queue_ent5(drq0_wr_queue_ent5[14:0]), | |
704 | .drq_wr_queue_ent6(drq0_wr_queue_ent6[14:0]), | |
705 | .drq_wr_queue_ent7(drq0_wr_queue_ent7[14:0]), | |
706 | .drq_wdq_valid(drq0_wdq_valid[7:0]), | |
707 | .woq_wr_queue_clear(woq0_wr_queue_clear[7:0]), | |
708 | .woq_wr_entry_picked(woq0_wr_entry_picked[7:0]), | |
709 | .drq_rd_addr_picked(drq0_rd_addr_picked[9:0]), | |
710 | .drq_rdq_free(drq0_rdq_free), | |
711 | .drq_rdq_full(drq0_rdq_full), | |
712 | .drq_empty(drq0_empty), | |
713 | .drq_rd_index_picked(drq0_rd_index_picked[2:0]), | |
714 | .drq_wr_index_picked(drq0_wr_index_picked[2:0]), | |
715 | .drq_wr_id_picked(drq0_wr_id_picked[2:0]), | |
716 | .drif_raw_hazard(drif0_raw_hazard), | |
717 | .drq_pd_mode_rd_incr(drq0_pd_mode_rd_incr[15:0]), | |
718 | .drq_pd_mode_rd_decr(drq0_pd_mode_rd_decr[15:0]), | |
719 | .drq_pd_mode_wr_incr(drq0_pd_mode_wr_incr[15:0]), | |
720 | .drq_rd_req(drq0_rd_req), | |
721 | .drq_wr_req(drq0_wr_req), | |
722 | .drif_init(drif_init), | |
723 | .drif_init_mcu_done(drif_init_mcu_done), | |
724 | .drif_mcu_state_1(drif_mcu_state_1), | |
725 | .drif_mcu_state_2(drif_mcu_state_2), | |
726 | .drif_mcu_state_4(drif_mcu_state_4), | |
727 | .drif_cmd_picked(drif_cmd_picked), | |
728 | .drif_blk_new_openbank(drif_blk_new_openbank), | |
729 | .pdmc_rank_avail(pdmc_rank_avail[15:0]), | |
730 | .drif_dimm_rd_available(drif_dimm_rd_available[7:0]), | |
731 | .drif_refresh_rank(drif_refresh_rank[3:0]), | |
732 | .drif_rd_picked(drif_rd_picked), | |
733 | .drif_wr_picked(drif_wr_picked), | |
734 | .drif_eight_bank_mode(drif_eight_bank_mode), | |
735 | .drif_stacked_dimm(drif_stacked_dimm), | |
736 | .tcu_aclk(tcu_aclk), | |
737 | .tcu_bclk(tcu_bclk), | |
738 | .tcu_scan_en(tcu_scan_en) | |
739 | ); | |
740 | ||
741 | mcu_drq_ctl drq1 ( | |
742 | .scan_in(drq1_scanin), | |
743 | .scan_out(drq1_scanout), | |
744 | .l1clk(l1clk), | |
745 | .l2if_rd_req(l2if1_rd_req), | |
746 | .l2if_wr_req(l2if1_wr_req), | |
747 | .drq_cpu_wr_addr(drif1_cpu_wr_addr[2:0]), | |
748 | .l2if_wdq_in_cntr(l2if1_wdq_in_cntr[3:0]), | |
749 | .l2b_rank_rd_adr(l2b1_rd_rank_adr), | |
750 | .l2b_dimm_rd_adr(l2b1_rd_dimm_adr[2:0]), | |
751 | .l2b_bank_rd_adr(l2b1_rd_bank_adr[2:0]), | |
752 | .l2b_addr_rd_err(l2b1_rd_addr_err), | |
753 | .l2b_addr_rd_par(l2b1_rd_addr_par), | |
754 | .l2b_rank_wr_adr(l2b1_wr_rank_adr), | |
755 | .l2b_dimm_wr_adr(l2b1_wr_dimm_adr[2:0]), | |
756 | .l2b_bank_wr_adr(l2b1_wr_bank_adr[2:0]), | |
757 | .l2b_addr_wr_err(l2b1_wr_addr_err), | |
758 | .l2b_addr_wr_par(l2b1_wr_addr_par), | |
759 | .rdpctl_drq_clear_ent(rdpctl_drq1_clear_ent[7:0]), | |
760 | .woq_wrq_clear_ent(woq1_wrq_clear_ent[7:0]), | |
761 | .drif_drq_clear_ent(drif_drq1_clear_ent[7:0]), | |
762 | .drq_rd_adr_queue7_en(drq1_rd_adr_queue7_en), | |
763 | .drq_rd_adr_queue6_en(drq1_rd_adr_queue6_en), | |
764 | .drq_rd_adr_queue5_en(drq1_rd_adr_queue5_en), | |
765 | .drq_rd_adr_queue4_en(drq1_rd_adr_queue4_en), | |
766 | .drq_rd_adr_queue3_en(drq1_rd_adr_queue3_en), | |
767 | .drq_rd_adr_queue2_en(drq1_rd_adr_queue2_en), | |
768 | .drq_rd_adr_queue1_en(drq1_rd_adr_queue1_en), | |
769 | .drq_rd_adr_queue0_en(drq1_rd_adr_queue0_en), | |
770 | .drq_rd_adr_queue_sel(drq1_rd_adr_queue_sel[7:0]), | |
771 | .drq_wr_adr_queue7_en(drq1_wr_adr_queue7_en), | |
772 | .drq_wr_adr_queue6_en(drq1_wr_adr_queue6_en), | |
773 | .drq_wr_adr_queue5_en(drq1_wr_adr_queue5_en), | |
774 | .drq_wr_adr_queue4_en(drq1_wr_adr_queue4_en), | |
775 | .drq_wr_adr_queue3_en(drq1_wr_adr_queue3_en), | |
776 | .drq_wr_adr_queue2_en(drq1_wr_adr_queue2_en), | |
777 | .drq_wr_adr_queue1_en(drq1_wr_adr_queue1_en), | |
778 | .drq_wr_adr_queue0_en(drq1_wr_adr_queue0_en), | |
779 | .drq_req_rdwr_addr_sel(drq1_req_rdwr_addr_sel), | |
780 | .drif_rd_entry_picked(drif1_rd_entry_picked[7:0]), | |
781 | .drif_wr_entry_picked(8'h0), | |
782 | .drq_rdbuf_valids(drq1_rdbuf_valids[7:0]), | |
783 | .drq_wrbuf_valids(drq1_wrbuf_valids[7:0]), | |
784 | .drq_pending_wr_req(drq1_pending_wr_req[7:0]), | |
785 | .drq_read_queue_cnt(drq1_read_queue_cnt[3:0]), | |
786 | .drq_write_queue_cnt(drq1_write_queue_cnt[3:0]), | |
787 | .drq_rd_entry0_val(drq1_rd_entry0_val[15:0]), | |
788 | .drq_rd_entry1_val(drq1_rd_entry1_val[15:0]), | |
789 | .drq_rd_entry2_val(drq1_rd_entry2_val[15:0]), | |
790 | .drq_rd_entry3_val(drq1_rd_entry3_val[15:0]), | |
791 | .drq_rd_entry4_val(drq1_rd_entry4_val[15:0]), | |
792 | .drq_rd_entry5_val(drq1_rd_entry5_val[15:0]), | |
793 | .drq_rd_entry6_val(drq1_rd_entry6_val[15:0]), | |
794 | .drq_rd_entry7_val(drq1_rd_entry7_val[15:0]), | |
795 | .drq_rd_bank_val(drq1_rd_bank_val[15:0]), | |
796 | .drq_rd_entry0_rank(drq1_rd_entry0_rank), | |
797 | .drq_rd_entry1_rank(drq1_rd_entry1_rank), | |
798 | .drq_rd_entry2_rank(drq1_rd_entry2_rank), | |
799 | .drq_rd_entry3_rank(drq1_rd_entry3_rank), | |
800 | .drq_rd_entry4_rank(drq1_rd_entry4_rank), | |
801 | .drq_rd_entry5_rank(drq1_rd_entry5_rank), | |
802 | .drq_rd_entry6_rank(drq1_rd_entry6_rank), | |
803 | .drq_rd_entry7_rank(drq1_rd_entry7_rank), | |
804 | .drq_wr_entry0_rank(drq1_wr_entry0_rank), | |
805 | .drq_wr_entry1_rank(drq1_wr_entry1_rank), | |
806 | .drq_wr_entry2_rank(drq1_wr_entry2_rank), | |
807 | .drq_wr_entry3_rank(drq1_wr_entry3_rank), | |
808 | .drq_wr_entry4_rank(drq1_wr_entry4_rank), | |
809 | .drq_wr_entry5_rank(drq1_wr_entry5_rank), | |
810 | .drq_wr_entry6_rank(drq1_wr_entry6_rank), | |
811 | .drq_wr_entry7_rank(drq1_wr_entry7_rank), | |
812 | .drq_rd_entry0_dimm(drq1_rd_entry0_dimm[2:0]), | |
813 | .drq_rd_entry1_dimm(drq1_rd_entry1_dimm[2:0]), | |
814 | .drq_rd_entry2_dimm(drq1_rd_entry2_dimm[2:0]), | |
815 | .drq_rd_entry3_dimm(drq1_rd_entry3_dimm[2:0]), | |
816 | .drq_rd_entry4_dimm(drq1_rd_entry4_dimm[2:0]), | |
817 | .drq_rd_entry5_dimm(drq1_rd_entry5_dimm[2:0]), | |
818 | .drq_rd_entry6_dimm(drq1_rd_entry6_dimm[2:0]), | |
819 | .drq_rd_entry7_dimm(drq1_rd_entry7_dimm[2:0]), | |
820 | .drq_wr_entry0_dimm(drq1_wr_entry0_dimm[2:0]), | |
821 | .drq_wr_entry1_dimm(drq1_wr_entry1_dimm[2:0]), | |
822 | .drq_wr_entry2_dimm(drq1_wr_entry2_dimm[2:0]), | |
823 | .drq_wr_entry3_dimm(drq1_wr_entry3_dimm[2:0]), | |
824 | .drq_wr_entry4_dimm(drq1_wr_entry4_dimm[2:0]), | |
825 | .drq_wr_entry5_dimm(drq1_wr_entry5_dimm[2:0]), | |
826 | .drq_wr_entry6_dimm(drq1_wr_entry6_dimm[2:0]), | |
827 | .drq_wr_entry7_dimm(drq1_wr_entry7_dimm[2:0]), | |
828 | .drq_wr_queue_ent0(drq1_wr_queue_ent0[14:0]), | |
829 | .drq_wr_queue_ent1(drq1_wr_queue_ent1[14:0]), | |
830 | .drq_wr_queue_ent2(drq1_wr_queue_ent2[14:0]), | |
831 | .drq_wr_queue_ent3(drq1_wr_queue_ent3[14:0]), | |
832 | .drq_wr_queue_ent4(drq1_wr_queue_ent4[14:0]), | |
833 | .drq_wr_queue_ent5(drq1_wr_queue_ent5[14:0]), | |
834 | .drq_wr_queue_ent6(drq1_wr_queue_ent6[14:0]), | |
835 | .drq_wr_queue_ent7(drq1_wr_queue_ent7[14:0]), | |
836 | .drq_wdq_valid(drq1_wdq_valid[7:0]), | |
837 | .woq_wr_queue_clear(woq1_wr_queue_clear[7:0]), | |
838 | .woq_wr_entry_picked(woq1_wr_entry_picked[7:0]), | |
839 | .drq_rd_addr_picked(drq1_rd_addr_picked[9:0]), | |
840 | .drq_rdq_free(drq1_rdq_free), | |
841 | .drq_rdq_full(drq1_rdq_full), | |
842 | .drq_empty(drq1_empty), | |
843 | .drq_rd_index_picked(drq1_rd_index_picked[2:0]), | |
844 | .drq_wr_index_picked(drq1_wr_index_picked[2:0]), | |
845 | .drq_wr_id_picked(drq1_wr_id_picked[2:0]), | |
846 | .drif_raw_hazard(drif1_raw_hazard), | |
847 | .drq_pd_mode_rd_incr(drq1_pd_mode_rd_incr[15:0]), | |
848 | .drq_pd_mode_rd_decr(drq1_pd_mode_rd_decr[15:0]), | |
849 | .drq_pd_mode_wr_incr(drq1_pd_mode_wr_incr[15:0]), | |
850 | .drq_rd_req(drq1_rd_req), | |
851 | .drq_wr_req(drq1_wr_req), | |
852 | .drif_init(drif_init), | |
853 | .drif_init_mcu_done(drif_init_mcu_done), | |
854 | .drif_mcu_state_1(drif_mcu_state_1), | |
855 | .drif_mcu_state_2(drif_mcu_state_2), | |
856 | .drif_mcu_state_4(drif_mcu_state_4), | |
857 | .drif_cmd_picked(drif_cmd_picked), | |
858 | .drif_blk_new_openbank(drif_blk_new_openbank), | |
859 | .pdmc_rank_avail(pdmc_rank_avail[15:0]), | |
860 | .drif_dimm_rd_available(drif_dimm_rd_available[7:0]), | |
861 | .drif_refresh_rank(drif_refresh_rank[3:0]), | |
862 | .drif_rd_picked(drif_rd_picked), | |
863 | .drif_wr_picked(drif_wr_picked), | |
864 | .drif_eight_bank_mode(drif_eight_bank_mode), | |
865 | .drif_stacked_dimm(drif_stacked_dimm), | |
866 | .tcu_aclk(tcu_aclk), | |
867 | .tcu_bclk(tcu_bclk), | |
868 | .tcu_scan_en(tcu_scan_en) | |
869 | ); | |
870 | ||
871 | mcu_woq_ctl woq ( | |
872 | .scan_in(woq_scanin), | |
873 | .scan_out(woq_scanout), | |
874 | .l1clk(l1clk), | |
875 | .woq0_wdq_rd(woq0_wdq_rd), | |
876 | .woq0_wr_queue_clear(woq0_wr_queue_clear[7:0]), | |
877 | .woq1_wdq_rd(woq1_wdq_rd), | |
878 | .woq1_wr_queue_clear(woq1_wr_queue_clear[7:0]), | |
879 | .woq_wdq_radr(woq_wdq_radr[4:0]), | |
880 | .woq_wadr_parity(woq_wadr_parity), | |
881 | .woq_io_wdata_sel(woq_io_wdata_sel[1:0]), | |
882 | .woq_entry0(woq_entry0[15:0]), | |
883 | .woq_entry1(woq_entry1[15:0]), | |
884 | .woq_entry_valid(woq_entry_valid[2:0]), | |
885 | .woq_entry0_val(woq_entry0_val[15:0]), | |
886 | .woq_entry1_val(woq_entry1_val[15:0]), | |
887 | .woq_wr_bank_val(woq_wr_bank_val[15:0]), | |
888 | .woq_wr_addr_picked(woq_wr_addr_picked[9:0]), | |
889 | .woq_wr1_addr_picked(woq_wr1_addr_picked[9:0]), | |
890 | .woq_wr2_addr_picked(woq_wr2_addr_picked[9:0]), | |
891 | .woq_wr_index_picked(woq_wr_index_picked[2:0]), | |
892 | .woq_wr1_index_picked(woq_wr1_index_picked[2:0]), | |
893 | .woq_wr2_index_picked(woq_wr2_index_picked[2:0]), | |
894 | .woq_wr_wdq_index_picked(woq_wr_wdq_index_picked[2:0]), | |
895 | .woq_wr1_wdq_index_picked(woq_wr1_wdq_index_picked[2:0]), | |
896 | .woq_wr2_wdq_index_picked(woq_wr2_wdq_index_picked[2:0]), | |
897 | .woq_wr_adr_queue_sel(woq_wr_adr_queue_sel[7:0]), | |
898 | .woq_wr1_adr_queue_sel(woq_wr1_adr_queue_sel[7:0]), | |
899 | .woq_wr2_adr_queue_sel(woq_wr2_adr_queue_sel[7:0]), | |
900 | .woq0_wr_entry_picked(woq0_wr_entry_picked[7:0]), | |
901 | .woq1_wr_entry_picked(woq1_wr_entry_picked[7:0]), | |
902 | .woq1_wr_picked(woq1_wr_picked[2:0]), | |
903 | .woq_wdata_wsn(woq_wdata_wsn), | |
904 | .woq_err_st_wait_free(woq_err_st_wait_free), | |
905 | .woq_err_fifo_empty(woq_err_fifo_empty), | |
906 | .woq_wr_req_out(woq_wr_req_out[1:0]), | |
907 | .woq_pd_mode_wr_decr(woq_pd_mode_wr_decr[15:0]), | |
908 | .woq0_wdq_entry_free(woq0_wdq_entry_free[7:0]), | |
909 | .woq1_wdq_entry_free(woq1_wdq_entry_free[7:0]), | |
910 | .woq0_wrq_clear_ent(woq0_wrq_clear_ent[7:0]), | |
911 | .woq1_wrq_clear_ent(woq1_wrq_clear_ent[7:0]), | |
912 | .woq_owr_empty(woq_owr_empty), | |
913 | .woq_empty(woq_empty), | |
914 | .woq_wr_error_mode(woq_wr_error_mode), | |
915 | .woq_wdata_send(woq_wdata_send), | |
916 | .woq_err_pdm_wr_incr(woq_err_pdm_wr_incr[15:0]), | |
917 | .woq_err_pdm_wr_decr(woq_err_pdm_wr_decr[15:0]), | |
918 | .drq0_wr_queue_ent0(drq0_wr_queue_ent0[14:0]), | |
919 | .drq0_wr_queue_ent1(drq0_wr_queue_ent1[14:0]), | |
920 | .drq0_wr_queue_ent2(drq0_wr_queue_ent2[14:0]), | |
921 | .drq0_wr_queue_ent3(drq0_wr_queue_ent3[14:0]), | |
922 | .drq0_wr_queue_ent4(drq0_wr_queue_ent4[14:0]), | |
923 | .drq0_wr_queue_ent5(drq0_wr_queue_ent5[14:0]), | |
924 | .drq0_wr_queue_ent6(drq0_wr_queue_ent6[14:0]), | |
925 | .drq0_wr_queue_ent7(drq0_wr_queue_ent7[14:0]), | |
926 | .drq0_wdq_valid(drq0_wdq_valid[7:0]), | |
927 | .drq1_wr_queue_ent0(drq1_wr_queue_ent0[14:0]), | |
928 | .drq1_wr_queue_ent1(drq1_wr_queue_ent1[14:0]), | |
929 | .drq1_wr_queue_ent2(drq1_wr_queue_ent2[14:0]), | |
930 | .drq1_wr_queue_ent3(drq1_wr_queue_ent3[14:0]), | |
931 | .drq1_wr_queue_ent4(drq1_wr_queue_ent4[14:0]), | |
932 | .drq1_wr_queue_ent5(drq1_wr_queue_ent5[14:0]), | |
933 | .drq1_wr_queue_ent6(drq1_wr_queue_ent6[14:0]), | |
934 | .drq1_wr_queue_ent7(drq1_wr_queue_ent7[14:0]), | |
935 | .drq1_wdq_valid(drq1_wdq_valid[7:0]), | |
936 | .drif_wr_entry_picked(drif_wr_entry_picked[2:0]), | |
937 | .drif_init(drif_init), | |
938 | .drif_init_mcu_done(drif_init_mcu_done), | |
939 | .drif_mcu_state_1(drif_mcu_state_1), | |
940 | .drif_mcu_state_2(drif_mcu_state_2), | |
941 | .drif_mcu_state_3(drif_mcu_state_3), | |
942 | .drif_mcu_state_4(drif_mcu_state_4), | |
943 | .drif_mcu_state_5(drif_mcu_state_5), | |
944 | .drif_mcu_state_6(drif_mcu_state_6), | |
945 | .drif_sync_frame_req_l(drif_sync_frame_req_l), | |
946 | .drif_sync_frame_req_early3_l(drif_sync_frame_req_early3_l), | |
947 | .drif_single_channel_mode(drif_single_channel_mode), | |
948 | .drif_pd_mode_pending(drif_pd_mode_pending), | |
949 | .drif_eight_bank_mode(drif_eight_bank_mode), | |
950 | .drif_stacked_dimm(drif_stacked_dimm), | |
951 | .drif_blk_new_openbank(drif_blk_new_openbank), | |
952 | .drif_err_fifo_empty(drif_err_fifo_empty), | |
953 | .drif_wr_bc_stall(drif_wr_bc_stall), | |
954 | .drif_refresh_rank(drif_refresh_rank[3:0]), | |
955 | .drif_hw_selfrsh(drif_hw_selfrsh), | |
956 | .fbdic_l0_state(fbdic_l0_state), | |
957 | .fbdic_chnl_reset_error_mode(fbdic_chnl_reset_error_mode), | |
958 | .drif_woq_free(drif_woq_free[1:0]), | |
959 | .fbdic_clear_wrq_ent(fbdic_clear_wrq_ent), | |
960 | .fbdic_scr_frame_req_d4(fbdic_scr_frame_req_d4), | |
961 | .fbdic_error_mode(fbdic_error_mode), | |
962 | .pdmc_rank_avail(pdmc_rank_avail[15:0]), | |
963 | .drif_dimm_wr_available(drif_dimm_wr_available[7:0]), | |
964 | .tcu_aclk(tcu_aclk), | |
965 | .tcu_bclk(tcu_bclk), | |
966 | .tcu_scan_en(tcu_scan_en) | |
967 | ); | |
968 | ||
969 | // fixscan start: | |
970 | assign drq0_scanin = scan_in ; | |
971 | assign drq1_scanin = drq0_scanout ; | |
972 | assign woq_scanin = drq1_scanout ; | |
973 | assign scan_out = woq_scanout ; | |
974 | // fixscan end: | |
975 | endmodule | |
976 | ||
977 | ||
978 | ||
979 | // any PARAMS parms go into naming of macro | |
980 | ||
981 | module mcu_reqq_ctl_msff_ctl_macro__width_6 ( | |
982 | din, | |
983 | l1clk, | |
984 | scan_in, | |
985 | siclk, | |
986 | soclk, | |
987 | dout, | |
988 | scan_out); | |
989 | wire [5:0] fdin; | |
990 | wire [4:0] so; | |
991 | ||
992 | input [5:0] din; | |
993 | input l1clk; | |
994 | input scan_in; | |
995 | ||
996 | ||
997 | input siclk; | |
998 | input soclk; | |
999 | ||
1000 | output [5:0] dout; | |
1001 | output scan_out; | |
1002 | assign fdin[5:0] = din[5:0]; | |
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | dff #(6) d0_0 ( | |
1010 | .l1clk(l1clk), | |
1011 | .siclk(siclk), | |
1012 | .soclk(soclk), | |
1013 | .d(fdin[5:0]), | |
1014 | .si({scan_in,so[4:0]}), | |
1015 | .so({so[4:0],scan_out}), | |
1016 | .q(dout[5:0]) | |
1017 | ); | |
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | endmodule | |
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | ||
1038 | ||
1039 | ||
1040 | ||
1041 | ||
1042 | ||
1043 | ||
1044 | // any PARAMS parms go into naming of macro | |
1045 | ||
1046 | module mcu_reqq_ctl_msff_ctl_macro__width_9 ( | |
1047 | din, | |
1048 | l1clk, | |
1049 | scan_in, | |
1050 | siclk, | |
1051 | soclk, | |
1052 | dout, | |
1053 | scan_out); | |
1054 | wire [8:0] fdin; | |
1055 | wire [7:0] so; | |
1056 | ||
1057 | input [8:0] din; | |
1058 | input l1clk; | |
1059 | input scan_in; | |
1060 | ||
1061 | ||
1062 | input siclk; | |
1063 | input soclk; | |
1064 | ||
1065 | output [8:0] dout; | |
1066 | output scan_out; | |
1067 | assign fdin[8:0] = din[8:0]; | |
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | dff #(9) d0_0 ( | |
1075 | .l1clk(l1clk), | |
1076 | .siclk(siclk), | |
1077 | .soclk(soclk), | |
1078 | .d(fdin[8:0]), | |
1079 | .si({scan_in,so[7:0]}), | |
1080 | .so({so[7:0],scan_out}), | |
1081 | .q(dout[8:0]) | |
1082 | ); | |
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | ||
1095 | endmodule | |
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | ||
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | // any PARAMS parms go into naming of macro | |
1110 | ||
1111 | module mcu_reqq_ctl_msff_ctl_macro__width_1 ( | |
1112 | din, | |
1113 | l1clk, | |
1114 | scan_in, | |
1115 | siclk, | |
1116 | soclk, | |
1117 | dout, | |
1118 | scan_out); | |
1119 | wire [0:0] fdin; | |
1120 | ||
1121 | input [0:0] din; | |
1122 | input l1clk; | |
1123 | input scan_in; | |
1124 | ||
1125 | ||
1126 | input siclk; | |
1127 | input soclk; | |
1128 | ||
1129 | output [0:0] dout; | |
1130 | output scan_out; | |
1131 | assign fdin[0:0] = din[0:0]; | |
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | dff #(1) d0_0 ( | |
1139 | .l1clk(l1clk), | |
1140 | .siclk(siclk), | |
1141 | .soclk(soclk), | |
1142 | .d(fdin[0:0]), | |
1143 | .si(scan_in), | |
1144 | .so(scan_out), | |
1145 | .q(dout[0:0]) | |
1146 | ); | |
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | endmodule | |
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | ||
1172 | ||
1173 | // any PARAMS parms go into naming of macro | |
1174 | ||
1175 | module mcu_reqq_ctl_msff_ctl_macro__width_8 ( | |
1176 | din, | |
1177 | l1clk, | |
1178 | scan_in, | |
1179 | siclk, | |
1180 | soclk, | |
1181 | dout, | |
1182 | scan_out); | |
1183 | wire [7:0] fdin; | |
1184 | wire [6:0] so; | |
1185 | ||
1186 | input [7:0] din; | |
1187 | input l1clk; | |
1188 | input scan_in; | |
1189 | ||
1190 | ||
1191 | input siclk; | |
1192 | input soclk; | |
1193 | ||
1194 | output [7:0] dout; | |
1195 | output scan_out; | |
1196 | assign fdin[7:0] = din[7:0]; | |
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | dff #(8) d0_0 ( | |
1204 | .l1clk(l1clk), | |
1205 | .siclk(siclk), | |
1206 | .soclk(soclk), | |
1207 | .d(fdin[7:0]), | |
1208 | .si({scan_in,so[6:0]}), | |
1209 | .so({so[6:0],scan_out}), | |
1210 | .q(dout[7:0]) | |
1211 | ); | |
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | ||
1223 | ||
1224 | endmodule | |
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | ||
1236 | ||
1237 | ||
1238 | // any PARAMS parms go into naming of macro | |
1239 | ||
1240 | module mcu_reqq_ctl_msff_ctl_macro__width_4 ( | |
1241 | din, | |
1242 | l1clk, | |
1243 | scan_in, | |
1244 | siclk, | |
1245 | soclk, | |
1246 | dout, | |
1247 | scan_out); | |
1248 | wire [3:0] fdin; | |
1249 | wire [2:0] so; | |
1250 | ||
1251 | input [3:0] din; | |
1252 | input l1clk; | |
1253 | input scan_in; | |
1254 | ||
1255 | ||
1256 | input siclk; | |
1257 | input soclk; | |
1258 | ||
1259 | output [3:0] dout; | |
1260 | output scan_out; | |
1261 | assign fdin[3:0] = din[3:0]; | |
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | dff #(4) d0_0 ( | |
1269 | .l1clk(l1clk), | |
1270 | .siclk(siclk), | |
1271 | .soclk(soclk), | |
1272 | .d(fdin[3:0]), | |
1273 | .si({scan_in,so[2:0]}), | |
1274 | .so({so[2:0],scan_out}), | |
1275 | .q(dout[3:0]) | |
1276 | ); | |
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | ||
1288 | ||
1289 | endmodule | |
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | // any PARAMS parms go into naming of macro | |
1304 | ||
1305 | module mcu_reqq_ctl_msff_ctl_macro__en_1__width_12 ( | |
1306 | din, | |
1307 | en, | |
1308 | l1clk, | |
1309 | scan_in, | |
1310 | siclk, | |
1311 | soclk, | |
1312 | dout, | |
1313 | scan_out); | |
1314 | wire [11:0] fdin; | |
1315 | wire [10:0] so; | |
1316 | ||
1317 | input [11:0] din; | |
1318 | input en; | |
1319 | input l1clk; | |
1320 | input scan_in; | |
1321 | ||
1322 | ||
1323 | input siclk; | |
1324 | input soclk; | |
1325 | ||
1326 | output [11:0] dout; | |
1327 | output scan_out; | |
1328 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | dff #(12) d0_0 ( | |
1336 | .l1clk(l1clk), | |
1337 | .siclk(siclk), | |
1338 | .soclk(soclk), | |
1339 | .d(fdin[11:0]), | |
1340 | .si({scan_in,so[10:0]}), | |
1341 | .so({so[10:0],scan_out}), | |
1342 | .q(dout[11:0]) | |
1343 | ); | |
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | endmodule | |
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | // any PARAMS parms go into naming of macro | |
1371 | ||
1372 | module mcu_reqq_ctl_msff_ctl_macro__en_1__width_15 ( | |
1373 | din, | |
1374 | en, | |
1375 | l1clk, | |
1376 | scan_in, | |
1377 | siclk, | |
1378 | soclk, | |
1379 | dout, | |
1380 | scan_out); | |
1381 | wire [14:0] fdin; | |
1382 | wire [13:0] so; | |
1383 | ||
1384 | input [14:0] din; | |
1385 | input en; | |
1386 | input l1clk; | |
1387 | input scan_in; | |
1388 | ||
1389 | ||
1390 | input siclk; | |
1391 | input soclk; | |
1392 | ||
1393 | output [14:0] dout; | |
1394 | output scan_out; | |
1395 | assign fdin[14:0] = (din[14:0] & {15{en}}) | (dout[14:0] & ~{15{en}}); | |
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | dff #(15) d0_0 ( | |
1403 | .l1clk(l1clk), | |
1404 | .siclk(siclk), | |
1405 | .soclk(soclk), | |
1406 | .d(fdin[14:0]), | |
1407 | .si({scan_in,so[13:0]}), | |
1408 | .so({so[13:0],scan_out}), | |
1409 | .q(dout[14:0]) | |
1410 | ); | |
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | endmodule | |
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | // any PARAMS parms go into naming of macro | |
1438 | ||
1439 | module mcu_reqq_ctl_msff_ctl_macro__en_1__width_4 ( | |
1440 | din, | |
1441 | en, | |
1442 | l1clk, | |
1443 | scan_in, | |
1444 | siclk, | |
1445 | soclk, | |
1446 | dout, | |
1447 | scan_out); | |
1448 | wire [3:0] fdin; | |
1449 | wire [2:0] so; | |
1450 | ||
1451 | input [3:0] din; | |
1452 | input en; | |
1453 | input l1clk; | |
1454 | input scan_in; | |
1455 | ||
1456 | ||
1457 | input siclk; | |
1458 | input soclk; | |
1459 | ||
1460 | output [3:0] dout; | |
1461 | output scan_out; | |
1462 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | dff #(4) d0_0 ( | |
1470 | .l1clk(l1clk), | |
1471 | .siclk(siclk), | |
1472 | .soclk(soclk), | |
1473 | .d(fdin[3:0]), | |
1474 | .si({scan_in,so[2:0]}), | |
1475 | .so({so[2:0],scan_out}), | |
1476 | .q(dout[3:0]) | |
1477 | ); | |
1478 | ||
1479 | ||
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ||
1489 | ||
1490 | endmodule | |
1491 | ||
1492 | ||
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | // any PARAMS parms go into naming of macro | |
1505 | ||
1506 | module mcu_reqq_ctl_msff_ctl_macro__width_16 ( | |
1507 | din, | |
1508 | l1clk, | |
1509 | scan_in, | |
1510 | siclk, | |
1511 | soclk, | |
1512 | dout, | |
1513 | scan_out); | |
1514 | wire [15:0] fdin; | |
1515 | wire [14:0] so; | |
1516 | ||
1517 | input [15:0] din; | |
1518 | input l1clk; | |
1519 | input scan_in; | |
1520 | ||
1521 | ||
1522 | input siclk; | |
1523 | input soclk; | |
1524 | ||
1525 | output [15:0] dout; | |
1526 | output scan_out; | |
1527 | assign fdin[15:0] = din[15:0]; | |
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | dff #(16) d0_0 ( | |
1535 | .l1clk(l1clk), | |
1536 | .siclk(siclk), | |
1537 | .soclk(soclk), | |
1538 | .d(fdin[15:0]), | |
1539 | .si({scan_in,so[14:0]}), | |
1540 | .so({so[14:0],scan_out}), | |
1541 | .q(dout[15:0]) | |
1542 | ); | |
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | endmodule | |
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | ||
1561 | // any PARAMS parms go into naming of macro | |
1562 | ||
1563 | module mcu_reqq_ctl_msff_ctl_macro__en_1 ( | |
1564 | din, | |
1565 | en, | |
1566 | l1clk, | |
1567 | scan_in, | |
1568 | siclk, | |
1569 | soclk, | |
1570 | dout, | |
1571 | scan_out); | |
1572 | wire [0:0] fdin; | |
1573 | ||
1574 | input [0:0] din; | |
1575 | input en; | |
1576 | input l1clk; | |
1577 | input scan_in; | |
1578 | ||
1579 | ||
1580 | input siclk; | |
1581 | input soclk; | |
1582 | ||
1583 | output [0:0] dout; | |
1584 | output scan_out; | |
1585 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1586 | ||
1587 | ||
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | dff #(1) d0_0 ( | |
1593 | .l1clk(l1clk), | |
1594 | .siclk(siclk), | |
1595 | .soclk(soclk), | |
1596 | .d(fdin[0:0]), | |
1597 | .si(scan_in), | |
1598 | .so(scan_out), | |
1599 | .q(dout[0:0]) | |
1600 | ); | |
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | ||
1612 | ||
1613 | endmodule | |
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 | ||
1623 | ||
1624 | ||
1625 | ||
1626 | ||
1627 | // any PARAMS parms go into naming of macro | |
1628 | ||
1629 | module mcu_reqq_ctl_msff_ctl_macro__en_1__width_3 ( | |
1630 | din, | |
1631 | en, | |
1632 | l1clk, | |
1633 | scan_in, | |
1634 | siclk, | |
1635 | soclk, | |
1636 | dout, | |
1637 | scan_out); | |
1638 | wire [2:0] fdin; | |
1639 | wire [1:0] so; | |
1640 | ||
1641 | input [2:0] din; | |
1642 | input en; | |
1643 | input l1clk; | |
1644 | input scan_in; | |
1645 | ||
1646 | ||
1647 | input siclk; | |
1648 | input soclk; | |
1649 | ||
1650 | output [2:0] dout; | |
1651 | output scan_out; | |
1652 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | dff #(3) d0_0 ( | |
1660 | .l1clk(l1clk), | |
1661 | .siclk(siclk), | |
1662 | .soclk(soclk), | |
1663 | .d(fdin[2:0]), | |
1664 | .si({scan_in,so[1:0]}), | |
1665 | .so({so[1:0],scan_out}), | |
1666 | .q(dout[2:0]) | |
1667 | ); | |
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | endmodule | |
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | ||
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | // any PARAMS parms go into naming of macro | |
1695 | ||
1696 | module mcu_reqq_ctl_msff_ctl_macro__width_5 ( | |
1697 | din, | |
1698 | l1clk, | |
1699 | scan_in, | |
1700 | siclk, | |
1701 | soclk, | |
1702 | dout, | |
1703 | scan_out); | |
1704 | wire [4:0] fdin; | |
1705 | wire [3:0] so; | |
1706 | ||
1707 | input [4:0] din; | |
1708 | input l1clk; | |
1709 | input scan_in; | |
1710 | ||
1711 | ||
1712 | input siclk; | |
1713 | input soclk; | |
1714 | ||
1715 | output [4:0] dout; | |
1716 | output scan_out; | |
1717 | assign fdin[4:0] = din[4:0]; | |
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | ||
1723 | ||
1724 | dff #(5) d0_0 ( | |
1725 | .l1clk(l1clk), | |
1726 | .siclk(siclk), | |
1727 | .soclk(soclk), | |
1728 | .d(fdin[4:0]), | |
1729 | .si({scan_in,so[3:0]}), | |
1730 | .so({so[3:0],scan_out}), | |
1731 | .q(dout[4:0]) | |
1732 | ); | |
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | ||
1743 | ||
1744 | ||
1745 | endmodule | |
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | // any PARAMS parms go into naming of macro | |
1760 | ||
1761 | module mcu_reqq_ctl_msff_ctl_macro__en_1__width_16 ( | |
1762 | din, | |
1763 | en, | |
1764 | l1clk, | |
1765 | scan_in, | |
1766 | siclk, | |
1767 | soclk, | |
1768 | dout, | |
1769 | scan_out); | |
1770 | wire [15:0] fdin; | |
1771 | wire [14:0] so; | |
1772 | ||
1773 | input [15:0] din; | |
1774 | input en; | |
1775 | input l1clk; | |
1776 | input scan_in; | |
1777 | ||
1778 | ||
1779 | input siclk; | |
1780 | input soclk; | |
1781 | ||
1782 | output [15:0] dout; | |
1783 | output scan_out; | |
1784 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
1785 | ||
1786 | ||
1787 | ||
1788 | ||
1789 | ||
1790 | ||
1791 | dff #(16) d0_0 ( | |
1792 | .l1clk(l1clk), | |
1793 | .siclk(siclk), | |
1794 | .soclk(soclk), | |
1795 | .d(fdin[15:0]), | |
1796 | .si({scan_in,so[14:0]}), | |
1797 | .so({so[14:0],scan_out}), | |
1798 | .q(dout[15:0]) | |
1799 | ); | |
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | endmodule | |
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | ||
1820 | ||
1821 | ||
1822 | ||
1823 | ||
1824 | ||
1825 | ||
1826 | // any PARAMS parms go into naming of macro | |
1827 | ||
1828 | module mcu_reqq_ctl_msff_ctl_macro__width_2 ( | |
1829 | din, | |
1830 | l1clk, | |
1831 | scan_in, | |
1832 | siclk, | |
1833 | soclk, | |
1834 | dout, | |
1835 | scan_out); | |
1836 | wire [1:0] fdin; | |
1837 | wire [0:0] so; | |
1838 | ||
1839 | input [1:0] din; | |
1840 | input l1clk; | |
1841 | input scan_in; | |
1842 | ||
1843 | ||
1844 | input siclk; | |
1845 | input soclk; | |
1846 | ||
1847 | output [1:0] dout; | |
1848 | output scan_out; | |
1849 | assign fdin[1:0] = din[1:0]; | |
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | ||
1856 | dff #(2) d0_0 ( | |
1857 | .l1clk(l1clk), | |
1858 | .siclk(siclk), | |
1859 | .soclk(soclk), | |
1860 | .d(fdin[1:0]), | |
1861 | .si({scan_in,so[0:0]}), | |
1862 | .so({so[0:0],scan_out}), | |
1863 | .q(dout[1:0]) | |
1864 | ); | |
1865 | ||
1866 | ||
1867 | ||
1868 | ||
1869 | ||
1870 | ||
1871 | ||
1872 | ||
1873 | ||
1874 | ||
1875 | ||
1876 | ||
1877 | endmodule | |
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | // any PARAMS parms go into naming of macro | |
1892 | ||
1893 | module mcu_reqq_ctl_msff_ctl_macro ( | |
1894 | din, | |
1895 | l1clk, | |
1896 | scan_in, | |
1897 | siclk, | |
1898 | soclk, | |
1899 | dout, | |
1900 | scan_out); | |
1901 | wire [0:0] fdin; | |
1902 | ||
1903 | input [0:0] din; | |
1904 | input l1clk; | |
1905 | input scan_in; | |
1906 | ||
1907 | ||
1908 | input siclk; | |
1909 | input soclk; | |
1910 | ||
1911 | output [0:0] dout; | |
1912 | output scan_out; | |
1913 | assign fdin[0:0] = din[0:0]; | |
1914 | ||
1915 | ||
1916 | ||
1917 | ||
1918 | ||
1919 | ||
1920 | dff #(1) d0_0 ( | |
1921 | .l1clk(l1clk), | |
1922 | .siclk(siclk), | |
1923 | .soclk(soclk), | |
1924 | .d(fdin[0:0]), | |
1925 | .si(scan_in), | |
1926 | .so(scan_out), | |
1927 | .q(dout[0:0]) | |
1928 | ); | |
1929 | ||
1930 | ||
1931 | ||
1932 | ||
1933 | ||
1934 | ||
1935 | ||
1936 | ||
1937 | ||
1938 | ||
1939 | ||
1940 | ||
1941 | endmodule | |
1942 | ||
1943 | ||
1944 | ||
1945 | ||
1946 | ||
1947 | ||
1948 | ||
1949 | ||
1950 | ||
1951 | ||
1952 | ||
1953 | ||
1954 | ||
1955 | // any PARAMS parms go into naming of macro | |
1956 | ||
1957 | module mcu_reqq_ctl_msff_ctl_macro__clr_1__width_16 ( | |
1958 | din, | |
1959 | clr, | |
1960 | l1clk, | |
1961 | scan_in, | |
1962 | siclk, | |
1963 | soclk, | |
1964 | dout, | |
1965 | scan_out); | |
1966 | wire [15:0] fdin; | |
1967 | wire [14:0] so; | |
1968 | ||
1969 | input [15:0] din; | |
1970 | input clr; | |
1971 | input l1clk; | |
1972 | input scan_in; | |
1973 | ||
1974 | ||
1975 | input siclk; | |
1976 | input soclk; | |
1977 | ||
1978 | output [15:0] dout; | |
1979 | output scan_out; | |
1980 | assign fdin[15:0] = din[15:0] & ~{16{clr}}; | |
1981 | ||
1982 | ||
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | dff #(16) d0_0 ( | |
1988 | .l1clk(l1clk), | |
1989 | .siclk(siclk), | |
1990 | .soclk(soclk), | |
1991 | .d(fdin[15:0]), | |
1992 | .si({scan_in,so[14:0]}), | |
1993 | .so({so[14:0],scan_out}), | |
1994 | .q(dout[15:0]) | |
1995 | ); | |
1996 | ||
1997 | ||
1998 | ||
1999 | ||
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | ||
2006 | ||
2007 | ||
2008 | endmodule | |
2009 | ||
2010 | ||
2011 | ||
2012 | ||
2013 | ||
2014 | ||
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | ||
2021 | ||
2022 | // any PARAMS parms go into naming of macro | |
2023 | ||
2024 | module mcu_reqq_ctl_msff_ctl_macro__clr_1__width_3 ( | |
2025 | din, | |
2026 | clr, | |
2027 | l1clk, | |
2028 | scan_in, | |
2029 | siclk, | |
2030 | soclk, | |
2031 | dout, | |
2032 | scan_out); | |
2033 | wire [2:0] fdin; | |
2034 | wire [1:0] so; | |
2035 | ||
2036 | input [2:0] din; | |
2037 | input clr; | |
2038 | input l1clk; | |
2039 | input scan_in; | |
2040 | ||
2041 | ||
2042 | input siclk; | |
2043 | input soclk; | |
2044 | ||
2045 | output [2:0] dout; | |
2046 | output scan_out; | |
2047 | assign fdin[2:0] = din[2:0] & ~{3{clr}}; | |
2048 | ||
2049 | ||
2050 | ||
2051 | ||
2052 | ||
2053 | ||
2054 | dff #(3) d0_0 ( | |
2055 | .l1clk(l1clk), | |
2056 | .siclk(siclk), | |
2057 | .soclk(soclk), | |
2058 | .d(fdin[2:0]), | |
2059 | .si({scan_in,so[1:0]}), | |
2060 | .so({so[1:0],scan_out}), | |
2061 | .q(dout[2:0]) | |
2062 | ); | |
2063 | ||
2064 | ||
2065 | ||
2066 | ||
2067 | ||
2068 | ||
2069 | ||
2070 | ||
2071 | ||
2072 | ||
2073 | ||
2074 | ||
2075 | endmodule | |
2076 | ||
2077 | ||
2078 | ||
2079 | ||
2080 | ||
2081 | ||
2082 | ||
2083 |