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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_ucbout_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_ucbout_ctl ( | |
36 | l1clk, | |
37 | scan_in, | |
38 | scan_out, | |
39 | tcu_aclk, | |
40 | tcu_bclk, | |
41 | tcu_scan_en, | |
42 | vld, | |
43 | data, | |
44 | stall, | |
45 | outdata_buf_busy, | |
46 | outdata_buf_in, | |
47 | outdata_vec_in, | |
48 | outdata_buf_wr); | |
49 | wire siclk; | |
50 | wire soclk; | |
51 | wire se; | |
52 | wire stall_d1_ff_scanin; | |
53 | wire stall_d1_ff_scanout; | |
54 | wire outdata_vec_ff_scanin; | |
55 | wire outdata_vec_ff_scanout; | |
56 | wire outdata_buf_ff_scanin; | |
57 | wire outdata_buf_ff_scanout; | |
58 | ||
59 | ||
60 | ||
61 | //parameter UCB_BUS_WIDTH = 4; | |
62 | //parameter REG_WIDTH = 64; // maximum data bits that needs to | |
63 | // be sent. Set to 64 or 128 | |
64 | ||
65 | // Globals | |
66 | input l1clk; | |
67 | input scan_in; | |
68 | output scan_out; | |
69 | input tcu_aclk; | |
70 | input tcu_bclk; | |
71 | input tcu_scan_en; | |
72 | ||
73 | ||
74 | // UCB bus interface | |
75 | output vld; | |
76 | output [3:0] data; | |
77 | input stall; | |
78 | ||
79 | ||
80 | // Local interface | |
81 | output outdata_buf_busy; | |
82 | input [127:0] outdata_buf_in; | |
83 | input [31:0] outdata_vec_in; | |
84 | input outdata_buf_wr; | |
85 | ||
86 | ||
87 | // Local signals | |
88 | wire stall_d1; | |
89 | wire [31:0] outdata_vec; | |
90 | wire [31:0] outdata_vec_next; | |
91 | wire [127:0] outdata_buf; | |
92 | wire [127:0] outdata_buf_next; | |
93 | wire load_outdata; | |
94 | wire shift_outdata; | |
95 | ||
96 | //////////////////////////////////////////////////////////////////////// | |
97 | // Code starts here | |
98 | //////////////////////////////////////////////////////////////////////// | |
99 | ||
100 | // Scan reassigns | |
101 | assign siclk = tcu_aclk; | |
102 | assign soclk = tcu_bclk; | |
103 | assign se = tcu_scan_en; | |
104 | ||
105 | /************************************************************ | |
106 | * UCB bus interface flops | |
107 | ************************************************************/ | |
108 | assign vld = outdata_vec[0]; | |
109 | assign data = outdata_buf[3:0]; | |
110 | ||
111 | mcu_ucbout_ctl_msff_ctl_macro__width_1 stall_d1_ff ( | |
112 | .scan_in(stall_d1_ff_scanin), | |
113 | .scan_out(stall_d1_ff_scanout), | |
114 | .din(stall), | |
115 | .l1clk(l1clk), | |
116 | .dout(stall_d1), | |
117 | .siclk(siclk), | |
118 | .soclk(soclk)); | |
119 | ||
120 | ||
121 | /************************************************************ | |
122 | * Outbound Data | |
123 | ************************************************************/ | |
124 | // accept new data only if there is none being processed | |
125 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
126 | ||
127 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
128 | ||
129 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
130 | ||
131 | assign outdata_vec_next = | |
132 | load_outdata ? outdata_vec_in: | |
133 | shift_outdata ? outdata_vec >> 1: | |
134 | outdata_vec; | |
135 | ||
136 | mcu_ucbout_ctl_msff_ctl_macro__width_32 outdata_vec_ff ( | |
137 | .scan_in(outdata_vec_ff_scanin), | |
138 | .scan_out(outdata_vec_ff_scanout), | |
139 | .din(outdata_vec_next), | |
140 | .l1clk(l1clk), | |
141 | .dout(outdata_vec), | |
142 | .siclk(siclk), | |
143 | .soclk(soclk)); | |
144 | ||
145 | assign outdata_buf_next = | |
146 | load_outdata ? outdata_buf_in: | |
147 | shift_outdata ? (outdata_buf >> 4): | |
148 | outdata_buf; | |
149 | ||
150 | mcu_ucbout_ctl_msff_ctl_macro__width_128 outdata_buf_ff ( | |
151 | .scan_in(outdata_buf_ff_scanin), | |
152 | .scan_out(outdata_buf_ff_scanout), | |
153 | .din(outdata_buf_next), | |
154 | .l1clk(l1clk), | |
155 | .dout(outdata_buf), | |
156 | .siclk(siclk), | |
157 | .soclk(soclk)); | |
158 | ||
159 | ||
160 | // fixscan start: | |
161 | assign stall_d1_ff_scanin = scan_in ; | |
162 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; | |
163 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; | |
164 | assign scan_out = outdata_buf_ff_scanout ; | |
165 | // fixscan end: | |
166 | endmodule | |
167 | ||
168 | ||
169 | ||
170 | ||
171 | ||
172 | ||
173 | ||
174 | ||
175 | ||
176 | ||
177 | ||
178 | ||
179 | // any PARAMS parms go into naming of macro | |
180 | ||
181 | module mcu_ucbout_ctl_msff_ctl_macro__width_1 ( | |
182 | din, | |
183 | l1clk, | |
184 | scan_in, | |
185 | siclk, | |
186 | soclk, | |
187 | dout, | |
188 | scan_out); | |
189 | wire [0:0] fdin; | |
190 | ||
191 | input [0:0] din; | |
192 | input l1clk; | |
193 | input scan_in; | |
194 | ||
195 | ||
196 | input siclk; | |
197 | input soclk; | |
198 | ||
199 | output [0:0] dout; | |
200 | output scan_out; | |
201 | assign fdin[0:0] = din[0:0]; | |
202 | ||
203 | ||
204 | ||
205 | ||
206 | ||
207 | ||
208 | dff #(1) d0_0 ( | |
209 | .l1clk(l1clk), | |
210 | .siclk(siclk), | |
211 | .soclk(soclk), | |
212 | .d(fdin[0:0]), | |
213 | .si(scan_in), | |
214 | .so(scan_out), | |
215 | .q(dout[0:0]) | |
216 | ); | |
217 | ||
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | ||
228 | ||
229 | endmodule | |
230 | ||
231 | ||
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | ||
238 | ||
239 | ||
240 | ||
241 | ||
242 | ||
243 | // any PARAMS parms go into naming of macro | |
244 | ||
245 | module mcu_ucbout_ctl_msff_ctl_macro__width_32 ( | |
246 | din, | |
247 | l1clk, | |
248 | scan_in, | |
249 | siclk, | |
250 | soclk, | |
251 | dout, | |
252 | scan_out); | |
253 | wire [31:0] fdin; | |
254 | wire [30:0] so; | |
255 | ||
256 | input [31:0] din; | |
257 | input l1clk; | |
258 | input scan_in; | |
259 | ||
260 | ||
261 | input siclk; | |
262 | input soclk; | |
263 | ||
264 | output [31:0] dout; | |
265 | output scan_out; | |
266 | assign fdin[31:0] = din[31:0]; | |
267 | ||
268 | ||
269 | ||
270 | ||
271 | ||
272 | ||
273 | dff #(32) d0_0 ( | |
274 | .l1clk(l1clk), | |
275 | .siclk(siclk), | |
276 | .soclk(soclk), | |
277 | .d(fdin[31:0]), | |
278 | .si({scan_in,so[30:0]}), | |
279 | .so({so[30:0],scan_out}), | |
280 | .q(dout[31:0]) | |
281 | ); | |
282 | ||
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | ||
292 | ||
293 | ||
294 | endmodule | |
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | ||
308 | // any PARAMS parms go into naming of macro | |
309 | ||
310 | module mcu_ucbout_ctl_msff_ctl_macro__width_128 ( | |
311 | din, | |
312 | l1clk, | |
313 | scan_in, | |
314 | siclk, | |
315 | soclk, | |
316 | dout, | |
317 | scan_out); | |
318 | wire [127:0] fdin; | |
319 | wire [126:0] so; | |
320 | ||
321 | input [127:0] din; | |
322 | input l1clk; | |
323 | input scan_in; | |
324 | ||
325 | ||
326 | input siclk; | |
327 | input soclk; | |
328 | ||
329 | output [127:0] dout; | |
330 | output scan_out; | |
331 | assign fdin[127:0] = din[127:0]; | |
332 | ||
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | dff #(128) d0_0 ( | |
339 | .l1clk(l1clk), | |
340 | .siclk(siclk), | |
341 | .soclk(soclk), | |
342 | .d(fdin[127:0]), | |
343 | .si({scan_in,so[126:0]}), | |
344 | .so({so[126:0],scan_out}), | |
345 | .q(dout[127:0]) | |
346 | ); | |
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | ||
358 | ||
359 | endmodule | |
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 |