projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: mcu_wrdp_dp.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module mcu_wrdp_dp ( | |
| 36 | l2clk, | |
| 37 | drl2clk, | |
| 38 | scan_in, | |
| 39 | scan_out, | |
| 40 | tcu_pce_ov, | |
| 41 | cmp_pce_ov, | |
| 42 | tcu_aclk, | |
| 43 | tcu_bclk, | |
| 44 | tcu_scan_en, | |
| 45 | bank0_wdata, | |
| 46 | bank1_wdata, | |
| 47 | scrub_rwen, | |
| 48 | mcu_scrub_wdata, | |
| 49 | wdata_sel, | |
| 50 | err_inj_reg, | |
| 51 | err_mask_reg, | |
| 52 | wadr_parity, | |
| 53 | l2poison_qw, | |
| 54 | fail_over_mask, | |
| 55 | fail_over_mask_l, | |
| 56 | io_wdata_sel, | |
| 57 | mcu_io_data_out, | |
| 58 | mbist_run, | |
| 59 | mbist_sel_hiorlo_72bits, | |
| 60 | mbist_sel_bank0or1, | |
| 61 | mbist_read_data, | |
| 62 | lfsr_in, | |
| 63 | lfsr_out, | |
| 64 | lfsr_out_0); | |
| 65 | wire pce_ov; | |
| 66 | wire stop; | |
| 67 | wire siclk; | |
| 68 | wire soclk; | |
| 69 | wire se; | |
| 70 | wire mbist_sel_hiorlo_72bits_l; | |
| 71 | wire mbist_sel_bank0or1_l; | |
| 72 | wire mbist_run_l; | |
| 73 | wire wdqrf00_data_sel; | |
| 74 | wire wdqrf01_data_sel; | |
| 75 | wire wdqrf10_data_sel; | |
| 76 | wire wdqrf11_data_sel; | |
| 77 | wire u_wdqrf00_data_scanin; | |
| 78 | wire u_wdqrf00_data_scanout; | |
| 79 | wire [63:0] wdqrf00_data; | |
| 80 | wire u_wdqrf01_data_scanin; | |
| 81 | wire u_wdqrf01_data_scanout; | |
| 82 | wire [63:0] wdqrf01_data; | |
| 83 | wire u_wdqrf10_data_scanin; | |
| 84 | wire u_wdqrf10_data_scanout; | |
| 85 | wire [63:0] wdqrf10_data; | |
| 86 | wire u_wdqrf11_data_scanin; | |
| 87 | wire u_wdqrf11_data_scanout; | |
| 88 | wire [63:0] wdqrf11_data; | |
| 89 | wire u_scrub_wdata_511_448_scanin; | |
| 90 | wire u_scrub_wdata_511_448_scanout; | |
| 91 | wire [511:0] scrub_wdata; | |
| 92 | wire u_scrub_wdata_447_384_scanin; | |
| 93 | wire u_scrub_wdata_447_384_scanout; | |
| 94 | wire u_scrub_wdata_383_320_scanin; | |
| 95 | wire u_scrub_wdata_383_320_scanout; | |
| 96 | wire u_scrub_wdata_319_256_scanin; | |
| 97 | wire u_scrub_wdata_319_256_scanout; | |
| 98 | wire u_scrub_wdata_255_192_scanin; | |
| 99 | wire u_scrub_wdata_255_192_scanout; | |
| 100 | wire u_scrub_wdata_191_128_scanin; | |
| 101 | wire u_scrub_wdata_191_128_scanout; | |
| 102 | wire u_scrub_wdata_127_64_scanin; | |
| 103 | wire u_scrub_wdata_127_64_scanout; | |
| 104 | wire u_scrub_wdata_63_0_scanin; | |
| 105 | wire u_scrub_wdata_63_0_scanout; | |
| 106 | wire u_wdata_127_64_scanin; | |
| 107 | wire u_wdata_127_64_scanout; | |
| 108 | wire [127:0] wdata; | |
| 109 | wire u_wdata_63_0_scanin; | |
| 110 | wire u_wdata_63_0_scanout; | |
| 111 | wire [3:0] wecc0; | |
| 112 | wire [3:0] wecc1; | |
| 113 | wire [3:0] wecc2; | |
| 114 | wire [3:0] wecc3; | |
| 115 | wire [15:0] err_inj_vec; | |
| 116 | wire [46:0] spare_nand_unused; | |
| 117 | wire [15:0] err_inj_ecc; | |
| 118 | wire [143:0] wr_data_muxed_nibbles; | |
| 119 | wire [143:4] mux_io_data_out; | |
| 120 | wire u_io_data_127_64_scanin; | |
| 121 | wire u_io_data_127_64_scanout; | |
| 122 | wire u_io_data_63_0_scanin; | |
| 123 | wire u_io_data_63_0_scanout; | |
| 124 | wire [15:0] mux_io_ecc_out; | |
| 125 | wire u_io_ecc_15_0_scanin; | |
| 126 | wire u_io_ecc_15_0_scanout; | |
| 127 | ||
| 128 | ||
| 129 | input l2clk; | |
| 130 | input drl2clk; | |
| 131 | ||
| 132 | input scan_in; | |
| 133 | output scan_out; | |
| 134 | input tcu_pce_ov; | |
| 135 | input cmp_pce_ov; | |
| 136 | input tcu_aclk; | |
| 137 | input tcu_bclk; | |
| 138 | input tcu_scan_en; | |
| 139 | ||
| 140 | input [127:0] bank0_wdata; // L2 bank0 write data from write data queue | |
| 141 | input [127:0] bank1_wdata; // L2 bank0 write data from write data queue | |
| 142 | ||
| 143 | input scrub_rwen; // scrub shift reg read/write en | |
| 144 | input [255:0] mcu_scrub_wdata; // scrubbed write data from MCU read | |
| 145 | ||
| 146 | input [3:0] wdata_sel; // select l2b0, l2b1, or scrubbed data to memory ( [0]:bank0 data, [1]: bank1 data, [2]: scrubbed data ) | |
| 147 | input err_inj_reg; // error inject reg | |
| 148 | input [15:0] err_mask_reg; // error mask reg | |
| 149 | input wadr_parity; // write address parity | |
| 150 | input l2poison_qw; // poison write ecc data | |
| 151 | input [34:0] fail_over_mask; | |
| 152 | input [34:0] fail_over_mask_l; | |
| 153 | input [1:0] io_wdata_sel; // select write data to IO | |
| 154 | output [143:0] mcu_io_data_out; // write data to IO. ECC: [143:128], DATA: [127:0] | |
| 155 | ||
| 156 | input mbist_run; | |
| 157 | input mbist_sel_hiorlo_72bits; | |
| 158 | input mbist_sel_bank0or1; | |
| 159 | output [63:0] mbist_read_data; | |
| 160 | ||
| 161 | input [11:0] lfsr_in; | |
| 162 | output [12:0] lfsr_out; | |
| 163 | output [3:0] lfsr_out_0; | |
| 164 | ||
| 165 | //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
| 166 | ||
| 167 | // Scan reassigns | |
| 168 | assign pce_ov = tcu_pce_ov; | |
| 169 | assign stop = 1'b0; | |
| 170 | assign siclk = tcu_aclk; | |
| 171 | assign soclk = tcu_bclk; | |
| 172 | assign se = tcu_scan_en; | |
| 173 | ||
| 174 | // MBIST registers and muxes | |
| 175 | mcu_wrdp_dp_inv_macro__width_3 u_mbist_signals ( | |
| 176 | .din ( { mbist_sel_hiorlo_72bits, mbist_sel_bank0or1, mbist_run } ), | |
| 177 | .dout( { mbist_sel_hiorlo_72bits_l, mbist_sel_bank0or1_l, mbist_run_l } )); | |
| 178 | ||
| 179 | mcu_wrdp_dp_nor_macro u_wdqrf00_data_sel ( | |
| 180 | .din0(mbist_sel_hiorlo_72bits), | |
| 181 | .din1(mbist_sel_bank0or1), | |
| 182 | .dout(wdqrf00_data_sel)); | |
| 183 | ||
| 184 | mcu_wrdp_dp_nor_macro u_wdqrf01_data_sel ( | |
| 185 | .din0(mbist_sel_hiorlo_72bits_l), | |
| 186 | .din1(mbist_sel_bank0or1), | |
| 187 | .dout(wdqrf01_data_sel)); | |
| 188 | ||
| 189 | mcu_wrdp_dp_nor_macro u_wdqrf10_data_sel ( | |
| 190 | .din0(mbist_sel_hiorlo_72bits), | |
| 191 | .din1(mbist_sel_bank0or1_l), | |
| 192 | .dout(wdqrf10_data_sel)); | |
| 193 | ||
| 194 | mcu_wrdp_dp_nor_macro u_wdqrf11_data_sel ( | |
| 195 | .din0(mbist_sel_hiorlo_72bits_l), | |
| 196 | .din1(mbist_sel_bank0or1_l), | |
| 197 | .dout(wdqrf11_data_sel)); | |
| 198 | ||
| 199 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_wdqrf00_data ( | |
| 200 | .scan_in(u_wdqrf00_data_scanin), | |
| 201 | .scan_out(u_wdqrf00_data_scanout), | |
| 202 | .din(bank0_wdata[127:64]), | |
| 203 | .dout(wdqrf00_data[63:0]), | |
| 204 | .en(mbist_run), | |
| 205 | .pce_ov(cmp_pce_ov), | |
| 206 | .clk(l2clk), | |
| 207 | .se(se), | |
| 208 | .siclk(siclk), | |
| 209 | .soclk(soclk), | |
| 210 | .stop(stop)); | |
| 211 | ||
| 212 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_wdqrf01_data ( | |
| 213 | .scan_in(u_wdqrf01_data_scanin), | |
| 214 | .scan_out(u_wdqrf01_data_scanout), | |
| 215 | .din(bank0_wdata[63:0]), | |
| 216 | .dout(wdqrf01_data[63:0]), | |
| 217 | .en(mbist_run), | |
| 218 | .pce_ov(cmp_pce_ov), | |
| 219 | .clk(l2clk), | |
| 220 | .se(se), | |
| 221 | .siclk(siclk), | |
| 222 | .soclk(soclk), | |
| 223 | .stop(stop)); | |
| 224 | ||
| 225 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_wdqrf10_data ( | |
| 226 | .scan_in(u_wdqrf10_data_scanin), | |
| 227 | .scan_out(u_wdqrf10_data_scanout), | |
| 228 | .din(bank1_wdata[127:64]), | |
| 229 | .dout(wdqrf10_data[63:0]), | |
| 230 | .en(mbist_run), | |
| 231 | .pce_ov(cmp_pce_ov), | |
| 232 | .clk(l2clk), | |
| 233 | .se(se), | |
| 234 | .siclk(siclk), | |
| 235 | .soclk(soclk), | |
| 236 | .stop(stop)); | |
| 237 | ||
| 238 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_wdqrf11_data ( | |
| 239 | .scan_in(u_wdqrf11_data_scanin), | |
| 240 | .scan_out(u_wdqrf11_data_scanout), | |
| 241 | .din(bank1_wdata[63:0]), | |
| 242 | .dout(wdqrf11_data[63:0]), | |
| 243 | .en(mbist_run), | |
| 244 | .pce_ov(cmp_pce_ov), | |
| 245 | .clk(l2clk), | |
| 246 | .se(se), | |
| 247 | .siclk(siclk), | |
| 248 | .soclk(soclk), | |
| 249 | .stop(stop)); | |
| 250 | ||
| 251 | mcu_wrdp_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 u_mbist_read_data ( | |
| 252 | .din0(wdqrf00_data[63:0]), | |
| 253 | .din1(wdqrf01_data[63:0]), | |
| 254 | .din2(wdqrf10_data[63:0]), | |
| 255 | .din3(wdqrf11_data[63:0]), | |
| 256 | .sel0(wdqrf00_data_sel), | |
| 257 | .sel1(wdqrf01_data_sel), | |
| 258 | .sel2(wdqrf10_data_sel), | |
| 259 | .sel3(wdqrf11_data_sel), | |
| 260 | .dout(mbist_read_data[63:0])); | |
| 261 | ||
| 262 | // scrub_wdata | |
| 263 | // [63:0] [127:64] | |
| 264 | // | | | |
| 265 | // v v | |
| 266 | // 511:448 447:384 | |
| 267 | // v v | |
| 268 | // 383:320 319:256 | |
| 269 | // v v | |
| 270 | // 255:192 191:128 | |
| 271 | // v v | |
| 272 | // 127:64 63:0 | |
| 273 | // | | | |
| 274 | // v v | |
| 275 | // write to memory | |
| 276 | ||
| 277 | ||
| 278 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_511_448 ( | |
| 279 | .scan_in(u_scrub_wdata_511_448_scanin), | |
| 280 | .scan_out(u_scrub_wdata_511_448_scanout), | |
| 281 | .clk ( drl2clk ), | |
| 282 | .en ( scrub_rwen ), | |
| 283 | .din ( mcu_scrub_wdata[63:0] ), | |
| 284 | .dout ( scrub_wdata[511:448] ), | |
| 285 | .se(se), | |
| 286 | .siclk(siclk), | |
| 287 | .soclk(soclk), | |
| 288 | .pce_ov(pce_ov), | |
| 289 | .stop(stop)); | |
| 290 | ||
| 291 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_447_384 ( | |
| 292 | .scan_in(u_scrub_wdata_447_384_scanin), | |
| 293 | .scan_out(u_scrub_wdata_447_384_scanout), | |
| 294 | .clk ( drl2clk ), | |
| 295 | .en ( scrub_rwen ), | |
| 296 | .din ( mcu_scrub_wdata[127:64] ), | |
| 297 | .dout ( scrub_wdata[447:384] ), | |
| 298 | .se(se), | |
| 299 | .siclk(siclk), | |
| 300 | .soclk(soclk), | |
| 301 | .pce_ov(pce_ov), | |
| 302 | .stop(stop)); | |
| 303 | ||
| 304 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_383_320 ( | |
| 305 | .scan_in(u_scrub_wdata_383_320_scanin), | |
| 306 | .scan_out(u_scrub_wdata_383_320_scanout), | |
| 307 | .clk ( drl2clk ), | |
| 308 | .en ( scrub_rwen ), | |
| 309 | .din ( mcu_scrub_wdata[191:128] ), | |
| 310 | .dout ( scrub_wdata[383:320] ), | |
| 311 | .se(se), | |
| 312 | .siclk(siclk), | |
| 313 | .soclk(soclk), | |
| 314 | .pce_ov(pce_ov), | |
| 315 | .stop(stop)); | |
| 316 | ||
| 317 | ||
| 318 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_319_256 ( | |
| 319 | .scan_in(u_scrub_wdata_319_256_scanin), | |
| 320 | .scan_out(u_scrub_wdata_319_256_scanout), | |
| 321 | .clk ( drl2clk ), | |
| 322 | .en ( scrub_rwen ), | |
| 323 | .din ( mcu_scrub_wdata[255:192] ), | |
| 324 | .dout ( scrub_wdata[319:256] ), | |
| 325 | .se(se), | |
| 326 | .siclk(siclk), | |
| 327 | .soclk(soclk), | |
| 328 | .pce_ov(pce_ov), | |
| 329 | .stop(stop)); | |
| 330 | ||
| 331 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_255_192 ( | |
| 332 | .scan_in(u_scrub_wdata_255_192_scanin), | |
| 333 | .scan_out(u_scrub_wdata_255_192_scanout), | |
| 334 | .clk ( drl2clk ), | |
| 335 | .en ( scrub_rwen ), | |
| 336 | .din ( scrub_wdata[511:448] ), | |
| 337 | .dout ( scrub_wdata[255:192] ), | |
| 338 | .se(se), | |
| 339 | .siclk(siclk), | |
| 340 | .soclk(soclk), | |
| 341 | .pce_ov(pce_ov), | |
| 342 | .stop(stop)); | |
| 343 | ||
| 344 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_191_128 ( | |
| 345 | .scan_in(u_scrub_wdata_191_128_scanin), | |
| 346 | .scan_out(u_scrub_wdata_191_128_scanout), | |
| 347 | .clk ( drl2clk ), | |
| 348 | .en ( scrub_rwen ), | |
| 349 | .din ( scrub_wdata[447:384] ), | |
| 350 | .dout ( scrub_wdata[191:128] ), | |
| 351 | .se(se), | |
| 352 | .siclk(siclk), | |
| 353 | .soclk(soclk), | |
| 354 | .pce_ov(pce_ov), | |
| 355 | .stop(stop)); | |
| 356 | ||
| 357 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_127_64 ( | |
| 358 | .scan_in(u_scrub_wdata_127_64_scanin), | |
| 359 | .scan_out(u_scrub_wdata_127_64_scanout), | |
| 360 | .clk ( drl2clk ), | |
| 361 | .en ( scrub_rwen ), | |
| 362 | .din ( scrub_wdata[383:320] ), | |
| 363 | .dout ( scrub_wdata[127:64] ), | |
| 364 | .se(se), | |
| 365 | .siclk(siclk), | |
| 366 | .soclk(soclk), | |
| 367 | .pce_ov(pce_ov), | |
| 368 | .stop(stop)); | |
| 369 | ||
| 370 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_scrub_wdata_63_0 ( | |
| 371 | .scan_in(u_scrub_wdata_63_0_scanin), | |
| 372 | .scan_out(u_scrub_wdata_63_0_scanout), | |
| 373 | .clk ( drl2clk ), | |
| 374 | .en ( scrub_rwen ), | |
| 375 | .din ( scrub_wdata[319:256] ), | |
| 376 | .dout ( scrub_wdata[63:0] ), | |
| 377 | .se(se), | |
| 378 | .siclk(siclk), | |
| 379 | .soclk(soclk), | |
| 380 | .pce_ov(pce_ov), | |
| 381 | .stop(stop)); | |
| 382 | ||
| 383 | ||
| 384 | // | |
| 385 | // memory write data from 3 sources - L2 bank0 WDQ, L2 bank1 WDQ, and scrubbed data | |
| 386 | // | |
| 387 | ||
| 388 | mcu_wrdp_dp_msff_macro__mux_aonpe__ports_4__stack_64c__width_64 u_wdata_127_64 ( | |
| 389 | .scan_in(u_wdata_127_64_scanin), | |
| 390 | .scan_out(u_wdata_127_64_scanout), | |
| 391 | .clk ( drl2clk ), | |
| 392 | .en ( 1'b1 ), | |
| 393 | .din0 ( bank0_wdata[127:64] ), | |
| 394 | .din1 ( bank1_wdata[127:64] ), | |
| 395 | .din2 ( scrub_wdata[127:64] ), | |
| 396 | .din3 ( scrub_wdata[255:192] ), | |
| 397 | .sel0 ( wdata_sel[0] ), // bank0 data | |
| 398 | .sel1 ( wdata_sel[1] ), // bank1 data | |
| 399 | .sel2 ( wdata_sel[2] ), // scrubbed data | |
| 400 | .sel3 ( wdata_sel[3] ), // scrubbed data | |
| 401 | .dout ( wdata[127:64] ), | |
| 402 | .se(se), | |
| 403 | .siclk(siclk), | |
| 404 | .soclk(soclk), | |
| 405 | .pce_ov(pce_ov), | |
| 406 | .stop(stop)); | |
| 407 | ||
| 408 | mcu_wrdp_dp_msff_macro__mux_aonpe__ports_4__stack_64c__width_64 u_wdata_63_0 ( | |
| 409 | .scan_in(u_wdata_63_0_scanin), | |
| 410 | .scan_out(u_wdata_63_0_scanout), | |
| 411 | .clk ( drl2clk ), | |
| 412 | .en ( 1'b1 ), | |
| 413 | .din0 ( bank0_wdata[63:0] ), | |
| 414 | .din1 ( bank1_wdata[63:0] ), | |
| 415 | .din2 ( scrub_wdata[63:0] ), | |
| 416 | .din3 ( scrub_wdata[191:128] ), | |
| 417 | .sel0 ( wdata_sel[0] ), // bank0 data | |
| 418 | .sel1 ( wdata_sel[1] ), // bank1 data | |
| 419 | .sel2 ( wdata_sel[2] ), // scrubbed data | |
| 420 | .sel3 ( wdata_sel[3] ), // scrubbed data | |
| 421 | .dout ( wdata[63:0] ), | |
| 422 | .se(se), | |
| 423 | .siclk(siclk), | |
| 424 | .soclk(soclk), | |
| 425 | .pce_ov(pce_ov), | |
| 426 | .stop(stop)); | |
| 427 | ||
| 428 | // Generate ECC data to DRAM | |
| 429 | ||
| 430 | mcu_eccgen_dp u_w_eccgen ( | |
| 431 | .din ( { wdata[63:0], wdata[127:64] } ), | |
| 432 | .adr_parity ( wadr_parity ), | |
| 433 | .ecc0_in ( {4 { 1'b0} } ), | |
| 434 | .ecc1_in ( {4 { 1'b0} } ), | |
| 435 | .ecc2_in ( {4 { 1'b0} } ), | |
| 436 | .ecc3_in ( {4 { 1'b0} } ), | |
| 437 | .ecc ( { wecc0[3:0], wecc1[3:0], wecc2[3:0], wecc3[3:0] } )); | |
| 438 | ||
| 439 | ||
| 440 | // Error injection vector: 16 bits | |
| 441 | ||
| 442 | mcu_wrdp_dp_and_macro__ports_2__stack_16r__width_16 u_err_inj_vec ( | |
| 443 | .din0 ( { 16 { err_inj_reg } } ), | |
| 444 | .din1 ( err_mask_reg[15:0] ), | |
| 445 | .dout ( err_inj_vec[15:0])); | |
| 446 | ||
| 447 | mcu_wrdp_dp_nand_macro__width_48 spare_nand ( | |
| 448 | .din0 ( {47'h0, lfsr_out_0[3]} ), | |
| 449 | .din1 ( {47'h0, lfsr_out_0[3]} ), | |
| 450 | .dout ( {spare_nand_unused[46:0], lfsr_out[12]})); | |
| 451 | ||
| 452 | // | |
| 453 | // Poison ECC data with signature: 16'h8221 ( refer to N2 PRM section A.7.4 ) | |
| 454 | // | |
| 455 | ||
| 456 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_15 ( .din0 ( wecc0[3] ), .din1 ( err_inj_vec[3] ), .dout ( err_inj_ecc[15] )); | |
| 457 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_14 ( .din0 ( wecc0[2] ), .din1 ( err_inj_vec[2] ), .dout ( err_inj_ecc[14] )); | |
| 458 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_13 ( .din0 ( wecc0[1] ), .din1 ( err_inj_vec[1] ), .dout ( err_inj_ecc[13] )); | |
| 459 | mcu_wrdp_dp_xor_macro__ports_3__width_1 u_err_inj_ecc_12 ( .din0 ( wecc0[0] ), .din1 ( err_inj_vec[0] ), .din2 ( l2poison_qw ), .dout ( err_inj_ecc[12] )); | |
| 460 | ||
| 461 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_11 ( .din0 ( wecc1[3] ), .din1 ( err_inj_vec[7] ), .dout ( err_inj_ecc[11] )); | |
| 462 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_10 ( .din0 ( wecc1[2] ), .din1 ( err_inj_vec[6] ), .dout ( err_inj_ecc[10] )); | |
| 463 | mcu_wrdp_dp_xor_macro__ports_3__width_1 u_err_inj_ecc_9 ( .din0 ( wecc1[1] ), .din1 ( err_inj_vec[5] ), .din2 ( l2poison_qw ), .dout ( err_inj_ecc[9] )); | |
| 464 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_8 ( .din0 ( wecc1[0] ), .din1 ( err_inj_vec[4] ), .dout ( err_inj_ecc[8] )); | |
| 465 | ||
| 466 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_7 ( .din0 ( wecc2[3] ), .din1 ( err_inj_vec[11] ), .dout ( err_inj_ecc[7] )); | |
| 467 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_6 ( .din0 ( wecc2[2] ), .din1 ( err_inj_vec[10] ), .dout ( err_inj_ecc[6] )); | |
| 468 | mcu_wrdp_dp_xor_macro__ports_3__width_1 u_err_inj_ecc_5 ( .din0 ( wecc2[1] ), .din1 ( err_inj_vec[9] ), .din2 ( l2poison_qw ), .dout ( err_inj_ecc[5] )); | |
| 469 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_4 ( .din0 ( wecc2[0] ), .din1 ( err_inj_vec[8] ), .dout ( err_inj_ecc[4] )); | |
| 470 | ||
| 471 | mcu_wrdp_dp_xor_macro__ports_3__width_1 u_err_inj_ecc_3 ( .din0 ( wecc3[3] ), .din1 ( err_inj_vec[15] ), .din2 ( l2poison_qw ), .dout ( err_inj_ecc[3] )); | |
| 472 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_2 ( .din0 ( wecc3[2] ), .din1 ( err_inj_vec[14] ), .dout ( err_inj_ecc[2] )); | |
| 473 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_1 ( .din0 ( wecc3[1] ), .din1 ( err_inj_vec[13] ), .dout ( err_inj_ecc[1] )); | |
| 474 | mcu_wrdp_dp_xor_macro__ports_2__width_1 u_err_inj_ecc_0 ( .din0 ( wecc3[0] ), .din1 ( err_inj_vec[12] ), .dout ( err_inj_ecc[0] )); | |
| 475 | ||
| 476 | // | |
| 477 | // Register 128 bits data and 16 bits ecc | |
| 478 | // | |
| 479 | // DRAM: ECC DATA | |
| 480 | // [143:128] [127:0] | |
| 481 | // | |
| 482 | ||
| 483 | assign wr_data_muxed_nibbles[143:0] = { err_inj_ecc[15:0], wdata[63:0], wdata[127:64] }; | |
| 484 | ||
| 485 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_143_140 ( | |
| 486 | .din0 ( wr_data_muxed_nibbles[127:124] ), | |
| 487 | .din1 ( wr_data_muxed_nibbles[143:140] ), | |
| 488 | .sel0 ( fail_over_mask[31] ), | |
| 489 | .sel1 ( fail_over_mask_l[31] ), | |
| 490 | .dout ( mux_io_data_out[143:140] )); | |
| 491 | ||
| 492 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_139_136 ( | |
| 493 | .din0 ( wr_data_muxed_nibbles[143:140] ), | |
| 494 | .din1 ( wr_data_muxed_nibbles[139:136] ), | |
| 495 | .sel0 ( fail_over_mask[32] ), | |
| 496 | .sel1 ( fail_over_mask_l[32] ), | |
| 497 | .dout ( mux_io_data_out[139:136] )); | |
| 498 | ||
| 499 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_135_132 ( | |
| 500 | .din0 ( wr_data_muxed_nibbles[139:136] ), | |
| 501 | .din1 ( wr_data_muxed_nibbles[135:132] ), | |
| 502 | .sel0 ( fail_over_mask[33] ), | |
| 503 | .sel1 ( fail_over_mask_l[33] ), | |
| 504 | .dout ( mux_io_data_out[135:132] )); | |
| 505 | ||
| 506 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_131_128 ( | |
| 507 | .din0 ( wr_data_muxed_nibbles[135:132] ), | |
| 508 | .din1 ( wr_data_muxed_nibbles[131:128] ), | |
| 509 | .sel0 ( fail_over_mask[34] ), | |
| 510 | .sel1 ( fail_over_mask_l[34] ), | |
| 511 | .dout ( mux_io_data_out[131:128] )); | |
| 512 | ||
| 513 | // sdram write data [127:64] | |
| 514 | ||
| 515 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_127_124 ( | |
| 516 | .din0 ( wr_data_muxed_nibbles[123:120] ), | |
| 517 | .din1 ( wr_data_muxed_nibbles[127:124] ), | |
| 518 | .sel0 ( fail_over_mask[30] ), | |
| 519 | .sel1 ( fail_over_mask_l[30] ), | |
| 520 | .dout ( mux_io_data_out[127:124] )); | |
| 521 | ||
| 522 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_123_120 ( | |
| 523 | .din0 ( wr_data_muxed_nibbles[119:116] ), | |
| 524 | .din1 ( wr_data_muxed_nibbles[123:120] ), | |
| 525 | .sel0 ( fail_over_mask[29] ), | |
| 526 | .sel1 ( fail_over_mask_l[29] ), | |
| 527 | .dout ( mux_io_data_out[123:120] )); | |
| 528 | ||
| 529 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_119_116 ( | |
| 530 | .din0 ( wr_data_muxed_nibbles[115:112] ), | |
| 531 | .din1 ( wr_data_muxed_nibbles[119:116] ), | |
| 532 | .sel0 ( fail_over_mask[28] ), | |
| 533 | .sel1 ( fail_over_mask_l[28] ), | |
| 534 | .dout ( mux_io_data_out[119:116] )); | |
| 535 | ||
| 536 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_115_112 ( | |
| 537 | .din0 ( wr_data_muxed_nibbles[111:108] ), | |
| 538 | .din1 ( wr_data_muxed_nibbles[115:112] ), | |
| 539 | .sel0 ( fail_over_mask[27] ), | |
| 540 | .sel1 ( fail_over_mask_l[27] ), | |
| 541 | .dout ( mux_io_data_out[115:112] )); | |
| 542 | ||
| 543 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_111_108 ( | |
| 544 | .din0 ( wr_data_muxed_nibbles[107:104] ), | |
| 545 | .din1 ( wr_data_muxed_nibbles[111:108] ), | |
| 546 | .sel0 ( fail_over_mask[26] ), | |
| 547 | .sel1 ( fail_over_mask_l[26] ), | |
| 548 | .dout ( mux_io_data_out[111:108] )); | |
| 549 | ||
| 550 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_107_104 ( | |
| 551 | .din0 ( wr_data_muxed_nibbles[103:100] ), | |
| 552 | .din1 ( wr_data_muxed_nibbles[107:104] ), | |
| 553 | .sel0 ( fail_over_mask[25] ), | |
| 554 | .sel1 ( fail_over_mask_l[25] ), | |
| 555 | .dout ( mux_io_data_out[107:104] )); | |
| 556 | ||
| 557 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_103_100 ( | |
| 558 | .din0 ( wr_data_muxed_nibbles[99:96] ), | |
| 559 | .din1 ( wr_data_muxed_nibbles[103:100] ), | |
| 560 | .sel0 ( fail_over_mask[24] ), | |
| 561 | .sel1 ( fail_over_mask_l[24] ), | |
| 562 | .dout ( mux_io_data_out[103:100] )); | |
| 563 | ||
| 564 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_99_96 ( | |
| 565 | .din0 ( wr_data_muxed_nibbles[95:92] ), | |
| 566 | .din1 ( wr_data_muxed_nibbles[99:96] ), | |
| 567 | .sel0 ( fail_over_mask[23] ), | |
| 568 | .sel1 ( fail_over_mask_l[23] ), | |
| 569 | .dout ( mux_io_data_out[99:96] )); | |
| 570 | ||
| 571 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_95_92 ( | |
| 572 | .din0 ( wr_data_muxed_nibbles[91:88] ), | |
| 573 | .din1 ( wr_data_muxed_nibbles[95:92] ), | |
| 574 | .sel0 ( fail_over_mask[22] ), | |
| 575 | .sel1 ( fail_over_mask_l[22] ), | |
| 576 | .dout ( mux_io_data_out[95:92] )); | |
| 577 | ||
| 578 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_91_88 ( | |
| 579 | .din0 ( wr_data_muxed_nibbles[87:84] ), | |
| 580 | .din1 ( wr_data_muxed_nibbles[91:88] ), | |
| 581 | .sel0 ( fail_over_mask[21] ), | |
| 582 | .sel1 ( fail_over_mask_l[21] ), | |
| 583 | .dout ( mux_io_data_out[91:88] )); | |
| 584 | ||
| 585 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_87_84 ( | |
| 586 | .din0 ( wr_data_muxed_nibbles[83:80] ), | |
| 587 | .din1 ( wr_data_muxed_nibbles[87:84] ), | |
| 588 | .sel0 ( fail_over_mask[20] ), | |
| 589 | .sel1 ( fail_over_mask_l[20] ), | |
| 590 | .dout ( mux_io_data_out[87:84] )); | |
| 591 | ||
| 592 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_83_80 ( | |
| 593 | .din0 ( wr_data_muxed_nibbles[79:76] ), | |
| 594 | .din1 ( wr_data_muxed_nibbles[83:80] ), | |
| 595 | .sel0 ( fail_over_mask[19] ), | |
| 596 | .sel1 ( fail_over_mask_l[19] ), | |
| 597 | .dout ( mux_io_data_out[83:80] )); | |
| 598 | ||
| 599 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_79_76 ( | |
| 600 | .din0 ( wr_data_muxed_nibbles[75:72] ), | |
| 601 | .din1 ( wr_data_muxed_nibbles[79:76] ), | |
| 602 | .sel0 ( fail_over_mask[18] ), | |
| 603 | .sel1 ( fail_over_mask_l[18] ), | |
| 604 | .dout ( mux_io_data_out[79:76] )); | |
| 605 | ||
| 606 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_75_72 ( | |
| 607 | .din0 ( wr_data_muxed_nibbles[71:68] ), | |
| 608 | .din1 ( wr_data_muxed_nibbles[75:72] ), | |
| 609 | .sel0 ( fail_over_mask[17] ), | |
| 610 | .sel1 ( fail_over_mask_l[17] ), | |
| 611 | .dout ( mux_io_data_out[75:72] )); | |
| 612 | ||
| 613 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_71_68 ( | |
| 614 | .din0 ( wr_data_muxed_nibbles[67:64] ), | |
| 615 | .din1 ( wr_data_muxed_nibbles[71:68] ), | |
| 616 | .sel0 ( fail_over_mask[16] ), | |
| 617 | .sel1 ( fail_over_mask_l[16] ), | |
| 618 | .dout ( mux_io_data_out[71:68] )); | |
| 619 | ||
| 620 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_67_64 ( | |
| 621 | .din0 ( wr_data_muxed_nibbles[63:60] ), | |
| 622 | .din1 ( wr_data_muxed_nibbles[67:64] ), | |
| 623 | .sel0 ( fail_over_mask[15] ), | |
| 624 | .sel1 ( fail_over_mask_l[15] ), | |
| 625 | .dout ( mux_io_data_out[67:64] )); | |
| 626 | ||
| 627 | // sdram write data [63:0] | |
| 628 | ||
| 629 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_63_60 ( | |
| 630 | .din0 ( wr_data_muxed_nibbles[59:56] ), | |
| 631 | .din1 ( wr_data_muxed_nibbles[63:60] ), | |
| 632 | .sel0 ( fail_over_mask[14] ), | |
| 633 | .sel1 ( fail_over_mask_l[14] ), | |
| 634 | .dout ( mux_io_data_out[63:60] )); | |
| 635 | ||
| 636 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_59_56 ( | |
| 637 | .din0 ( wr_data_muxed_nibbles[55:52] ), | |
| 638 | .din1 ( wr_data_muxed_nibbles[59:56] ), | |
| 639 | .sel0 ( fail_over_mask[13] ), | |
| 640 | .sel1 ( fail_over_mask_l[13] ), | |
| 641 | .dout ( mux_io_data_out[59:56] )); | |
| 642 | ||
| 643 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_55_52 ( | |
| 644 | .din0 ( wr_data_muxed_nibbles[51:48] ), | |
| 645 | .din1 ( wr_data_muxed_nibbles[55:52] ), | |
| 646 | .sel0 ( fail_over_mask[12] ), | |
| 647 | .sel1 ( fail_over_mask_l[12] ), | |
| 648 | .dout ( mux_io_data_out[55:52] )); | |
| 649 | ||
| 650 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_51_48 ( | |
| 651 | .din0 ( wr_data_muxed_nibbles[47:44] ), | |
| 652 | .din1 ( wr_data_muxed_nibbles[51:48] ), | |
| 653 | .sel0 ( fail_over_mask[11] ), | |
| 654 | .sel1 ( fail_over_mask_l[11] ), | |
| 655 | .dout ( mux_io_data_out[51:48] )); | |
| 656 | ||
| 657 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_47_44 ( | |
| 658 | .din0 ( wr_data_muxed_nibbles[43:40] ), | |
| 659 | .din1 ( wr_data_muxed_nibbles[47:44] ), | |
| 660 | .sel0 ( fail_over_mask[10] ), | |
| 661 | .sel1 ( fail_over_mask_l[10] ), | |
| 662 | .dout ( mux_io_data_out[47:44] )); | |
| 663 | ||
| 664 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_43_40 ( | |
| 665 | .din0 ( wr_data_muxed_nibbles[39:36] ), | |
| 666 | .din1 ( wr_data_muxed_nibbles[43:40] ), | |
| 667 | .sel0 ( fail_over_mask[9] ), | |
| 668 | .sel1 ( fail_over_mask_l[9] ), | |
| 669 | .dout ( mux_io_data_out[43:40] )); | |
| 670 | ||
| 671 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_39_36 ( | |
| 672 | .din0 ( wr_data_muxed_nibbles[35:32] ), | |
| 673 | .din1 ( wr_data_muxed_nibbles[39:36] ), | |
| 674 | .sel0 ( fail_over_mask[8] ), | |
| 675 | .sel1 ( fail_over_mask_l[8] ), | |
| 676 | .dout ( mux_io_data_out[39:36] )); | |
| 677 | ||
| 678 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_35_32 ( | |
| 679 | .din0 ( wr_data_muxed_nibbles[31:28] ), | |
| 680 | .din1 ( wr_data_muxed_nibbles[35:32] ), | |
| 681 | .sel0 ( fail_over_mask[7] ), | |
| 682 | .sel1 ( fail_over_mask_l[7] ), | |
| 683 | .dout ( mux_io_data_out[35:32] )); | |
| 684 | ||
| 685 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_31_28 ( | |
| 686 | .din0 ( wr_data_muxed_nibbles[27:24] ), | |
| 687 | .din1 ( wr_data_muxed_nibbles[31:28] ), | |
| 688 | .sel0 ( fail_over_mask[6] ), | |
| 689 | .sel1 ( fail_over_mask_l[6] ), | |
| 690 | .dout ( mux_io_data_out[31:28] )); | |
| 691 | ||
| 692 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_27_24 ( | |
| 693 | .din0 ( wr_data_muxed_nibbles[23:20] ), | |
| 694 | .din1 ( wr_data_muxed_nibbles[27:24] ), | |
| 695 | .sel0 ( fail_over_mask[5] ), | |
| 696 | .sel1 ( fail_over_mask_l[5] ), | |
| 697 | .dout ( mux_io_data_out[27:24] )); | |
| 698 | ||
| 699 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_23_20 ( | |
| 700 | .din0 ( wr_data_muxed_nibbles[19:16] ), | |
| 701 | .din1 ( wr_data_muxed_nibbles[23:20] ), | |
| 702 | .sel0 ( fail_over_mask[4] ), | |
| 703 | .sel1 ( fail_over_mask_l[4] ), | |
| 704 | .dout ( mux_io_data_out[23:20] )); | |
| 705 | ||
| 706 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_19_16 ( | |
| 707 | .din0 ( wr_data_muxed_nibbles[15:12] ), | |
| 708 | .din1 ( wr_data_muxed_nibbles[19:16] ), | |
| 709 | .sel0 ( fail_over_mask[3] ), | |
| 710 | .sel1 ( fail_over_mask_l[3] ), | |
| 711 | .dout ( mux_io_data_out[19:16] )); | |
| 712 | ||
| 713 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_15_12 ( | |
| 714 | .din0 ( wr_data_muxed_nibbles[11:8] ), | |
| 715 | .din1 ( wr_data_muxed_nibbles[15:12] ), | |
| 716 | .sel0 ( fail_over_mask[2] ), | |
| 717 | .sel1 ( fail_over_mask_l[2] ), | |
| 718 | .dout ( mux_io_data_out[15:12] )); | |
| 719 | ||
| 720 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_11_8 ( | |
| 721 | .din0 ( wr_data_muxed_nibbles[7:4] ), | |
| 722 | .din1 ( wr_data_muxed_nibbles[11:8] ), | |
| 723 | .sel0 ( fail_over_mask[1] ), | |
| 724 | .sel1 ( fail_over_mask_l[1] ), | |
| 725 | .dout ( mux_io_data_out[11:8] )); | |
| 726 | ||
| 727 | mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 u_mux_data_out_7_4 ( | |
| 728 | .din0 ( wr_data_muxed_nibbles[3:0] ), | |
| 729 | .din1 ( wr_data_muxed_nibbles[7:4] ), | |
| 730 | .sel0 ( fail_over_mask[0] ), | |
| 731 | .sel1 ( fail_over_mask_l[0] ), | |
| 732 | .dout ( mux_io_data_out[7:4] )); | |
| 733 | ||
| 734 | ||
| 735 | // Data out reg to SDRAM. Multiplex high/low order data to support 1DIMM mode. | |
| 736 | ||
| 737 | mcu_wrdp_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 u_io_data_127_64 ( | |
| 738 | .scan_in(u_io_data_127_64_scanin), | |
| 739 | .scan_out(u_io_data_127_64_scanout), | |
| 740 | .clk ( drl2clk), | |
| 741 | .en ( 1'b1 ), | |
| 742 | .din0 ( mux_io_data_out[135:72] ), | |
| 743 | .din1 ( { mux_io_data_out[63:4], wr_data_muxed_nibbles[3:0] } ), | |
| 744 | .sel0 ( io_wdata_sel[0] ), // high order data | |
| 745 | .sel1 ( io_wdata_sel[1] ), // low order data | |
| 746 | .dout ( mcu_io_data_out[135:72] ), | |
| 747 | .se(se), | |
| 748 | .siclk(siclk), | |
| 749 | .soclk(soclk), | |
| 750 | .pce_ov(pce_ov), | |
| 751 | .stop(stop)); | |
| 752 | ||
| 753 | mcu_wrdp_dp_msff_macro__stack_64c__width_64 u_io_data_63_0 ( | |
| 754 | .scan_in(u_io_data_63_0_scanin), | |
| 755 | .scan_out(u_io_data_63_0_scanout), | |
| 756 | .clk ( drl2clk), | |
| 757 | .en ( 1'b1 ), | |
| 758 | .din ( { mux_io_data_out[63:4], wr_data_muxed_nibbles[3:0] } ), | |
| 759 | .dout ( mcu_io_data_out[63:0] ), | |
| 760 | .se(se), | |
| 761 | .siclk(siclk), | |
| 762 | .soclk(soclk), | |
| 763 | .pce_ov(pce_ov), | |
| 764 | .stop(stop)); | |
| 765 | ||
| 766 | ||
| 767 | // ECC out reg to SDRAM. Multiplex high/low order ECC to support Single Channel mode. | |
| 768 | ||
| 769 | mcu_wrdp_dp_mux_macro__mux_aonpe__ports_2__stack_32c__width_16 u_io_muxecc_15_0 ( | |
| 770 | .din0 ( { mux_io_data_out[143:136], mux_io_data_out[71:64] } ), | |
| 771 | .din1 ( { mux_io_data_out[71:64], {8 {1'b0}} } ), | |
| 772 | .sel0 ( io_wdata_sel[0] ), // high order ECC[7:0] | |
| 773 | .sel1 ( io_wdata_sel[1] ), // low order ECC[15:8] | |
| 774 | .dout ( mux_io_ecc_out[15:0] )); | |
| 775 | ||
| 776 | ||
| 777 | mcu_wrdp_dp_msff_macro__stack_32c__width_32 u_io_ecc_15_0 ( | |
| 778 | .scan_in(u_io_ecc_15_0_scanin), | |
| 779 | .scan_out(u_io_ecc_15_0_scanout), | |
| 780 | .clk ( drl2clk), | |
| 781 | .en ( 1'b1 ), | |
| 782 | .din ( { {4{lfsr_in[0]}},lfsr_in[11:0], mux_io_ecc_out[15:0] } ), | |
| 783 | .dout ( { lfsr_out_0[3:0], lfsr_out[11:0], mcu_io_data_out[143:136], mcu_io_data_out[71:64] } ), | |
| 784 | .se(se), | |
| 785 | .siclk(siclk), | |
| 786 | .soclk(soclk), | |
| 787 | .pce_ov(pce_ov), | |
| 788 | .stop(stop)); | |
| 789 | ||
| 790 | ||
| 791 | ||
| 792 | // fixscan start: | |
| 793 | assign u_wdqrf00_data_scanin = scan_in ; | |
| 794 | assign u_wdqrf01_data_scanin = u_wdqrf00_data_scanout ; | |
| 795 | assign u_wdqrf10_data_scanin = u_wdqrf01_data_scanout ; | |
| 796 | assign u_wdqrf11_data_scanin = u_wdqrf10_data_scanout ; | |
| 797 | assign u_scrub_wdata_511_448_scanin = u_wdqrf11_data_scanout ; | |
| 798 | assign u_scrub_wdata_447_384_scanin = u_scrub_wdata_511_448_scanout; | |
| 799 | assign u_scrub_wdata_383_320_scanin = u_scrub_wdata_447_384_scanout; | |
| 800 | assign u_scrub_wdata_319_256_scanin = u_scrub_wdata_383_320_scanout; | |
| 801 | assign u_scrub_wdata_255_192_scanin = u_scrub_wdata_319_256_scanout; | |
| 802 | assign u_scrub_wdata_191_128_scanin = u_scrub_wdata_255_192_scanout; | |
| 803 | assign u_scrub_wdata_127_64_scanin = u_scrub_wdata_191_128_scanout; | |
| 804 | assign u_scrub_wdata_63_0_scanin = u_scrub_wdata_127_64_scanout; | |
| 805 | assign u_wdata_127_64_scanin = u_scrub_wdata_63_0_scanout; | |
| 806 | assign u_wdata_63_0_scanin = u_wdata_127_64_scanout ; | |
| 807 | assign u_io_data_127_64_scanin = u_wdata_63_0_scanout ; | |
| 808 | assign u_io_data_63_0_scanin = u_io_data_127_64_scanout ; | |
| 809 | assign u_io_ecc_15_0_scanin = u_io_data_63_0_scanout ; | |
| 810 | assign scan_out = u_io_ecc_15_0_scanout ; | |
| 811 | // fixscan end: | |
| 812 | endmodule // mcu_wrdp_dp | |
| 813 | ||
| 814 | ||
| 815 | // | |
| 816 | // invert macro | |
| 817 | // | |
| 818 | // | |
| 819 | ||
| 820 | ||
| 821 | ||
| 822 | ||
| 823 | ||
| 824 | module mcu_wrdp_dp_inv_macro__width_3 ( | |
| 825 | din, | |
| 826 | dout); | |
| 827 | input [2:0] din; | |
| 828 | output [2:0] dout; | |
| 829 | ||
| 830 | ||
| 831 | ||
| 832 | ||
| 833 | ||
| 834 | ||
| 835 | inv #(3) d0_0 ( | |
| 836 | .in(din[2:0]), | |
| 837 | .out(dout[2:0]) | |
| 838 | ); | |
| 839 | ||
| 840 | ||
| 841 | ||
| 842 | ||
| 843 | ||
| 844 | ||
| 845 | ||
| 846 | ||
| 847 | ||
| 848 | endmodule | |
| 849 | ||
| 850 | ||
| 851 | ||
| 852 | ||
| 853 | ||
| 854 | // | |
| 855 | // nor macro for ports = 2,3 | |
| 856 | // | |
| 857 | // | |
| 858 | ||
| 859 | ||
| 860 | ||
| 861 | ||
| 862 | ||
| 863 | module mcu_wrdp_dp_nor_macro ( | |
| 864 | din0, | |
| 865 | din1, | |
| 866 | dout); | |
| 867 | input [0:0] din0; | |
| 868 | input [0:0] din1; | |
| 869 | output [0:0] dout; | |
| 870 | ||
| 871 | ||
| 872 | ||
| 873 | ||
| 874 | ||
| 875 | ||
| 876 | nor2 #(1) d0_0 ( | |
| 877 | .in0(din0[0:0]), | |
| 878 | .in1(din1[0:0]), | |
| 879 | .out(dout[0:0]) | |
| 880 | ); | |
| 881 | ||
| 882 | ||
| 883 | ||
| 884 | ||
| 885 | ||
| 886 | ||
| 887 | ||
| 888 | endmodule | |
| 889 | ||
| 890 | ||
| 891 | ||
| 892 | ||
| 893 | ||
| 894 | ||
| 895 | ||
| 896 | ||
| 897 | ||
| 898 | // any PARAMS parms go into naming of macro | |
| 899 | ||
| 900 | module mcu_wrdp_dp_msff_macro__stack_64c__width_64 ( | |
| 901 | din, | |
| 902 | clk, | |
| 903 | en, | |
| 904 | se, | |
| 905 | scan_in, | |
| 906 | siclk, | |
| 907 | soclk, | |
| 908 | pce_ov, | |
| 909 | stop, | |
| 910 | dout, | |
| 911 | scan_out); | |
| 912 | wire l1clk; | |
| 913 | wire siclk_out; | |
| 914 | wire soclk_out; | |
| 915 | wire [62:0] so; | |
| 916 | ||
| 917 | input [63:0] din; | |
| 918 | ||
| 919 | ||
| 920 | input clk; | |
| 921 | input en; | |
| 922 | input se; | |
| 923 | input scan_in; | |
| 924 | input siclk; | |
| 925 | input soclk; | |
| 926 | input pce_ov; | |
| 927 | input stop; | |
| 928 | ||
| 929 | ||
| 930 | ||
| 931 | output [63:0] dout; | |
| 932 | ||
| 933 | ||
| 934 | output scan_out; | |
| 935 | ||
| 936 | ||
| 937 | ||
| 938 | ||
| 939 | cl_dp1_l1hdr_8x c0_0 ( | |
| 940 | .l2clk(clk), | |
| 941 | .pce(en), | |
| 942 | .aclk(siclk), | |
| 943 | .bclk(soclk), | |
| 944 | .l1clk(l1clk), | |
| 945 | .se(se), | |
| 946 | .pce_ov(pce_ov), | |
| 947 | .stop(stop), | |
| 948 | .siclk_out(siclk_out), | |
| 949 | .soclk_out(soclk_out) | |
| 950 | ); | |
| 951 | dff #(64) d0_0 ( | |
| 952 | .l1clk(l1clk), | |
| 953 | .siclk(siclk_out), | |
| 954 | .soclk(soclk_out), | |
| 955 | .d(din[63:0]), | |
| 956 | .si({scan_in,so[62:0]}), | |
| 957 | .so({so[62:0],scan_out}), | |
| 958 | .q(dout[63:0]) | |
| 959 | ); | |
| 960 | ||
| 961 | ||
| 962 | ||
| 963 | ||
| 964 | ||
| 965 | ||
| 966 | ||
| 967 | ||
| 968 | ||
| 969 | ||
| 970 | ||
| 971 | ||
| 972 | ||
| 973 | ||
| 974 | ||
| 975 | ||
| 976 | ||
| 977 | ||
| 978 | ||
| 979 | ||
| 980 | endmodule | |
| 981 | ||
| 982 | ||
| 983 | ||
| 984 | ||
| 985 | ||
| 986 | ||
| 987 | ||
| 988 | ||
| 989 | ||
| 990 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 991 | // also for pass-gate with decoder | |
| 992 | ||
| 993 | ||
| 994 | ||
| 995 | ||
| 996 | ||
| 997 | // any PARAMS parms go into naming of macro | |
| 998 | ||
| 999 | module mcu_wrdp_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 ( | |
| 1000 | din0, | |
| 1001 | sel0, | |
| 1002 | din1, | |
| 1003 | sel1, | |
| 1004 | din2, | |
| 1005 | sel2, | |
| 1006 | din3, | |
| 1007 | sel3, | |
| 1008 | dout); | |
| 1009 | wire buffout0; | |
| 1010 | wire buffout1; | |
| 1011 | wire buffout2; | |
| 1012 | wire buffout3; | |
| 1013 | ||
| 1014 | input [63:0] din0; | |
| 1015 | input sel0; | |
| 1016 | input [63:0] din1; | |
| 1017 | input sel1; | |
| 1018 | input [63:0] din2; | |
| 1019 | input sel2; | |
| 1020 | input [63:0] din3; | |
| 1021 | input sel3; | |
| 1022 | output [63:0] dout; | |
| 1023 | ||
| 1024 | ||
| 1025 | ||
| 1026 | ||
| 1027 | ||
| 1028 | cl_dp1_muxbuff4_8x c0_0 ( | |
| 1029 | .in0(sel0), | |
| 1030 | .in1(sel1), | |
| 1031 | .in2(sel2), | |
| 1032 | .in3(sel3), | |
| 1033 | .out0(buffout0), | |
| 1034 | .out1(buffout1), | |
| 1035 | .out2(buffout2), | |
| 1036 | .out3(buffout3) | |
| 1037 | ); | |
| 1038 | mux4s #(64) d0_0 ( | |
| 1039 | .sel0(buffout0), | |
| 1040 | .sel1(buffout1), | |
| 1041 | .sel2(buffout2), | |
| 1042 | .sel3(buffout3), | |
| 1043 | .in0(din0[63:0]), | |
| 1044 | .in1(din1[63:0]), | |
| 1045 | .in2(din2[63:0]), | |
| 1046 | .in3(din3[63:0]), | |
| 1047 | .dout(dout[63:0]) | |
| 1048 | ); | |
| 1049 | ||
| 1050 | ||
| 1051 | ||
| 1052 | ||
| 1053 | ||
| 1054 | ||
| 1055 | ||
| 1056 | ||
| 1057 | ||
| 1058 | ||
| 1059 | ||
| 1060 | ||
| 1061 | ||
| 1062 | endmodule | |
| 1063 | ||
| 1064 | ||
| 1065 | ||
| 1066 | ||
| 1067 | ||
| 1068 | ||
| 1069 | // any PARAMS parms go into naming of macro | |
| 1070 | ||
| 1071 | module mcu_wrdp_dp_msff_macro__mux_aonpe__ports_4__stack_64c__width_64 ( | |
| 1072 | din0, | |
| 1073 | sel0, | |
| 1074 | din1, | |
| 1075 | sel1, | |
| 1076 | din2, | |
| 1077 | sel2, | |
| 1078 | din3, | |
| 1079 | sel3, | |
| 1080 | clk, | |
| 1081 | en, | |
| 1082 | se, | |
| 1083 | scan_in, | |
| 1084 | siclk, | |
| 1085 | soclk, | |
| 1086 | pce_ov, | |
| 1087 | stop, | |
| 1088 | dout, | |
| 1089 | scan_out); | |
| 1090 | wire buffout0; | |
| 1091 | wire buffout1; | |
| 1092 | wire buffout2; | |
| 1093 | wire buffout3; | |
| 1094 | wire [63:0] muxout; | |
| 1095 | wire l1clk; | |
| 1096 | wire siclk_out; | |
| 1097 | wire soclk_out; | |
| 1098 | wire [62:0] so; | |
| 1099 | ||
| 1100 | input [63:0] din0; | |
| 1101 | input sel0; | |
| 1102 | input [63:0] din1; | |
| 1103 | input sel1; | |
| 1104 | input [63:0] din2; | |
| 1105 | input sel2; | |
| 1106 | input [63:0] din3; | |
| 1107 | input sel3; | |
| 1108 | ||
| 1109 | ||
| 1110 | input clk; | |
| 1111 | input en; | |
| 1112 | input se; | |
| 1113 | input scan_in; | |
| 1114 | input siclk; | |
| 1115 | input soclk; | |
| 1116 | input pce_ov; | |
| 1117 | input stop; | |
| 1118 | ||
| 1119 | ||
| 1120 | ||
| 1121 | output [63:0] dout; | |
| 1122 | ||
| 1123 | ||
| 1124 | output scan_out; | |
| 1125 | ||
| 1126 | ||
| 1127 | ||
| 1128 | ||
| 1129 | cl_dp1_muxbuff4_8x c1_0 ( | |
| 1130 | .in0(sel0), | |
| 1131 | .in1(sel1), | |
| 1132 | .in2(sel2), | |
| 1133 | .in3(sel3), | |
| 1134 | .out0(buffout0), | |
| 1135 | .out1(buffout1), | |
| 1136 | .out2(buffout2), | |
| 1137 | .out3(buffout3) | |
| 1138 | ); | |
| 1139 | mux4s #(64) d1_0 ( | |
| 1140 | .sel0(buffout0), | |
| 1141 | .sel1(buffout1), | |
| 1142 | .sel2(buffout2), | |
| 1143 | .sel3(buffout3), | |
| 1144 | .in0(din0[63:0]), | |
| 1145 | .in1(din1[63:0]), | |
| 1146 | .in2(din2[63:0]), | |
| 1147 | .in3(din3[63:0]), | |
| 1148 | .dout(muxout[63:0]) | |
| 1149 | ); | |
| 1150 | cl_dp1_l1hdr_8x c0_0 ( | |
| 1151 | .l2clk(clk), | |
| 1152 | .pce(en), | |
| 1153 | .aclk(siclk), | |
| 1154 | .bclk(soclk), | |
| 1155 | .l1clk(l1clk), | |
| 1156 | .se(se), | |
| 1157 | .pce_ov(pce_ov), | |
| 1158 | .stop(stop), | |
| 1159 | .siclk_out(siclk_out), | |
| 1160 | .soclk_out(soclk_out) | |
| 1161 | ); | |
| 1162 | dff #(64) d0_0 ( | |
| 1163 | .l1clk(l1clk), | |
| 1164 | .siclk(siclk_out), | |
| 1165 | .soclk(soclk_out), | |
| 1166 | .d(muxout[63:0]), | |
| 1167 | .si({scan_in,so[62:0]}), | |
| 1168 | .so({so[62:0],scan_out}), | |
| 1169 | .q(dout[63:0]) | |
| 1170 | ); | |
| 1171 | ||
| 1172 | ||
| 1173 | ||
| 1174 | ||
| 1175 | ||
| 1176 | endmodule | |
| 1177 | ||
| 1178 | ||
| 1179 | ||
| 1180 | // | |
| 1181 | // buff macro | |
| 1182 | // | |
| 1183 | // | |
| 1184 | ||
| 1185 | ||
| 1186 | ||
| 1187 | ||
| 1188 | ||
| 1189 | module mcu_wrdp_dp_buff_macro__stack_64c__width_64 ( | |
| 1190 | din, | |
| 1191 | dout); | |
| 1192 | input [63:0] din; | |
| 1193 | output [63:0] dout; | |
| 1194 | ||
| 1195 | ||
| 1196 | ||
| 1197 | ||
| 1198 | ||
| 1199 | ||
| 1200 | buff #(64) d0_0 ( | |
| 1201 | .in(din[63:0]), | |
| 1202 | .out(dout[63:0]) | |
| 1203 | ); | |
| 1204 | ||
| 1205 | ||
| 1206 | ||
| 1207 | ||
| 1208 | ||
| 1209 | ||
| 1210 | ||
| 1211 | ||
| 1212 | endmodule | |
| 1213 | ||
| 1214 | ||
| 1215 | ||
| 1216 | ||
| 1217 | ||
| 1218 | // | |
| 1219 | // buff macro | |
| 1220 | // | |
| 1221 | // | |
| 1222 | ||
| 1223 | ||
| 1224 | ||
| 1225 | ||
| 1226 | ||
| 1227 | module mcu_wrdp_dp_buff_macro__stack_2l__width_2 ( | |
| 1228 | din, | |
| 1229 | dout); | |
| 1230 | input [1:0] din; | |
| 1231 | output [1:0] dout; | |
| 1232 | ||
| 1233 | ||
| 1234 | ||
| 1235 | ||
| 1236 | ||
| 1237 | ||
| 1238 | buff #(2) d0_0 ( | |
| 1239 | .in(din[1:0]), | |
| 1240 | .out(dout[1:0]) | |
| 1241 | ); | |
| 1242 | ||
| 1243 | ||
| 1244 | ||
| 1245 | ||
| 1246 | ||
| 1247 | ||
| 1248 | ||
| 1249 | ||
| 1250 | endmodule | |
| 1251 | ||
| 1252 | ||
| 1253 | ||
| 1254 | ||
| 1255 | ||
| 1256 | // | |
| 1257 | // xor macro for ports = 2,3 | |
| 1258 | // | |
| 1259 | // | |
| 1260 | ||
| 1261 | ||
| 1262 | ||
| 1263 | ||
| 1264 | ||
| 1265 | module mcu_wrdp_dp_xor_macro__dxor_8x__ports_3__width_1 ( | |
| 1266 | din0, | |
| 1267 | din1, | |
| 1268 | din2, | |
| 1269 | dout); | |
| 1270 | input [0:0] din0; | |
| 1271 | input [0:0] din1; | |
| 1272 | input [0:0] din2; | |
| 1273 | output [0:0] dout; | |
| 1274 | ||
| 1275 | ||
| 1276 | ||
| 1277 | ||
| 1278 | ||
| 1279 | xor3 #(1) d0_0 ( | |
| 1280 | .in0(din0[0:0]), | |
| 1281 | .in1(din1[0:0]), | |
| 1282 | .in2(din2[0:0]), | |
| 1283 | .out(dout[0:0]) | |
| 1284 | ); | |
| 1285 | ||
| 1286 | ||
| 1287 | ||
| 1288 | ||
| 1289 | ||
| 1290 | ||
| 1291 | ||
| 1292 | ||
| 1293 | endmodule | |
| 1294 | ||
| 1295 | ||
| 1296 | ||
| 1297 | ||
| 1298 | ||
| 1299 | // | |
| 1300 | // buff macro | |
| 1301 | // | |
| 1302 | // | |
| 1303 | ||
| 1304 | ||
| 1305 | ||
| 1306 | ||
| 1307 | ||
| 1308 | module mcu_wrdp_dp_buff_macro__stack_16l__width_16 ( | |
| 1309 | din, | |
| 1310 | dout); | |
| 1311 | input [15:0] din; | |
| 1312 | output [15:0] dout; | |
| 1313 | ||
| 1314 | ||
| 1315 | ||
| 1316 | ||
| 1317 | ||
| 1318 | ||
| 1319 | buff #(16) d0_0 ( | |
| 1320 | .in(din[15:0]), | |
| 1321 | .out(dout[15:0]) | |
| 1322 | ); | |
| 1323 | ||
| 1324 | ||
| 1325 | ||
| 1326 | ||
| 1327 | ||
| 1328 | ||
| 1329 | ||
| 1330 | ||
| 1331 | endmodule | |
| 1332 | ||
| 1333 | ||
| 1334 | ||
| 1335 | ||
| 1336 | ||
| 1337 | // | |
| 1338 | // and macro for ports = 2,3,4 | |
| 1339 | // | |
| 1340 | // | |
| 1341 | ||
| 1342 | ||
| 1343 | ||
| 1344 | ||
| 1345 | ||
| 1346 | module mcu_wrdp_dp_and_macro__ports_2__stack_16r__width_16 ( | |
| 1347 | din0, | |
| 1348 | din1, | |
| 1349 | dout); | |
| 1350 | input [15:0] din0; | |
| 1351 | input [15:0] din1; | |
| 1352 | output [15:0] dout; | |
| 1353 | ||
| 1354 | ||
| 1355 | ||
| 1356 | ||
| 1357 | ||
| 1358 | ||
| 1359 | and2 #(16) d0_0 ( | |
| 1360 | .in0(din0[15:0]), | |
| 1361 | .in1(din1[15:0]), | |
| 1362 | .out(dout[15:0]) | |
| 1363 | ); | |
| 1364 | ||
| 1365 | ||
| 1366 | ||
| 1367 | ||
| 1368 | ||
| 1369 | ||
| 1370 | ||
| 1371 | ||
| 1372 | ||
| 1373 | endmodule | |
| 1374 | ||
| 1375 | ||
| 1376 | ||
| 1377 | ||
| 1378 | ||
| 1379 | // | |
| 1380 | // nand macro for ports = 2,3,4 | |
| 1381 | // | |
| 1382 | // | |
| 1383 | ||
| 1384 | ||
| 1385 | ||
| 1386 | ||
| 1387 | ||
| 1388 | module mcu_wrdp_dp_nand_macro__width_48 ( | |
| 1389 | din0, | |
| 1390 | din1, | |
| 1391 | dout); | |
| 1392 | input [47:0] din0; | |
| 1393 | input [47:0] din1; | |
| 1394 | output [47:0] dout; | |
| 1395 | ||
| 1396 | ||
| 1397 | ||
| 1398 | ||
| 1399 | ||
| 1400 | ||
| 1401 | nand2 #(48) d0_0 ( | |
| 1402 | .in0(din0[47:0]), | |
| 1403 | .in1(din1[47:0]), | |
| 1404 | .out(dout[47:0]) | |
| 1405 | ); | |
| 1406 | ||
| 1407 | ||
| 1408 | ||
| 1409 | ||
| 1410 | ||
| 1411 | ||
| 1412 | ||
| 1413 | ||
| 1414 | ||
| 1415 | endmodule | |
| 1416 | ||
| 1417 | ||
| 1418 | ||
| 1419 | ||
| 1420 | ||
| 1421 | // | |
| 1422 | // xor macro for ports = 2,3 | |
| 1423 | // | |
| 1424 | // | |
| 1425 | ||
| 1426 | ||
| 1427 | ||
| 1428 | ||
| 1429 | ||
| 1430 | module mcu_wrdp_dp_xor_macro__ports_2__width_1 ( | |
| 1431 | din0, | |
| 1432 | din1, | |
| 1433 | dout); | |
| 1434 | input [0:0] din0; | |
| 1435 | input [0:0] din1; | |
| 1436 | output [0:0] dout; | |
| 1437 | ||
| 1438 | ||
| 1439 | ||
| 1440 | ||
| 1441 | ||
| 1442 | xor2 #(1) d0_0 ( | |
| 1443 | .in0(din0[0:0]), | |
| 1444 | .in1(din1[0:0]), | |
| 1445 | .out(dout[0:0]) | |
| 1446 | ); | |
| 1447 | ||
| 1448 | ||
| 1449 | ||
| 1450 | ||
| 1451 | ||
| 1452 | ||
| 1453 | ||
| 1454 | ||
| 1455 | endmodule | |
| 1456 | ||
| 1457 | ||
| 1458 | ||
| 1459 | ||
| 1460 | ||
| 1461 | // | |
| 1462 | // xor macro for ports = 2,3 | |
| 1463 | // | |
| 1464 | // | |
| 1465 | ||
| 1466 | ||
| 1467 | ||
| 1468 | ||
| 1469 | ||
| 1470 | module mcu_wrdp_dp_xor_macro__ports_3__width_1 ( | |
| 1471 | din0, | |
| 1472 | din1, | |
| 1473 | din2, | |
| 1474 | dout); | |
| 1475 | input [0:0] din0; | |
| 1476 | input [0:0] din1; | |
| 1477 | input [0:0] din2; | |
| 1478 | output [0:0] dout; | |
| 1479 | ||
| 1480 | ||
| 1481 | ||
| 1482 | ||
| 1483 | ||
| 1484 | xor3 #(1) d0_0 ( | |
| 1485 | .in0(din0[0:0]), | |
| 1486 | .in1(din1[0:0]), | |
| 1487 | .in2(din2[0:0]), | |
| 1488 | .out(dout[0:0]) | |
| 1489 | ); | |
| 1490 | ||
| 1491 | ||
| 1492 | ||
| 1493 | ||
| 1494 | ||
| 1495 | ||
| 1496 | ||
| 1497 | ||
| 1498 | endmodule | |
| 1499 | ||
| 1500 | ||
| 1501 | ||
| 1502 | ||
| 1503 | ||
| 1504 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1505 | // also for pass-gate with decoder | |
| 1506 | ||
| 1507 | ||
| 1508 | ||
| 1509 | ||
| 1510 | ||
| 1511 | // any PARAMS parms go into naming of macro | |
| 1512 | ||
| 1513 | module mcu_wrdp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_4 ( | |
| 1514 | din0, | |
| 1515 | sel0, | |
| 1516 | din1, | |
| 1517 | sel1, | |
| 1518 | dout); | |
| 1519 | input [3:0] din0; | |
| 1520 | input sel0; | |
| 1521 | input [3:0] din1; | |
| 1522 | input sel1; | |
| 1523 | output [3:0] dout; | |
| 1524 | ||
| 1525 | ||
| 1526 | ||
| 1527 | ||
| 1528 | ||
| 1529 | mux2s #(4) d0_0 ( | |
| 1530 | .sel0(sel0), | |
| 1531 | .sel1(sel1), | |
| 1532 | .in0(din0[3:0]), | |
| 1533 | .in1(din1[3:0]), | |
| 1534 | .dout(dout[3:0]) | |
| 1535 | ); | |
| 1536 | ||
| 1537 | ||
| 1538 | ||
| 1539 | ||
| 1540 | ||
| 1541 | ||
| 1542 | ||
| 1543 | ||
| 1544 | ||
| 1545 | ||
| 1546 | ||
| 1547 | ||
| 1548 | ||
| 1549 | endmodule | |
| 1550 | ||
| 1551 | ||
| 1552 | ||
| 1553 | ||
| 1554 | ||
| 1555 | ||
| 1556 | // any PARAMS parms go into naming of macro | |
| 1557 | ||
| 1558 | module mcu_wrdp_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 ( | |
| 1559 | din0, | |
| 1560 | sel0, | |
| 1561 | din1, | |
| 1562 | sel1, | |
| 1563 | clk, | |
| 1564 | en, | |
| 1565 | se, | |
| 1566 | scan_in, | |
| 1567 | siclk, | |
| 1568 | soclk, | |
| 1569 | pce_ov, | |
| 1570 | stop, | |
| 1571 | dout, | |
| 1572 | scan_out); | |
| 1573 | wire buffout0; | |
| 1574 | wire buffout1; | |
| 1575 | wire [63:0] muxout; | |
| 1576 | wire l1clk; | |
| 1577 | wire siclk_out; | |
| 1578 | wire soclk_out; | |
| 1579 | wire [62:0] so; | |
| 1580 | ||
| 1581 | input [63:0] din0; | |
| 1582 | input sel0; | |
| 1583 | input [63:0] din1; | |
| 1584 | input sel1; | |
| 1585 | ||
| 1586 | ||
| 1587 | input clk; | |
| 1588 | input en; | |
| 1589 | input se; | |
| 1590 | input scan_in; | |
| 1591 | input siclk; | |
| 1592 | input soclk; | |
| 1593 | input pce_ov; | |
| 1594 | input stop; | |
| 1595 | ||
| 1596 | ||
| 1597 | ||
| 1598 | output [63:0] dout; | |
| 1599 | ||
| 1600 | ||
| 1601 | output scan_out; | |
| 1602 | ||
| 1603 | ||
| 1604 | ||
| 1605 | ||
| 1606 | cl_dp1_muxbuff2_8x c1_0 ( | |
| 1607 | .in0(sel0), | |
| 1608 | .in1(sel1), | |
| 1609 | .out0(buffout0), | |
| 1610 | .out1(buffout1) | |
| 1611 | ); | |
| 1612 | mux2s #(64) d1_0 ( | |
| 1613 | .sel0(buffout0), | |
| 1614 | .sel1(buffout1), | |
| 1615 | .in0(din0[63:0]), | |
| 1616 | .in1(din1[63:0]), | |
| 1617 | .dout(muxout[63:0]) | |
| 1618 | ); | |
| 1619 | cl_dp1_l1hdr_8x c0_0 ( | |
| 1620 | .l2clk(clk), | |
| 1621 | .pce(en), | |
| 1622 | .aclk(siclk), | |
| 1623 | .bclk(soclk), | |
| 1624 | .l1clk(l1clk), | |
| 1625 | .se(se), | |
| 1626 | .pce_ov(pce_ov), | |
| 1627 | .stop(stop), | |
| 1628 | .siclk_out(siclk_out), | |
| 1629 | .soclk_out(soclk_out) | |
| 1630 | ); | |
| 1631 | dff #(64) d0_0 ( | |
| 1632 | .l1clk(l1clk), | |
| 1633 | .siclk(siclk_out), | |
| 1634 | .soclk(soclk_out), | |
| 1635 | .d(muxout[63:0]), | |
| 1636 | .si({scan_in,so[62:0]}), | |
| 1637 | .so({so[62:0],scan_out}), | |
| 1638 | .q(dout[63:0]) | |
| 1639 | ); | |
| 1640 | ||
| 1641 | ||
| 1642 | ||
| 1643 | ||
| 1644 | ||
| 1645 | ||
| 1646 | ||
| 1647 | ||
| 1648 | ||
| 1649 | ||
| 1650 | ||
| 1651 | ||
| 1652 | ||
| 1653 | ||
| 1654 | ||
| 1655 | ||
| 1656 | ||
| 1657 | ||
| 1658 | ||
| 1659 | ||
| 1660 | endmodule | |
| 1661 | ||
| 1662 | ||
| 1663 | ||
| 1664 | ||
| 1665 | ||
| 1666 | ||
| 1667 | ||
| 1668 | ||
| 1669 | ||
| 1670 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1671 | // also for pass-gate with decoder | |
| 1672 | ||
| 1673 | ||
| 1674 | ||
| 1675 | ||
| 1676 | ||
| 1677 | // any PARAMS parms go into naming of macro | |
| 1678 | ||
| 1679 | module mcu_wrdp_dp_mux_macro__mux_aonpe__ports_2__stack_32c__width_16 ( | |
| 1680 | din0, | |
| 1681 | sel0, | |
| 1682 | din1, | |
| 1683 | sel1, | |
| 1684 | dout); | |
| 1685 | wire buffout0; | |
| 1686 | wire buffout1; | |
| 1687 | ||
| 1688 | input [15:0] din0; | |
| 1689 | input sel0; | |
| 1690 | input [15:0] din1; | |
| 1691 | input sel1; | |
| 1692 | output [15:0] dout; | |
| 1693 | ||
| 1694 | ||
| 1695 | ||
| 1696 | ||
| 1697 | ||
| 1698 | cl_dp1_muxbuff2_8x c0_0 ( | |
| 1699 | .in0(sel0), | |
| 1700 | .in1(sel1), | |
| 1701 | .out0(buffout0), | |
| 1702 | .out1(buffout1) | |
| 1703 | ); | |
| 1704 | mux2s #(16) d0_0 ( | |
| 1705 | .sel0(buffout0), | |
| 1706 | .sel1(buffout1), | |
| 1707 | .in0(din0[15:0]), | |
| 1708 | .in1(din1[15:0]), | |
| 1709 | .dout(dout[15:0]) | |
| 1710 | ); | |
| 1711 | ||
| 1712 | ||
| 1713 | ||
| 1714 | ||
| 1715 | ||
| 1716 | ||
| 1717 | ||
| 1718 | ||
| 1719 | ||
| 1720 | ||
| 1721 | ||
| 1722 | ||
| 1723 | ||
| 1724 | endmodule | |
| 1725 | ||
| 1726 | ||
| 1727 | ||
| 1728 | ||
| 1729 | ||
| 1730 | ||
| 1731 | // any PARAMS parms go into naming of macro | |
| 1732 | ||
| 1733 | module mcu_wrdp_dp_msff_macro__stack_32c__width_32 ( | |
| 1734 | din, | |
| 1735 | clk, | |
| 1736 | en, | |
| 1737 | se, | |
| 1738 | scan_in, | |
| 1739 | siclk, | |
| 1740 | soclk, | |
| 1741 | pce_ov, | |
| 1742 | stop, | |
| 1743 | dout, | |
| 1744 | scan_out); | |
| 1745 | wire l1clk; | |
| 1746 | wire siclk_out; | |
| 1747 | wire soclk_out; | |
| 1748 | wire [30:0] so; | |
| 1749 | ||
| 1750 | input [31:0] din; | |
| 1751 | ||
| 1752 | ||
| 1753 | input clk; | |
| 1754 | input en; | |
| 1755 | input se; | |
| 1756 | input scan_in; | |
| 1757 | input siclk; | |
| 1758 | input soclk; | |
| 1759 | input pce_ov; | |
| 1760 | input stop; | |
| 1761 | ||
| 1762 | ||
| 1763 | ||
| 1764 | output [31:0] dout; | |
| 1765 | ||
| 1766 | ||
| 1767 | output scan_out; | |
| 1768 | ||
| 1769 | ||
| 1770 | ||
| 1771 | ||
| 1772 | cl_dp1_l1hdr_8x c0_0 ( | |
| 1773 | .l2clk(clk), | |
| 1774 | .pce(en), | |
| 1775 | .aclk(siclk), | |
| 1776 | .bclk(soclk), | |
| 1777 | .l1clk(l1clk), | |
| 1778 | .se(se), | |
| 1779 | .pce_ov(pce_ov), | |
| 1780 | .stop(stop), | |
| 1781 | .siclk_out(siclk_out), | |
| 1782 | .soclk_out(soclk_out) | |
| 1783 | ); | |
| 1784 | dff #(32) d0_0 ( | |
| 1785 | .l1clk(l1clk), | |
| 1786 | .siclk(siclk_out), | |
| 1787 | .soclk(soclk_out), | |
| 1788 | .d(din[31:0]), | |
| 1789 | .si({scan_in,so[30:0]}), | |
| 1790 | .so({so[30:0],scan_out}), | |
| 1791 | .q(dout[31:0]) | |
| 1792 | ); | |
| 1793 | ||
| 1794 | ||
| 1795 | ||
| 1796 | ||
| 1797 | ||
| 1798 | ||
| 1799 | ||
| 1800 | ||
| 1801 | ||
| 1802 | ||
| 1803 | ||
| 1804 | ||
| 1805 | ||
| 1806 | ||
| 1807 | ||
| 1808 | ||
| 1809 | ||
| 1810 | ||
| 1811 | ||
| 1812 | ||
| 1813 | endmodule | |
| 1814 | ||
| 1815 | ||
| 1816 | ||
| 1817 | ||
| 1818 | ||
| 1819 | ||
| 1820 | ||
| 1821 |