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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_c2ibuf4_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_c2ibuf4_ctl ( | |
36 | iol2clk, | |
37 | tcu_scan_en, | |
38 | scan_in, | |
39 | scan_out, | |
40 | tcu_pce_ov, | |
41 | tcu_clk_stop, | |
42 | tcu_aclk, | |
43 | tcu_bclk, | |
44 | c2i_packet_vld, | |
45 | ucb_sel, | |
46 | ucb_buf_acpt, | |
47 | c2i_packet, | |
48 | iob_ucb_vld, | |
49 | iob_ucb_data, | |
50 | ucb_iob_stall) ; | |
51 | wire dbl_buf_wr; | |
52 | wire dbl_buf_full; | |
53 | wire dbl_buf_rd; | |
54 | wire dbl_buf_vld; | |
55 | wire outdata_buf_busy; | |
56 | wire outdata_buf_wr; | |
57 | wire wr_buf0; | |
58 | wire buf1_vld; | |
59 | wire buf0_vld; | |
60 | wire buf1_older; | |
61 | wire wr_buf1; | |
62 | wire rd_buf0; | |
63 | wire rd_buf1; | |
64 | wire rd_buf; | |
65 | wire buf1_older_n; | |
66 | wire buf1_older_ff_scanin; | |
67 | wire buf1_older_ff_scanout; | |
68 | wire l1clk; | |
69 | wire en_vld0; | |
70 | wire en_vld1; | |
71 | wire buf0_vld_ff_scanin; | |
72 | wire buf0_vld_ff_scanout; | |
73 | wire buf1_vld_ff_scanin; | |
74 | wire buf1_vld_ff_scanout; | |
75 | wire buf0_obj_p_ff_scanin; | |
76 | wire buf0_obj_p_ff_scanout; | |
77 | wire [63:0] buf0_obj_p; | |
78 | wire buf0_obj_h_ff_scanin; | |
79 | wire buf0_obj_h_ff_scanout; | |
80 | wire [54:0] buf0_obj_h; | |
81 | wire buf1_obj_p_ff_scanin; | |
82 | wire buf1_obj_p_ff_scanout; | |
83 | wire [63:0] buf1_obj_p; | |
84 | wire buf1_obj_h_ff_scanin; | |
85 | wire buf1_obj_h_ff_scanout; | |
86 | wire [54:0] buf1_obj_h; | |
87 | wire [127:0] outdata_buf_in; | |
88 | wire [31:0] outdata_vec; | |
89 | wire [127:0] outdata_buf; | |
90 | wire stall_d1_ff_scanin; | |
91 | wire stall_d1_ff_scanout; | |
92 | wire stall_d1; | |
93 | wire rdy1; | |
94 | wire rdy0_ff_scanin; | |
95 | wire rdy0_ff_scanout; | |
96 | wire rdy0; | |
97 | wire rdy1_ff_scanin; | |
98 | wire rdy1_ff_scanout; | |
99 | wire load_outdata; | |
100 | wire shift_outdata; | |
101 | wire [31:0] outdata_vec_next; | |
102 | wire outdata_vec_ff_scanin; | |
103 | wire outdata_vec_ff_scanout; | |
104 | wire [127:0] outdata_buf_next; | |
105 | wire outdata_buf_ff_scanin; | |
106 | wire outdata_buf_ff_scanout; | |
107 | wire siclk; | |
108 | wire soclk; | |
109 | wire se; | |
110 | wire pce_ov; | |
111 | wire stop; | |
112 | ||
113 | ||
114 | ||
115 | ||
116 | //////////////////////////////////////////////////////////////////////// | |
117 | // Signal declarations | |
118 | //////////////////////////////////////////////////////////////////////// | |
119 | // Global interface | |
120 | input iol2clk; | |
121 | ||
122 | input tcu_scan_en; | |
123 | input scan_in; | |
124 | output scan_out; | |
125 | input tcu_pce_ov; | |
126 | input tcu_clk_stop; | |
127 | input tcu_aclk; | |
128 | input tcu_bclk; | |
129 | ||
130 | ||
131 | ||
132 | // slow control interface | |
133 | input c2i_packet_vld; | |
134 | input ucb_sel; | |
135 | output ucb_buf_acpt; | |
136 | ||
137 | ||
138 | // slow datapath interface | |
139 | input [127:0] c2i_packet; | |
140 | ||
141 | ||
142 | // UCB interface | |
143 | output iob_ucb_vld; | |
144 | output [3:0] iob_ucb_data; | |
145 | input ucb_iob_stall; | |
146 | ||
147 | ||
148 | // Internal signals | |
149 | ||
150 | ||
151 | ||
152 | //////////////////////////////////////////////////////////////////////// | |
153 | // Code starts here | |
154 | //////////////////////////////////////////////////////////////////////// | |
155 | ||
156 | assign dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full; | |
157 | assign ucb_buf_acpt = dbl_buf_wr; | |
158 | assign dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy; | |
159 | assign outdata_buf_wr = dbl_buf_rd; | |
160 | //assign outdata_vec_in = {128/UCB_BUS_WIDTH{1'b1}}; | |
161 | ||
162 | /****************************************************************** | |
163 | //dbl_buf #(128) dbl_buf ( | |
164 | // .clk(l2clk), | |
165 | // .wr(dbl_buf_wr), | |
166 | // .din(c2i_packet[127:0]), | |
167 | // .rd(dbl_buf_rd), | |
168 | // .dout(outdata_buf_in[127:0]), | |
169 | // .vld(dbl_buf_vld), | |
170 | // .full(dbl_buf_full)); | |
171 | ******************************************************************/ | |
172 | assign wr_buf0 = dbl_buf_wr & (buf1_vld | (~buf0_vld & ~buf1_older)); | |
173 | assign wr_buf1 = dbl_buf_wr & (buf0_vld | (~buf1_vld & buf1_older)); | |
174 | ||
175 | // read from the older entry | |
176 | assign rd_buf0 = dbl_buf_rd & ~buf1_older; | |
177 | assign rd_buf1 = dbl_buf_rd & buf1_older; | |
178 | ||
179 | // flip older pointer when an entry is read | |
180 | assign rd_buf = dbl_buf_rd & (buf0_vld | buf1_vld); | |
181 | assign buf1_older_n = ~buf1_older; | |
182 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_1 buf1_older_ff | |
183 | ( | |
184 | .scan_in(buf1_older_ff_scanin), | |
185 | .scan_out(buf1_older_ff_scanout), | |
186 | .dout (buf1_older), | |
187 | .l1clk (l1clk), | |
188 | .en (rd_buf), | |
189 | .din (buf1_older_n), | |
190 | .siclk(siclk), | |
191 | .soclk(soclk) | |
192 | ); | |
193 | ||
194 | // set valid bit for writes and reset for reads | |
195 | assign en_vld0 = wr_buf0 | rd_buf0; | |
196 | assign en_vld1 = wr_buf1 | rd_buf1; | |
197 | ||
198 | // the actual buffers | |
199 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_1 buf0_vld_ff | |
200 | ( | |
201 | .scan_in(buf0_vld_ff_scanin), | |
202 | .scan_out(buf0_vld_ff_scanout), | |
203 | .dout (buf0_vld), | |
204 | .l1clk (l1clk), | |
205 | .en (en_vld0), | |
206 | .din (wr_buf0), | |
207 | .siclk(siclk), | |
208 | .soclk(soclk) | |
209 | ); | |
210 | ||
211 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_1 buf1_vld_ff | |
212 | ( | |
213 | .scan_in(buf1_vld_ff_scanin), | |
214 | .scan_out(buf1_vld_ff_scanout), | |
215 | .dout (buf1_vld), | |
216 | .l1clk (l1clk), | |
217 | .en (en_vld1), | |
218 | .din (wr_buf1), | |
219 | .siclk(siclk), | |
220 | .soclk(soclk) | |
221 | ); | |
222 | ||
223 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_64 buf0_obj_p_ff | |
224 | ( | |
225 | .scan_in(buf0_obj_p_ff_scanin), | |
226 | .scan_out(buf0_obj_p_ff_scanout), | |
227 | .dout (buf0_obj_p[63:0]), | |
228 | .l1clk (l1clk), | |
229 | .en (wr_buf0), | |
230 | .din (c2i_packet[127:64]), | |
231 | .siclk(siclk), | |
232 | .soclk(soclk) | |
233 | ); | |
234 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_55 buf0_obj_h_ff | |
235 | ( | |
236 | .scan_in(buf0_obj_h_ff_scanin), | |
237 | .scan_out(buf0_obj_h_ff_scanout), | |
238 | .dout (buf0_obj_h[54:0]), | |
239 | .l1clk (l1clk), | |
240 | .en (wr_buf0), | |
241 | .din (c2i_packet[54:0]), | |
242 | .siclk(siclk), | |
243 | .soclk(soclk) | |
244 | ); | |
245 | ||
246 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_64 buf1_obj_p_ff | |
247 | ( | |
248 | .scan_in(buf1_obj_p_ff_scanin), | |
249 | .scan_out(buf1_obj_p_ff_scanout), | |
250 | .dout (buf1_obj_p[63:0]), | |
251 | .l1clk (l1clk), | |
252 | .en (wr_buf1), | |
253 | .din (c2i_packet[127:64]), | |
254 | .siclk(siclk), | |
255 | .soclk(soclk) | |
256 | ); | |
257 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_55 buf1_obj_h_ff | |
258 | ( | |
259 | .scan_in(buf1_obj_h_ff_scanin), | |
260 | .scan_out(buf1_obj_h_ff_scanout), | |
261 | .dout (buf1_obj_h[54:0]), | |
262 | .l1clk (l1clk), | |
263 | .en (wr_buf1), | |
264 | .din (c2i_packet[54:0]), | |
265 | .siclk(siclk), | |
266 | .soclk(soclk) | |
267 | ); | |
268 | ||
269 | // mux out the older entry | |
270 | assign outdata_buf_in[127:0] = (buf1_older) ? {buf1_obj_p[63:0],9'b0,buf1_obj_h[54:0]} : | |
271 | {buf0_obj_p[63:0],9'b0,buf0_obj_h[54:0]} ; | |
272 | ||
273 | assign dbl_buf_vld = buf0_vld | buf1_vld; | |
274 | assign dbl_buf_full = buf0_vld & buf1_vld; | |
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | /******************************************************************* | |
282 | //ucb_bus_out #(UCB_BUS_WIDTH) ucb_bus_out ( | |
283 | // .clk(l2clk), | |
284 | // .outdata_buf_wr(outdata_buf_wr), | |
285 | // .outdata_buf_in(outdata_buf_in[127:0]), | |
286 | // .outdata_vec_in(outdata_vec_in[128/UCB_BUS_WIDTH-1:0]), | |
287 | // .outdata_buf_busy(outdata_buf_busy), | |
288 | // .vld(iob_ucb_vld), | |
289 | // .data(iob_ucb_data[UCB_BUS_WIDTH-1:0]), | |
290 | // .stall(ucb_iob_stall)); | |
291 | *******************************************************************/ | |
292 | ||
293 | ||
294 | assign iob_ucb_vld = outdata_vec[0]; | |
295 | assign iob_ucb_data[3:0] = outdata_buf[3:0]; | |
296 | ||
297 | ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_1 stall_d1_ff | |
298 | ( | |
299 | .scan_in(stall_d1_ff_scanin), | |
300 | .scan_out(stall_d1_ff_scanout), | |
301 | .dout (stall_d1), | |
302 | .l1clk (l1clk), | |
303 | .en (rdy1), | |
304 | .din (ucb_iob_stall), | |
305 | .siclk(siclk), | |
306 | .soclk(soclk) | |
307 | ); | |
308 | ||
309 | ncu_c2ibuf4_ctl_msff_ctl_macro__width_1 rdy0_ff | |
310 | ( | |
311 | .scan_in(rdy0_ff_scanin), | |
312 | .scan_out(rdy0_ff_scanout), | |
313 | .dout (rdy0), | |
314 | .l1clk (l1clk), | |
315 | .din (1'b1), | |
316 | .siclk(siclk), | |
317 | .soclk(soclk) | |
318 | ); | |
319 | ||
320 | ncu_c2ibuf4_ctl_msff_ctl_macro__width_1 rdy1_ff | |
321 | ( | |
322 | .scan_in(rdy1_ff_scanin), | |
323 | .scan_out(rdy1_ff_scanout), | |
324 | .dout (rdy1), | |
325 | .l1clk (l1clk), | |
326 | .din (rdy0), | |
327 | .siclk(siclk), | |
328 | .soclk(soclk) | |
329 | ); | |
330 | ||
331 | /************************************************************ | |
332 | * Outbound Data | |
333 | ************************************************************/ | |
334 | // accept new data only if there is none being processed | |
335 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
336 | ||
337 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
338 | ||
339 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
340 | ||
341 | assign outdata_vec_next[31:0] = | |
342 | //load_outdata ? outdata_vec_in[128/UCB_BUS_WIDTH-1:0] : | |
343 | load_outdata ? 32'hffff_ffff : | |
344 | //shift_outdata ? outdata_vec[128/UCB_BUS_WIDTH-1:0] >> 1 : | |
345 | shift_outdata ? {1'b0,outdata_vec[31:1]} : | |
346 | outdata_vec[31:0] ; | |
347 | ||
348 | ncu_c2ibuf4_ctl_msff_ctl_macro__width_32 outdata_vec_ff | |
349 | ( | |
350 | .scan_in(outdata_vec_ff_scanin), | |
351 | .scan_out(outdata_vec_ff_scanout), | |
352 | .dout (outdata_vec[31:0]), | |
353 | .l1clk (l1clk), | |
354 | .din (outdata_vec_next[31:0]), | |
355 | .siclk(siclk), | |
356 | .soclk(soclk) | |
357 | ); | |
358 | ||
359 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] : | |
360 | shift_outdata ? (outdata_buf[127:0] >> 4) : | |
361 | outdata_buf[127:0] ; | |
362 | ||
363 | ncu_c2ibuf4_ctl_msff_ctl_macro__width_128 outdata_buf_ff | |
364 | ( | |
365 | .scan_in(outdata_buf_ff_scanin), | |
366 | .scan_out(outdata_buf_ff_scanout), | |
367 | .dout (outdata_buf[127:0]), | |
368 | .l1clk (l1clk), | |
369 | .din (outdata_buf_next[127:0]), | |
370 | .siclk(siclk), | |
371 | .soclk(soclk) | |
372 | ); | |
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | /**** adding clock header ****/ | |
379 | ncu_c2ibuf4_ctl_l1clkhdr_ctl_macro clkgen ( | |
380 | .l2clk (iol2clk), | |
381 | .l1en (1'b1), | |
382 | .l1clk (l1clk), | |
383 | .pce_ov(pce_ov), | |
384 | .stop(stop), | |
385 | .se(se) | |
386 | ); | |
387 | ||
388 | /*** building tcu port ***/ | |
389 | assign siclk = tcu_aclk; | |
390 | assign soclk = tcu_bclk; | |
391 | assign se = tcu_scan_en; | |
392 | assign pce_ov = tcu_pce_ov; | |
393 | assign stop = tcu_clk_stop; | |
394 | ||
395 | // fixscan start: | |
396 | assign buf1_older_ff_scanin = scan_in ; | |
397 | assign buf0_vld_ff_scanin = buf1_older_ff_scanout ; | |
398 | assign buf1_vld_ff_scanin = buf0_vld_ff_scanout ; | |
399 | assign buf0_obj_p_ff_scanin = buf1_vld_ff_scanout ; | |
400 | assign buf0_obj_h_ff_scanin = buf0_obj_p_ff_scanout ; | |
401 | assign buf1_obj_p_ff_scanin = buf0_obj_h_ff_scanout ; | |
402 | assign buf1_obj_h_ff_scanin = buf1_obj_p_ff_scanout ; | |
403 | assign stall_d1_ff_scanin = buf1_obj_h_ff_scanout ; | |
404 | assign rdy0_ff_scanin = stall_d1_ff_scanout ; | |
405 | assign rdy1_ff_scanin = rdy0_ff_scanout ; | |
406 | assign outdata_vec_ff_scanin = rdy1_ff_scanout ; | |
407 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; | |
408 | assign scan_out = outdata_buf_ff_scanout ; | |
409 | // fixscan end: | |
410 | endmodule // c2i_buf | |
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | // any PARAMS parms go into naming of macro | |
419 | ||
420 | module ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_1 ( | |
421 | din, | |
422 | en, | |
423 | l1clk, | |
424 | scan_in, | |
425 | siclk, | |
426 | soclk, | |
427 | dout, | |
428 | scan_out); | |
429 | wire [0:0] fdin; | |
430 | ||
431 | input [0:0] din; | |
432 | input en; | |
433 | input l1clk; | |
434 | input scan_in; | |
435 | ||
436 | ||
437 | input siclk; | |
438 | input soclk; | |
439 | ||
440 | output [0:0] dout; | |
441 | output scan_out; | |
442 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | ||
449 | dff #(1) d0_0 ( | |
450 | .l1clk(l1clk), | |
451 | .siclk(siclk), | |
452 | .soclk(soclk), | |
453 | .d(fdin[0:0]), | |
454 | .si(scan_in), | |
455 | .so(scan_out), | |
456 | .q(dout[0:0]) | |
457 | ); | |
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | ||
470 | endmodule | |
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | // any PARAMS parms go into naming of macro | |
485 | ||
486 | module ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_64 ( | |
487 | din, | |
488 | en, | |
489 | l1clk, | |
490 | scan_in, | |
491 | siclk, | |
492 | soclk, | |
493 | dout, | |
494 | scan_out); | |
495 | wire [63:0] fdin; | |
496 | wire [62:0] so; | |
497 | ||
498 | input [63:0] din; | |
499 | input en; | |
500 | input l1clk; | |
501 | input scan_in; | |
502 | ||
503 | ||
504 | input siclk; | |
505 | input soclk; | |
506 | ||
507 | output [63:0] dout; | |
508 | output scan_out; | |
509 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); | |
510 | ||
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | dff #(64) d0_0 ( | |
517 | .l1clk(l1clk), | |
518 | .siclk(siclk), | |
519 | .soclk(soclk), | |
520 | .d(fdin[63:0]), | |
521 | .si({scan_in,so[62:0]}), | |
522 | .so({so[62:0],scan_out}), | |
523 | .q(dout[63:0]) | |
524 | ); | |
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | endmodule | |
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | // any PARAMS parms go into naming of macro | |
552 | ||
553 | module ncu_c2ibuf4_ctl_msff_ctl_macro__en_1__width_55 ( | |
554 | din, | |
555 | en, | |
556 | l1clk, | |
557 | scan_in, | |
558 | siclk, | |
559 | soclk, | |
560 | dout, | |
561 | scan_out); | |
562 | wire [54:0] fdin; | |
563 | wire [53:0] so; | |
564 | ||
565 | input [54:0] din; | |
566 | input en; | |
567 | input l1clk; | |
568 | input scan_in; | |
569 | ||
570 | ||
571 | input siclk; | |
572 | input soclk; | |
573 | ||
574 | output [54:0] dout; | |
575 | output scan_out; | |
576 | assign fdin[54:0] = (din[54:0] & {55{en}}) | (dout[54:0] & ~{55{en}}); | |
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | dff #(55) d0_0 ( | |
584 | .l1clk(l1clk), | |
585 | .siclk(siclk), | |
586 | .soclk(soclk), | |
587 | .d(fdin[54:0]), | |
588 | .si({scan_in,so[53:0]}), | |
589 | .so({so[53:0],scan_out}), | |
590 | .q(dout[54:0]) | |
591 | ); | |
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | endmodule | |
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | // any PARAMS parms go into naming of macro | |
619 | ||
620 | module ncu_c2ibuf4_ctl_msff_ctl_macro__width_1 ( | |
621 | din, | |
622 | l1clk, | |
623 | scan_in, | |
624 | siclk, | |
625 | soclk, | |
626 | dout, | |
627 | scan_out); | |
628 | wire [0:0] fdin; | |
629 | ||
630 | input [0:0] din; | |
631 | input l1clk; | |
632 | input scan_in; | |
633 | ||
634 | ||
635 | input siclk; | |
636 | input soclk; | |
637 | ||
638 | output [0:0] dout; | |
639 | output scan_out; | |
640 | assign fdin[0:0] = din[0:0]; | |
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | dff #(1) d0_0 ( | |
648 | .l1clk(l1clk), | |
649 | .siclk(siclk), | |
650 | .soclk(soclk), | |
651 | .d(fdin[0:0]), | |
652 | .si(scan_in), | |
653 | .so(scan_out), | |
654 | .q(dout[0:0]) | |
655 | ); | |
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | endmodule | |
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | // any PARAMS parms go into naming of macro | |
683 | ||
684 | module ncu_c2ibuf4_ctl_msff_ctl_macro__width_32 ( | |
685 | din, | |
686 | l1clk, | |
687 | scan_in, | |
688 | siclk, | |
689 | soclk, | |
690 | dout, | |
691 | scan_out); | |
692 | wire [31:0] fdin; | |
693 | wire [30:0] so; | |
694 | ||
695 | input [31:0] din; | |
696 | input l1clk; | |
697 | input scan_in; | |
698 | ||
699 | ||
700 | input siclk; | |
701 | input soclk; | |
702 | ||
703 | output [31:0] dout; | |
704 | output scan_out; | |
705 | assign fdin[31:0] = din[31:0]; | |
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | dff #(32) d0_0 ( | |
713 | .l1clk(l1clk), | |
714 | .siclk(siclk), | |
715 | .soclk(soclk), | |
716 | .d(fdin[31:0]), | |
717 | .si({scan_in,so[30:0]}), | |
718 | .so({so[30:0],scan_out}), | |
719 | .q(dout[31:0]) | |
720 | ); | |
721 | ||
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | endmodule | |
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | // any PARAMS parms go into naming of macro | |
748 | ||
749 | module ncu_c2ibuf4_ctl_msff_ctl_macro__width_128 ( | |
750 | din, | |
751 | l1clk, | |
752 | scan_in, | |
753 | siclk, | |
754 | soclk, | |
755 | dout, | |
756 | scan_out); | |
757 | wire [127:0] fdin; | |
758 | wire [126:0] so; | |
759 | ||
760 | input [127:0] din; | |
761 | input l1clk; | |
762 | input scan_in; | |
763 | ||
764 | ||
765 | input siclk; | |
766 | input soclk; | |
767 | ||
768 | output [127:0] dout; | |
769 | output scan_out; | |
770 | assign fdin[127:0] = din[127:0]; | |
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | dff #(128) d0_0 ( | |
778 | .l1clk(l1clk), | |
779 | .siclk(siclk), | |
780 | .soclk(soclk), | |
781 | .d(fdin[127:0]), | |
782 | .si({scan_in,so[126:0]}), | |
783 | .so({so[126:0],scan_out}), | |
784 | .q(dout[127:0]) | |
785 | ); | |
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | ||
792 | ||
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | endmodule | |
799 | ||
800 | ||
801 | ||
802 | ||
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | // any PARAMS parms go into naming of macro | |
813 | ||
814 | module ncu_c2ibuf4_ctl_l1clkhdr_ctl_macro ( | |
815 | l2clk, | |
816 | l1en, | |
817 | pce_ov, | |
818 | stop, | |
819 | se, | |
820 | l1clk); | |
821 | ||
822 | ||
823 | input l2clk; | |
824 | input l1en; | |
825 | input pce_ov; | |
826 | input stop; | |
827 | input se; | |
828 | output l1clk; | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | cl_sc1_l1hdr_8x c_0 ( | |
835 | ||
836 | ||
837 | .l2clk(l2clk), | |
838 | .pce(l1en), | |
839 | .l1clk(l1clk), | |
840 | .se(se), | |
841 | .pce_ov(pce_ov), | |
842 | .stop(stop) | |
843 | ); | |
844 | ||
845 | ||
846 | ||
847 | endmodule | |
848 | ||
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 |