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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_c2ibufpio_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define RF_RDEN_OFFSTATE 1'b1 | |
36 | ||
37 | //==================================== | |
38 | `define NCU_INTMANRF_DEPTH 128 | |
39 | `define NCU_INTMANRF_DATAWIDTH 16 | |
40 | `define NCU_INTMANRF_ADDRWIDTH 7 | |
41 | //==================================== | |
42 | ||
43 | //==================================== | |
44 | `define NCU_MONDORF_DEPTH 64 | |
45 | `define NCU_MONDORF_DATAWIDTH 72 | |
46 | `define NCU_MONDORF_ADDRWIDTH 6 | |
47 | //==================================== | |
48 | ||
49 | //==================================== | |
50 | `define NCU_CPUBUFRF_DEPTH 32 | |
51 | `define NCU_CPUBUFRF_DATAWIDTH 144 | |
52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 | |
53 | //==================================== | |
54 | ||
55 | //==================================== | |
56 | `define NCU_IOBUFRF_DEPTH 32 | |
57 | `define NCU_IOBUFRF_DATAWIDTH 144 | |
58 | `define NCU_IOBUFRF_ADDRWIDTH 5 | |
59 | //==================================== | |
60 | ||
61 | //==================================== | |
62 | `define NCU_IOBUF1RF_DEPTH 32 | |
63 | `define NCU_IOBUF1RF_DATAWIDTH 32 | |
64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 | |
65 | //==================================== | |
66 | ||
67 | //==================================== | |
68 | `define NCU_INTBUFRF_DEPTH 32 | |
69 | `define NCU_INTBUFRF_DATAWIDTH 144 | |
70 | `define NCU_INTBUFRF_ADDRWIDTH 5 | |
71 | //==================================== | |
72 | ||
73 | //== fix me : need to remove when warm // | |
74 | //== becomes available // | |
75 | `define WMR_LENGTH 10'd999 | |
76 | `define WMR_LENGTH_P1 10'd1000 | |
77 | ||
78 | //// NCU CSR_MAN address 80_0000_xxxx //// | |
79 | `define NCU_CSR_MAN 16'h0000 | |
80 | `define NCU_CREG_INTMAN 16'h0000 | |
81 | //`define NCU_CREG_INTVECDISP 16'h0800 | |
82 | `define NCU_CREG_MONDOINVEC 16'h0a00 | |
83 | `define NCU_CREG_SERNUM 16'h1000 | |
84 | `define NCU_CREG_FUSESTAT 16'h1008 | |
85 | `define NCU_CREG_COREAVAIL 16'h1010 | |
86 | `define NCU_CREG_BANKAVAIL 16'h1018 | |
87 | `define NCU_CREG_BANK_ENABLE 16'h1020 | |
88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 | |
89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 | |
90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 | |
91 | ||
92 | ||
93 | `define NCU_CREG_MEM32_BASE 16'h2000 | |
94 | `define NCU_CREG_MEM32_MASK 16'h2008 | |
95 | `define NCU_CREG_MEM64_BASE 16'h2010 | |
96 | `define NCU_CREG_MEM64_MASK 16'h2018 | |
97 | `define NCU_CREG_IOCON_BASE 16'h2020 | |
98 | `define NCU_CREG_IOCON_MASK 16'h2028 | |
99 | `define NCU_CREG_MMUFSH 16'h2030 | |
100 | ||
101 | `define NCU_CREG_ESR 16'h3000 | |
102 | `define NCU_CREG_ELE 16'h3008 | |
103 | `define NCU_CREG_EIE 16'h3010 | |
104 | `define NCU_CREG_EJR 16'h3018 | |
105 | `define NCU_CREG_FEE 16'h3020 | |
106 | `define NCU_CREG_PER 16'h3028 | |
107 | `define NCU_CREG_SIISYN 16'h3030 | |
108 | `define NCU_CREG_NCUSYN 16'h3038 | |
109 | `define NCU_CREG_SCKSEL 16'h3040 | |
110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 | |
111 | ||
112 | //// NUC CSR_MONDO address 80_0004_xxxx //// | |
113 | `define NCU_CSR_MONDO 16'h0004 | |
114 | `define NCU_CREG_MDATA0 16'h0000 | |
115 | `define NCU_CREG_MDATA1 16'h0200 | |
116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 | |
117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 | |
118 | `define NCU_CREG_MBUSY 16'h0800 | |
119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 | |
120 | ||
121 | ||
122 | ||
123 | // ASI shared reg 90_xxxx_xxxx// | |
124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" | |
125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" | |
126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" | |
127 | `define NCU_ASI_COREAVAIL 16'h0000 | |
128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 | |
129 | `define NCU_ASI_CORE_ENABLE 16'h0020 | |
130 | `define NCU_ASI_XIR_STEERING 16'h0030 | |
131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 | |
132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 | |
133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 | |
134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 | |
135 | `define NCU_ASI_INTVECDISP 16'h0000 | |
136 | `define NCU_ASI_ERR_STR 16'h1000 | |
137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 | |
138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 | |
139 | ||
140 | ||
141 | //// UCB packet type //// | |
142 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
143 | `define UCB_READ_ACK 4'b0001 | |
144 | `define UCB_WRITE_ACK 4'b0010 | |
145 | `define UCB_IFILL_ACK 4'b0011 | |
146 | `define UCB_IFILL_NACK 4'b0111 | |
147 | ||
148 | `define UCB_READ_REQ 4'b0100 // req types | |
149 | `define UCB_WRITE_REQ 4'b0101 | |
150 | `define UCB_IFILL_REQ 4'b0110 | |
151 | ||
152 | `define UCB_INT 4'b1000 // plain interrupt | |
153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue | |
155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce | |
156 | `define UCB_RESET_VEC 4'b0101 // reset with vector | |
157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
159 | ||
160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce | |
161 | ||
162 | ||
163 | //// PCX packet type //// | |
164 | `define PCX_LOAD_RQ 5'b00000 | |
165 | `define PCX_IMISS_RQ 5'b10000 | |
166 | `define PCX_STORE_RQ 5'b00001 | |
167 | `define PCX_FWD_RQs 5'b01101 | |
168 | `define PCX_FWD_RPYs 5'b01110 | |
169 | ||
170 | //// CPX packet type //// | |
171 | //`define CPX_LOAD_RET 4'b0000 | |
172 | `define CPX_LOAD_RET 4'b1000 | |
173 | `define CPX_ST_ACK 4'b0100 | |
174 | //`define CPX_IFILL_RET 4'b0001 | |
175 | `define CPX_IFILL_RET 4'b1001 | |
176 | `define CPX_INT_RET 4'b0111 | |
177 | `define CPX_INT_SOC 4'b1101 | |
178 | //`define CPX_FWD_RQ_RET 4'b1010 | |
179 | //`define CPX_FWD_RPY_RET 4'b1011 | |
180 | ||
181 | ||
182 | ||
183 | ||
184 | //// Global CSR decode //// | |
185 | `define NCU_CSR 8'h80 | |
186 | `define NIU_CSR 8'h81 | |
187 | //`define RNG_CSR 8'h82 | |
188 | `define DBG1_CSR 8'h86 | |
189 | `define CCU_CSR 8'h83 | |
190 | `define MCU_CSR 8'h84 | |
191 | `define TCU_CSR 8'h85 | |
192 | `define DMU_CSR 8'h88 | |
193 | `define RCU_CSR 8'h89 | |
194 | `define NCU_ASI 8'h90 | |
195 | /////8'h91 ~ 9F reserved | |
196 | /////8'hA0 ~ BF L2 CSR//// | |
197 | `define DMU_PIO 4'hC // C0 ~ CF | |
198 | /////8'hB0 ~ FE reserved | |
199 | `define SSI_CSR 8'hFF | |
200 | ||
201 | ||
202 | //// NCU_SSI //// | |
203 | `define SSI_ADDR 12'hFF_F | |
204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 | |
205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 | |
206 | ||
207 | `define IF_IDLE 2'b00 | |
208 | `define IF_ACPT 2'b01 | |
209 | `define IF_DROP 2'b10 | |
210 | ||
211 | `define SSI_IDLE 3'b000 | |
212 | `define SSI_REQ 3'b001 | |
213 | `define SSI_WDATA 3'b011 | |
214 | `define SSI_REQ_PAR 3'b101 | |
215 | `define SSI_ACK 3'b111 | |
216 | `define SSI_RDATA 3'b110 | |
217 | `define SSI_ACK_PAR 3'b010 | |
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | ||
228 | module ncu_c2ibufpio_ctl ( | |
229 | iol2clk, | |
230 | tcu_scan_en, | |
231 | scan_in, | |
232 | scan_out, | |
233 | tcu_pce_ov, | |
234 | tcu_clk_stop, | |
235 | tcu_aclk, | |
236 | tcu_bclk, | |
237 | tcu_dbr_gateoff, | |
238 | c2i_packet, | |
239 | dmupio_addr35to24, | |
240 | c2i_packet_vld, | |
241 | ucb_sel, | |
242 | ucb_buf_acpt, | |
243 | com_map, | |
244 | mmufsh_data, | |
245 | mmufsh_vld, | |
246 | mmu_ld, | |
247 | dmu_ncu_wrack_vld, | |
248 | dmu_ncu_wrack_tag, | |
249 | dmu_ncu_wrack_par, | |
250 | dmu_cr_id_rtn_err, | |
251 | dmu_cr_id_rtn_erri, | |
252 | sii_cr_id_rtn_vld, | |
253 | sii_cr_id_rtn, | |
254 | dmubuf_din, | |
255 | dmubuf0_wr, | |
256 | dmubuf1_wr, | |
257 | dmubuf_waddr, | |
258 | dmubuf_raddr, | |
259 | dmubuf_rden, | |
260 | dmubuf0_dout, | |
261 | dmubuf1_dout, | |
262 | dmupio_wack_iopkt, | |
263 | dmupio_srvc_wack, | |
264 | c2i_wait, | |
265 | iobuf_avail, | |
266 | ncu_dmu_pio_data, | |
267 | ncu_dmu_pio_hdr_vld, | |
268 | ncu_dmu_mmu_addr_vld, | |
269 | ncu_dmu_dpar, | |
270 | dmubufsyn, | |
271 | dmubuf_pue, | |
272 | dmubuf_pei, | |
273 | mb1_dmubuf0_wr_en, | |
274 | mb1_dmubuf1_wr_en, | |
275 | mb1_dmubuf0_rd_en, | |
276 | mb1_dmubuf1_rd_en, | |
277 | mb1_addr, | |
278 | mb1_wdata, | |
279 | mb1_run) ; | |
280 | wire fifo_wr; | |
281 | wire fifo_full; | |
282 | wire [143:0] dmubuf_din_f; | |
283 | wire [11:0] parity; | |
284 | wire [4:0] ct_cmd_ecc; | |
285 | wire pipe_full; | |
286 | wire aov; | |
287 | wire pav; | |
288 | wire pbv; | |
289 | wire fifo_dout_v; | |
290 | wire raddr_inc; | |
291 | wire aog; | |
292 | wire fifo_rd; | |
293 | wire [6:0] raddr_p1; | |
294 | wire [6:0] raddr; | |
295 | wire [6:0] raddr_muxed; | |
296 | wire [6:0] waddr_n; | |
297 | wire [6:0] waddr_p1; | |
298 | wire [6:0] waddr; | |
299 | wire aov_n; | |
300 | wire dmubuf_rden_nobist_eco; | |
301 | wire pa_ld; | |
302 | wire fifo_dout_ld; | |
303 | wire pb_ld; | |
304 | wire pbs_n; | |
305 | wire pas; | |
306 | wire pbs; | |
307 | wire mov; | |
308 | wire fifo_dout_v_n; | |
309 | wire a_full; | |
310 | wire t_full; | |
311 | wire fifo_full_n; | |
312 | wire [143:0] dmubuf_dout; | |
313 | wire dmubuf1_sel2; | |
314 | wire aog_ff_scanin; | |
315 | wire aog_ff_scanout; | |
316 | wire l1clk; | |
317 | wire aov_ff_scanin; | |
318 | wire aov_ff_scanout; | |
319 | wire pav_ff_scanin; | |
320 | wire pav_ff_scanout; | |
321 | wire pbv_ff_scanin; | |
322 | wire pbv_ff_scanout; | |
323 | wire pbs_ff_scanin; | |
324 | wire pbs_ff_scanout; | |
325 | wire dmubuf1_sel1_ff_scanin; | |
326 | wire dmubuf1_sel1_ff_scanout; | |
327 | wire dmubuf1_sel1; | |
328 | wire dmubuf1_sel2_ff_scanin; | |
329 | wire dmubuf1_sel2_ff_scanout; | |
330 | wire raddr_ff_scanin; | |
331 | wire raddr_ff_scanout; | |
332 | wire waddr_ff_scanin; | |
333 | wire waddr_ff_scanout; | |
334 | wire fifo_full_ff_scanin; | |
335 | wire fifo_full_ff_scanout; | |
336 | wire [143:0] dout_muxed_a; | |
337 | wire [143:0] pad; | |
338 | wire pad_ff_scanin; | |
339 | wire pad_ff_scanout; | |
340 | wire dmubuf_ue_n; | |
341 | wire unused_ce; | |
342 | wire [10:0] dout_muxed_b; | |
343 | wire [4:0] unused_co; | |
344 | wire [11:0] dmubuf_pfail_n; | |
345 | wire fifo_dout_v_ff_scanin; | |
346 | wire fifo_dout_v_ff_scanout; | |
347 | wire [126:0] dout_muxed; | |
348 | wire fifo_dout_ff_scanin; | |
349 | wire fifo_dout_ff_scanout; | |
350 | wire [126:0] fifo_dout; | |
351 | wire fifo_dout_pue_ff_scanin; | |
352 | wire fifo_dout_pue_ff_scanout; | |
353 | wire fifo_dout_pue; | |
354 | wire fifo_dout_pe_ff_scanin; | |
355 | wire fifo_dout_pe_ff_scanout; | |
356 | wire fifo_dout_pe; | |
357 | wire fifo_dout_ue_ff_scanin; | |
358 | wire fifo_dout_ue_ff_scanout; | |
359 | wire fifo_dout_ue; | |
360 | wire [4:0] dmubufsyn_rtyp; | |
361 | wire dmubufsyn_ff_scanin; | |
362 | wire dmubufsyn_ff_scanout; | |
363 | wire fifo_rd_from_pio; | |
364 | wire piowr; | |
365 | wire pio_rdy; | |
366 | wire dmu_pio_bb; | |
367 | wire cr_id_vld; | |
368 | wire pio_ld; | |
369 | wire cr_id_con; | |
370 | wire [2:0] pa_lower3bits; | |
371 | wire eco060628net1; | |
372 | wire [63:0] pio_hdr; | |
373 | wire [63:0] ncu_dmu_pio_data_n; | |
374 | wire [63:0] dmu_pio_pld; | |
375 | wire [1:0] ncu_dmu_dpar_n; | |
376 | wire dmu_pio_bb_n; | |
377 | wire dmu_pio_bb_ff_scanin; | |
378 | wire dmu_pio_bb_ff_scanout; | |
379 | wire dmu_pio_pld_ff_scanin; | |
380 | wire dmu_pio_pld_ff_scanout; | |
381 | wire ncu_dmu_pio_hdr_vld_f; | |
382 | wire ncu_dmu_pio_hdr_vld_ff_scanin; | |
383 | wire ncu_dmu_pio_hdr_vld_ff_scanout; | |
384 | wire ncu_dmu_pio_data_ff_scanin; | |
385 | wire ncu_dmu_pio_data_ff_scanout; | |
386 | wire ncu_dmu_dpar_ff_scanin; | |
387 | wire ncu_dmu_dpar_ff_scanout; | |
388 | wire ncu_dmu_mmu_addr_vld_f; | |
389 | wire ncu_dmu_mmu_addr_vld_ff_scanin; | |
390 | wire ncu_dmu_mmu_addr_vld_ff_scanout; | |
391 | wire [3:0] dmupio_cpx_type; | |
392 | wire [144:0] dmupio_wrack_pkt; | |
393 | wire [7:0] dmupio_wrack_cpu; | |
394 | wire rdy0_ff_scanin; | |
395 | wire rdy0_ff_scanout; | |
396 | wire rdy0; | |
397 | wire rdy1_ff_scanin; | |
398 | wire rdy1_ff_scanout; | |
399 | wire rdy1; | |
400 | wire cr_id_rtn1_vld_ff_scanin; | |
401 | wire cr_id_rtn1_vld_ff_scanout; | |
402 | wire dmu_cr_id_rtn_vld; | |
403 | wire cr_id_rtn1_ff_scanin; | |
404 | wire cr_id_rtn1_ff_scanout; | |
405 | wire [3:0] dmu_cr_id_rtn; | |
406 | wire cr_id_rtn1_par_ff_scanin; | |
407 | wire cr_id_rtn1_par_ff_scanout; | |
408 | wire dmu_cr_id_rtn_par; | |
409 | wire [15:0] cr_id_rtn1_sel; | |
410 | wire [15:0] cr_id_rtn2_sel; | |
411 | wire [15:0] cr_id_rtn_sel; | |
412 | wire [15:0] cr_id_con_sel; | |
413 | wire [15:0] token_avail_n; | |
414 | wire [15:0] token_avail; | |
415 | wire [15:0] token_avail_n_; | |
416 | wire [15:0] token_avail_; | |
417 | wire token_avail_l_ff_scanin; | |
418 | wire token_avail_l_ff_scanout; | |
419 | wire siclk; | |
420 | wire soclk; | |
421 | wire se; | |
422 | wire pce_ov; | |
423 | wire stop; | |
424 | ||
425 | ||
426 | input iol2clk; | |
427 | input tcu_scan_en; | |
428 | input scan_in; | |
429 | output scan_out; | |
430 | ||
431 | input tcu_pce_ov; | |
432 | input tcu_clk_stop; | |
433 | input tcu_aclk; | |
434 | input tcu_bclk; | |
435 | input tcu_dbr_gateoff; | |
436 | ||
437 | //// | |
438 | input [127:0] c2i_packet; | |
439 | input [11:0] dmupio_addr35to24; | |
440 | input c2i_packet_vld; | |
441 | input ucb_sel; | |
442 | output ucb_buf_acpt; | |
443 | input [1:0] com_map; | |
444 | input [63:0] mmufsh_data; | |
445 | input mmufsh_vld; | |
446 | output mmu_ld; | |
447 | ||
448 | input dmu_ncu_wrack_vld; | |
449 | input [3:0] dmu_ncu_wrack_tag; | |
450 | input dmu_ncu_wrack_par; | |
451 | output dmu_cr_id_rtn_err; | |
452 | input dmu_cr_id_rtn_erri; | |
453 | input sii_cr_id_rtn_vld; | |
454 | input [3:0] sii_cr_id_rtn; | |
455 | ||
456 | output [143:0] dmubuf_din; | |
457 | output dmubuf0_wr; | |
458 | output dmubuf1_wr; | |
459 | output [4:0] dmubuf_waddr; | |
460 | output [4:0] dmubuf_raddr; | |
461 | output dmubuf_rden; | |
462 | input [143:0] dmubuf0_dout; | |
463 | input [143:0] dmubuf1_dout; | |
464 | ||
465 | output [152:0] dmupio_wack_iopkt; | |
466 | output dmupio_srvc_wack; | |
467 | output c2i_wait; | |
468 | input iobuf_avail; | |
469 | ||
470 | output [63:0] ncu_dmu_pio_data; | |
471 | output ncu_dmu_pio_hdr_vld; | |
472 | output ncu_dmu_mmu_addr_vld; | |
473 | output [1:0] ncu_dmu_dpar; | |
474 | ||
475 | //// ecc err //// | |
476 | output [46:0] dmubufsyn; | |
477 | output dmubuf_pue; | |
478 | input dmubuf_pei; | |
479 | ||
480 | // mb1 // | |
481 | input mb1_dmubuf0_wr_en; | |
482 | input mb1_dmubuf1_wr_en; | |
483 | input mb1_dmubuf0_rd_en; | |
484 | input mb1_dmubuf1_rd_en; | |
485 | input [4:0] mb1_addr; | |
486 | input [7:0] mb1_wdata; | |
487 | input mb1_run; | |
488 | ||
489 | ||
490 | reg [4:0] cr_id; | |
491 | ||
492 | ||
493 | assign fifo_wr = c2i_packet_vld & ucb_sel & ~fifo_full; | |
494 | assign ucb_buf_acpt = fifo_wr; | |
495 | ||
496 | //// fifo_din //// | |
497 | assign dmubuf_din_f[143:0] = { | |
498 | parity[11:0], //[143:132] | |
499 | ct_cmd_ecc[4:0], //[131:127] | |
500 | c2i_packet[127:64], //[126:63] pld | |
501 | c2i_packet[63:55], //[62:54] bis,bytemask | |
502 | com_map[1:0], //[53:52] | |
503 | c2i_packet[52:51], //[51:50] dummy, not used// | |
504 | //c2i_packet[50:39], //[49:38] pa35to24 | |
505 | dmupio_addr35to24[11:0], //[49:38] pa35to24 | |
506 | c2i_packet[38:15], //[37:14] pa23to0 | |
507 | c2i_packet[14:12], //[13:11] req_size | |
508 | c2i_packet[10:0] }; //[10:0] 1bit bufid,cputhr[5:0],cmd[3:0]// | |
509 | assign dmubuf_din = mb1_run ? {18{mb1_wdata[7:0]}} : dmubuf_din_f[143:0]; | |
510 | ||
511 | //// ecc / par generation //// | |
512 | ncu_eccgen11_ctl c2ibufpioeccgen11 (.din(c2i_packet[10:0]), .dout(ct_cmd_ecc[4:0]) ); | |
513 | ||
514 | assign parity[0] = ~^{c2i_packet[12],c2i_packet[24],c2i_packet[36], dmupio_addr35to24[9], c2i_packet[60], | |
515 | c2i_packet[72],c2i_packet[84],c2i_packet[96], c2i_packet[108],c2i_packet[120]}; | |
516 | assign parity[1] = ~^{c2i_packet[13],c2i_packet[25],c2i_packet[37], dmupio_addr35to24[10],c2i_packet[61], | |
517 | c2i_packet[73],c2i_packet[85],c2i_packet[97], c2i_packet[109],c2i_packet[121]}; | |
518 | assign parity[2] = ~^{c2i_packet[14],c2i_packet[26],c2i_packet[38], dmupio_addr35to24[11],c2i_packet[62], | |
519 | c2i_packet[74],c2i_packet[86],c2i_packet[98], c2i_packet[110],c2i_packet[122]}; | |
520 | assign parity[3] = ~^{c2i_packet[15],c2i_packet[27],dmupio_addr35to24[0],c2i_packet[51], c2i_packet[63], | |
521 | c2i_packet[75],c2i_packet[87],c2i_packet[99], c2i_packet[111],c2i_packet[123]}; | |
522 | assign parity[4] = ~^{c2i_packet[16],c2i_packet[28],dmupio_addr35to24[1],c2i_packet[52], c2i_packet[64], | |
523 | c2i_packet[76],c2i_packet[88],c2i_packet[100],c2i_packet[112],c2i_packet[124]}; | |
524 | assign parity[5] = ~^{c2i_packet[17],c2i_packet[29],dmupio_addr35to24[2],com_map[0], c2i_packet[65], | |
525 | c2i_packet[77],c2i_packet[89],c2i_packet[101],c2i_packet[113],c2i_packet[125]}; | |
526 | assign parity[6] = ~^{c2i_packet[18],c2i_packet[30],dmupio_addr35to24[3],com_map[1], c2i_packet[66], | |
527 | c2i_packet[78],c2i_packet[90],c2i_packet[102],c2i_packet[114],c2i_packet[126]}; | |
528 | assign parity[7] = ~^{c2i_packet[19],c2i_packet[31],dmupio_addr35to24[4],c2i_packet[55], c2i_packet[67], | |
529 | c2i_packet[79],c2i_packet[91],c2i_packet[103],c2i_packet[115],c2i_packet[127]}; | |
530 | assign parity[8] = ~^{c2i_packet[20],c2i_packet[32],dmupio_addr35to24[5],c2i_packet[56], c2i_packet[68], | |
531 | c2i_packet[80],c2i_packet[92],c2i_packet[104],c2i_packet[116]}; | |
532 | assign parity[9] = ~^{c2i_packet[21],c2i_packet[33],dmupio_addr35to24[6],c2i_packet[57], c2i_packet[69], | |
533 | c2i_packet[81],c2i_packet[93],c2i_packet[105],c2i_packet[117]}; | |
534 | assign parity[10]= ~^{c2i_packet[22],c2i_packet[34],dmupio_addr35to24[7],c2i_packet[58], c2i_packet[70], | |
535 | c2i_packet[82],c2i_packet[94],c2i_packet[106],c2i_packet[118]}; | |
536 | assign parity[11]= ~^{c2i_packet[23],c2i_packet[35],dmupio_addr35to24[8],c2i_packet[59], c2i_packet[71], | |
537 | c2i_packet[83],c2i_packet[95],c2i_packet[107],c2i_packet[119]}; | |
538 | ||
539 | ||
540 | ||
541 | //====================================================================== | |
542 | //================== dbl_buf =========================================== | |
543 | // jimmu : ============ (now has become 64entries fifo)================= | |
544 | ////write dbl_buf//// | |
545 | //fifo_din | |
546 | //fifo_wr | |
547 | //fifo_full | |
548 | ////read dbl_buf//// | |
549 | //fifo_dout_v | |
550 | //fifo_dout | |
551 | //fifo_rd | |
552 | //// mem signals //// | |
553 | //memdin | |
554 | //memwaddr | |
555 | //memwren | |
556 | //wr_clk | |
557 | //memdout | |
558 | //memraddr | |
559 | //memrden | |
560 | //rd_clk | |
561 | ||
562 | assign pipe_full = ~aov ? (pav & pbv & fifo_dout_v) : | |
563 | ~pav ? (pbv & fifo_dout_v) : | |
564 | ~pbv ? (fifo_dout_v) : 1'b1 ; | |
565 | ||
566 | assign raddr_inc = aog & (fifo_rd | ~pipe_full) ; | |
567 | assign raddr_p1[6:0] = raddr[6:0]+7'd1 ; | |
568 | assign raddr_muxed[6:0] = raddr_inc ? raddr_p1[6:0] : raddr[6:0] ; | |
569 | ||
570 | assign waddr_n[6:0] = fifo_wr ? waddr_p1[6:0] : waddr[6:0] ; | |
571 | assign waddr_p1[6:0] = waddr[6:0]+7'd1 ; | |
572 | ||
573 | assign aov_n = dmubuf_rden_nobist_eco & (raddr_inc | ~aog); | |
574 | ||
575 | assign pa_ld = (pav==fifo_dout_ld) ; | |
576 | ||
577 | assign pb_ld = (~pav | fifo_dout_ld | ~pbv) ; | |
578 | ||
579 | assign pbs_n = pas ? (aov & !pbv & pav)&fifo_rd : fifo_dout_ld ; | |
580 | ||
581 | assign pas = ~pbs; | |
582 | ||
583 | assign mov = pas ? pav : pbv ; | |
584 | ||
585 | assign fifo_dout_ld = mov & (~fifo_dout_v | fifo_rd) ; | |
586 | assign fifo_dout_v_n = fifo_dout_v ? (~fifo_rd|mov) : mov ; | |
587 | ||
588 | assign a_full = (waddr_p1[6]^raddr[6]) & (waddr_p1[5:0]==raddr[5:0]) ; | |
589 | assign t_full = (waddr[6]^raddr[6]) & (waddr[5:0]==raddr[5:0]) ; | |
590 | assign fifo_full_n = (a_full&(fifo_wr&~fifo_rd))|t_full; | |
591 | ||
592 | assign dmubuf_waddr[4:0] = mb1_run ? mb1_addr[4:0] : waddr[4:0] ; | |
593 | assign dmubuf0_wr= mb1_run ? mb1_dmubuf0_wr_en : (fifo_wr&~waddr[5]); | |
594 | assign dmubuf1_wr= mb1_run ? mb1_dmubuf1_wr_en : (fifo_wr& waddr[5]); | |
595 | ||
596 | assign dmubuf_raddr[4:0] = mb1_run ? mb1_addr[4:0] : raddr_muxed[4:0] ; | |
597 | assign dmubuf_rden = mb1_run ? (mb1_dmubuf0_rd_en|mb1_dmubuf1_rd_en) : (waddr[6:0]!=raddr_muxed[6:0]) ; | |
598 | assign dmubuf_rden_nobist_eco = (waddr[6:0]!=raddr_muxed[6:0]) ; | |
599 | assign dmubuf_dout[143:0] = dmubuf1_sel2 ? dmubuf1_dout[143:0] : dmubuf0_dout[143:0] ; | |
600 | ||
601 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 aog_ff | |
602 | ( | |
603 | .scan_in(aog_ff_scanin), | |
604 | .scan_out(aog_ff_scanout), | |
605 | .dout (aog), | |
606 | .l1clk (l1clk), | |
607 | .din (dmubuf_rden_nobist_eco ), | |
608 | .siclk(siclk), | |
609 | .soclk(soclk) | |
610 | ); | |
611 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 aov_ff | |
612 | ( | |
613 | .scan_in(aov_ff_scanin), | |
614 | .scan_out(aov_ff_scanout), | |
615 | .dout (aov), | |
616 | .l1clk (l1clk), | |
617 | .din (aov_n), | |
618 | .siclk(siclk), | |
619 | .soclk(soclk) | |
620 | ); | |
621 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 pav_ff | |
622 | ( | |
623 | .scan_in(pav_ff_scanin), | |
624 | .scan_out(pav_ff_scanout), | |
625 | .dout (pav), | |
626 | .l1clk (l1clk), | |
627 | .en (pa_ld), | |
628 | .din (pbv), | |
629 | .siclk(siclk), | |
630 | .soclk(soclk) | |
631 | ); | |
632 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 pbv_ff | |
633 | ( | |
634 | .scan_in(pbv_ff_scanin), | |
635 | .scan_out(pbv_ff_scanout), | |
636 | .dout (pbv), | |
637 | .l1clk (l1clk), | |
638 | .en (pb_ld), | |
639 | .din (aov), | |
640 | .siclk(siclk), | |
641 | .soclk(soclk) | |
642 | ); | |
643 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 pbs_ff | |
644 | ( | |
645 | .scan_in(pbs_ff_scanin), | |
646 | .scan_out(pbs_ff_scanout), | |
647 | .dout (pbs), | |
648 | .l1clk (l1clk), | |
649 | .din (pbs_n), | |
650 | .siclk(siclk), | |
651 | .soclk(soclk) | |
652 | ); | |
653 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 dmubuf1_sel1_ff | |
654 | ( | |
655 | .scan_in(dmubuf1_sel1_ff_scanin), | |
656 | .scan_out(dmubuf1_sel1_ff_scanout), | |
657 | .dout (dmubuf1_sel1), | |
658 | .l1clk (l1clk), | |
659 | .din (raddr_muxed[5]), | |
660 | .siclk(siclk), | |
661 | .soclk(soclk) | |
662 | ); | |
663 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 dmubuf1_sel2_ff | |
664 | ( | |
665 | .scan_in(dmubuf1_sel2_ff_scanin), | |
666 | .scan_out(dmubuf1_sel2_ff_scanout), | |
667 | .dout (dmubuf1_sel2), | |
668 | .l1clk (l1clk), | |
669 | .din (dmubuf1_sel1), | |
670 | .siclk(siclk), | |
671 | .soclk(soclk) | |
672 | ); | |
673 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_7 raddr_ff | |
674 | ( | |
675 | .scan_in(raddr_ff_scanin), | |
676 | .scan_out(raddr_ff_scanout), | |
677 | .dout (raddr[6:0]), | |
678 | .l1clk (l1clk), | |
679 | .din (raddr_muxed[6:0]), | |
680 | .siclk(siclk), | |
681 | .soclk(soclk) | |
682 | ); | |
683 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_7 waddr_ff | |
684 | ( | |
685 | .scan_in(waddr_ff_scanin), | |
686 | .scan_out(waddr_ff_scanout), | |
687 | .dout (waddr[6:0]), | |
688 | .l1clk (l1clk), | |
689 | .din (waddr_n[6:0]), | |
690 | .siclk(siclk), | |
691 | .soclk(soclk) | |
692 | ); | |
693 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 fifo_full_ff | |
694 | ( | |
695 | .scan_in(fifo_full_ff_scanin), | |
696 | .scan_out(fifo_full_ff_scanout), | |
697 | .dout (fifo_full), | |
698 | .l1clk (l1clk), | |
699 | .din (fifo_full_n), | |
700 | .siclk(siclk), | |
701 | .soclk(soclk) | |
702 | ); | |
703 | ||
704 | ||
705 | // jimmy : cntr[15:0] <= mov ? cntr[15:0]+1'b1 : cntr[15:0] ; | |
706 | ||
707 | assign dout_muxed_a[143:0] = pas ? pad[143:0] : dmubuf_dout[143:0] ; | |
708 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_144 pad_ff | |
709 | ( | |
710 | .scan_in(pad_ff_scanin), | |
711 | .scan_out(pad_ff_scanout), | |
712 | .dout (pad[143:0]), | |
713 | .l1clk (l1clk), | |
714 | .en (pa_ld), | |
715 | .din ((dmubuf_dout[143:0])), | |
716 | .siclk(siclk), | |
717 | .soclk(soclk) | |
718 | ); | |
719 | ||
720 | ncu_eccchk11_ctl c2ibufpioeccchk11 ( .din(dout_muxed_a[10:0]), | |
721 | .ci(dout_muxed_a[131:127]), | |
722 | .ue(dmubuf_ue_n), | |
723 | .ce(unused_ce), | |
724 | .dout(dout_muxed_b[10:0]), | |
725 | .co(unused_co[4:0]) ); | |
726 | ||
727 | assign dmubuf_pfail_n[0] = ~^{dout_muxed_a[11],dout_muxed_a[23],dout_muxed_a[35],dout_muxed_a[47],dout_muxed_a[59],dout_muxed_a[71], | |
728 | dout_muxed_a[83],dout_muxed_a[95], dout_muxed_a[107],dout_muxed_a[119],dout_muxed_a[132], dmubuf_pei}; | |
729 | assign dmubuf_pfail_n[1] = ~^{dout_muxed_a[12],dout_muxed_a[24],dout_muxed_a[36],dout_muxed_a[48],dout_muxed_a[60],dout_muxed_a[72], | |
730 | dout_muxed_a[84],dout_muxed_a[96], dout_muxed_a[108],dout_muxed_a[120],dout_muxed_a[133]}; | |
731 | assign dmubuf_pfail_n[2] = ~^{dout_muxed_a[13],dout_muxed_a[25],dout_muxed_a[37],dout_muxed_a[49],dout_muxed_a[61],dout_muxed_a[73], | |
732 | dout_muxed_a[85],dout_muxed_a[97], dout_muxed_a[109],dout_muxed_a[121],dout_muxed_a[134]}; | |
733 | assign dmubuf_pfail_n[3] = ~^{dout_muxed_a[14],dout_muxed_a[26],dout_muxed_a[38],dout_muxed_a[50],dout_muxed_a[62],dout_muxed_a[74], | |
734 | dout_muxed_a[86],dout_muxed_a[98], dout_muxed_a[110],dout_muxed_a[122],dout_muxed_a[135]}; | |
735 | assign dmubuf_pfail_n[4] = ~^{dout_muxed_a[15],dout_muxed_a[27],dout_muxed_a[39],dout_muxed_a[51],dout_muxed_a[63],dout_muxed_a[75], | |
736 | dout_muxed_a[87],dout_muxed_a[99 ],dout_muxed_a[111],dout_muxed_a[123],dout_muxed_a[136]}; | |
737 | assign dmubuf_pfail_n[5] = ~^{dout_muxed_a[16],dout_muxed_a[28],dout_muxed_a[40],dout_muxed_a[52],dout_muxed_a[64],dout_muxed_a[76], | |
738 | dout_muxed_a[88],dout_muxed_a[100],dout_muxed_a[112],dout_muxed_a[124],dout_muxed_a[137]}; | |
739 | assign dmubuf_pfail_n[6] = ~^{dout_muxed_a[17],dout_muxed_a[29],dout_muxed_a[41],dout_muxed_a[53],dout_muxed_a[65],dout_muxed_a[77], | |
740 | dout_muxed_a[89],dout_muxed_a[101],dout_muxed_a[113],dout_muxed_a[125],dout_muxed_a[138]}; | |
741 | assign dmubuf_pfail_n[7] = ~^{dout_muxed_a[18],dout_muxed_a[30],dout_muxed_a[42],dout_muxed_a[54],dout_muxed_a[66],dout_muxed_a[78], | |
742 | dout_muxed_a[90],dout_muxed_a[102],dout_muxed_a[114],dout_muxed_a[126],dout_muxed_a[139]}; | |
743 | assign dmubuf_pfail_n[8] = ~^{dout_muxed_a[19],dout_muxed_a[31],dout_muxed_a[43],dout_muxed_a[55],dout_muxed_a[67],dout_muxed_a[79], | |
744 | dout_muxed_a[91],dout_muxed_a[103],dout_muxed_a[115],dout_muxed_a[140]}; | |
745 | assign dmubuf_pfail_n[9] = ~^{dout_muxed_a[20],dout_muxed_a[32],dout_muxed_a[44],dout_muxed_a[56],dout_muxed_a[68],dout_muxed_a[80], | |
746 | dout_muxed_a[92],dout_muxed_a[104],dout_muxed_a[116],dout_muxed_a[141]}; | |
747 | assign dmubuf_pfail_n[10]= ~^{dout_muxed_a[21],dout_muxed_a[33],dout_muxed_a[45],dout_muxed_a[57],dout_muxed_a[69],dout_muxed_a[81], | |
748 | dout_muxed_a[93],dout_muxed_a[105],dout_muxed_a[117],dout_muxed_a[142]}; | |
749 | assign dmubuf_pfail_n[11]= ~^{dout_muxed_a[22],dout_muxed_a[34],dout_muxed_a[46],dout_muxed_a[58],dout_muxed_a[70],dout_muxed_a[82], | |
750 | dout_muxed_a[94],dout_muxed_a[106],dout_muxed_a[118],dout_muxed_a[143]}; | |
751 | ||
752 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 fifo_dout_v_ff | |
753 | ( | |
754 | .scan_in(fifo_dout_v_ff_scanin), | |
755 | .scan_out(fifo_dout_v_ff_scanout), | |
756 | .dout (fifo_dout_v), | |
757 | .l1clk (l1clk), | |
758 | .din (fifo_dout_v_n), | |
759 | .siclk(siclk), | |
760 | .soclk(soclk) | |
761 | ); | |
762 | ||
763 | assign dout_muxed[126:0] = {dout_muxed_a[126:11],dout_muxed_b[10:0]}; | |
764 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_127 fifo_dout_ff | |
765 | ( | |
766 | .scan_in(fifo_dout_ff_scanin), | |
767 | .scan_out(fifo_dout_ff_scanout), | |
768 | .dout (fifo_dout[126:0]), | |
769 | .l1clk (l1clk), | |
770 | .en (fifo_dout_ld), | |
771 | .din (dout_muxed[126:0]), | |
772 | .siclk(siclk), | |
773 | .soclk(soclk) | |
774 | ); | |
775 | ||
776 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 fifo_dout_pue_ff | |
777 | ( | |
778 | .scan_in(fifo_dout_pue_ff_scanin), | |
779 | .scan_out(fifo_dout_pue_ff_scanout), | |
780 | .dout (fifo_dout_pue), | |
781 | .l1clk (l1clk), | |
782 | .en (fifo_rd|~fifo_dout_v), | |
783 | .din ((|{dmubuf_pfail_n[11:0],dmubuf_ue_n})&fifo_dout_v_n), | |
784 | .siclk(siclk), | |
785 | .soclk(soclk) | |
786 | ); | |
787 | ||
788 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 fifo_dout_pe_ff | |
789 | ( | |
790 | .scan_in(fifo_dout_pe_ff_scanin), | |
791 | .scan_out(fifo_dout_pe_ff_scanout), | |
792 | .dout (fifo_dout_pe), | |
793 | .l1clk (l1clk), | |
794 | .en (fifo_rd|~fifo_dout_v), | |
795 | .din ((|{dmubuf_pfail_n[11:0]})&fifo_dout_v_n), | |
796 | .siclk(siclk), | |
797 | .soclk(soclk) | |
798 | ); | |
799 | ||
800 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 fifo_dout_ue_ff | |
801 | ( | |
802 | .scan_in(fifo_dout_ue_ff_scanin), | |
803 | .scan_out(fifo_dout_ue_ff_scanout), | |
804 | .dout (fifo_dout_ue), | |
805 | .l1clk (l1clk), | |
806 | .en (fifo_rd|~fifo_dout_v), | |
807 | .din (dmubuf_ue_n&fifo_dout_v_n), | |
808 | .siclk(siclk), | |
809 | .soclk(soclk) | |
810 | ); | |
811 | ||
812 | assign dmubufsyn_rtyp[4:0] = dout_muxed_b[0] ? `PCX_STORE_RQ : `PCX_LOAD_RQ ; | |
813 | ||
814 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_47 dmubufsyn_ff | |
815 | ( | |
816 | .scan_in(dmubufsyn_ff_scanin), | |
817 | .scan_out(dmubufsyn_ff_scanout), | |
818 | .dout (dmubufsyn[46:0]), | |
819 | .l1clk (l1clk), | |
820 | .en (fifo_dout_ld), | |
821 | .din ({dmubufsyn_rtyp[4:0],dout_muxed_b[9:4],dout_muxed[49:14]}), | |
822 | .siclk(siclk), | |
823 | .soclk(soclk) | |
824 | ); | |
825 | ||
826 | assign dmubuf_pue = fifo_dout_pue ; | |
827 | ||
828 | assign fifo_rd = fifo_rd_from_pio | (fifo_dout_ue) | (fifo_dout_pe&iobuf_avail) ; | |
829 | ||
830 | //=========================================== dbl_buf ================= | |
831 | //===================================================================== | |
832 | //===================================================================== | |
833 | ||
834 | ||
835 | ||
836 | assign piowr = (fifo_dout[3:0]==`UCB_WRITE_REQ) ; //nq signal // | |
837 | ||
838 | assign pio_rdy = fifo_dout_v & ~fifo_dout_pue & ~dmu_pio_bb & ~mmufsh_vld & cr_id_vld ; | |
839 | assign pio_ld = pio_rdy & ((piowr&iobuf_avail)|~piowr); | |
840 | assign fifo_rd_from_pio = pio_ld; | |
841 | assign cr_id_con = pio_ld; | |
842 | assign mmu_ld = mmufsh_vld & ~dmu_pio_bb; | |
843 | ||
844 | //eco 060628 zero out addr bit 28 for cmd_map = io space (when bit 28 is 1)// | |
845 | // | |
846 | ||
847 | ||
848 | ||
849 | //// puting together the PIO packet //// | |
850 | assign pa_lower3bits[2:0] = fifo_dout[16:14] & {3{~piowr}} ; //turn off lower 3 bits for pio wr// | |
851 | assign eco060628net1 = fifo_dout[53]&fifo_dout[42] ; //fixing bug117042 : turning off addr bit28 for io mapping// | |
852 | assign pio_hdr[63:0] = { 3'b0, //rsvd [63:61] | |
853 | ~piowr, //piord [60], piowr=1 write, piowr=0 read | |
854 | //byte_cnt[3:0], //byte count [53:50] | |
855 | cr_id[3:0], //cr_id [59:56] | |
856 | fifo_dout[61:54], //byte mask [55:48] | |
857 | {1'b0,fifo_dout[10]}, //bufid [47:46] | |
858 | fifo_dout[9:4], //cputh_id [45:40] | |
859 | 2'b0, //rsvd [39:38] | |
860 | fifo_dout[53:52], //com map [37:36] | |
861 | fifo_dout[49:43], //addr35:29 [35:29] | |
862 | eco060628net1, //addr28 [28] | |
863 | fifo_dout[41:17], //addr27:3 [27:3] | |
864 | pa_lower3bits[2:0] //addr2:0 [2:0] | |
865 | }; | |
866 | /////////////////////////////////////////////////////////////////////// | |
867 | /////////////////////////////////////////////////////////////////////// | |
868 | ||
869 | assign ncu_dmu_pio_data_n[63:0] = mmu_ld ? mmufsh_data[63:0] : | |
870 | pio_ld ? pio_hdr[63:0] : dmu_pio_pld[63:0] ; | |
871 | ||
872 | ///////////////////////////////// | |
873 | /////// original parity ///////// | |
874 | //assign ncu_dmu_dpar_n[1:0] = mmu_ld ? {^mmufsh_data[63:32],^mmufsh_data[31:0]} : | |
875 | //pio_ld ? {^pio_hdr[63:32],^pio_hdr[31:0]} : | |
876 | //{^dmu_pio_pld[63:32],^dmu_pio_pld[31:0]} ; | |
877 | ///////////////////////////////// | |
878 | ///// new parity //////////////// | |
879 | assign ncu_dmu_dpar_n[0] = | |
880 | ~^{ncu_dmu_pio_data_n[0], ncu_dmu_pio_data_n[2], ncu_dmu_pio_data_n[4], ncu_dmu_pio_data_n[6], | |
881 | ncu_dmu_pio_data_n[8], ncu_dmu_pio_data_n[10],ncu_dmu_pio_data_n[12],ncu_dmu_pio_data_n[14], | |
882 | ncu_dmu_pio_data_n[16],ncu_dmu_pio_data_n[18],ncu_dmu_pio_data_n[20],ncu_dmu_pio_data_n[22], | |
883 | ncu_dmu_pio_data_n[24],ncu_dmu_pio_data_n[26],ncu_dmu_pio_data_n[28],ncu_dmu_pio_data_n[30], | |
884 | ncu_dmu_pio_data_n[32],ncu_dmu_pio_data_n[34],ncu_dmu_pio_data_n[36],ncu_dmu_pio_data_n[38], | |
885 | ncu_dmu_pio_data_n[40],ncu_dmu_pio_data_n[42],ncu_dmu_pio_data_n[44],ncu_dmu_pio_data_n[46], | |
886 | ncu_dmu_pio_data_n[48],ncu_dmu_pio_data_n[50],ncu_dmu_pio_data_n[52],ncu_dmu_pio_data_n[54], | |
887 | ncu_dmu_pio_data_n[56],ncu_dmu_pio_data_n[58],ncu_dmu_pio_data_n[60],ncu_dmu_pio_data_n[62] }; | |
888 | ||
889 | assign ncu_dmu_dpar_n[1] = | |
890 | ~^{ncu_dmu_pio_data_n[1], ncu_dmu_pio_data_n[3], ncu_dmu_pio_data_n[5], ncu_dmu_pio_data_n[7], | |
891 | ncu_dmu_pio_data_n[9], ncu_dmu_pio_data_n[11],ncu_dmu_pio_data_n[13],ncu_dmu_pio_data_n[15], | |
892 | ncu_dmu_pio_data_n[17],ncu_dmu_pio_data_n[19],ncu_dmu_pio_data_n[21],ncu_dmu_pio_data_n[23], | |
893 | ncu_dmu_pio_data_n[25],ncu_dmu_pio_data_n[27],ncu_dmu_pio_data_n[29],ncu_dmu_pio_data_n[31], | |
894 | ncu_dmu_pio_data_n[33],ncu_dmu_pio_data_n[35],ncu_dmu_pio_data_n[37],ncu_dmu_pio_data_n[39], | |
895 | ncu_dmu_pio_data_n[41],ncu_dmu_pio_data_n[43],ncu_dmu_pio_data_n[45],ncu_dmu_pio_data_n[47], | |
896 | ncu_dmu_pio_data_n[49],ncu_dmu_pio_data_n[51],ncu_dmu_pio_data_n[53],ncu_dmu_pio_data_n[55], | |
897 | ncu_dmu_pio_data_n[57],ncu_dmu_pio_data_n[59],ncu_dmu_pio_data_n[61],ncu_dmu_pio_data_n[63] }; | |
898 | ||
899 | ||
900 | ||
901 | assign dmu_pio_bb_n = pio_ld & piowr; | |
902 | ||
903 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 dmu_pio_bb_ff | |
904 | ( | |
905 | .scan_in(dmu_pio_bb_ff_scanin), | |
906 | .scan_out(dmu_pio_bb_ff_scanout), | |
907 | .dout (dmu_pio_bb), | |
908 | .l1clk (l1clk), | |
909 | .din (dmu_pio_bb_n), | |
910 | .siclk(siclk), | |
911 | .soclk(soclk) | |
912 | ); | |
913 | ||
914 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_64 dmu_pio_pld_ff | |
915 | ( | |
916 | .scan_in(dmu_pio_pld_ff_scanin), | |
917 | .scan_out(dmu_pio_pld_ff_scanout), | |
918 | .dout (dmu_pio_pld[63:0]), | |
919 | .l1clk (l1clk), | |
920 | .din (fifo_dout[126:63]), | |
921 | .siclk(siclk), | |
922 | .soclk(soclk) | |
923 | ); | |
924 | ||
925 | assign ncu_dmu_pio_hdr_vld = ncu_dmu_pio_hdr_vld_f & tcu_dbr_gateoff; | |
926 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 ncu_dmu_pio_hdr_vld_ff | |
927 | ( | |
928 | .scan_in(ncu_dmu_pio_hdr_vld_ff_scanin), | |
929 | .scan_out(ncu_dmu_pio_hdr_vld_ff_scanout), | |
930 | .dout (ncu_dmu_pio_hdr_vld_f), | |
931 | .l1clk (l1clk), | |
932 | .din (pio_ld), | |
933 | .siclk(siclk), | |
934 | .soclk(soclk) | |
935 | ); | |
936 | ||
937 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_64 ncu_dmu_pio_data_ff | |
938 | ( | |
939 | .scan_in(ncu_dmu_pio_data_ff_scanin), | |
940 | .scan_out(ncu_dmu_pio_data_ff_scanout), | |
941 | .dout (ncu_dmu_pio_data[63:0]), | |
942 | .l1clk (l1clk), | |
943 | .din (ncu_dmu_pio_data_n[63:0]), | |
944 | .siclk(siclk), | |
945 | .soclk(soclk) | |
946 | ); | |
947 | ||
948 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_2 ncu_dmu_dpar_ff | |
949 | ( | |
950 | .scan_in(ncu_dmu_dpar_ff_scanin), | |
951 | .scan_out(ncu_dmu_dpar_ff_scanout), | |
952 | .dout (ncu_dmu_dpar[1:0]), | |
953 | .l1clk (l1clk), | |
954 | .din (ncu_dmu_dpar_n[1:0]), | |
955 | .siclk(siclk), | |
956 | .soclk(soclk) | |
957 | ); | |
958 | ||
959 | assign ncu_dmu_mmu_addr_vld = ncu_dmu_mmu_addr_vld_f & tcu_dbr_gateoff; | |
960 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 ncu_dmu_mmu_addr_vld_ff | |
961 | ( | |
962 | .scan_in(ncu_dmu_mmu_addr_vld_ff_scanin), | |
963 | .scan_out(ncu_dmu_mmu_addr_vld_ff_scanout), | |
964 | .dout (ncu_dmu_mmu_addr_vld_f), | |
965 | .l1clk (l1clk), | |
966 | .din (mmu_ld), | |
967 | .siclk(siclk), | |
968 | .soclk(soclk) | |
969 | ); | |
970 | ||
971 | assign dmupio_cpx_type[3:0] = piowr ? `CPX_ST_ACK : `CPX_LOAD_RET ; | |
972 | assign dmupio_wrack_pkt[144:0] = | |
973 | {dmupio_cpx_type[3:0], //[144:141] rtntype | |
974 | 1'b0, //[140] l2miss | |
975 | ~piowr,1'b0, //[139:138] err | |
976 | 1'b1, //[137] nc | |
977 | fifo_dout[6:4], //[136:134] thr | |
978 | 6'b0, //[133:128] misc | |
979 | 2'b0, //[127:126] | |
980 | fifo_dout[62], //[125] bis | |
981 | 2'b0, //[124:123] | |
982 | fifo_dout[19:18], //[122:121] addr[5:4] | |
983 | fifo_dout[9:7], //[120:118] cpuid | |
984 | 1'b0, //[117] | |
985 | fifo_dout[24:20], //[116:112] addr[10:6] | |
986 | 7'b0, | |
987 | fifo_dout[17], //addr[3] | |
988 | fifo_dout[61:54], //bytemask | |
989 | 32'b0, | |
990 | fifo_dout[126:63] }; //data | |
991 | ||
992 | assign dmupio_wrack_cpu[7:0] = 8'b0000_0001 << fifo_dout[9:7] ; | |
993 | assign dmupio_wack_iopkt[152:0] = {dmupio_wrack_cpu[7:0],dmupio_wrack_pkt[144:0]}; | |
994 | ||
995 | // adding fifo_dout[10] to the equation. fifo_dout[10] is the 1bit bufid | |
996 | // no ack is needed if a packet is from TCU with bufid 1 | |
997 | assign dmupio_srvc_wack = iobuf_avail & ((pio_rdy&piowr)|(fifo_dout_pe))&~fifo_dout[10]; | |
998 | assign c2i_wait = (pio_rdy&piowr)|(fifo_dout_pe)&~fifo_dout[10] ; | |
999 | ||
1000 | ||
1001 | ||
1002 | //=========== token engine =============== | |
1003 | ||
1004 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 rdy0_ff | |
1005 | ( | |
1006 | .scan_in(rdy0_ff_scanin), | |
1007 | .scan_out(rdy0_ff_scanout), | |
1008 | .dout (rdy0), | |
1009 | .l1clk (l1clk), | |
1010 | .din (1'b1), | |
1011 | .siclk(siclk), | |
1012 | .soclk(soclk) | |
1013 | ); | |
1014 | ||
1015 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 rdy1_ff | |
1016 | ( | |
1017 | .scan_in(rdy1_ff_scanin), | |
1018 | .scan_out(rdy1_ff_scanout), | |
1019 | .dout (rdy1), | |
1020 | .l1clk (l1clk), | |
1021 | .din (rdy0), | |
1022 | .siclk(siclk), | |
1023 | .soclk(soclk) | |
1024 | ); | |
1025 | ||
1026 | // flop input from dmu// | |
1027 | ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 cr_id_rtn1_vld_ff | |
1028 | ( | |
1029 | .scan_in(cr_id_rtn1_vld_ff_scanin), | |
1030 | .scan_out(cr_id_rtn1_vld_ff_scanout), | |
1031 | .dout (dmu_cr_id_rtn_vld), | |
1032 | .l1clk (l1clk), | |
1033 | .en (rdy1), | |
1034 | .din (dmu_ncu_wrack_vld), | |
1035 | .siclk(siclk), | |
1036 | .soclk(soclk) | |
1037 | ); | |
1038 | ||
1039 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_4 cr_id_rtn1_ff | |
1040 | ( | |
1041 | .scan_in(cr_id_rtn1_ff_scanin), | |
1042 | .scan_out(cr_id_rtn1_ff_scanout), | |
1043 | .dout (dmu_cr_id_rtn[3:0]), | |
1044 | .l1clk (l1clk), | |
1045 | .din (dmu_ncu_wrack_tag[3:0]), | |
1046 | .siclk(siclk), | |
1047 | .soclk(soclk) | |
1048 | ); | |
1049 | ||
1050 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 cr_id_rtn1_par_ff | |
1051 | ( | |
1052 | .scan_in(cr_id_rtn1_par_ff_scanin), | |
1053 | .scan_out(cr_id_rtn1_par_ff_scanout), | |
1054 | .dout (dmu_cr_id_rtn_par), | |
1055 | .l1clk (l1clk), | |
1056 | .din (dmu_ncu_wrack_par), | |
1057 | .siclk(siclk), | |
1058 | .soclk(soclk) | |
1059 | ); | |
1060 | ||
1061 | //assign dmu_cr_id_rtn_err = dmu_ncu_wrack_vld & (^dmu_cr_id_rtn[3:0]^dmu_cr_id_rtn_par^dmu_cr_id_rtn_erri); | |
1062 | assign dmu_cr_id_rtn_err = dmu_cr_id_rtn_vld & ~(^dmu_cr_id_rtn[3:0]^dmu_cr_id_rtn_par^dmu_cr_id_rtn_erri); | |
1063 | ||
1064 | assign cr_id_rtn1_sel[15:0] = {16{dmu_cr_id_rtn_vld}} & (16'h0001 << dmu_cr_id_rtn[3:0]) ; | |
1065 | assign cr_id_rtn2_sel[15:0] = {16{sii_cr_id_rtn_vld}} & (16'h0001 << sii_cr_id_rtn[3:0]) ; | |
1066 | ||
1067 | assign cr_id_rtn_sel[15:0] = cr_id_rtn1_sel[15:0] | cr_id_rtn2_sel[15:0] ; | |
1068 | assign cr_id_con_sel[15:0] = {16{cr_id_con}} & (16'h0001 << cr_id[3:0]) ; | |
1069 | ||
1070 | assign cr_id_vld = cr_id[4]; | |
1071 | ||
1072 | assign token_avail_n[15:0] = cr_id_rtn_sel[15:0] | | |
1073 | ( token_avail[15:0] & (~cr_id_con_sel[15:0]) ) ; | |
1074 | ||
1075 | // token_avail should be powered up with all 1's (16'hffff) | |
1076 | assign token_avail_n_[15:0] = ~token_avail_n[15:0]; | |
1077 | assign token_avail[15:0] = ~token_avail_[15:0]; | |
1078 | ncu_c2ibufpio_ctl_msff_ctl_macro__width_16 token_avail_l_ff | |
1079 | ( | |
1080 | .scan_in(token_avail_l_ff_scanin), | |
1081 | .scan_out(token_avail_l_ff_scanout), | |
1082 | .dout (token_avail_[15:0]), | |
1083 | .l1clk (l1clk), | |
1084 | .din (token_avail_n_[15:0]), | |
1085 | .siclk(siclk), | |
1086 | .soclk(soclk) | |
1087 | ); | |
1088 | ||
1089 | always@(token_avail) begin | |
1090 | casex(token_avail[15:0]) // 0in case -parallel -full | |
1091 | 16'bxxxx_xxxx_xxxx_xxx1: cr_id[4:0] = 5'h10; | |
1092 | 16'bxxxx_xxxx_xxxx_xx10: cr_id[4:0] = 5'h11; | |
1093 | 16'bxxxx_xxxx_xxxx_x100: cr_id[4:0] = 5'h12; | |
1094 | 16'bxxxx_xxxx_xxxx_1000: cr_id[4:0] = 5'h13; | |
1095 | 16'bxxxx_xxxx_xxx1_0000: cr_id[4:0] = 5'h14; | |
1096 | 16'bxxxx_xxxx_xx10_0000: cr_id[4:0] = 5'h15; | |
1097 | 16'bxxxx_xxxx_x100_0000: cr_id[4:0] = 5'h16; | |
1098 | 16'bxxxx_xxxx_1000_0000: cr_id[4:0] = 5'h17; | |
1099 | 16'bxxxx_xxx1_0000_0000: cr_id[4:0] = 5'h18; | |
1100 | 16'bxxxx_xx10_0000_0000: cr_id[4:0] = 5'h19; | |
1101 | 16'bxxxx_x100_0000_0000: cr_id[4:0] = 5'h1a; | |
1102 | 16'bxxxx_1000_0000_0000: cr_id[4:0] = 5'h1b; | |
1103 | 16'bxxx1_0000_0000_0000: cr_id[4:0] = 5'h1c; | |
1104 | 16'bxx10_0000_0000_0000: cr_id[4:0] = 5'h1d; | |
1105 | 16'bx100_0000_0000_0000: cr_id[4:0] = 5'h1e; | |
1106 | 16'b1000_0000_0000_0000: cr_id[4:0] = 5'h1f; | |
1107 | default: cr_id[4:0] = 5'h00; | |
1108 | endcase | |
1109 | end | |
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | /**** adding clock header ****/ | |
1117 | ncu_c2ibufpio_ctl_l1clkhdr_ctl_macro clkgen ( | |
1118 | .l2clk (iol2clk), | |
1119 | .l1en (1'b1), | |
1120 | .l1clk (l1clk), | |
1121 | .pce_ov(pce_ov), | |
1122 | .stop(stop), | |
1123 | .se(se) | |
1124 | ); | |
1125 | ||
1126 | /*** building tcu port ***/ | |
1127 | assign siclk = tcu_aclk; | |
1128 | assign soclk = tcu_bclk; | |
1129 | assign se = tcu_scan_en; | |
1130 | assign pce_ov = tcu_pce_ov; | |
1131 | assign stop = tcu_clk_stop; | |
1132 | ||
1133 | // fixscan start: | |
1134 | assign aog_ff_scanin = scan_in ; | |
1135 | assign aov_ff_scanin = aog_ff_scanout ; | |
1136 | assign pav_ff_scanin = aov_ff_scanout ; | |
1137 | assign pbv_ff_scanin = pav_ff_scanout ; | |
1138 | assign pbs_ff_scanin = pbv_ff_scanout ; | |
1139 | assign dmubuf1_sel1_ff_scanin = pbs_ff_scanout ; | |
1140 | assign dmubuf1_sel2_ff_scanin = dmubuf1_sel1_ff_scanout ; | |
1141 | assign raddr_ff_scanin = dmubuf1_sel2_ff_scanout ; | |
1142 | assign waddr_ff_scanin = raddr_ff_scanout ; | |
1143 | assign fifo_full_ff_scanin = waddr_ff_scanout ; | |
1144 | assign pad_ff_scanin = fifo_full_ff_scanout ; | |
1145 | assign fifo_dout_v_ff_scanin = pad_ff_scanout ; | |
1146 | assign fifo_dout_ff_scanin = fifo_dout_v_ff_scanout ; | |
1147 | assign fifo_dout_pue_ff_scanin = fifo_dout_ff_scanout ; | |
1148 | assign fifo_dout_pe_ff_scanin = fifo_dout_pue_ff_scanout ; | |
1149 | assign fifo_dout_ue_ff_scanin = fifo_dout_pe_ff_scanout ; | |
1150 | assign dmubufsyn_ff_scanin = fifo_dout_ue_ff_scanout ; | |
1151 | assign dmu_pio_bb_ff_scanin = dmubufsyn_ff_scanout ; | |
1152 | assign dmu_pio_pld_ff_scanin = dmu_pio_bb_ff_scanout ; | |
1153 | assign ncu_dmu_pio_hdr_vld_ff_scanin = dmu_pio_pld_ff_scanout ; | |
1154 | assign ncu_dmu_pio_data_ff_scanin = ncu_dmu_pio_hdr_vld_ff_scanout; | |
1155 | assign ncu_dmu_dpar_ff_scanin = ncu_dmu_pio_data_ff_scanout; | |
1156 | assign ncu_dmu_mmu_addr_vld_ff_scanin = ncu_dmu_dpar_ff_scanout ; | |
1157 | assign rdy0_ff_scanin = ncu_dmu_mmu_addr_vld_ff_scanout; | |
1158 | assign rdy1_ff_scanin = rdy0_ff_scanout ; | |
1159 | assign cr_id_rtn1_vld_ff_scanin = rdy1_ff_scanout ; | |
1160 | assign cr_id_rtn1_ff_scanin = cr_id_rtn1_vld_ff_scanout; | |
1161 | assign cr_id_rtn1_par_ff_scanin = cr_id_rtn1_ff_scanout ; | |
1162 | assign token_avail_l_ff_scanin = cr_id_rtn1_par_ff_scanout; | |
1163 | assign scan_out = token_avail_l_ff_scanout ; | |
1164 | // fixscan end: | |
1165 | endmodule | |
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | // any PARAMS parms go into naming of macro | |
1172 | ||
1173 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_1 ( | |
1174 | din, | |
1175 | l1clk, | |
1176 | scan_in, | |
1177 | siclk, | |
1178 | soclk, | |
1179 | dout, | |
1180 | scan_out); | |
1181 | wire [0:0] fdin; | |
1182 | ||
1183 | input [0:0] din; | |
1184 | input l1clk; | |
1185 | input scan_in; | |
1186 | ||
1187 | ||
1188 | input siclk; | |
1189 | input soclk; | |
1190 | ||
1191 | output [0:0] dout; | |
1192 | output scan_out; | |
1193 | assign fdin[0:0] = din[0:0]; | |
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | dff #(1) d0_0 ( | |
1201 | .l1clk(l1clk), | |
1202 | .siclk(siclk), | |
1203 | .soclk(soclk), | |
1204 | .d(fdin[0:0]), | |
1205 | .si(scan_in), | |
1206 | .so(scan_out), | |
1207 | .q(dout[0:0]) | |
1208 | ); | |
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | endmodule | |
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | // any PARAMS parms go into naming of macro | |
1236 | ||
1237 | module ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_1 ( | |
1238 | din, | |
1239 | en, | |
1240 | l1clk, | |
1241 | scan_in, | |
1242 | siclk, | |
1243 | soclk, | |
1244 | dout, | |
1245 | scan_out); | |
1246 | wire [0:0] fdin; | |
1247 | ||
1248 | input [0:0] din; | |
1249 | input en; | |
1250 | input l1clk; | |
1251 | input scan_in; | |
1252 | ||
1253 | ||
1254 | input siclk; | |
1255 | input soclk; | |
1256 | ||
1257 | output [0:0] dout; | |
1258 | output scan_out; | |
1259 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | dff #(1) d0_0 ( | |
1267 | .l1clk(l1clk), | |
1268 | .siclk(siclk), | |
1269 | .soclk(soclk), | |
1270 | .d(fdin[0:0]), | |
1271 | .si(scan_in), | |
1272 | .so(scan_out), | |
1273 | .q(dout[0:0]) | |
1274 | ); | |
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | endmodule | |
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | // any PARAMS parms go into naming of macro | |
1302 | ||
1303 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_7 ( | |
1304 | din, | |
1305 | l1clk, | |
1306 | scan_in, | |
1307 | siclk, | |
1308 | soclk, | |
1309 | dout, | |
1310 | scan_out); | |
1311 | wire [6:0] fdin; | |
1312 | wire [5:0] so; | |
1313 | ||
1314 | input [6:0] din; | |
1315 | input l1clk; | |
1316 | input scan_in; | |
1317 | ||
1318 | ||
1319 | input siclk; | |
1320 | input soclk; | |
1321 | ||
1322 | output [6:0] dout; | |
1323 | output scan_out; | |
1324 | assign fdin[6:0] = din[6:0]; | |
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | dff #(7) d0_0 ( | |
1332 | .l1clk(l1clk), | |
1333 | .siclk(siclk), | |
1334 | .soclk(soclk), | |
1335 | .d(fdin[6:0]), | |
1336 | .si({scan_in,so[5:0]}), | |
1337 | .so({so[5:0],scan_out}), | |
1338 | .q(dout[6:0]) | |
1339 | ); | |
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | ||
1350 | ||
1351 | ||
1352 | endmodule | |
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | // any PARAMS parms go into naming of macro | |
1367 | ||
1368 | module ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_144 ( | |
1369 | din, | |
1370 | en, | |
1371 | l1clk, | |
1372 | scan_in, | |
1373 | siclk, | |
1374 | soclk, | |
1375 | dout, | |
1376 | scan_out); | |
1377 | wire [143:0] fdin; | |
1378 | wire [142:0] so; | |
1379 | ||
1380 | input [143:0] din; | |
1381 | input en; | |
1382 | input l1clk; | |
1383 | input scan_in; | |
1384 | ||
1385 | ||
1386 | input siclk; | |
1387 | input soclk; | |
1388 | ||
1389 | output [143:0] dout; | |
1390 | output scan_out; | |
1391 | assign fdin[143:0] = (din[143:0] & {144{en}}) | (dout[143:0] & ~{144{en}}); | |
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | dff #(144) d0_0 ( | |
1399 | .l1clk(l1clk), | |
1400 | .siclk(siclk), | |
1401 | .soclk(soclk), | |
1402 | .d(fdin[143:0]), | |
1403 | .si({scan_in,so[142:0]}), | |
1404 | .so({so[142:0],scan_out}), | |
1405 | .q(dout[143:0]) | |
1406 | ); | |
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | endmodule | |
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | // any PARAMS parms go into naming of macro | |
1427 | ||
1428 | module ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_127 ( | |
1429 | din, | |
1430 | en, | |
1431 | l1clk, | |
1432 | scan_in, | |
1433 | siclk, | |
1434 | soclk, | |
1435 | dout, | |
1436 | scan_out); | |
1437 | wire [126:0] fdin; | |
1438 | wire [125:0] so; | |
1439 | ||
1440 | input [126:0] din; | |
1441 | input en; | |
1442 | input l1clk; | |
1443 | input scan_in; | |
1444 | ||
1445 | ||
1446 | input siclk; | |
1447 | input soclk; | |
1448 | ||
1449 | output [126:0] dout; | |
1450 | output scan_out; | |
1451 | assign fdin[126:0] = (din[126:0] & {127{en}}) | (dout[126:0] & ~{127{en}}); | |
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | dff #(127) d0_0 ( | |
1459 | .l1clk(l1clk), | |
1460 | .siclk(siclk), | |
1461 | .soclk(soclk), | |
1462 | .d(fdin[126:0]), | |
1463 | .si({scan_in,so[125:0]}), | |
1464 | .so({so[125:0],scan_out}), | |
1465 | .q(dout[126:0]) | |
1466 | ); | |
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | endmodule | |
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ||
1489 | ||
1490 | ||
1491 | ||
1492 | ||
1493 | // any PARAMS parms go into naming of macro | |
1494 | ||
1495 | module ncu_c2ibufpio_ctl_msff_ctl_macro__en_1__width_47 ( | |
1496 | din, | |
1497 | en, | |
1498 | l1clk, | |
1499 | scan_in, | |
1500 | siclk, | |
1501 | soclk, | |
1502 | dout, | |
1503 | scan_out); | |
1504 | wire [46:0] fdin; | |
1505 | wire [45:0] so; | |
1506 | ||
1507 | input [46:0] din; | |
1508 | input en; | |
1509 | input l1clk; | |
1510 | input scan_in; | |
1511 | ||
1512 | ||
1513 | input siclk; | |
1514 | input soclk; | |
1515 | ||
1516 | output [46:0] dout; | |
1517 | output scan_out; | |
1518 | assign fdin[46:0] = (din[46:0] & {47{en}}) | (dout[46:0] & ~{47{en}}); | |
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | dff #(47) d0_0 ( | |
1526 | .l1clk(l1clk), | |
1527 | .siclk(siclk), | |
1528 | .soclk(soclk), | |
1529 | .d(fdin[46:0]), | |
1530 | .si({scan_in,so[45:0]}), | |
1531 | .so({so[45:0],scan_out}), | |
1532 | .q(dout[46:0]) | |
1533 | ); | |
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | endmodule | |
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | // any PARAMS parms go into naming of macro | |
1561 | ||
1562 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_64 ( | |
1563 | din, | |
1564 | l1clk, | |
1565 | scan_in, | |
1566 | siclk, | |
1567 | soclk, | |
1568 | dout, | |
1569 | scan_out); | |
1570 | wire [63:0] fdin; | |
1571 | wire [62:0] so; | |
1572 | ||
1573 | input [63:0] din; | |
1574 | input l1clk; | |
1575 | input scan_in; | |
1576 | ||
1577 | ||
1578 | input siclk; | |
1579 | input soclk; | |
1580 | ||
1581 | output [63:0] dout; | |
1582 | output scan_out; | |
1583 | assign fdin[63:0] = din[63:0]; | |
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | ||
1589 | ||
1590 | dff #(64) d0_0 ( | |
1591 | .l1clk(l1clk), | |
1592 | .siclk(siclk), | |
1593 | .soclk(soclk), | |
1594 | .d(fdin[63:0]), | |
1595 | .si({scan_in,so[62:0]}), | |
1596 | .so({so[62:0],scan_out}), | |
1597 | .q(dout[63:0]) | |
1598 | ); | |
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | endmodule | |
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 | ||
1623 | ||
1624 | ||
1625 | // any PARAMS parms go into naming of macro | |
1626 | ||
1627 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_2 ( | |
1628 | din, | |
1629 | l1clk, | |
1630 | scan_in, | |
1631 | siclk, | |
1632 | soclk, | |
1633 | dout, | |
1634 | scan_out); | |
1635 | wire [1:0] fdin; | |
1636 | wire [0:0] so; | |
1637 | ||
1638 | input [1:0] din; | |
1639 | input l1clk; | |
1640 | input scan_in; | |
1641 | ||
1642 | ||
1643 | input siclk; | |
1644 | input soclk; | |
1645 | ||
1646 | output [1:0] dout; | |
1647 | output scan_out; | |
1648 | assign fdin[1:0] = din[1:0]; | |
1649 | ||
1650 | ||
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | dff #(2) d0_0 ( | |
1656 | .l1clk(l1clk), | |
1657 | .siclk(siclk), | |
1658 | .soclk(soclk), | |
1659 | .d(fdin[1:0]), | |
1660 | .si({scan_in,so[0:0]}), | |
1661 | .so({so[0:0],scan_out}), | |
1662 | .q(dout[1:0]) | |
1663 | ); | |
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | endmodule | |
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | ||
1689 | ||
1690 | // any PARAMS parms go into naming of macro | |
1691 | ||
1692 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_4 ( | |
1693 | din, | |
1694 | l1clk, | |
1695 | scan_in, | |
1696 | siclk, | |
1697 | soclk, | |
1698 | dout, | |
1699 | scan_out); | |
1700 | wire [3:0] fdin; | |
1701 | wire [2:0] so; | |
1702 | ||
1703 | input [3:0] din; | |
1704 | input l1clk; | |
1705 | input scan_in; | |
1706 | ||
1707 | ||
1708 | input siclk; | |
1709 | input soclk; | |
1710 | ||
1711 | output [3:0] dout; | |
1712 | output scan_out; | |
1713 | assign fdin[3:0] = din[3:0]; | |
1714 | ||
1715 | ||
1716 | ||
1717 | ||
1718 | ||
1719 | ||
1720 | dff #(4) d0_0 ( | |
1721 | .l1clk(l1clk), | |
1722 | .siclk(siclk), | |
1723 | .soclk(soclk), | |
1724 | .d(fdin[3:0]), | |
1725 | .si({scan_in,so[2:0]}), | |
1726 | .so({so[2:0],scan_out}), | |
1727 | .q(dout[3:0]) | |
1728 | ); | |
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | endmodule | |
1742 | ||
1743 | ||
1744 | ||
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | // any PARAMS parms go into naming of macro | |
1756 | ||
1757 | module ncu_c2ibufpio_ctl_msff_ctl_macro__width_16 ( | |
1758 | din, | |
1759 | l1clk, | |
1760 | scan_in, | |
1761 | siclk, | |
1762 | soclk, | |
1763 | dout, | |
1764 | scan_out); | |
1765 | wire [15:0] fdin; | |
1766 | wire [14:0] so; | |
1767 | ||
1768 | input [15:0] din; | |
1769 | input l1clk; | |
1770 | input scan_in; | |
1771 | ||
1772 | ||
1773 | input siclk; | |
1774 | input soclk; | |
1775 | ||
1776 | output [15:0] dout; | |
1777 | output scan_out; | |
1778 | assign fdin[15:0] = din[15:0]; | |
1779 | ||
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | ||
1785 | dff #(16) d0_0 ( | |
1786 | .l1clk(l1clk), | |
1787 | .siclk(siclk), | |
1788 | .soclk(soclk), | |
1789 | .d(fdin[15:0]), | |
1790 | .si({scan_in,so[14:0]}), | |
1791 | .so({so[14:0],scan_out}), | |
1792 | .q(dout[15:0]) | |
1793 | ); | |
1794 | ||
1795 | ||
1796 | ||
1797 | ||
1798 | ||
1799 | ||
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | endmodule | |
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | ||
1820 | // any PARAMS parms go into naming of macro | |
1821 | ||
1822 | module ncu_c2ibufpio_ctl_l1clkhdr_ctl_macro ( | |
1823 | l2clk, | |
1824 | l1en, | |
1825 | pce_ov, | |
1826 | stop, | |
1827 | se, | |
1828 | l1clk); | |
1829 | ||
1830 | ||
1831 | input l2clk; | |
1832 | input l1en; | |
1833 | input pce_ov; | |
1834 | input stop; | |
1835 | input se; | |
1836 | output l1clk; | |
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | cl_sc1_l1hdr_8x c_0 ( | |
1843 | ||
1844 | ||
1845 | .l2clk(l2clk), | |
1846 | .pce(l1en), | |
1847 | .l1clk(l1clk), | |
1848 | .se(se), | |
1849 | .pce_ov(pce_ov), | |
1850 | .stop(stop) | |
1851 | ); | |
1852 | ||
1853 | ||
1854 | ||
1855 | endmodule | |
1856 | ||
1857 | ||
1858 | ||
1859 | ||
1860 | ||
1861 | ||
1862 | ||
1863 |