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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_ctrl_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define RF_RDEN_OFFSTATE 1'b1 | |
36 | ||
37 | //==================================== | |
38 | `define NCU_INTMANRF_DEPTH 128 | |
39 | `define NCU_INTMANRF_DATAWIDTH 16 | |
40 | `define NCU_INTMANRF_ADDRWIDTH 7 | |
41 | //==================================== | |
42 | ||
43 | //==================================== | |
44 | `define NCU_MONDORF_DEPTH 64 | |
45 | `define NCU_MONDORF_DATAWIDTH 72 | |
46 | `define NCU_MONDORF_ADDRWIDTH 6 | |
47 | //==================================== | |
48 | ||
49 | //==================================== | |
50 | `define NCU_CPUBUFRF_DEPTH 32 | |
51 | `define NCU_CPUBUFRF_DATAWIDTH 144 | |
52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 | |
53 | //==================================== | |
54 | ||
55 | //==================================== | |
56 | `define NCU_IOBUFRF_DEPTH 32 | |
57 | `define NCU_IOBUFRF_DATAWIDTH 144 | |
58 | `define NCU_IOBUFRF_ADDRWIDTH 5 | |
59 | //==================================== | |
60 | ||
61 | //==================================== | |
62 | `define NCU_IOBUF1RF_DEPTH 32 | |
63 | `define NCU_IOBUF1RF_DATAWIDTH 32 | |
64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 | |
65 | //==================================== | |
66 | ||
67 | //==================================== | |
68 | `define NCU_INTBUFRF_DEPTH 32 | |
69 | `define NCU_INTBUFRF_DATAWIDTH 144 | |
70 | `define NCU_INTBUFRF_ADDRWIDTH 5 | |
71 | //==================================== | |
72 | ||
73 | //== fix me : need to remove when warm // | |
74 | //== becomes available // | |
75 | `define WMR_LENGTH 10'd999 | |
76 | `define WMR_LENGTH_P1 10'd1000 | |
77 | ||
78 | //// NCU CSR_MAN address 80_0000_xxxx //// | |
79 | `define NCU_CSR_MAN 16'h0000 | |
80 | `define NCU_CREG_INTMAN 16'h0000 | |
81 | //`define NCU_CREG_INTVECDISP 16'h0800 | |
82 | `define NCU_CREG_MONDOINVEC 16'h0a00 | |
83 | `define NCU_CREG_SERNUM 16'h1000 | |
84 | `define NCU_CREG_FUSESTAT 16'h1008 | |
85 | `define NCU_CREG_COREAVAIL 16'h1010 | |
86 | `define NCU_CREG_BANKAVAIL 16'h1018 | |
87 | `define NCU_CREG_BANK_ENABLE 16'h1020 | |
88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 | |
89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 | |
90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 | |
91 | ||
92 | ||
93 | `define NCU_CREG_MEM32_BASE 16'h2000 | |
94 | `define NCU_CREG_MEM32_MASK 16'h2008 | |
95 | `define NCU_CREG_MEM64_BASE 16'h2010 | |
96 | `define NCU_CREG_MEM64_MASK 16'h2018 | |
97 | `define NCU_CREG_IOCON_BASE 16'h2020 | |
98 | `define NCU_CREG_IOCON_MASK 16'h2028 | |
99 | `define NCU_CREG_MMUFSH 16'h2030 | |
100 | ||
101 | `define NCU_CREG_ESR 16'h3000 | |
102 | `define NCU_CREG_ELE 16'h3008 | |
103 | `define NCU_CREG_EIE 16'h3010 | |
104 | `define NCU_CREG_EJR 16'h3018 | |
105 | `define NCU_CREG_FEE 16'h3020 | |
106 | `define NCU_CREG_PER 16'h3028 | |
107 | `define NCU_CREG_SIISYN 16'h3030 | |
108 | `define NCU_CREG_NCUSYN 16'h3038 | |
109 | `define NCU_CREG_SCKSEL 16'h3040 | |
110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 | |
111 | ||
112 | //// NUC CSR_MONDO address 80_0004_xxxx //// | |
113 | `define NCU_CSR_MONDO 16'h0004 | |
114 | `define NCU_CREG_MDATA0 16'h0000 | |
115 | `define NCU_CREG_MDATA1 16'h0200 | |
116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 | |
117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 | |
118 | `define NCU_CREG_MBUSY 16'h0800 | |
119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 | |
120 | ||
121 | ||
122 | ||
123 | // ASI shared reg 90_xxxx_xxxx// | |
124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" | |
125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" | |
126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" | |
127 | `define NCU_ASI_COREAVAIL 16'h0000 | |
128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 | |
129 | `define NCU_ASI_CORE_ENABLE 16'h0020 | |
130 | `define NCU_ASI_XIR_STEERING 16'h0030 | |
131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 | |
132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 | |
133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 | |
134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 | |
135 | `define NCU_ASI_INTVECDISP 16'h0000 | |
136 | `define NCU_ASI_ERR_STR 16'h1000 | |
137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 | |
138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 | |
139 | ||
140 | ||
141 | //// UCB packet type //// | |
142 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
143 | `define UCB_READ_ACK 4'b0001 | |
144 | `define UCB_WRITE_ACK 4'b0010 | |
145 | `define UCB_IFILL_ACK 4'b0011 | |
146 | `define UCB_IFILL_NACK 4'b0111 | |
147 | ||
148 | `define UCB_READ_REQ 4'b0100 // req types | |
149 | `define UCB_WRITE_REQ 4'b0101 | |
150 | `define UCB_IFILL_REQ 4'b0110 | |
151 | ||
152 | `define UCB_INT 4'b1000 // plain interrupt | |
153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue | |
155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce | |
156 | `define UCB_RESET_VEC 4'b0101 // reset with vector | |
157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
159 | ||
160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce | |
161 | ||
162 | ||
163 | //// PCX packet type //// | |
164 | `define PCX_LOAD_RQ 5'b00000 | |
165 | `define PCX_IMISS_RQ 5'b10000 | |
166 | `define PCX_STORE_RQ 5'b00001 | |
167 | `define PCX_FWD_RQs 5'b01101 | |
168 | `define PCX_FWD_RPYs 5'b01110 | |
169 | ||
170 | //// CPX packet type //// | |
171 | //`define CPX_LOAD_RET 4'b0000 | |
172 | `define CPX_LOAD_RET 4'b1000 | |
173 | `define CPX_ST_ACK 4'b0100 | |
174 | //`define CPX_IFILL_RET 4'b0001 | |
175 | `define CPX_IFILL_RET 4'b1001 | |
176 | `define CPX_INT_RET 4'b0111 | |
177 | `define CPX_INT_SOC 4'b1101 | |
178 | //`define CPX_FWD_RQ_RET 4'b1010 | |
179 | //`define CPX_FWD_RPY_RET 4'b1011 | |
180 | ||
181 | ||
182 | ||
183 | ||
184 | //// Global CSR decode //// | |
185 | `define NCU_CSR 8'h80 | |
186 | `define NIU_CSR 8'h81 | |
187 | //`define RNG_CSR 8'h82 | |
188 | `define DBG1_CSR 8'h86 | |
189 | `define CCU_CSR 8'h83 | |
190 | `define MCU_CSR 8'h84 | |
191 | `define TCU_CSR 8'h85 | |
192 | `define DMU_CSR 8'h88 | |
193 | `define RCU_CSR 8'h89 | |
194 | `define NCU_ASI 8'h90 | |
195 | /////8'h91 ~ 9F reserved | |
196 | /////8'hA0 ~ BF L2 CSR//// | |
197 | `define DMU_PIO 4'hC // C0 ~ CF | |
198 | /////8'hB0 ~ FE reserved | |
199 | `define SSI_CSR 8'hFF | |
200 | ||
201 | ||
202 | //// NCU_SSI //// | |
203 | `define SSI_ADDR 12'hFF_F | |
204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 | |
205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 | |
206 | ||
207 | `define IF_IDLE 2'b00 | |
208 | `define IF_ACPT 2'b01 | |
209 | `define IF_DROP 2'b10 | |
210 | ||
211 | `define SSI_IDLE 3'b000 | |
212 | `define SSI_REQ 3'b001 | |
213 | `define SSI_WDATA 3'b011 | |
214 | `define SSI_REQ_PAR 3'b101 | |
215 | `define SSI_ACK 3'b111 | |
216 | `define SSI_RDATA 3'b110 | |
217 | `define SSI_ACK_PAR 3'b010 | |
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | module ncu_ctrl_ctl ( | |
228 | iol2clk, | |
229 | scan_in, | |
230 | scan_out, | |
231 | tcu_pce_ov, | |
232 | tcu_clk_stop, | |
233 | tcu_scan_en, | |
234 | tcu_aclk, | |
235 | tcu_bclk, | |
236 | tcu_dbr_gateoff, | |
237 | ncu_scksel_sh, | |
238 | ncu_man_ucb_sel, | |
239 | ncu_man_ucb_buf_acpt, | |
240 | ncu_int_ucb_sel, | |
241 | ncu_int_ucb_buf_acpt, | |
242 | bounce_ucb_sel, | |
243 | bounce_ucb_buf_acpt, | |
244 | c2i_packet_vld, | |
245 | c2i_packet_is_rd_req, | |
246 | c2i_packet_is_wr_req, | |
247 | c2i_packet, | |
248 | rd_nack_ucb_sel, | |
249 | rd_nack_ucb_buf_acpt, | |
250 | c2i_rd_nack_packet, | |
251 | tap_mondo_acc_addr_s, | |
252 | tap_mondo_acc_seq_s, | |
253 | tap_mondo_wr_s, | |
254 | tap_mondo_din_s, | |
255 | tap_mondo_acc_seq_d2_f, | |
256 | tap_mondo_acc_addr_invld_d2_f, | |
257 | tap_mondo_dout_d2_f, | |
258 | mmufsh_data, | |
259 | mmufsh_vld, | |
260 | mmu_ld, | |
261 | mem32_mask, | |
262 | mem32_base, | |
263 | mem32_en, | |
264 | mem64_mask, | |
265 | mem64_base, | |
266 | mem64_en, | |
267 | iocon_mask, | |
268 | iocon_base, | |
269 | iocon_en, | |
270 | ncu_man_int_rd, | |
271 | ncu_man_int_vld, | |
272 | ncu_man_int_packet, | |
273 | ncu_man_ack_rd, | |
274 | ncu_man_ack_vld, | |
275 | ncu_man_ack_packet, | |
276 | ncu_int_ack_rd, | |
277 | ncu_int_ack_vld, | |
278 | ncu_int_ack_packet, | |
279 | bounce_ack_rd, | |
280 | bounce_ack_vld, | |
281 | bounce_ack_packet, | |
282 | rd_nack_rd, | |
283 | rd_nack_vld, | |
284 | rd_nack_packet, | |
285 | io_intman_addr, | |
286 | mondoinvec, | |
287 | lhs_intman_acc, | |
288 | intman_pchkf2i2c, | |
289 | io_rd_intman_d2, | |
290 | efu_ncu_fuse_data, | |
291 | efu_ncu_coreavail_dshift, | |
292 | efu_ncu_bankavail_dshift, | |
293 | efu_ncu_fusestat_dshift, | |
294 | efu_ncu_sernum0_dshift, | |
295 | efu_ncu_sernum1_dshift, | |
296 | efu_ncu_sernum2_dshift, | |
297 | ncu_tcu_bank_avail, | |
298 | rst_ncu_unpark_thread, | |
299 | rst_ncu_xir_inv, | |
300 | ncu_rst_xir_done, | |
301 | ncu_spc7_core_enable_status, | |
302 | ncu_spc6_core_enable_status, | |
303 | ncu_spc5_core_enable_status, | |
304 | ncu_spc4_core_enable_status, | |
305 | ncu_spc3_core_enable_status, | |
306 | ncu_spc2_core_enable_status, | |
307 | ncu_spc1_core_enable_status, | |
308 | ncu_spc0_core_enable_status, | |
309 | core_running, | |
310 | core_running_status, | |
311 | coreavail, | |
312 | ncu_dbg1_error_event, | |
313 | tcu_wmr_vec_mask, | |
314 | cmp_tick_enable, | |
315 | l2pm, | |
316 | ncu_spc_pm, | |
317 | ncu_spc_ba01, | |
318 | l2idxhs_en_status, | |
319 | intman_tbl_raddr, | |
320 | intman_tbl_waddr, | |
321 | intman_tbl_wr, | |
322 | intman_tbl_rden, | |
323 | intman_tbl_din, | |
324 | intman_tbl_dout, | |
325 | mb1_raddr, | |
326 | mb1_waddr, | |
327 | mb1_wdata, | |
328 | mb1_intman_wr_en, | |
329 | mb1_intman_rd_en, | |
330 | mb1_run, | |
331 | ncu_rst_fatal_error, | |
332 | ncu_tcu_soc_error, | |
333 | raserrce, | |
334 | raserrue, | |
335 | niu_ncu_d_pe, | |
336 | ncu_niu_d_pei, | |
337 | niu_ncu_ctag_ue, | |
338 | ncu_niu_ctag_uei, | |
339 | niu_ncu_ctag_ce, | |
340 | ncu_niu_ctag_cei, | |
341 | sio_ncu_ctag_ce, | |
342 | ncu_sio_ctag_cei, | |
343 | sio_ncu_ctag_ue, | |
344 | ncu_sio_ctag_uei, | |
345 | ncu_sio_d_pei, | |
346 | dmu_cr_id_rtn_err, | |
347 | dmu_cr_id_rtn_erri, | |
348 | dmu_ncu_d_pe, | |
349 | ncu_dmu_d_pei, | |
350 | dmu_ncu_siicr_pe, | |
351 | ncu_dmu_siicr_pei, | |
352 | dmu_ncu_ctag_ue, | |
353 | ncu_dmu_ctag_uei, | |
354 | dmu_ncu_ctag_ce, | |
355 | ncu_dmu_ctag_cei, | |
356 | dmu_ncu_ncucr_pe, | |
357 | ncu_dmu_ncucr_pei, | |
358 | dmu_ncu_ie, | |
359 | ncu_dmu_iei, | |
360 | sii_ncu_dmua_pe, | |
361 | ncu_sii_dmua_pei, | |
362 | sii_ncu_niud_pe, | |
363 | ncu_sii_niud_pei, | |
364 | sii_ncu_dmud_pe, | |
365 | ncu_sii_dmud_pei, | |
366 | sii_ncu_niua_pe, | |
367 | ncu_sii_niua_pei, | |
368 | sii_ncu_dmuctag_ce, | |
369 | ncu_sii_dmuctag_cei, | |
370 | sii_ncu_niuctag_ce, | |
371 | ncu_sii_niuctag_cei, | |
372 | sii_ncu_dmuctag_ue, | |
373 | ncu_sii_dmuctag_uei, | |
374 | sii_ncu_niuctag_ue, | |
375 | ncu_sii_niuctag_uei, | |
376 | mcu0_ncu_ecc, | |
377 | ncu_mcu0_ecci, | |
378 | mcu0_ncu_fbr, | |
379 | ncu_mcu0_fbri, | |
380 | mcu0_ncu_fbu, | |
381 | ncu_mcu0_fbui, | |
382 | mcu1_ncu_ecc, | |
383 | ncu_mcu1_ecci, | |
384 | mcu1_ncu_fbr, | |
385 | ncu_mcu1_fbri, | |
386 | mcu1_ncu_fbu, | |
387 | ncu_mcu1_fbui, | |
388 | mcu2_ncu_ecc, | |
389 | ncu_mcu2_ecci, | |
390 | mcu2_ncu_fbr, | |
391 | ncu_mcu2_fbri, | |
392 | mcu2_ncu_fbu, | |
393 | ncu_mcu2_fbui, | |
394 | mcu3_ncu_ecc, | |
395 | ncu_mcu3_ecci, | |
396 | mcu3_ncu_fbr, | |
397 | ncu_mcu3_fbri, | |
398 | mcu3_ncu_fbu, | |
399 | ncu_mcu3_fbui, | |
400 | ncuctag_ce, | |
401 | ncuctag_cei, | |
402 | ncuctag_ue, | |
403 | ncuctag_uei, | |
404 | ncusiid_pei, | |
405 | ncusiid_pe, | |
406 | dmubuf_pue, | |
407 | dmubuf_pei, | |
408 | iobuf_ue_f, | |
409 | iobuf_uei, | |
410 | cpubuf_ue, | |
411 | cpubuf_uei, | |
412 | cpubuf_pe, | |
413 | cpubuf_pei, | |
414 | intbuf_ue_f, | |
415 | intbuf_uei, | |
416 | mondotbl_pe_f, | |
417 | mondotbl_pei, | |
418 | siierrsyn, | |
419 | siierrsyn_done, | |
420 | dmubufsyn, | |
421 | cpubufsyn, | |
422 | ncudpsyn, | |
423 | wmr_protect, | |
424 | aclk_wmr) ; | |
425 | wire [3:0] intman_par_din; | |
426 | wire [5:0] intman_ct_din; | |
427 | wire [5:0] intman_vec_din; | |
428 | wire [3:0] intman_par_dout; | |
429 | wire [5:0] intman_ct_dout; | |
430 | wire [5:0] intman_vec_dout; | |
431 | wire ncu_man_ucb_buf_acpt_d1; | |
432 | wire ncu_man_ucb_buf_acpt_d2; | |
433 | wire ncu_man_ucb_buf_acpt_d3; | |
434 | wire ncu_man_ucb_c2i_packet_is_rd_req; | |
435 | wire ncu_man_ack_buf_full; | |
436 | wire ncu_man_int_buf_full; | |
437 | wire xir_busy; | |
438 | wire rasper_ipg; | |
439 | wire ncu_man_ucb_buf_acpt_d1_ff_scanin; | |
440 | wire ncu_man_ucb_buf_acpt_d1_ff_scanout; | |
441 | wire l1clk; | |
442 | wire ncu_man_ucb_buf_acpt_d2_ff_scanin; | |
443 | wire ncu_man_ucb_buf_acpt_d2_ff_scanout; | |
444 | wire ncu_man_ucb_buf_acpt_d3_ff_scanin; | |
445 | wire ncu_man_ucb_buf_acpt_d3_ff_scanout; | |
446 | wire ncu_man_ucb_c2i_packet_data_ff_scanin; | |
447 | wire ncu_man_ucb_c2i_packet_data_ff_scanout; | |
448 | wire [63:0] ncu_man_ucb_c2i_packet_data; | |
449 | wire ncu_man_ucb_c2i_packet_addr_ff_scanin; | |
450 | wire ncu_man_ucb_c2i_packet_addr_ff_scanout; | |
451 | wire [39:0] ncu_man_ucb_c2i_packet_addr; | |
452 | wire ncu_man_ucb_c2i_packet_buf_id_ff_scanin; | |
453 | wire ncu_man_ucb_c2i_packet_buf_id_ff_scanout; | |
454 | wire [1:0] ncu_man_ucb_c2i_packet_buf_id; | |
455 | wire ncu_man_ucb_c2i_packet_cputhr_ff_scanin; | |
456 | wire ncu_man_ucb_c2i_packet_cputhr_ff_scanout; | |
457 | wire [5:0] ncu_man_ucb_c2i_packet_cputhr; | |
458 | wire ncu_man_ucb_c2i_packet_is_rd_req_ff_scanin; | |
459 | wire ncu_man_ucb_c2i_packet_is_rd_req_ff_scanout; | |
460 | wire ncu_man_ucb_c2i_packet_is_wr_req_ff_scanin; | |
461 | wire ncu_man_ucb_c2i_packet_is_wr_req_ff_scanout; | |
462 | wire ncu_man_ucb_c2i_packet_is_wr_req; | |
463 | wire ncu_man_acc; | |
464 | wire ncu_asi_a_acc; | |
465 | wire ncu_asi_b_acc; | |
466 | wire ncu_asi_c_acc; | |
467 | wire creg_intman_dec; | |
468 | wire creg_sernum_dec; | |
469 | wire creg_coreavail_dec; | |
470 | wire creg_fusestat_dec; | |
471 | wire creg_bankavail_dec; | |
472 | wire creg_bank_en_dec; | |
473 | wire creg_bank_en_status_dec; | |
474 | wire creg_l2idxhs_en_dec; | |
475 | wire creg_l2idxhs_en_status_dec; | |
476 | wire creg_mondoinvec_dec; | |
477 | wire creg_mem32_base_dec; | |
478 | wire creg_mem32_mask_dec; | |
479 | wire creg_mem64_base_dec; | |
480 | wire creg_mem64_mask_dec; | |
481 | wire creg_iocon_base_dec; | |
482 | wire creg_iocon_mask_dec; | |
483 | wire creg_mmufsh_dec; | |
484 | wire creg_esr_dec; | |
485 | wire creg_ele_dec; | |
486 | wire creg_eie_dec; | |
487 | wire creg_ejr_dec; | |
488 | wire creg_fee_dec; | |
489 | wire creg_per_dec; | |
490 | wire creg_siisyn_dec; | |
491 | wire creg_ncusyn_dec; | |
492 | wire creg_ncu_scksel_dec; | |
493 | wire creg_dbgtrigen_dec; | |
494 | wire asi_coreavail_dec; | |
495 | wire asi_core_enable_status_dec; | |
496 | wire asi_core_enable_dec; | |
497 | wire asi_xir_steering_dec; | |
498 | wire asi_core_running_dec; | |
499 | wire asi_core_running_status_dec; | |
500 | wire asi_core_runningw1s_dec; | |
501 | wire asi_core_runningw1c_dec; | |
502 | wire asi_ras_err_steering_dec; | |
503 | wire asi_wmr_vec_mask_dec; | |
504 | wire asi_cmp_tick_enable_dec; | |
505 | wire asi_intvecdisp_dec; | |
506 | wire creg_nomatch; | |
507 | wire ncu_man_int_buf_wr; | |
508 | wire intvecdisp_int_wr; | |
509 | wire rasper_int_wr; | |
510 | wire xir_int_wr; | |
511 | wire [24:0] ncu_man_int_buf_din; | |
512 | wire [24:0] xir_int_pkt; | |
513 | wire [24:0] rasper_int_pkt; | |
514 | wire [24:0] intvecdisp_int_pkt; | |
515 | wire aa_wr_buf0; | |
516 | wire aa_buf1_vld; | |
517 | wire aa_buf0_vld; | |
518 | wire aa_buf1_older; | |
519 | wire aa_wr_buf1; | |
520 | wire aa_rd_buf0; | |
521 | wire ncu_man_int_buf_rd; | |
522 | wire aa_rd_buf1; | |
523 | wire aa_rd_buf; | |
524 | wire aa_buf1_older_inv; | |
525 | wire aa_buf1_older_ff_scanin; | |
526 | wire aa_buf1_older_ff_scanout; | |
527 | wire aa_en_vld0; | |
528 | wire aa_en_vld1; | |
529 | wire aa_buf0_vld_ff_scanin; | |
530 | wire aa_buf0_vld_ff_scanout; | |
531 | wire aa_buf1_vld_ff_scanin; | |
532 | wire aa_buf1_vld_ff_scanout; | |
533 | wire aa_buf0_obj_ff_scanin; | |
534 | wire aa_buf0_obj_ff_scanout; | |
535 | wire [24:0] aa_buf0_obj; | |
536 | wire aa_buf1_obj_ff_scanin; | |
537 | wire aa_buf1_obj_ff_scanout; | |
538 | wire [24:0] aa_buf1_obj; | |
539 | wire [24:0] ncu_man_int_buf_dout; | |
540 | wire ncu_man_int_buf_vld; | |
541 | wire ncu_man_ack_buf_wr; | |
542 | wire [63:0] ncu_man_ack_i2c_packet_data; | |
543 | wire [63:0] creg_intman; | |
544 | wire [63:0] creg_sernum; | |
545 | wire [63:0] creg_coreavail; | |
546 | wire [63:0] creg_fusestat; | |
547 | wire [63:0] creg_bankavail; | |
548 | wire [63:0] creg_bank_en; | |
549 | wire [63:0] creg_bank_en_status; | |
550 | wire [63:0] creg_l2idxhs_en; | |
551 | wire [63:0] creg_l2idxhs_en_status; | |
552 | wire [63:0] creg_mondoinvec; | |
553 | wire [63:0] creg_mem32_base; | |
554 | wire [63:0] creg_mem32_mask; | |
555 | wire [63:0] creg_mem64_base; | |
556 | wire [63:0] creg_mem64_mask; | |
557 | wire [63:0] creg_iocon_base; | |
558 | wire [63:0] creg_iocon_mask; | |
559 | wire [63:0] creg_esr; | |
560 | wire [63:0] creg_ele; | |
561 | wire [63:0] creg_eie; | |
562 | wire [63:0] creg_ejr; | |
563 | wire [63:0] creg_fee; | |
564 | wire [63:0] creg_per; | |
565 | wire [63:0] creg_siisyn; | |
566 | wire [63:0] creg_ncusyn; | |
567 | wire [63:0] creg_ncu_scksel; | |
568 | wire [63:0] creg_dbgtrigen; | |
569 | wire [63:0] creg_core_enable_status; | |
570 | wire [63:0] creg_core_enable; | |
571 | wire [63:0] xir_steering; | |
572 | wire [63:0] creg_err_steering; | |
573 | wire [63:0] creg_wmr_vec_mask; | |
574 | wire [63:0] creg_cmp_tick_enable; | |
575 | wire [63:0] creg_core_running_status; | |
576 | wire [3:0] ncu_man_ack_i2c_packet_type; | |
577 | wire intman_pe_n; | |
578 | wire [127:0] ncu_man_ack_i2c_packet; | |
579 | wire [127:0] ncu_man_ack_buf_din; | |
580 | wire bb_wr_buf0; | |
581 | wire bb_buf1_vld; | |
582 | wire bb_buf0_vld; | |
583 | wire bb_buf1_older; | |
584 | wire bb_wr_buf1; | |
585 | wire bb_rd_buf0; | |
586 | wire ncu_man_ack_buf_rd; | |
587 | wire bb_rd_buf1; | |
588 | wire bb_rd_buf; | |
589 | wire bb_buf1_older_inv; | |
590 | wire bb_buf1_older_ff_scanin; | |
591 | wire bb_buf1_older_ff_scanout; | |
592 | wire bb_en_vld0; | |
593 | wire bb_en_vld1; | |
594 | wire bb_buf0_vld_ff_scanin; | |
595 | wire bb_buf0_vld_ff_scanout; | |
596 | wire bb_buf1_vld_ff_scanin; | |
597 | wire bb_buf1_vld_ff_scanout; | |
598 | wire bb_buf0_obj_ff_scanin; | |
599 | wire bb_buf0_obj_ff_scanout; | |
600 | wire [127:0] bb_buf0_obj; | |
601 | wire bb_buf1_obj_ff_scanin; | |
602 | wire bb_buf1_obj_ff_scanout; | |
603 | wire [127:0] bb_buf1_obj; | |
604 | wire [127:0] ncu_man_ack_buf_dout; | |
605 | wire ncu_man_ack_buf_vld; | |
606 | wire [6:0] lhs_intman_addr; | |
607 | wire [6:0] intman_tbl_addr; | |
608 | wire c2i_rd_intman; | |
609 | wire intman_pchk_v; | |
610 | wire [3:0] intman_pchk; | |
611 | wire intman_pei; | |
612 | wire intman_pe_ff_scanin; | |
613 | wire intman_pe_ff_scanout; | |
614 | wire intman_pe; | |
615 | wire intmansyn_ff_scanin; | |
616 | wire intmansyn_ff_scanout; | |
617 | wire [54:0] intmansyn; | |
618 | wire [54:0] intmansyn_n; | |
619 | wire asi_intvecdisp_wr; | |
620 | wire [5:0] intvecdisp_int_vec; | |
621 | wire [5:0] intvecdisp_int_thr; | |
622 | wire coreavail_done; | |
623 | wire coreavail_dshift_d1; | |
624 | wire coreavail_dshift_d2; | |
625 | wire bankavail_done; | |
626 | wire bankavail_dshift_d1; | |
627 | wire bankavail_dshift_d2; | |
628 | wire coreavail_en; | |
629 | wire bankavail_en; | |
630 | wire fuse_stat_en; | |
631 | wire fuse_stat_dshift_d1; | |
632 | wire sernum0_en; | |
633 | wire sernum0_dshift_d1; | |
634 | wire sernum1_en; | |
635 | wire sernum1_dshift_d1; | |
636 | wire sernum2_en; | |
637 | wire sernum2_dshift_d1; | |
638 | wire fuse_data_d1_ff_scanin; | |
639 | wire fuse_data_d1_ff_scanout; | |
640 | wire fuse_data_d1; | |
641 | wire coreavail_dshift_d1_ff_scanin; | |
642 | wire coreavail_dshift_d1_ff_scanout; | |
643 | wire coreavail_dshift_d2_ff_scanin; | |
644 | wire coreavail_dshift_d2_ff_scanout; | |
645 | wire bankavail_dshift_d1_ff_scanin; | |
646 | wire bankavail_dshift_d1_ff_scanout; | |
647 | wire bankavail_dshift_d2_ff_scanin; | |
648 | wire bankavail_dshift_d2_ff_scanout; | |
649 | wire fuse_stat_dshift_d1_ff_scanin; | |
650 | wire fuse_stat_dshift_d1_ff_scanout; | |
651 | wire sernum0_dshift_d1_ff_scanin; | |
652 | wire sernum0_dshift_d1_ff_scanout; | |
653 | wire sernum1_dshift_d1_ff_scanin; | |
654 | wire sernum1_dshift_d1_ff_scanout; | |
655 | wire sernum2_dshift_d1_ff_scanin; | |
656 | wire sernum2_dshift_d1_ff_scanout; | |
657 | wire [21:0] sernum0_next; | |
658 | wire [21:0] sernum0; | |
659 | wire sernum0_ff_scanin; | |
660 | wire sernum0_ff_scanout; | |
661 | wire [21:0] sernum1_next; | |
662 | wire [21:0] sernum1; | |
663 | wire sernum1_ff_scanin; | |
664 | wire sernum1_ff_scanout; | |
665 | wire [19:0] sernum2_next; | |
666 | wire [19:0] sernum2; | |
667 | wire sernum2_ff_scanin; | |
668 | wire sernum2_ff_scanout; | |
669 | wire [63:0] fusestat_next; | |
670 | wire [63:0] fusestat; | |
671 | wire [63:0] fusestat_ff_in; | |
672 | wire fusestat_ff_scanin; | |
673 | wire fusestat_ff_scanout; | |
674 | wire [63:0] fusestat_ff_out; | |
675 | wire [7:0] coreavail_next; | |
676 | wire [7:0] coreavail_ff_in; | |
677 | wire coreavail_ff_scanin; | |
678 | wire coreavail_ff_scanout; | |
679 | wire [7:0] coreavail_ff_out; | |
680 | wire [7:0] bankavail_next; | |
681 | wire [7:0] bankavail; | |
682 | wire [7:0] bankavail_ff_in; | |
683 | wire bankavail_ff_scanin; | |
684 | wire bankavail_ff_scanout; | |
685 | wire [7:0] bankavail_ff_out; | |
686 | wire creg_mondoinvec_wr; | |
687 | wire creg_mondoinvec_ff_scanin; | |
688 | wire creg_mondoinvec_ff_scanout; | |
689 | wire creg_mem32_base_wr; | |
690 | wire creg_mem32_en_ff_scanin; | |
691 | wire creg_mem32_en_ff_scanout; | |
692 | wire creg_mem32_base_ff_scanin; | |
693 | wire creg_mem32_base_ff_scanout; | |
694 | wire creg_mem32_mask_wr; | |
695 | wire creg_mem32_mask_ff_scanin; | |
696 | wire creg_mem32_mask_ff_scanout; | |
697 | wire creg_mem64_base_wr; | |
698 | wire creg_mem64_en_ff_scanin; | |
699 | wire creg_mem64_en_ff_scanout; | |
700 | wire creg_mem64_base_ff_scanin; | |
701 | wire creg_mem64_base_ff_scanout; | |
702 | wire creg_mem64_mask_wr; | |
703 | wire creg_mem64_mask_ff_scanin; | |
704 | wire creg_mem64_mask_ff_scanout; | |
705 | wire creg_iocon_base_wr; | |
706 | wire creg_iocon_en_ff_scanin; | |
707 | wire creg_iocon_en_ff_scanout; | |
708 | wire creg_iocon_base_ff_scanin; | |
709 | wire creg_iocon_base_ff_scanout; | |
710 | wire creg_iocon_mask_wr; | |
711 | wire creg_iocon_mask_ff_scanin; | |
712 | wire creg_iocon_mask_ff_scanout; | |
713 | wire creg_mmufsh_wr; | |
714 | wire creg_mmufsh_ff_scanin; | |
715 | wire creg_mmufsh_ff_scanout; | |
716 | wire mmufsh_vld_next; | |
717 | wire mmufsh_vld_ff_scanin; | |
718 | wire mmufsh_vld_ff_scanout; | |
719 | wire tap_mondo_acc_outstanding; | |
720 | wire tap_mondo_acc_outstanding_d1; | |
721 | wire asi_ras_err_steering_wr; | |
722 | wire asi_wmr_vec_mask_wr; | |
723 | wire asi_cmp_tick_enable_wr; | |
724 | wire [5:0] ras_err_steering_n; | |
725 | wire [5:0] ras_err_steering; | |
726 | wire wmr_vec_mask_n; | |
727 | wire wmr_vec_mask; | |
728 | wire cmp_tick_enable_n; | |
729 | wire asi_wmr_vec_mask_ff_scanin; | |
730 | wire asi_wmr_vec_mask_ff_scanout; | |
731 | wire asi_cmp_tick_enable_ff_scanin; | |
732 | wire asi_cmp_tick_enable_ff_scanout; | |
733 | wire asi_ras_err_steering_ff_scanin; | |
734 | wire asi_ras_err_steering_ff_scanout; | |
735 | wire tap_mondo_acc_addr_39_16_ff_scanin; | |
736 | wire tap_mondo_acc_addr_39_16_ff_scanout; | |
737 | wire [23:0] tap_mondo_acc_addr_39_16; | |
738 | wire tap_mondo_acc_addr_s_ff_scanin; | |
739 | wire tap_mondo_acc_addr_s_ff_scanout; | |
740 | wire tap_mondo_din_s_ff_scanin; | |
741 | wire tap_mondo_din_s_ff_scanout; | |
742 | wire ncu_int_ucb_c2i_packet_is_rd_req_ff_scanin; | |
743 | wire ncu_int_ucb_c2i_packet_is_rd_req_ff_scanout; | |
744 | wire ncu_int_ucb_c2i_packet_is_rd_req; | |
745 | wire ncu_int_ucb_c2i_packet_is_wr_req_ff_scanin; | |
746 | wire ncu_int_ucb_c2i_packet_is_wr_req_ff_scanout; | |
747 | wire ncu_int_ucb_c2i_packet_is_wr_req; | |
748 | wire tap_mondo_acc_seq_next; | |
749 | wire tap_mondo_acc_seq; | |
750 | wire tap_mondo_acc_seq_ff_scanin; | |
751 | wire tap_mondo_acc_seq_ff_scanout; | |
752 | wire tap_mondo_acc_addr_invld_d2_ff_scanin; | |
753 | wire tap_mondo_acc_addr_invld_d2_ff_scanout; | |
754 | wire tap_mondo_acc_addr_invld_d2; | |
755 | wire tap_mondo_acc_seq_d2_ff_scanin; | |
756 | wire tap_mondo_acc_seq_d2_ff_scanout; | |
757 | wire tap_mondo_acc_seq_d2; | |
758 | wire tap_mondo_dout_d2_ff_scanin; | |
759 | wire tap_mondo_dout_d2_ff_scanout; | |
760 | wire [63:0] tap_mondo_dout_d2; | |
761 | wire tap_mondo_acc_outstanding_d1_ff_scanin; | |
762 | wire tap_mondo_acc_outstanding_d1_ff_scanout; | |
763 | wire tap_mondo_rd_done; | |
764 | wire [3:0] ncu_int_ucb_i2c_packet_type; | |
765 | wire [127:0] ncu_int_ucb_i2c_packet; | |
766 | wire ncu_int_ack_packet_ff_scanin; | |
767 | wire ncu_int_ack_packet_ff_scanout; | |
768 | wire ncu_int_ack_vld_next; | |
769 | wire ncu_int_ack_vld_ff_scanin; | |
770 | wire ncu_int_ack_vld_ff_scanout; | |
771 | wire bounce_ack_buf_wr; | |
772 | wire bounce_ack_buf_full; | |
773 | wire [127:0] bounce_ack_buf_din; | |
774 | wire cc_wr_buf0; | |
775 | wire cc_buf1_vld; | |
776 | wire cc_buf0_vld; | |
777 | wire cc_buf1_older; | |
778 | wire cc_wr_buf1; | |
779 | wire cc_rd_buf0; | |
780 | wire bounce_ack_buf_rd; | |
781 | wire cc_rd_buf1; | |
782 | wire cc_rd_buf; | |
783 | wire cc_buf1_older_inv; | |
784 | wire cc_buf1_older_ff_scanin; | |
785 | wire cc_buf1_older_ff_scanout; | |
786 | wire cc_en_vld0; | |
787 | wire cc_en_vld1; | |
788 | wire cc_buf0_vld_ff_scanin; | |
789 | wire cc_buf0_vld_ff_scanout; | |
790 | wire cc_buf1_vld_ff_scanin; | |
791 | wire cc_buf1_vld_ff_scanout; | |
792 | wire cc_buf0_obj_ff_scanin; | |
793 | wire cc_buf0_obj_ff_scanout; | |
794 | wire [127:0] cc_buf0_obj; | |
795 | wire cc_buf1_obj_ff_scanin; | |
796 | wire cc_buf1_obj_ff_scanout; | |
797 | wire [127:0] cc_buf1_obj; | |
798 | wire [127:0] bounce_ack_buf_dout; | |
799 | wire bounce_ack_buf_vld; | |
800 | wire rd_nack_buf_wr; | |
801 | wire rd_nack_buf_full; | |
802 | wire [63:0] rd_nack_buf_din; | |
803 | wire dd_wr_buf0; | |
804 | wire dd_buf1_vld; | |
805 | wire dd_buf0_vld; | |
806 | wire dd_buf1_older; | |
807 | wire dd_wr_buf1; | |
808 | wire dd_rd_buf0; | |
809 | wire rd_nack_buf_rd; | |
810 | wire dd_rd_buf1; | |
811 | wire dd_rd_buf; | |
812 | wire dd_buf1_older_inv; | |
813 | wire dd_buf1_older_ff_scanin; | |
814 | wire dd_buf1_older_ff_scanout; | |
815 | wire dd_en_vld0; | |
816 | wire dd_en_vld1; | |
817 | wire dd_buf0_vld_ff_scanin; | |
818 | wire dd_buf0_vld_ff_scanout; | |
819 | wire dd_buf1_vld_ff_scanin; | |
820 | wire dd_buf1_vld_ff_scanout; | |
821 | wire dd_buf0_obj_ff_scanin; | |
822 | wire dd_buf0_obj_ff_scanout; | |
823 | wire [63:0] dd_buf0_obj; | |
824 | wire dd_buf1_obj_ff_scanin; | |
825 | wire dd_buf1_obj_ff_scanout; | |
826 | wire [63:0] dd_buf1_obj; | |
827 | wire [63:0] rd_nack_buf_dout; | |
828 | wire rd_nack_buf_vld; | |
829 | wire wmr_upd_en; | |
830 | wire wmr_protect_d1; | |
831 | wire wmr_protect_d2; | |
832 | wire wmr_protect_d1_ff_scanin; | |
833 | wire wmr_protect_d1_ff_scanout; | |
834 | wire wmr_protect_d2_ff_scanin; | |
835 | wire wmr_protect_d2_ff_scanout; | |
836 | wire por_upd_en_next; | |
837 | wire por_upd_en; | |
838 | wire por_upd_en_d1; | |
839 | wire por_upd_en_ff_scanin; | |
840 | wire por_upd_en_ff_scanout; | |
841 | wire [7:0] core_enable_a0_default; | |
842 | wire [7:0] c2i_core_en; | |
843 | wire c2i_core_en_a0; | |
844 | wire asi_core_en_wr; | |
845 | wire [7:0] core_enable_next; | |
846 | wire [7:0] core_enable; | |
847 | wire [7:0] core_enable_ff_in; | |
848 | wire core_enable_ff_scanin; | |
849 | wire core_enable_ff_scanout; | |
850 | wire [7:0] core_enable_ff_out; | |
851 | wire [7:0] core_enable_status_next; | |
852 | wire [7:0] core_enable_status; | |
853 | wire [7:0] core_enable_status_ff_in; | |
854 | wire core_enable_status7_ff_scanin; | |
855 | wire core_enable_status7_ff_scanout; | |
856 | wire core_enable_status6_ff_scanin; | |
857 | wire core_enable_status6_ff_scanout; | |
858 | wire core_enable_status5_ff_scanin; | |
859 | wire core_enable_status5_ff_scanout; | |
860 | wire core_enable_status4_ff_scanin; | |
861 | wire core_enable_status4_ff_scanout; | |
862 | wire core_enable_status3_ff_scanin; | |
863 | wire core_enable_status3_ff_scanout; | |
864 | wire core_enable_status2_ff_scanin; | |
865 | wire core_enable_status2_ff_scanout; | |
866 | wire core_enable_status1_ff_scanin; | |
867 | wire core_enable_status1_ff_scanout; | |
868 | wire core_enable_status0_ff_scanin; | |
869 | wire core_enable_status0_ff_scanout; | |
870 | wire coreavail_done_d1_ff_scanin; | |
871 | wire coreavail_done_d1_ff_scanout; | |
872 | wire coreavail_done_d1; | |
873 | wire asi_xir_steering_wr; | |
874 | wire [63:0] core_enable_status64; | |
875 | wire [63:0] c2i_data_by_core_enable_status; | |
876 | wire [63:0] xir_steering_next; | |
877 | wire xir_snapd_vec_vld; | |
878 | wire [55:0] xir_snapd_vec; | |
879 | wire [55:0] xir_snapd_vec_next; | |
880 | wire xir_trigger_d1; | |
881 | wire xir_ld_mini_vec; | |
882 | wire xir_srvcd_mini_vec_vld; | |
883 | wire [7:0] xir_mini_vec_next; | |
884 | wire xir_srvc; | |
885 | wire [7:0] xir_mini_vec; | |
886 | wire xir_trigger_d0_next; | |
887 | wire xir_trigger; | |
888 | wire [2:0] xir_cpuid_p1; | |
889 | wire [2:0] xir_cpuid; | |
890 | wire [2:0] xir_cpuid_next; | |
891 | wire xir_cpuid_inc; | |
892 | wire xir_busy_next; | |
893 | wire xir_trigger_d0; | |
894 | wire xir_busy_falling; | |
895 | wire xir_busy_d1; | |
896 | wire ncu_rst_xir_done_next; | |
897 | wire xir_trigger_next; | |
898 | wire xir_trigger_q; | |
899 | wire [63:0] xir_steering_ff_in; | |
900 | wire xir_steering_ff_scanin; | |
901 | wire xir_steering_ff_scanout; | |
902 | wire [63:0] xir_steering_ff_out; | |
903 | wire xir_trigger_ff_scanin; | |
904 | wire xir_trigger_ff_scanout; | |
905 | wire xir_trigger_d0_ff_scanin; | |
906 | wire xir_trigger_d0_ff_scanout; | |
907 | wire xir_trigger_d1_ff_scanin; | |
908 | wire xir_trigger_d1_ff_scanout; | |
909 | wire xir_snapd_vec_ff_scanin; | |
910 | wire xir_snapd_vec_ff_scanout; | |
911 | wire xir_mini_vec_ff_scanin; | |
912 | wire xir_mini_vec_ff_scanout; | |
913 | wire xir_cpuid_ff_scanin; | |
914 | wire xir_cpuid_ff_scanout; | |
915 | wire xir_busy_ff_scanin; | |
916 | wire xir_busy_ff_scanout; | |
917 | wire xir_busy_d1_ff_scanin; | |
918 | wire xir_busy_d1_ff_scanout; | |
919 | wire ncu_rst_xir_done_ff_scanin; | |
920 | wire ncu_rst_xir_done_ff_scanout; | |
921 | wire [63:0] enable_status_lowest_thr_1hot; | |
922 | wire [63:0] core_running_a0_default; | |
923 | wire [63:0] c2i_w1cdata_by_core_running; | |
924 | wire c2i_core_running_a0; | |
925 | wire c2i_core_runningw1c_a0; | |
926 | wire [63:0] core_runningrw_data; | |
927 | wire [63:0] core_runningw1c_data; | |
928 | wire asi_core_running_wr; | |
929 | wire asi_core_runningw1s_wr; | |
930 | wire asi_core_runningw1c_wr; | |
931 | wire [63:0] core_running_next; | |
932 | wire wake_thread; | |
933 | wire core_running_ff_scanin; | |
934 | wire core_running_ff_scanout; | |
935 | wire core_running_ff_in; | |
936 | wire core_running0_ff_scanin; | |
937 | wire core_running0_ff_scanout; | |
938 | wire core_running_ff_out; | |
939 | wire unpark_thread_d1_ff_scanin; | |
940 | wire unpark_thread_d1_ff_scanout; | |
941 | wire unpark_thread_d1; | |
942 | wire unpark_thread_d2_ff_scanin; | |
943 | wire unpark_thread_d2_ff_scanout; | |
944 | wire unpark_thread_d2; | |
945 | wire wake_ok__ff_scanin; | |
946 | wire wake_ok__ff_scanout; | |
947 | wire wake_ok_inv; | |
948 | wire wake_thread_n; | |
949 | wire wake_thread_ff_scanin; | |
950 | wire wake_thread_ff_scanout; | |
951 | wire core_running_status_ff_scanin; | |
952 | wire core_running_status_ff_scanout; | |
953 | wire core_running_status_ff_in; | |
954 | wire core_running_status0_ff_scanin; | |
955 | wire core_running_status0_ff_scanout; | |
956 | wire core_running_status_ff_out; | |
957 | wire [3:0] bankavail_pair; | |
958 | wire bank_en_wr; | |
959 | wire [7:0] c2i_bank_en; | |
960 | wire c2i_bank_en_a0; | |
961 | wire [7:0] bank_en_next; | |
962 | wire [7:0] bank_en; | |
963 | wire [7:0] bank_en_ff_in; | |
964 | wire bank_en_ff_scanin; | |
965 | wire bank_en_ff_scanout; | |
966 | wire [7:0] bank_en_ff_out; | |
967 | wire l2pm_en; | |
968 | wire [7:0] bank_en_full_status; | |
969 | wire [3:0] bank_en_pair_status; | |
970 | wire [4:0] bank_en_final_status; | |
971 | wire [4:0] l2pm_preview_ff_din; | |
972 | wire [4:0] l2pm_ff_din; | |
973 | wire l2pm_preview_ff_scanin; | |
974 | wire l2pm_preview_ff_scanout; | |
975 | wire [4:0] l2pm_preview_ff_q; | |
976 | wire [4:0] l2pm_preview; | |
977 | wire l2pm_ff_scanin; | |
978 | wire l2pm_ff_scanout; | |
979 | wire [3:1] l2pm_ff_q; | |
980 | wire l2idxhs_en_wr; | |
981 | wire l2idxhs_en_ff_scanin; | |
982 | wire l2idxhs_en_ff_scanout; | |
983 | wire l2idxhs_en; | |
984 | wire l2idxhs_en_status_ff_scanin; | |
985 | wire l2idxhs_en_status_ff_scanout; | |
986 | wire creg_esr_wr; | |
987 | wire iobuf_ue_ff_scanin; | |
988 | wire iobuf_ue_ff_scanout; | |
989 | wire iobuf_ue; | |
990 | wire intbuf_ue_ff_scanin; | |
991 | wire intbuf_ue_ff_scanout; | |
992 | wire intbuf_ue; | |
993 | wire mondotbl_pe_ff_scanin; | |
994 | wire mondotbl_pe_ff_scanout; | |
995 | wire mondotbl_pe; | |
996 | wire mcu3_ncu_ecc_d_ff_scanin; | |
997 | wire mcu3_ncu_ecc_d_ff_scanout; | |
998 | wire mcu3_ncu_ecc_d; | |
999 | wire mcu3_ncu_fbr_d_ff_scanin; | |
1000 | wire mcu3_ncu_fbr_d_ff_scanout; | |
1001 | wire mcu3_ncu_fbr_d; | |
1002 | wire mcu3_ncu_fbu_d_ff_scanin; | |
1003 | wire mcu3_ncu_fbu_d_ff_scanout; | |
1004 | wire mcu3_ncu_fbu_d; | |
1005 | wire mcu2_ncu_ecc_d_ff_scanin; | |
1006 | wire mcu2_ncu_ecc_d_ff_scanout; | |
1007 | wire mcu2_ncu_ecc_d; | |
1008 | wire mcu2_ncu_fbr_d_ff_scanin; | |
1009 | wire mcu2_ncu_fbr_d_ff_scanout; | |
1010 | wire mcu2_ncu_fbr_d; | |
1011 | wire mcu2_ncu_fbu_d_ff_scanin; | |
1012 | wire mcu2_ncu_fbu_d_ff_scanout; | |
1013 | wire mcu2_ncu_fbu_d; | |
1014 | wire mcu1_ncu_ecc_d_ff_scanin; | |
1015 | wire mcu1_ncu_ecc_d_ff_scanout; | |
1016 | wire mcu1_ncu_ecc_d; | |
1017 | wire mcu1_ncu_fbr_d_ff_scanin; | |
1018 | wire mcu1_ncu_fbr_d_ff_scanout; | |
1019 | wire mcu1_ncu_fbr_d; | |
1020 | wire mcu1_ncu_fbu_d_ff_scanin; | |
1021 | wire mcu1_ncu_fbu_d_ff_scanout; | |
1022 | wire mcu1_ncu_fbu_d; | |
1023 | wire mcu0_ncu_ecc_d_ff_scanin; | |
1024 | wire mcu0_ncu_ecc_d_ff_scanout; | |
1025 | wire mcu0_ncu_ecc_d; | |
1026 | wire mcu0_ncu_fbr_d_ff_scanin; | |
1027 | wire mcu0_ncu_fbr_d_ff_scanout; | |
1028 | wire mcu0_ncu_fbr_d; | |
1029 | wire mcu0_ncu_fbu_d_ff_scanin; | |
1030 | wire mcu0_ncu_fbu_d_ff_scanout; | |
1031 | wire mcu0_ncu_fbu_d; | |
1032 | wire niu_ncu_d_pe_d_ff_scanin; | |
1033 | wire niu_ncu_d_pe_d_ff_scanout; | |
1034 | wire niu_ncu_d_pe_d; | |
1035 | wire niu_ncu_ctag_ue_d_ff_scanin; | |
1036 | wire niu_ncu_ctag_ue_d_ff_scanout; | |
1037 | wire niu_ncu_ctag_ue_d; | |
1038 | wire niu_ncu_ctag_ce_d_ff_scanin; | |
1039 | wire niu_ncu_ctag_ce_d_ff_scanout; | |
1040 | wire niu_ncu_ctag_ce_d; | |
1041 | wire sio_ncu_ctag_ce_d_ff_scanin; | |
1042 | wire sio_ncu_ctag_ce_d_ff_scanout; | |
1043 | wire sio_ncu_ctag_ce_d; | |
1044 | wire sio_ncu_ctag_ue_d_ff_scanin; | |
1045 | wire sio_ncu_ctag_ue_d_ff_scanout; | |
1046 | wire sio_ncu_ctag_ue_d; | |
1047 | wire dmu_ncu_d_pe_d_ff_scanin; | |
1048 | wire dmu_ncu_d_pe_d_ff_scanout; | |
1049 | wire dmu_ncu_d_pe_d; | |
1050 | wire dmu_ncu_siicr_pe_d_ff_scanin; | |
1051 | wire dmu_ncu_siicr_pe_d_ff_scanout; | |
1052 | wire dmu_ncu_siicr_pe_d; | |
1053 | wire dmu_ncu_ctag_ue_d_ff_scanin; | |
1054 | wire dmu_ncu_ctag_ue_d_ff_scanout; | |
1055 | wire dmu_ncu_ctag_ue_d; | |
1056 | wire dmu_ncu_ctag_ce_d_ff_scanin; | |
1057 | wire dmu_ncu_ctag_ce_d_ff_scanout; | |
1058 | wire dmu_ncu_ctag_ce_d; | |
1059 | wire dmu_ncu_ncucr_pe_d_ff_scanin; | |
1060 | wire dmu_ncu_ncucr_pe_d_ff_scanout; | |
1061 | wire dmu_ncu_ncucr_pe_d; | |
1062 | wire dmu_ncu_ie_d_ff_scanin; | |
1063 | wire dmu_ncu_ie_d_ff_scanout; | |
1064 | wire dmu_ncu_ie_d; | |
1065 | wire sii_ncu_dmua_pe_d_ff_scanin; | |
1066 | wire sii_ncu_dmua_pe_d_ff_scanout; | |
1067 | wire sii_ncu_dmua_pe_d; | |
1068 | wire sii_ncu_niud_pe_d_ff_scanin; | |
1069 | wire sii_ncu_niud_pe_d_ff_scanout; | |
1070 | wire sii_ncu_niud_pe_d; | |
1071 | wire sii_ncu_dmud_pe_d_ff_scanin; | |
1072 | wire sii_ncu_dmud_pe_d_ff_scanout; | |
1073 | wire sii_ncu_dmud_pe_d; | |
1074 | wire sii_ncu_niua_pe_d_ff_scanin; | |
1075 | wire sii_ncu_niua_pe_d_ff_scanout; | |
1076 | wire sii_ncu_niua_pe_d; | |
1077 | wire sii_ncu_dmuctag_ce_d_ff_scanin; | |
1078 | wire sii_ncu_dmuctag_ce_d_ff_scanout; | |
1079 | wire sii_ncu_dmuctag_ce_d; | |
1080 | wire sii_ncu_niuctag_ce_d_ff_scanin; | |
1081 | wire sii_ncu_niuctag_ce_d_ff_scanout; | |
1082 | wire sii_ncu_niuctag_ce_d; | |
1083 | wire sii_ncu_dmuctag_ue_d_ff_scanin; | |
1084 | wire sii_ncu_dmuctag_ue_d_ff_scanout; | |
1085 | wire sii_ncu_dmuctag_ue_d; | |
1086 | wire sii_ncu_niuctag_ue_d_ff_scanin; | |
1087 | wire sii_ncu_niuctag_ue_d_ff_scanout; | |
1088 | wire sii_ncu_niuctag_ue_d; | |
1089 | wire [42:0] raserr_in; | |
1090 | wire [42:0] rasesr_in; | |
1091 | wire [42:0] rasele; | |
1092 | wire [42:0] rasesr_din; | |
1093 | wire rasesr2per_tgr; | |
1094 | wire [42:0] rasesr; | |
1095 | wire [42:0] rasesr_n; | |
1096 | wire dbgtrigen; | |
1097 | wire rasesr_ff_scanin; | |
1098 | wire rasesr_ff_scanout; | |
1099 | wire rasesr_v_n; | |
1100 | wire rasesr_v_ff_scanin; | |
1101 | wire rasesr_v_ff_scanout; | |
1102 | wire rasesr_v; | |
1103 | wire creg_ele_wr; | |
1104 | wire [42:0] rasele_ff_in; | |
1105 | wire rasele_ff_scanin; | |
1106 | wire rasele_ff_scanout; | |
1107 | wire [42:0] rasele_ff_out; | |
1108 | wire [5:0] siierrsyn_va; | |
1109 | wire [5:0] siierrsyn_vb; | |
1110 | wire [5:0] siisynlog_en; | |
1111 | wire [2:0] siietag; | |
1112 | wire [5:0] ncuerrsyn_va; | |
1113 | wire [42:0] rasper; | |
1114 | wire ncuerrsyn_vb; | |
1115 | wire creg_eie_wr; | |
1116 | wire raseie_ff_scanin; | |
1117 | wire raseie_ff_scanout; | |
1118 | wire [42:0] raseie; | |
1119 | wire creg_ejr_wr; | |
1120 | wire rasejr_ff_scanin; | |
1121 | wire rasejr_ff_scanout; | |
1122 | wire [42:0] rasejr; | |
1123 | wire bit20_d1_ff_scanin; | |
1124 | wire bit20_d1_ff_scanout; | |
1125 | wire bit20_d1; | |
1126 | wire bit20_d2_ff_scanin; | |
1127 | wire bit20_d2_ff_scanout; | |
1128 | wire bit20_d2; | |
1129 | wire bit20_d3_ff_scanin; | |
1130 | wire bit20_d3_ff_scanout; | |
1131 | wire bit20_d3; | |
1132 | wire bit20_d4_ff_scanin; | |
1133 | wire bit20_d4_ff_scanout; | |
1134 | wire bit20_d4; | |
1135 | wire bit20_d5_ff_scanin; | |
1136 | wire bit20_d5_ff_scanout; | |
1137 | wire bit20_d5; | |
1138 | wire ncu_dmu_d_pei_f; | |
1139 | wire ncu_dmu_siicr_pei_f; | |
1140 | wire ncu_dmu_ctag_uei_f; | |
1141 | wire ncu_dmu_ctag_cei_f; | |
1142 | wire ncu_dmu_ncucr_pei_f; | |
1143 | wire ncu_dmu_iei_f; | |
1144 | wire ncu_niu_ctag_cei_f; | |
1145 | wire ncu_niu_ctag_uei_f; | |
1146 | wire ncu_niu_d_pei_f; | |
1147 | wire creg_fee_wr; | |
1148 | wire rasfee_ff_scanin; | |
1149 | wire rasfee_ff_scanout; | |
1150 | wire [42:0] rasfee; | |
1151 | wire ncu_rst_fatal_error_n; | |
1152 | wire ncu_rst_fatal_error_ff_scanin; | |
1153 | wire ncu_rst_fatal_error_ff_scanout; | |
1154 | wire creg_per_wr; | |
1155 | wire [42:0] rasper_in; | |
1156 | wire rasper_in_v; | |
1157 | wire [42:0] rasper_n; | |
1158 | wire rasper_ff_scanin; | |
1159 | wire rasper_ff_scanout; | |
1160 | wire rasper_v; | |
1161 | wire rasper_v_n; | |
1162 | wire rasper_v_ff_scanin; | |
1163 | wire rasper_v_ff_scanout; | |
1164 | wire rasper_ipg_n; | |
1165 | wire rasper_srvc; | |
1166 | wire rasper_ipg_ff_scanin; | |
1167 | wire rasper_ipg_ff_scanout; | |
1168 | wire rasesr2per_tgr_d_ff_scanin; | |
1169 | wire rasesr2per_tgr_d_ff_scanout; | |
1170 | wire rasesr2per_tgr_d; | |
1171 | wire ncu_tcu_soc_error_ff_scanin; | |
1172 | wire ncu_tcu_soc_error_ff_scanout; | |
1173 | wire [3:0] ucb_soc_int_type; | |
1174 | wire creg_siisyn_wr; | |
1175 | wire [58:0] siisyn_n; | |
1176 | wire siierrsyn_vc; | |
1177 | wire siisyn_v; | |
1178 | wire siisyn_ff_scanin; | |
1179 | wire siisyn_ff_scanout; | |
1180 | wire [58:0] siisyn; | |
1181 | wire siisyn_v_n; | |
1182 | wire siisyn_v_ff_scanin; | |
1183 | wire siisyn_v_ff_scanout; | |
1184 | wire creg_ncusyn_wr; | |
1185 | wire creg_ncu_scksel_wr; | |
1186 | wire creg_dbgtrigen_wr; | |
1187 | wire [60:0] ncuerrsyn; | |
1188 | wire [4:0] ncu_etag; | |
1189 | wire [60:0] ncusyn_n; | |
1190 | wire ncuerrsyn_vc; | |
1191 | wire ncusyn_v; | |
1192 | wire ncusyn_ff_scanin; | |
1193 | wire ncusyn_ff_scanout; | |
1194 | wire [60:0] ncusyn; | |
1195 | wire ncusyn_v_n; | |
1196 | wire ncusyn_v_ff_scanin; | |
1197 | wire ncusyn_v_ff_scanout; | |
1198 | wire [1:0] ncu_scksel_n; | |
1199 | wire [1:0] ncu_scksel; | |
1200 | wire ncu_scksel_ff_scanin; | |
1201 | wire ncu_scksel_ff_scanout; | |
1202 | wire scksel_sh_ff_scanin; | |
1203 | wire scksel_sh_ff_scanout; | |
1204 | wire dbgtrigen_n; | |
1205 | wire dbgtrigen_ff_scanin; | |
1206 | wire dbgtrigen_ff_scanout; | |
1207 | wire siclk; | |
1208 | wire soclk; | |
1209 | wire se; | |
1210 | wire pce_ov; | |
1211 | wire stop; | |
1212 | wire wmrp_chain_scanout; | |
1213 | ||
1214 | ||
1215 | //////////////////////////////////////////////////////////////////////// | |
1216 | // Signal declarations | |
1217 | //////////////////////////////////////////////////////////////////////// | |
1218 | // Global interface | |
1219 | input iol2clk; | |
1220 | ||
1221 | input scan_in; | |
1222 | output scan_out; | |
1223 | input tcu_pce_ov; | |
1224 | input tcu_clk_stop; | |
1225 | input tcu_scan_en; | |
1226 | input tcu_aclk; | |
1227 | input tcu_bclk; | |
1228 | input tcu_dbr_gateoff; | |
1229 | output[1:0] ncu_scksel_sh; // goes to ssisif_ctl | |
1230 | ||
1231 | // c2i interface | |
1232 | // Accessing IOB control registers | |
1233 | // Bounce back master request/ack | |
1234 | // Read Nack | |
1235 | input ncu_man_ucb_sel; | |
1236 | output ncu_man_ucb_buf_acpt; | |
1237 | ||
1238 | input ncu_int_ucb_sel; | |
1239 | output ncu_int_ucb_buf_acpt; | |
1240 | ||
1241 | input bounce_ucb_sel; | |
1242 | output bounce_ucb_buf_acpt; | |
1243 | ||
1244 | input c2i_packet_vld; | |
1245 | ||
1246 | input c2i_packet_is_rd_req; | |
1247 | input c2i_packet_is_wr_req; | |
1248 | input [127:0] c2i_packet; | |
1249 | ||
1250 | input rd_nack_ucb_sel; | |
1251 | output rd_nack_ucb_buf_acpt; | |
1252 | input [63:0] c2i_rd_nack_packet; | |
1253 | ||
1254 | // c2i interface | |
1255 | // Interrupt status tbl read/write from TAP | |
1256 | output [21:0] tap_mondo_acc_addr_s; | |
1257 | output tap_mondo_acc_seq_s; | |
1258 | output tap_mondo_wr_s; | |
1259 | output [63:0] tap_mondo_din_s; | |
1260 | ||
1261 | input tap_mondo_acc_seq_d2_f; | |
1262 | input tap_mondo_acc_addr_invld_d2_f; | |
1263 | input [63:0] tap_mondo_dout_d2_f; | |
1264 | ||
1265 | // c2i interface | |
1266 | // dmupio related signals | |
1267 | output [63:0] mmufsh_data; | |
1268 | output mmufsh_vld; | |
1269 | input mmu_ld; | |
1270 | ||
1271 | output [11:0] mem32_mask; | |
1272 | output [11:0] mem32_base; | |
1273 | output mem32_en; | |
1274 | output [11:0] mem64_mask; | |
1275 | output [11:0] mem64_base; | |
1276 | output mem64_en; | |
1277 | output [11:0] iocon_mask; | |
1278 | output [11:0] iocon_base; | |
1279 | output iocon_en; | |
1280 | ||
1281 | // i2c interface | |
1282 | // Sending interrupts/Returning acks or nacks | |
1283 | input ncu_man_int_rd; | |
1284 | output ncu_man_int_vld; | |
1285 | output [24:0] ncu_man_int_packet; | |
1286 | ||
1287 | input ncu_man_ack_rd; | |
1288 | output ncu_man_ack_vld; | |
1289 | output [127:0] ncu_man_ack_packet; | |
1290 | ||
1291 | input ncu_int_ack_rd; | |
1292 | output ncu_int_ack_vld; | |
1293 | output [127:0] ncu_int_ack_packet; | |
1294 | ||
1295 | input bounce_ack_rd; | |
1296 | output bounce_ack_vld; | |
1297 | output [127:0] bounce_ack_packet; | |
1298 | ||
1299 | input rd_nack_rd; | |
1300 | output rd_nack_vld; | |
1301 | output [63:0] rd_nack_packet; | |
1302 | ||
1303 | // i2c interface | |
1304 | input [6:0] io_intman_addr; | |
1305 | output [5:0] mondoinvec; | |
1306 | output lhs_intman_acc; | |
1307 | output intman_pchkf2i2c; | |
1308 | input io_rd_intman_d2; | |
1309 | ||
1310 | // efuse control interface | |
1311 | input efu_ncu_fuse_data; | |
1312 | input efu_ncu_coreavail_dshift; | |
1313 | input efu_ncu_bankavail_dshift; | |
1314 | input efu_ncu_fusestat_dshift; | |
1315 | input efu_ncu_sernum0_dshift; | |
1316 | input efu_ncu_sernum1_dshift; | |
1317 | input efu_ncu_sernum2_dshift; | |
1318 | output [7:0] ncu_tcu_bank_avail; | |
1319 | //output [3:0] ncu_tcu_bank_en_status; | |
1320 | ||
1321 | // ASI related | |
1322 | input rst_ncu_unpark_thread; | |
1323 | input rst_ncu_xir_inv; | |
1324 | output ncu_rst_xir_done; | |
1325 | ||
1326 | //output [7:0] core_enable_status; | |
1327 | ||
1328 | output ncu_spc7_core_enable_status; | |
1329 | output ncu_spc6_core_enable_status; | |
1330 | output ncu_spc5_core_enable_status; | |
1331 | output ncu_spc4_core_enable_status; | |
1332 | output ncu_spc3_core_enable_status; | |
1333 | output ncu_spc2_core_enable_status; | |
1334 | output ncu_spc1_core_enable_status; | |
1335 | output ncu_spc0_core_enable_status; | |
1336 | ||
1337 | output [63:0] core_running; | |
1338 | input [63:0] core_running_status; | |
1339 | output [7:0] coreavail; | |
1340 | output ncu_dbg1_error_event; | |
1341 | output tcu_wmr_vec_mask; | |
1342 | output cmp_tick_enable; | |
1343 | ||
1344 | // partial mode | |
1345 | output [4:0] l2pm ; | |
1346 | output ncu_spc_pm; | |
1347 | output ncu_spc_ba01; | |
1348 | ||
1349 | // index hashing | |
1350 | output l2idxhs_en_status; | |
1351 | ||
1352 | /**** intman mem ****/ | |
1353 | output [6:0] intman_tbl_raddr; | |
1354 | output [6:0] intman_tbl_waddr; | |
1355 | output intman_tbl_wr; | |
1356 | output intman_tbl_rden; | |
1357 | output [15:0] intman_tbl_din; | |
1358 | input [15:0] intman_tbl_dout; | |
1359 | ||
1360 | // mb1 signals | |
1361 | input [6:0] mb1_raddr; | |
1362 | input [6:0] mb1_waddr; | |
1363 | input [7:0] mb1_wdata; | |
1364 | input mb1_intman_wr_en; | |
1365 | input mb1_intman_rd_en; | |
1366 | input mb1_run; | |
1367 | ||
1368 | // ras, err, ecc // | |
1369 | output ncu_rst_fatal_error; | |
1370 | output ncu_tcu_soc_error; | |
1371 | output raserrce; | |
1372 | output raserrue; | |
1373 | ||
1374 | input niu_ncu_d_pe; | |
1375 | output ncu_niu_d_pei; | |
1376 | input niu_ncu_ctag_ue; | |
1377 | output ncu_niu_ctag_uei; | |
1378 | input niu_ncu_ctag_ce; | |
1379 | output ncu_niu_ctag_cei; | |
1380 | input sio_ncu_ctag_ce; | |
1381 | output ncu_sio_ctag_cei; | |
1382 | input sio_ncu_ctag_ue; | |
1383 | output ncu_sio_ctag_uei; | |
1384 | //input sio_ncu_d_pe; | |
1385 | output ncu_sio_d_pei; | |
1386 | ||
1387 | input dmu_cr_id_rtn_err; | |
1388 | output dmu_cr_id_rtn_erri; | |
1389 | input dmu_ncu_d_pe; | |
1390 | output ncu_dmu_d_pei; | |
1391 | input dmu_ncu_siicr_pe; | |
1392 | output ncu_dmu_siicr_pei; | |
1393 | input dmu_ncu_ctag_ue; | |
1394 | output ncu_dmu_ctag_uei; | |
1395 | input dmu_ncu_ctag_ce; | |
1396 | output ncu_dmu_ctag_cei; | |
1397 | input dmu_ncu_ncucr_pe; | |
1398 | output ncu_dmu_ncucr_pei; | |
1399 | input dmu_ncu_ie; | |
1400 | output ncu_dmu_iei; | |
1401 | ||
1402 | input sii_ncu_dmua_pe; | |
1403 | output ncu_sii_dmua_pei; | |
1404 | input sii_ncu_niud_pe; | |
1405 | output ncu_sii_niud_pei; | |
1406 | input sii_ncu_dmud_pe; | |
1407 | output ncu_sii_dmud_pei; | |
1408 | input sii_ncu_niua_pe; | |
1409 | output ncu_sii_niua_pei; | |
1410 | input sii_ncu_dmuctag_ce; | |
1411 | output ncu_sii_dmuctag_cei; | |
1412 | input sii_ncu_niuctag_ce; | |
1413 | output ncu_sii_niuctag_cei; | |
1414 | input sii_ncu_dmuctag_ue; | |
1415 | output ncu_sii_dmuctag_uei; | |
1416 | input sii_ncu_niuctag_ue; | |
1417 | output ncu_sii_niuctag_uei; | |
1418 | ||
1419 | input mcu0_ncu_ecc; | |
1420 | output ncu_mcu0_ecci; | |
1421 | input mcu0_ncu_fbr; | |
1422 | output ncu_mcu0_fbri; | |
1423 | input mcu0_ncu_fbu; | |
1424 | output ncu_mcu0_fbui; | |
1425 | ||
1426 | input mcu1_ncu_ecc; | |
1427 | output ncu_mcu1_ecci; | |
1428 | input mcu1_ncu_fbr; | |
1429 | output ncu_mcu1_fbri; | |
1430 | input mcu1_ncu_fbu; | |
1431 | output ncu_mcu1_fbui; | |
1432 | ||
1433 | input mcu2_ncu_ecc; | |
1434 | output ncu_mcu2_ecci; | |
1435 | input mcu2_ncu_fbr; | |
1436 | output ncu_mcu2_fbri; | |
1437 | input mcu2_ncu_fbu; | |
1438 | output ncu_mcu2_fbui; | |
1439 | ||
1440 | input mcu3_ncu_ecc; | |
1441 | output ncu_mcu3_ecci; | |
1442 | input mcu3_ncu_fbr; | |
1443 | output ncu_mcu3_fbri; | |
1444 | input mcu3_ncu_fbu; | |
1445 | output ncu_mcu3_fbui; | |
1446 | ||
1447 | input ncuctag_ce; | |
1448 | output ncuctag_cei; | |
1449 | input ncuctag_ue; | |
1450 | output ncuctag_uei; | |
1451 | output ncusiid_pei; | |
1452 | input ncusiid_pe; | |
1453 | input dmubuf_pue; | |
1454 | output dmubuf_pei; | |
1455 | input iobuf_ue_f; | |
1456 | output iobuf_uei; | |
1457 | input cpubuf_ue; | |
1458 | output cpubuf_uei; | |
1459 | input cpubuf_pe; | |
1460 | output cpubuf_pei; | |
1461 | input intbuf_ue_f; | |
1462 | output intbuf_uei; | |
1463 | input mondotbl_pe_f; | |
1464 | output mondotbl_pei; | |
1465 | ||
1466 | input [63:0] siierrsyn; | |
1467 | input siierrsyn_done; | |
1468 | ||
1469 | input [46:0] dmubufsyn; | |
1470 | input [50:0] cpubufsyn; | |
1471 | input [15:0] ncudpsyn; | |
1472 | ||
1473 | input wmr_protect; | |
1474 | input aclk_wmr; | |
1475 | //assign wmr_protect=1'b0; | |
1476 | ||
1477 | ///////////////////////////////////////////////////////////////////////// | |
1478 | assign intman_tbl_din[15:0] = mb1_run ? {2{mb1_wdata[7:0]}} : | |
1479 | {intman_par_din[3:0],intman_ct_din[5:0],intman_vec_din[5:0]} ; | |
1480 | assign intman_par_din[0] = ~^{intman_vec_din[0],intman_vec_din[4],intman_ct_din[2]}; | |
1481 | assign intman_par_din[1] = ~^{intman_vec_din[1],intman_vec_din[5],intman_ct_din[3]}; | |
1482 | assign intman_par_din[2] = ~^{intman_vec_din[2],intman_ct_din[0],intman_ct_din[4]}; | |
1483 | assign intman_par_din[3] = ~^{intman_vec_din[3],intman_ct_din[1],intman_ct_din[5]}; | |
1484 | ||
1485 | assign {intman_par_dout[3:0], | |
1486 | intman_ct_dout[5:0], | |
1487 | intman_vec_dout[5:0]} = intman_tbl_dout[15:0] ; | |
1488 | ||
1489 | //reg [3:0] intvecdisp_int_type; | |
1490 | reg [7:0] coreavail_lowest_1hot ; | |
1491 | reg [7:0] xir_srvcd_mini_vec; | |
1492 | reg [2:0] xir_mini_thr; | |
1493 | reg xir_mini_vec_vld; | |
1494 | reg [7:0] enable_status_lowest_1hot; | |
1495 | ||
1496 | ||
1497 | ||
1498 | /***************************************************************** | |
1499 | * ncu_man_ucb | |
1500 | *****************************************************************/ | |
1501 | // Flop c2i_packet | |
1502 | assign ncu_man_ucb_buf_acpt = | |
1503 | c2i_packet_vld & ncu_man_ucb_sel & | |
1504 | ~ncu_man_ucb_buf_acpt_d1 & | |
1505 | ~ncu_man_ucb_buf_acpt_d2 & | |
1506 | ~(ncu_man_ucb_buf_acpt_d3 & ncu_man_ucb_c2i_packet_is_rd_req) & //something man ack in process | |
1507 | ~(ncu_man_ack_buf_full & c2i_packet_is_rd_req ) & | |
1508 | ~((ncu_man_int_buf_full|xir_busy|rasper_ipg) & c2i_packet_is_wr_req ) ; | |
1509 | //~ncu_man_int_buf_full & //~ncu_man_ack_buf_full; | |
1510 | ||
1511 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_man_ucb_buf_acpt_d1_ff | |
1512 | ( | |
1513 | .scan_in(ncu_man_ucb_buf_acpt_d1_ff_scanin), | |
1514 | .scan_out(ncu_man_ucb_buf_acpt_d1_ff_scanout), | |
1515 | .dout (ncu_man_ucb_buf_acpt_d1), | |
1516 | .l1clk (l1clk), | |
1517 | .din (ncu_man_ucb_buf_acpt), | |
1518 | .siclk(siclk), | |
1519 | .soclk(soclk) | |
1520 | ); | |
1521 | ||
1522 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_man_ucb_buf_acpt_d2_ff | |
1523 | ( | |
1524 | .scan_in(ncu_man_ucb_buf_acpt_d2_ff_scanin), | |
1525 | .scan_out(ncu_man_ucb_buf_acpt_d2_ff_scanout), | |
1526 | .dout (ncu_man_ucb_buf_acpt_d2), | |
1527 | .l1clk (l1clk), | |
1528 | .din (ncu_man_ucb_buf_acpt_d1), | |
1529 | .siclk(siclk), | |
1530 | .soclk(soclk) | |
1531 | ); | |
1532 | ||
1533 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_man_ucb_buf_acpt_d3_ff | |
1534 | ( | |
1535 | .scan_in(ncu_man_ucb_buf_acpt_d3_ff_scanin), | |
1536 | .scan_out(ncu_man_ucb_buf_acpt_d3_ff_scanout), | |
1537 | .dout (ncu_man_ucb_buf_acpt_d3), | |
1538 | .l1clk (l1clk), | |
1539 | .din (ncu_man_ucb_buf_acpt_d2), | |
1540 | .siclk(siclk), | |
1541 | .soclk(soclk) | |
1542 | ); | |
1543 | ||
1544 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 ncu_man_ucb_c2i_packet_data_ff | |
1545 | ( | |
1546 | .scan_in(ncu_man_ucb_c2i_packet_data_ff_scanin), | |
1547 | .scan_out(ncu_man_ucb_c2i_packet_data_ff_scanout), | |
1548 | .dout (ncu_man_ucb_c2i_packet_data[63:0]), | |
1549 | .l1clk (l1clk), | |
1550 | .en (ncu_man_ucb_buf_acpt), | |
1551 | .din (c2i_packet[127:64]), | |
1552 | .siclk(siclk), | |
1553 | .soclk(soclk) | |
1554 | ); | |
1555 | ||
1556 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_40 ncu_man_ucb_c2i_packet_addr_ff | |
1557 | ( | |
1558 | .scan_in(ncu_man_ucb_c2i_packet_addr_ff_scanin), | |
1559 | .scan_out(ncu_man_ucb_c2i_packet_addr_ff_scanout), | |
1560 | .dout (ncu_man_ucb_c2i_packet_addr[39:0]), | |
1561 | .l1clk (l1clk), | |
1562 | .en (ncu_man_ucb_buf_acpt), | |
1563 | .din (c2i_packet[54:15]), | |
1564 | .siclk(siclk), | |
1565 | .soclk(soclk) | |
1566 | ); | |
1567 | ||
1568 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_2 ncu_man_ucb_c2i_packet_buf_id_ff | |
1569 | ( | |
1570 | .scan_in(ncu_man_ucb_c2i_packet_buf_id_ff_scanin), | |
1571 | .scan_out(ncu_man_ucb_c2i_packet_buf_id_ff_scanout), | |
1572 | .dout (ncu_man_ucb_c2i_packet_buf_id[1:0]), | |
1573 | .l1clk (l1clk), | |
1574 | .en (ncu_man_ucb_buf_acpt), | |
1575 | .din (c2i_packet[11:10]), | |
1576 | .siclk(siclk), | |
1577 | .soclk(soclk) | |
1578 | ); | |
1579 | ||
1580 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_6 ncu_man_ucb_c2i_packet_cputhr_ff | |
1581 | ( | |
1582 | .scan_in(ncu_man_ucb_c2i_packet_cputhr_ff_scanin), | |
1583 | .scan_out(ncu_man_ucb_c2i_packet_cputhr_ff_scanout), | |
1584 | .dout (ncu_man_ucb_c2i_packet_cputhr[5:0]), | |
1585 | .l1clk (l1clk), | |
1586 | .en (ncu_man_ucb_buf_acpt), | |
1587 | .din (c2i_packet[9:4]), | |
1588 | .siclk(siclk), | |
1589 | .soclk(soclk) | |
1590 | ); | |
1591 | ||
1592 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ncu_man_ucb_c2i_packet_is_rd_req_ff | |
1593 | ( | |
1594 | .scan_in(ncu_man_ucb_c2i_packet_is_rd_req_ff_scanin), | |
1595 | .scan_out(ncu_man_ucb_c2i_packet_is_rd_req_ff_scanout), | |
1596 | .dout (ncu_man_ucb_c2i_packet_is_rd_req), | |
1597 | .l1clk (l1clk), | |
1598 | .en (ncu_man_ucb_buf_acpt), | |
1599 | .din (c2i_packet_is_rd_req), | |
1600 | .siclk(siclk), | |
1601 | .soclk(soclk) | |
1602 | ); | |
1603 | ||
1604 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ncu_man_ucb_c2i_packet_is_wr_req_ff | |
1605 | ( | |
1606 | .scan_in(ncu_man_ucb_c2i_packet_is_wr_req_ff_scanin), | |
1607 | .scan_out(ncu_man_ucb_c2i_packet_is_wr_req_ff_scanout), | |
1608 | .dout (ncu_man_ucb_c2i_packet_is_wr_req), | |
1609 | .l1clk (l1clk), | |
1610 | .en (ncu_man_ucb_buf_acpt), | |
1611 | .din (c2i_packet_is_wr_req), | |
1612 | .siclk(siclk), | |
1613 | .soclk(soclk) | |
1614 | ); | |
1615 | ||
1616 | /***************************************************************** | |
1617 | * Decoding here for requests directed to IOB registers | |
1618 | *****************************************************************/ | |
1619 | //assign ncu_asi_acc = ncu_man_ucb_c2i_packet_addr[36] ; | |
1620 | //jimmy : addr[31:16] has already been checked for csr_man space if [36] is 0// | |
1621 | //jimmy : addr[31:32] needs to be further seperate if asi (i.e.[39:32]==h90) // | |
1622 | assign ncu_man_acc = ~ncu_man_ucb_c2i_packet_addr[36] ; | |
1623 | ||
1624 | assign ncu_asi_a_acc = ncu_man_ucb_c2i_packet_addr[36] & | |
1625 | (ncu_man_ucb_c2i_packet_addr[25:16]==`NCU_ASI_A_HIT); | |
1626 | ||
1627 | assign ncu_asi_b_acc = ncu_man_ucb_c2i_packet_addr[36] & | |
1628 | (ncu_man_ucb_c2i_packet_addr[25:16]==`NCU_ASI_B_HIT); | |
1629 | ||
1630 | assign ncu_asi_c_acc = ncu_man_ucb_c2i_packet_addr[36] & | |
1631 | (ncu_man_ucb_c2i_packet_addr[25:16]==`NCU_ASI_C_HIT); | |
1632 | ||
1633 | assign creg_intman_dec = ncu_man_acc & | |
1634 | ((ncu_man_ucb_c2i_packet_addr[15:0]&16'hfc07)==`NCU_CREG_INTMAN); | |
1635 | assign creg_sernum_dec = ncu_man_acc & | |
1636 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_SERNUM); | |
1637 | assign creg_coreavail_dec = ncu_man_acc & | |
1638 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_COREAVAIL); | |
1639 | assign creg_fusestat_dec = ncu_man_acc & | |
1640 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_FUSESTAT); | |
1641 | assign creg_bankavail_dec = ncu_man_acc & | |
1642 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_BANKAVAIL); | |
1643 | assign creg_bank_en_dec = ncu_man_acc & | |
1644 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_BANK_ENABLE); | |
1645 | assign creg_bank_en_status_dec = ncu_man_acc & | |
1646 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_BANK_ENABLE_STATUS); | |
1647 | assign creg_l2idxhs_en_dec = ncu_man_acc & | |
1648 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_L2_HASH_ENABLE); | |
1649 | assign creg_l2idxhs_en_status_dec = ncu_man_acc & | |
1650 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_L2_HASH_ENABLE_STATUS); | |
1651 | assign creg_mondoinvec_dec = ncu_man_acc & | |
1652 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MONDOINVEC); | |
1653 | assign creg_mem32_base_dec = ncu_man_acc & | |
1654 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MEM32_BASE); | |
1655 | assign creg_mem32_mask_dec = ncu_man_acc & | |
1656 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MEM32_MASK); | |
1657 | assign creg_mem64_base_dec = ncu_man_acc & | |
1658 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MEM64_BASE); | |
1659 | assign creg_mem64_mask_dec = ncu_man_acc & | |
1660 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MEM64_MASK); | |
1661 | assign creg_iocon_base_dec = ncu_man_acc & | |
1662 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_IOCON_BASE); | |
1663 | assign creg_iocon_mask_dec = ncu_man_acc & | |
1664 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_IOCON_MASK); | |
1665 | assign creg_mmufsh_dec = ncu_man_acc & | |
1666 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_MMUFSH); | |
1667 | assign creg_esr_dec = ncu_man_acc & | |
1668 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_ESR); | |
1669 | assign creg_ele_dec = ncu_man_acc & | |
1670 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_ELE); | |
1671 | assign creg_eie_dec = ncu_man_acc & | |
1672 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_EIE); | |
1673 | assign creg_ejr_dec = ncu_man_acc & | |
1674 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_EJR); | |
1675 | assign creg_fee_dec = ncu_man_acc & | |
1676 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_FEE); | |
1677 | assign creg_per_dec = ncu_man_acc & | |
1678 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_PER); | |
1679 | assign creg_siisyn_dec = ncu_man_acc & | |
1680 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_SIISYN); | |
1681 | assign creg_ncusyn_dec = ncu_man_acc & | |
1682 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_NCUSYN); | |
1683 | assign creg_ncu_scksel_dec = ncu_man_acc & | |
1684 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_SCKSEL); | |
1685 | assign creg_dbgtrigen_dec = ncu_man_acc & | |
1686 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_CREG_DBGTRIG_EN); | |
1687 | ||
1688 | assign asi_coreavail_dec = ncu_asi_a_acc & | |
1689 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_COREAVAIL); | |
1690 | assign asi_core_enable_status_dec = ncu_asi_a_acc & | |
1691 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_ENABLE_STATUS); | |
1692 | assign asi_core_enable_dec = ncu_asi_a_acc & | |
1693 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_ENABLE); | |
1694 | assign asi_xir_steering_dec = ncu_asi_a_acc & | |
1695 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_XIR_STEERING); | |
1696 | assign asi_core_running_dec = ncu_asi_a_acc & | |
1697 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_RUNNINGRW); | |
1698 | assign asi_core_running_status_dec = ncu_asi_a_acc & | |
1699 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_RUNNING_STATUS); | |
1700 | assign asi_core_runningw1s_dec = ncu_asi_a_acc & | |
1701 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_RUNNING_W1S); | |
1702 | assign asi_core_runningw1c_dec = ncu_asi_a_acc & | |
1703 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CORE_RUNNING_W1C); | |
1704 | assign asi_ras_err_steering_dec = ncu_asi_a_acc & | |
1705 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_ERR_STR); | |
1706 | // new ASI for ras error sterring register, Jane | |
1707 | assign asi_wmr_vec_mask_dec = ncu_asi_c_acc & | |
1708 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_WMR_VEC_MASK); | |
1709 | assign asi_cmp_tick_enable_dec = ncu_asi_a_acc & | |
1710 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_CMP_TICK_ENABLE); | |
1711 | assign asi_intvecdisp_dec = ncu_asi_b_acc & | |
1712 | (ncu_man_ucb_c2i_packet_addr[15:0]==`NCU_ASI_INTVECDISP); | |
1713 | ||
1714 | ||
1715 | // Send nack if address doesn't match any register | |
1716 | assign creg_nomatch = ~ ( creg_intman_dec | | |
1717 | creg_sernum_dec | | |
1718 | creg_coreavail_dec | | |
1719 | creg_bankavail_dec | | |
1720 | creg_bank_en_dec | | |
1721 | creg_bank_en_status_dec | | |
1722 | creg_l2idxhs_en_dec | | |
1723 | creg_l2idxhs_en_status_dec | | |
1724 | creg_fusestat_dec | | |
1725 | creg_mondoinvec_dec | | |
1726 | creg_mem32_base_dec | | |
1727 | creg_mem32_mask_dec | | |
1728 | creg_mem64_base_dec | | |
1729 | creg_mem64_mask_dec | | |
1730 | creg_iocon_base_dec | | |
1731 | creg_iocon_mask_dec | | |
1732 | creg_mmufsh_dec | | |
1733 | creg_esr_dec | | |
1734 | creg_ele_dec | | |
1735 | creg_eie_dec | | |
1736 | creg_ejr_dec | | |
1737 | creg_fee_dec | | |
1738 | creg_per_dec | | |
1739 | creg_siisyn_dec | | |
1740 | creg_ncusyn_dec | | |
1741 | creg_ncu_scksel_dec | | |
1742 | creg_dbgtrigen_dec | | |
1743 | asi_coreavail_dec | | |
1744 | asi_core_enable_status_dec | | |
1745 | asi_core_enable_dec | | |
1746 | asi_xir_steering_dec | | |
1747 | asi_core_running_dec | | |
1748 | asi_core_running_status_dec | | |
1749 | asi_core_runningw1s_dec | | |
1750 | asi_core_runningw1c_dec | | |
1751 | asi_ras_err_steering_dec | // Jane | |
1752 | asi_wmr_vec_mask_dec | | |
1753 | asi_cmp_tick_enable_dec | | |
1754 | asi_intvecdisp_dec ) ; | |
1755 | ||
1756 | ||
1757 | // Double buffer for ncu_man_int | |
1758 | assign ncu_man_int_buf_wr = intvecdisp_int_wr | rasper_int_wr | xir_int_wr ; | |
1759 | ||
1760 | assign ncu_man_int_buf_din[24:0] = xir_int_wr ? xir_int_pkt[24:0] : | |
1761 | rasper_int_wr ? rasper_int_pkt[24:0] : intvecdisp_int_pkt[24:0] ; | |
1762 | //============================================= | |
1763 | //dbl_buf #(64) ncu_man_int_buf ( | |
1764 | // .clk(iol2clk), | |
1765 | // .wr(ncu_man_int_buf_wr), | |
1766 | // .din(ncu_man_int_buf_din[63:0]), | |
1767 | // .vld(ncu_man_int_buf_vld), | |
1768 | // .dout(ncu_man_int_buf_dout[63:0]), | |
1769 | // .rd(ncu_man_int_buf_rd), | |
1770 | // .full(ncu_man_int_buf_full)); | |
1771 | //============================================================================= | |
1772 | //============================================================================= | |
1773 | //========================================================== dbl_buf ========== | |
1774 | // Buffer Output | |
1775 | ||
1776 | // if both entries are empty, write to entry pointed to by the older pointer | |
1777 | assign aa_wr_buf0 = ncu_man_int_buf_wr & (aa_buf1_vld | (~aa_buf0_vld & ~aa_buf1_older)); | |
1778 | assign aa_wr_buf1 = ncu_man_int_buf_wr & (aa_buf0_vld | (~aa_buf1_vld & aa_buf1_older)); | |
1779 | ||
1780 | // read from the older entry | |
1781 | assign aa_rd_buf0 = ncu_man_int_buf_rd & ~aa_buf1_older; | |
1782 | assign aa_rd_buf1 = ncu_man_int_buf_rd & aa_buf1_older; | |
1783 | ||
1784 | // flip older pointer when an entry is read | |
1785 | assign aa_rd_buf = ncu_man_int_buf_rd & (aa_buf0_vld | aa_buf1_vld); | |
1786 | assign aa_buf1_older_inv = ~aa_buf1_older; | |
1787 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 aa_buf1_older_ff | |
1788 | ( | |
1789 | .scan_in(aa_buf1_older_ff_scanin), | |
1790 | .scan_out(aa_buf1_older_ff_scanout), | |
1791 | .dout (aa_buf1_older), | |
1792 | .l1clk (l1clk), | |
1793 | .en (aa_rd_buf), | |
1794 | .din (aa_buf1_older_inv), | |
1795 | .siclk(siclk), | |
1796 | .soclk(soclk) | |
1797 | ); | |
1798 | ||
1799 | // set valid bit for writes and reset for reads | |
1800 | assign aa_en_vld0 = aa_wr_buf0 | aa_rd_buf0; | |
1801 | assign aa_en_vld1 = aa_wr_buf1 | aa_rd_buf1; | |
1802 | ||
1803 | // the actual buffers | |
1804 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 aa_buf0_vld_ff | |
1805 | ( | |
1806 | .scan_in(aa_buf0_vld_ff_scanin), | |
1807 | .scan_out(aa_buf0_vld_ff_scanout), | |
1808 | .dout (aa_buf0_vld), | |
1809 | .l1clk (l1clk), | |
1810 | .en (aa_en_vld0), | |
1811 | .din (aa_wr_buf0), | |
1812 | .siclk(siclk), | |
1813 | .soclk(soclk) | |
1814 | ); | |
1815 | ||
1816 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 aa_buf1_vld_ff | |
1817 | ( | |
1818 | .scan_in(aa_buf1_vld_ff_scanin), | |
1819 | .scan_out(aa_buf1_vld_ff_scanout), | |
1820 | .dout (aa_buf1_vld), | |
1821 | .l1clk (l1clk), | |
1822 | .en (aa_en_vld1), | |
1823 | .din (aa_wr_buf1), | |
1824 | .siclk(siclk), | |
1825 | .soclk(soclk) | |
1826 | ); | |
1827 | ||
1828 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_25 aa_buf0_obj_ff | |
1829 | ( | |
1830 | .scan_in(aa_buf0_obj_ff_scanin), | |
1831 | .scan_out(aa_buf0_obj_ff_scanout), | |
1832 | .dout (aa_buf0_obj[24:0]), | |
1833 | .l1clk (l1clk), | |
1834 | .en (aa_wr_buf0), | |
1835 | .din (ncu_man_int_buf_din[24:0]), | |
1836 | .siclk(siclk), | |
1837 | .soclk(soclk) | |
1838 | ); | |
1839 | ||
1840 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_25 aa_buf1_obj_ff | |
1841 | ( | |
1842 | .scan_in(aa_buf1_obj_ff_scanin), | |
1843 | .scan_out(aa_buf1_obj_ff_scanout), | |
1844 | .dout (aa_buf1_obj[24:0]), | |
1845 | .l1clk (l1clk), | |
1846 | .en (aa_wr_buf1), | |
1847 | .din (ncu_man_int_buf_din[24:0]), | |
1848 | .siclk(siclk), | |
1849 | .soclk(soclk) | |
1850 | ); | |
1851 | ||
1852 | // mux out the older entry | |
1853 | assign ncu_man_int_buf_dout[24:0] = (aa_buf1_older) ? aa_buf1_obj[24:0] : aa_buf0_obj[24:0] ; | |
1854 | ||
1855 | assign ncu_man_int_buf_vld = aa_buf0_vld | aa_buf1_vld; | |
1856 | assign ncu_man_int_buf_full = aa_buf0_vld & aa_buf1_vld; | |
1857 | //============================================= | |
1858 | assign ncu_man_int_vld = ncu_man_int_buf_vld; | |
1859 | ||
1860 | assign ncu_man_int_packet[24:0] = ncu_man_int_buf_dout[24:0]; | |
1861 | ||
1862 | assign ncu_man_int_buf_rd = ncu_man_int_rd; | |
1863 | //========================================================== dbl_buf ========== | |
1864 | //============================================================================= | |
1865 | //============================================================================= | |
1866 | ||
1867 | ||
1868 | ||
1869 | // Double buffer for ncu_man_ack | |
1870 | //assign ncu_man_ack_buf_wr = ncu_man_ucb_buf_acpt_d3 & ncu_man_acc & ncu_man_ucb_c2i_packet_is_rd_req; | |
1871 | assign ncu_man_ack_buf_wr = ncu_man_ucb_buf_acpt_d3 & ncu_man_ucb_c2i_packet_is_rd_req; | |
1872 | ||
1873 | assign ncu_man_ack_i2c_packet_data[63:0] = | |
1874 | ({64{creg_intman_dec}} & creg_intman[63:0]) | | |
1875 | ({64{creg_sernum_dec}} & creg_sernum[63:0]) | | |
1876 | ({64{creg_coreavail_dec|asi_coreavail_dec}} & creg_coreavail[63:0]) | | |
1877 | ({64{creg_fusestat_dec}} & creg_fusestat[63:0]) | | |
1878 | ({64{creg_bankavail_dec}} & creg_bankavail[63:0]) | | |
1879 | ({64{creg_bank_en_dec}} & creg_bank_en[63:0]) | | |
1880 | ({64{creg_bank_en_status_dec}} & creg_bank_en_status[63:0]) | | |
1881 | ({64{creg_l2idxhs_en_dec}} & creg_l2idxhs_en[63:0]) | | |
1882 | ({64{creg_l2idxhs_en_status_dec}} & creg_l2idxhs_en_status[63:0]) | | |
1883 | ({64{creg_mondoinvec_dec}} & creg_mondoinvec[63:0]) | | |
1884 | ({64{creg_mem32_base_dec}} & creg_mem32_base[63:0]) | | |
1885 | ({64{creg_mem32_mask_dec}} & creg_mem32_mask[63:0]) | | |
1886 | ({64{creg_mem64_base_dec}} & creg_mem64_base[63:0]) | | |
1887 | ({64{creg_mem64_mask_dec}} & creg_mem64_mask[63:0]) | | |
1888 | ({64{creg_iocon_base_dec}} & creg_iocon_base[63:0]) | | |
1889 | ({64{creg_iocon_mask_dec}} & creg_iocon_mask[63:0]) | | |
1890 | ({64{creg_mmufsh_dec}} & mmufsh_data[63:0]) | | |
1891 | ({64{creg_esr_dec}} & creg_esr[63:0]) | | |
1892 | ({64{creg_ele_dec}} & creg_ele[63:0]) | | |
1893 | ({64{creg_eie_dec}} & creg_eie[63:0]) | | |
1894 | ({64{creg_ejr_dec}} & creg_ejr[63:0]) | | |
1895 | ({64{creg_fee_dec}} & creg_fee[63:0]) | | |
1896 | ({64{creg_per_dec}} & creg_per[63:0]) | | |
1897 | ({64{creg_siisyn_dec}} & creg_siisyn[63:0]) | | |
1898 | ({64{creg_ncusyn_dec}} & creg_ncusyn[63:0]) | | |
1899 | ({64{creg_ncu_scksel_dec}} & creg_ncu_scksel[63:0]) | | |
1900 | ({64{creg_dbgtrigen_dec}} & creg_dbgtrigen[63:0]) | | |
1901 | ({64{asi_core_enable_status_dec}} & creg_core_enable_status[63:0]) | | |
1902 | ({64{asi_core_enable_dec}} & creg_core_enable[63:0]) | | |
1903 | ({64{asi_xir_steering_dec}} & xir_steering[63:0]) | | |
1904 | ({64{asi_ras_err_steering_dec}} & creg_err_steering[63:0]) | | |
1905 | ({64{asi_wmr_vec_mask_dec}} & creg_wmr_vec_mask[63:0]) | | |
1906 | ({64{asi_cmp_tick_enable_dec}} & creg_cmp_tick_enable[63:0]) | | |
1907 | ({64{asi_core_running_dec}} & core_running[63:0]) | | |
1908 | ({64{asi_core_running_status_dec}} & creg_core_running_status[63:0]) ; | |
1909 | ||
1910 | assign ncu_man_ack_i2c_packet_type[3:0] = (creg_nomatch|intman_pe_n) ? `UCB_READ_NACK : `UCB_READ_ACK ; | |
1911 | // intman_pe_n was added to fix bug 92709. when interrupt table error | |
1912 | // happens, NCU nack back to cpu. | |
1913 | ||
1914 | //assign ncu_man_ack_i2c_packet_type[3:0] = (creg_nomatch) ? `UCB_READ_NACK : `UCB_READ_ACK ; | |
1915 | ||
1916 | assign ncu_man_ack_i2c_packet[127:0] = {ncu_man_ack_i2c_packet_data[63:0], | |
1917 | 9'b0, //// UCB_RSV_WIDTH, | |
1918 | ncu_man_ucb_c2i_packet_addr[39:0], //// UCB_ADDR | |
1919 | 3'b0, //// UCB_SIZE (dummy) | |
1920 | ncu_man_ucb_c2i_packet_buf_id[1:0], //// UCB_BUF_ID | |
1921 | ncu_man_ucb_c2i_packet_cputhr[5:0], //// UCB_CPUTHR | |
1922 | ncu_man_ack_i2c_packet_type[3:0] }; | |
1923 | ||
1924 | assign ncu_man_ack_buf_din[127:0] = ncu_man_ack_i2c_packet[127:0]; | |
1925 | //========================================================== | |
1926 | //dbl_buf #(128) ncu_man_ack_buf ( | |
1927 | // .clk(iol2clk), | |
1928 | // .wr(ncu_man_ack_buf_wr), | |
1929 | // .rd(ncu_man_ack_buf_rd), | |
1930 | // .din(ncu_man_ack_buf_din[127:0]), | |
1931 | // .vld(ncu_man_ack_buf_vld), | |
1932 | // .dout(ncu_man_ack_buf_dout[127:0]), | |
1933 | // .full(ncu_man_ack_buf_full)); */ | |
1934 | //============================================================================= | |
1935 | //============================================================================= | |
1936 | //========================================================== dbl_buf ========== | |
1937 | // Buffer Output | |
1938 | ||
1939 | // if both entries are empty, write to entry pointed to by the older pointer | |
1940 | assign bb_wr_buf0 = ncu_man_ack_buf_wr & (bb_buf1_vld | (~bb_buf0_vld & ~bb_buf1_older)); | |
1941 | assign bb_wr_buf1 = ncu_man_ack_buf_wr & (bb_buf0_vld | (~bb_buf1_vld & bb_buf1_older)); | |
1942 | ||
1943 | // read from the older entry | |
1944 | assign bb_rd_buf0 = ncu_man_ack_buf_rd & ~bb_buf1_older; | |
1945 | assign bb_rd_buf1 = ncu_man_ack_buf_rd & bb_buf1_older; | |
1946 | ||
1947 | // flip older pointer when an entry is read | |
1948 | assign bb_rd_buf = ncu_man_ack_buf_rd & (bb_buf0_vld | bb_buf1_vld); | |
1949 | assign bb_buf1_older_inv = ~bb_buf1_older; | |
1950 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 bb_buf1_older_ff | |
1951 | ( | |
1952 | .scan_in(bb_buf1_older_ff_scanin), | |
1953 | .scan_out(bb_buf1_older_ff_scanout), | |
1954 | .dout (bb_buf1_older), | |
1955 | .l1clk (l1clk), | |
1956 | .en (bb_rd_buf), | |
1957 | .din (bb_buf1_older_inv), | |
1958 | .siclk(siclk), | |
1959 | .soclk(soclk) | |
1960 | ); | |
1961 | ||
1962 | // set valid bit for writes and reset for reads | |
1963 | assign bb_en_vld0 = bb_wr_buf0 | bb_rd_buf0; | |
1964 | assign bb_en_vld1 = bb_wr_buf1 | bb_rd_buf1; | |
1965 | ||
1966 | // the actual buffers | |
1967 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 bb_buf0_vld_ff | |
1968 | ( | |
1969 | .scan_in(bb_buf0_vld_ff_scanin), | |
1970 | .scan_out(bb_buf0_vld_ff_scanout), | |
1971 | .dout (bb_buf0_vld), | |
1972 | .l1clk (l1clk), | |
1973 | .en (bb_en_vld0), | |
1974 | .din (bb_wr_buf0), | |
1975 | .siclk(siclk), | |
1976 | .soclk(soclk) | |
1977 | ); | |
1978 | ||
1979 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 bb_buf1_vld_ff | |
1980 | ( | |
1981 | .scan_in(bb_buf1_vld_ff_scanin), | |
1982 | .scan_out(bb_buf1_vld_ff_scanout), | |
1983 | .dout (bb_buf1_vld), | |
1984 | .l1clk (l1clk), | |
1985 | .en (bb_en_vld1), | |
1986 | .din (bb_wr_buf1), | |
1987 | .siclk(siclk), | |
1988 | .soclk(soclk) | |
1989 | ); | |
1990 | ||
1991 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 bb_buf0_obj_ff | |
1992 | ( | |
1993 | .scan_in(bb_buf0_obj_ff_scanin), | |
1994 | .scan_out(bb_buf0_obj_ff_scanout), | |
1995 | .dout (bb_buf0_obj[127:0]), | |
1996 | .l1clk (l1clk), | |
1997 | .en (bb_wr_buf0), | |
1998 | .din (ncu_man_ack_buf_din[127:0]), | |
1999 | .siclk(siclk), | |
2000 | .soclk(soclk) | |
2001 | ); | |
2002 | ||
2003 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 bb_buf1_obj_ff | |
2004 | ( | |
2005 | .scan_in(bb_buf1_obj_ff_scanin), | |
2006 | .scan_out(bb_buf1_obj_ff_scanout), | |
2007 | .dout (bb_buf1_obj[127:0]), | |
2008 | .l1clk (l1clk), | |
2009 | .en (bb_wr_buf1), | |
2010 | .din (ncu_man_ack_buf_din[127:0]), | |
2011 | .siclk(siclk), | |
2012 | .soclk(soclk) | |
2013 | ); | |
2014 | ||
2015 | // mux out the older entry | |
2016 | assign ncu_man_ack_buf_dout[127:0] = (bb_buf1_older) ? bb_buf1_obj[127:0] : bb_buf0_obj[127:0] ; | |
2017 | ||
2018 | assign ncu_man_ack_buf_vld = bb_buf0_vld | bb_buf1_vld; | |
2019 | assign ncu_man_ack_buf_full = bb_buf0_vld & bb_buf1_vld; | |
2020 | ||
2021 | assign ncu_man_ack_vld = ncu_man_ack_buf_vld; | |
2022 | ||
2023 | assign ncu_man_ack_packet = ncu_man_ack_buf_dout; | |
2024 | ||
2025 | assign ncu_man_ack_buf_rd = ncu_man_ack_rd; | |
2026 | //========================================================== dbl_buf ========== | |
2027 | //============================================================================= | |
2028 | //============================================================================= | |
2029 | ||
2030 | ||
2031 | ||
2032 | /***************************************************************** | |
2033 | * IOB Interrupt Management Register | |
2034 | *****************************************************************/ | |
2035 | assign lhs_intman_addr[6:0] = ncu_man_ucb_c2i_packet_addr[9:3]; | |
2036 | ||
2037 | // Setup array access in cycle 1 | |
2038 | assign lhs_intman_acc = ncu_man_ucb_buf_acpt_d1 & creg_intman_dec ; | |
2039 | ||
2040 | ||
2041 | assign intman_vec_din[5:0] = ncu_man_ucb_c2i_packet_data[5:0]; | |
2042 | assign intman_ct_din[5:0] = ncu_man_ucb_c2i_packet_data[13:8]; | |
2043 | assign intman_tbl_addr[6:0] = (lhs_intman_acc) ? lhs_intman_addr[6:0] : io_intman_addr[6:0]; | |
2044 | assign intman_tbl_raddr[6:0] = mb1_run ? mb1_raddr[6:0] : intman_tbl_addr[6:0]; | |
2045 | assign intman_tbl_waddr[6:0] = mb1_run ? mb1_waddr[6:0] : intman_tbl_addr[6:0]; | |
2046 | assign intman_tbl_wr = mb1_run ? mb1_intman_wr_en : (lhs_intman_acc & ncu_man_ucb_c2i_packet_is_wr_req); | |
2047 | assign intman_tbl_rden = mb1_run ? mb1_intman_rd_en : (~intman_tbl_wr); | |
2048 | ||
2049 | // intman tbl par chk // | |
2050 | assign c2i_rd_intman = (ncu_man_ucb_buf_acpt_d3&ncu_man_ucb_c2i_packet_is_rd_req&creg_intman_dec) ; | |
2051 | // | |
2052 | ||
2053 | assign intman_pchk_v = c2i_rd_intman | io_rd_intman_d2 ; // either c2i or io read intman table. | |
2054 | ||
2055 | assign intman_pchkf2i2c = (|intman_pchk[3:0]); // parity check. | |
2056 | assign intman_pe_n = intman_pchkf2i2c & intman_pchk_v ; | |
2057 | // interrupt table error, interrupt table parity check valid and parity | |
2058 | // check result is "error". | |
2059 | ||
2060 | assign intman_pchk[0] = ~^{intman_vec_dout[0],intman_vec_dout[4],intman_ct_dout[2],intman_par_dout[0], | |
2061 | intman_pei}; | |
2062 | assign intman_pchk[1] = ~^{intman_vec_dout[1],intman_vec_dout[5],intman_ct_dout[3],intman_par_dout[1]}; | |
2063 | assign intman_pchk[2] = ~^{intman_vec_dout[2],intman_ct_dout[0], intman_ct_dout[4],intman_par_dout[2]}; | |
2064 | assign intman_pchk[3] = ~^{intman_vec_dout[3],intman_ct_dout[1], intman_ct_dout[5],intman_par_dout[3]}; | |
2065 | ||
2066 | ncu_ctrl_ctl_msff_ctl_macro__width_1 intman_pe_ff | |
2067 | ( | |
2068 | .scan_in(intman_pe_ff_scanin), | |
2069 | .scan_out(intman_pe_ff_scanout), | |
2070 | .dout (intman_pe), | |
2071 | .l1clk (l1clk), | |
2072 | .din (intman_pe_n), | |
2073 | .siclk(siclk), | |
2074 | .soclk(soclk) | |
2075 | ); | |
2076 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_55 intmansyn_ff | |
2077 | ( | |
2078 | .scan_in(intmansyn_ff_scanin), | |
2079 | .scan_out(intmansyn_ff_scanout), | |
2080 | .dout (intmansyn[54:0]), | |
2081 | .l1clk (l1clk), | |
2082 | .en (intman_pe_n), | |
2083 | //.din (intman_ct_dout[5:0]) | |
2084 | .din (intmansyn_n[54:0]), | |
2085 | .siclk(siclk), | |
2086 | .soclk(soclk) | |
2087 | ); | |
2088 | ||
2089 | ||
2090 | assign creg_intman[63:0] = { 48'b0, // reserved [63:16] | |
2091 | 2'b00, // hw int [15:14] | |
2092 | intman_ct_dout[5:0],// interrupt cpu ID [13:8] | |
2093 | 2'b00, // reserved [7:6] | |
2094 | intman_vec_dout[5:0] }; // interrupt vector [5:0] | |
2095 | ||
2096 | /***************************************************************** | |
2097 | * IOB Remote Interrupt Vector Dispatch Register | |
2098 | * jimmy: assume man_int_buf never get full, needs to be fix here | |
2099 | *****************************************************************/ | |
2100 | assign asi_intvecdisp_wr = ncu_man_ucb_buf_acpt_d2 & | |
2101 | asi_intvecdisp_dec & ncu_man_ucb_c2i_packet_is_wr_req ; | |
2102 | ||
2103 | assign intvecdisp_int_wr = asi_intvecdisp_wr; | |
2104 | ||
2105 | assign intvecdisp_int_vec[5:0] = ncu_man_ucb_c2i_packet_data[5:0]; | |
2106 | assign intvecdisp_int_thr[5:0] = ncu_man_ucb_c2i_packet_data[13:8]; | |
2107 | ||
2108 | // decoding trap type // | |
2109 | ||
2110 | //always @( ncu_man_ucb_c2i_packet_data) | |
2111 | //case (ncu_man_ucb_c2i_packet_data[17:16]) | |
2112 | //2'b00: intvecdisp_int_type[3:0] = `UCB_INT_VEC; | |
2113 | //2'b01: intvecdisp_int_type[3:0] = `UCB_RESET_VEC; | |
2114 | //2'b10: intvecdisp_int_type[3:0] = `UCB_IDLE_VEC; | |
2115 | //2'b11: intvecdisp_int_type[3:0] = `UCB_RESUME_VEC; | |
2116 | //endcase // case(ncu_man_ucb_c2i_packet_data[17:16]) | |
2117 | ||
2118 | assign intvecdisp_int_pkt[24:0] = { ////7'b0, // reserved | |
2119 | intvecdisp_int_vec[5:0], | |
2120 | ////32'b0, // reserved | |
2121 | 9'h00, // dummy dev_id// | |
2122 | intvecdisp_int_thr[5:0], | |
2123 | //intvecdisp_int_type[3:0] }; | |
2124 | `UCB_INT_VEC }; | |
2125 | ||
2126 | ||
2127 | // No real storage for this one, just read back zeros. | |
2128 | //assign creg_intvecdisp[63:0] = 64'b0; | |
2129 | ||
2130 | /**************************************** | |
2131 | //// efuse interface and reg control //// | |
2132 | *****************************************/ | |
2133 | ||
2134 | ||
2135 | assign coreavail_done = ~coreavail_dshift_d1 & coreavail_dshift_d2 ; // detect deassert of efu_ncu_coreavail_dshift | |
2136 | assign bankavail_done = ~bankavail_dshift_d1 & bankavail_dshift_d2 ; // detect deassert of efu_ncu_bankavail_dshift | |
2137 | assign coreavail_en = coreavail_dshift_d1; | |
2138 | assign bankavail_en = bankavail_dshift_d1; | |
2139 | assign fuse_stat_en = fuse_stat_dshift_d1; | |
2140 | assign sernum0_en = sernum0_dshift_d1; | |
2141 | assign sernum1_en = sernum1_dshift_d1; | |
2142 | assign sernum2_en = sernum2_dshift_d1; | |
2143 | ||
2144 | ||
2145 | ncu_ctrl_ctl_msff_ctl_macro__width_1 fuse_data_d1_ff | |
2146 | ( | |
2147 | .scan_in(fuse_data_d1_ff_scanin), | |
2148 | .scan_out(fuse_data_d1_ff_scanout), | |
2149 | .dout (fuse_data_d1), | |
2150 | .l1clk (l1clk), | |
2151 | .din (efu_ncu_fuse_data), | |
2152 | .siclk(siclk), | |
2153 | .soclk(soclk) | |
2154 | ); | |
2155 | ||
2156 | ncu_ctrl_ctl_msff_ctl_macro__width_1 coreavail_dshift_d1_ff | |
2157 | ( | |
2158 | .scan_in(coreavail_dshift_d1_ff_scanin), | |
2159 | .scan_out(coreavail_dshift_d1_ff_scanout), | |
2160 | .dout (coreavail_dshift_d1), | |
2161 | .l1clk (l1clk), | |
2162 | .din (efu_ncu_coreavail_dshift), | |
2163 | .siclk(siclk), | |
2164 | .soclk(soclk) | |
2165 | ); | |
2166 | ||
2167 | ncu_ctrl_ctl_msff_ctl_macro__width_1 coreavail_dshift_d2_ff | |
2168 | ( | |
2169 | .scan_in(coreavail_dshift_d2_ff_scanin), | |
2170 | .scan_out(coreavail_dshift_d2_ff_scanout), | |
2171 | .dout (coreavail_dshift_d2), | |
2172 | .l1clk (l1clk), | |
2173 | .din (coreavail_dshift_d1), | |
2174 | .siclk(siclk), | |
2175 | .soclk(soclk) | |
2176 | ); | |
2177 | ||
2178 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bankavail_dshift_d1_ff | |
2179 | ( | |
2180 | .scan_in(bankavail_dshift_d1_ff_scanin), | |
2181 | .scan_out(bankavail_dshift_d1_ff_scanout), | |
2182 | .dout (bankavail_dshift_d1), | |
2183 | .l1clk (l1clk), | |
2184 | .din (efu_ncu_bankavail_dshift), | |
2185 | .siclk(siclk), | |
2186 | .soclk(soclk) | |
2187 | ); | |
2188 | ||
2189 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bankavail_dshift_d2_ff | |
2190 | ( | |
2191 | .scan_in(bankavail_dshift_d2_ff_scanin), | |
2192 | .scan_out(bankavail_dshift_d2_ff_scanout), | |
2193 | .dout (bankavail_dshift_d2), | |
2194 | .l1clk (l1clk), | |
2195 | .din (bankavail_dshift_d1), | |
2196 | .siclk(siclk), | |
2197 | .soclk(soclk) | |
2198 | ); | |
2199 | ||
2200 | ncu_ctrl_ctl_msff_ctl_macro__width_1 fuse_stat_dshift_d1_ff | |
2201 | ( | |
2202 | .scan_in(fuse_stat_dshift_d1_ff_scanin), | |
2203 | .scan_out(fuse_stat_dshift_d1_ff_scanout), | |
2204 | .dout (fuse_stat_dshift_d1), | |
2205 | .l1clk (l1clk), | |
2206 | .din (efu_ncu_fusestat_dshift), | |
2207 | .siclk(siclk), | |
2208 | .soclk(soclk) | |
2209 | ); | |
2210 | ||
2211 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sernum0_dshift_d1_ff | |
2212 | ( | |
2213 | .scan_in(sernum0_dshift_d1_ff_scanin), | |
2214 | .scan_out(sernum0_dshift_d1_ff_scanout), | |
2215 | .dout (sernum0_dshift_d1), | |
2216 | .l1clk (l1clk), | |
2217 | .din (efu_ncu_sernum0_dshift), | |
2218 | .siclk(siclk), | |
2219 | .soclk(soclk) | |
2220 | ); | |
2221 | ||
2222 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sernum1_dshift_d1_ff | |
2223 | ( | |
2224 | .scan_in(sernum1_dshift_d1_ff_scanin), | |
2225 | .scan_out(sernum1_dshift_d1_ff_scanout), | |
2226 | .dout (sernum1_dshift_d1), | |
2227 | .l1clk (l1clk), | |
2228 | .din (efu_ncu_sernum1_dshift), | |
2229 | .siclk(siclk), | |
2230 | .soclk(soclk) | |
2231 | ); | |
2232 | ||
2233 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sernum2_dshift_d1_ff | |
2234 | ( | |
2235 | .scan_in(sernum2_dshift_d1_ff_scanin), | |
2236 | .scan_out(sernum2_dshift_d1_ff_scanout), | |
2237 | .dout (sernum2_dshift_d1), | |
2238 | .l1clk (l1clk), | |
2239 | .din (efu_ncu_sernum2_dshift), | |
2240 | .siclk(siclk), | |
2241 | .soclk(soclk) | |
2242 | ); | |
2243 | ||
2244 | ||
2245 | ||
2246 | /***************************************************************** | |
2247 | * IOB Processor Serial Number Register | |
2248 | *****************************************************************/ | |
2249 | ||
2250 | assign sernum0_next[21:0] = {sernum0[20:0],fuse_data_d1} ; | |
2251 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_22 sernum0_ff | |
2252 | ( | |
2253 | .scan_in(sernum0_ff_scanin), | |
2254 | .scan_out(sernum0_ff_scanout), | |
2255 | .dout (sernum0[21:0]), | |
2256 | .l1clk (l1clk), | |
2257 | .siclk (aclk_wmr), | |
2258 | .en (sernum0_en), | |
2259 | .din (sernum0_next[21:0]), | |
2260 | .soclk(soclk) | |
2261 | ); | |
2262 | ||
2263 | assign sernum1_next[21:0] = {sernum1[20:0],fuse_data_d1} ; | |
2264 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_22 sernum1_ff | |
2265 | ( | |
2266 | .scan_in(sernum1_ff_scanin), | |
2267 | .scan_out(sernum1_ff_scanout), | |
2268 | .dout (sernum1[21:0]), | |
2269 | .l1clk (l1clk), | |
2270 | .siclk (aclk_wmr), | |
2271 | .en (sernum1_en), | |
2272 | .din (sernum1_next[21:0]), | |
2273 | .soclk(soclk) | |
2274 | ); | |
2275 | ||
2276 | assign sernum2_next[19:0] = {sernum2[18:0],fuse_data_d1} ; | |
2277 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_20 sernum2_ff | |
2278 | ( | |
2279 | .scan_in(sernum2_ff_scanin), | |
2280 | .scan_out(sernum2_ff_scanout), | |
2281 | .dout (sernum2[19:0]), | |
2282 | .l1clk (l1clk), | |
2283 | .siclk (aclk_wmr), | |
2284 | .en (sernum2_en), | |
2285 | .din (sernum2_next[19:0]), | |
2286 | .soclk(soclk) | |
2287 | ); | |
2288 | ||
2289 | assign creg_sernum[63:0] = {sernum2[19:0],sernum1[21:0],sernum0[21:0]}; | |
2290 | ||
2291 | ||
2292 | ||
2293 | ||
2294 | /***************************************************************** | |
2295 | * IOB Fuse Status Register | |
2296 | *****************************************************************/ | |
2297 | ||
2298 | assign fusestat_next[63:0] = {fusestat[62:0],fuse_data_d1} ; | |
2299 | ||
2300 | assign fusestat_ff_in[63:0] = ~fusestat_next[63:0]; | |
2301 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 fusestat_ff | |
2302 | ( | |
2303 | .scan_in(fusestat_ff_scanin), | |
2304 | .scan_out(fusestat_ff_scanout), | |
2305 | .dout (fusestat_ff_out[63:0]), | |
2306 | .l1clk (l1clk), | |
2307 | .siclk (aclk_wmr), | |
2308 | .en (fuse_stat_en), | |
2309 | .din (fusestat_ff_in[63:0]), | |
2310 | .soclk(soclk) | |
2311 | ); | |
2312 | ||
2313 | assign creg_fusestat[63:0] = ~fusestat_ff_out[63:0] ; | |
2314 | assign fusestat[63:0] = ~fusestat_ff_out[63:0]; | |
2315 | ||
2316 | ||
2317 | ||
2318 | /***************************************************************** | |
2319 | * IOB Core Available Register | |
2320 | *****************************************************************/ | |
2321 | ||
2322 | assign coreavail_next[7:0] = {coreavail[6:0],fuse_data_d1} ; | |
2323 | ||
2324 | assign coreavail_ff_in[7:0] = ~coreavail_next[7:0]; // initial value are all '1' after flash reset | |
2325 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_8 coreavail_ff | |
2326 | ( | |
2327 | .scan_in(coreavail_ff_scanin), | |
2328 | .scan_out(coreavail_ff_scanout), | |
2329 | .dout (coreavail_ff_out[7:0]), | |
2330 | .l1clk (l1clk), | |
2331 | .siclk (aclk_wmr), | |
2332 | .en (coreavail_en), | |
2333 | .din (coreavail_ff_in[7:0]), | |
2334 | .soclk(soclk) | |
2335 | ); | |
2336 | assign coreavail[7:0] = ~coreavail_ff_out[7:0]; | |
2337 | ||
2338 | assign creg_coreavail[63:0] = {{8{coreavail[7]}},{8{coreavail[6]}}, | |
2339 | {8{coreavail[5]}},{8{coreavail[4]}}, | |
2340 | {8{coreavail[3]}},{8{coreavail[2]}}, | |
2341 | {8{coreavail[1]}},{8{coreavail[0]}}}; | |
2342 | ||
2343 | ||
2344 | /* | |
2345 | msff_ctl_macro coreavail_ff (width=8, en=1) | |
2346 | ( | |
2347 | .scan_in(coreavail_ff_scanin), | |
2348 | .scan_out(coreavail_ff_scanout), | |
2349 | .dout (coreavail[7:0]), | |
2350 | .l1clk (l1clk), | |
2351 | .en (coreavail_en), | |
2352 | .din (coreavail_next[7:0]) | |
2353 | ); | |
2354 | */ | |
2355 | ||
2356 | /***************************************************************** | |
2357 | * IOB bank Available Register | |
2358 | *****************************************************************/ | |
2359 | ||
2360 | assign bankavail_next[7:0] = {bankavail[6:0],fuse_data_d1} ; | |
2361 | ||
2362 | assign bankavail_ff_in[7:0] = ~bankavail_next[7:0]; // initial value are all '1' after flash reset | |
2363 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_8 bankavail_ff | |
2364 | ( | |
2365 | .scan_in(bankavail_ff_scanin), | |
2366 | .scan_out(bankavail_ff_scanout), | |
2367 | .dout (bankavail_ff_out[7:0]), | |
2368 | .l1clk (l1clk), | |
2369 | .siclk (aclk_wmr), | |
2370 | .en (bankavail_en), | |
2371 | .din (bankavail_ff_in[7:0]), | |
2372 | .soclk(soclk) | |
2373 | ); | |
2374 | assign bankavail[7:0] = ~bankavail_ff_out[7:0]; | |
2375 | ||
2376 | assign creg_bankavail[63:0] = {56'b0,bankavail[7:0]} ; | |
2377 | assign ncu_tcu_bank_avail[7:0] = bankavail[7:0]; | |
2378 | ||
2379 | ||
2380 | /* | |
2381 | msff_ctl_macro bankavail_ff (width=8, en=1) | |
2382 | ( | |
2383 | .scan_in(bankavail_ff_scanin), | |
2384 | .scan_out(bankavail_ff_scanout), | |
2385 | .dout (bankavail[7:0]), | |
2386 | .l1clk (l1clk), | |
2387 | .en (bankavail_en), | |
2388 | .din (bankavail_next[7:0]) | |
2389 | ); | |
2390 | */ | |
2391 | ||
2392 | ||
2393 | /***************************************************************** | |
2394 | * IOB mondo Interrupt Vector Register | |
2395 | *****************************************************************/ | |
2396 | ||
2397 | assign creg_mondoinvec_wr = ncu_man_ucb_buf_acpt_d2 & | |
2398 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mondoinvec_dec; | |
2399 | ||
2400 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_6 creg_mondoinvec_ff | |
2401 | ( | |
2402 | .scan_in(creg_mondoinvec_ff_scanin), | |
2403 | .scan_out(creg_mondoinvec_ff_scanout), | |
2404 | .dout (mondoinvec[5:0]), | |
2405 | .l1clk (l1clk), | |
2406 | .en (creg_mondoinvec_wr), | |
2407 | .din (ncu_man_ucb_c2i_packet_data[5:0]), | |
2408 | .siclk(siclk), | |
2409 | .soclk(soclk) | |
2410 | ); | |
2411 | ||
2412 | assign creg_mondoinvec[63:0] = {58'b0,mondoinvec[5:0]}; | |
2413 | ||
2414 | ||
2415 | /************************************************************** | |
2416 | * IOB mem32 base register | |
2417 | **************************************************************/ | |
2418 | assign creg_mem32_base_wr = ncu_man_ucb_buf_acpt_d2 & | |
2419 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mem32_base_dec; | |
2420 | ||
2421 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 creg_mem32_en_ff | |
2422 | ( | |
2423 | .scan_in(creg_mem32_en_ff_scanin), | |
2424 | .scan_out(creg_mem32_en_ff_scanout), | |
2425 | .dout (mem32_en), | |
2426 | .l1clk (l1clk), | |
2427 | .en (creg_mem32_base_wr), | |
2428 | .din (ncu_man_ucb_c2i_packet_data[63]), | |
2429 | .siclk(siclk), | |
2430 | .soclk(soclk) | |
2431 | ); | |
2432 | ||
2433 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_mem32_base_ff | |
2434 | ( | |
2435 | .scan_in(creg_mem32_base_ff_scanin), | |
2436 | .scan_out(creg_mem32_base_ff_scanout), | |
2437 | .dout (mem32_base[11:0]), | |
2438 | .l1clk (l1clk), | |
2439 | .en (creg_mem32_base_wr), | |
2440 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2441 | .siclk(siclk), | |
2442 | .soclk(soclk) | |
2443 | ); | |
2444 | ||
2445 | assign creg_mem32_base[63:0] = {mem32_en,27'b0,mem32_base[11:0],24'b0} ; | |
2446 | ||
2447 | ||
2448 | ||
2449 | /************************************************************** | |
2450 | * IOB mem32 mask register | |
2451 | **************************************************************/ | |
2452 | assign creg_mem32_mask_wr = ncu_man_ucb_buf_acpt_d2 & | |
2453 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mem32_mask_dec; | |
2454 | ||
2455 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_mem32_mask_ff | |
2456 | ( | |
2457 | .scan_in(creg_mem32_mask_ff_scanin), | |
2458 | .scan_out(creg_mem32_mask_ff_scanout), | |
2459 | .dout (mem32_mask[11:0]), | |
2460 | .l1clk (l1clk), | |
2461 | .en (creg_mem32_mask_wr), | |
2462 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2463 | .siclk(siclk), | |
2464 | .soclk(soclk) | |
2465 | ); | |
2466 | ||
2467 | assign creg_mem32_mask[63:0] = {24'b0,4'hf,mem32_mask[11:0],24'b0} ; | |
2468 | ||
2469 | ||
2470 | ||
2471 | /************************************************************** | |
2472 | * IOB mem64 base register | |
2473 | **************************************************************/ | |
2474 | assign creg_mem64_base_wr = ncu_man_ucb_buf_acpt_d2 & | |
2475 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mem64_base_dec; | |
2476 | ||
2477 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 creg_mem64_en_ff | |
2478 | ( | |
2479 | .scan_in(creg_mem64_en_ff_scanin), | |
2480 | .scan_out(creg_mem64_en_ff_scanout), | |
2481 | .dout (mem64_en), | |
2482 | .l1clk (l1clk), | |
2483 | .en (creg_mem64_base_wr), | |
2484 | .din (ncu_man_ucb_c2i_packet_data[63]), | |
2485 | .siclk(siclk), | |
2486 | .soclk(soclk) | |
2487 | ); | |
2488 | ||
2489 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_mem64_base_ff | |
2490 | ( | |
2491 | .scan_in(creg_mem64_base_ff_scanin), | |
2492 | .scan_out(creg_mem64_base_ff_scanout), | |
2493 | .dout (mem64_base[11:0]), | |
2494 | .l1clk (l1clk), | |
2495 | .en (creg_mem64_base_wr), | |
2496 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2497 | .siclk(siclk), | |
2498 | .soclk(soclk) | |
2499 | ); | |
2500 | ||
2501 | assign creg_mem64_base[63:0] = {mem64_en,27'b0,mem64_base[11:0],24'b0} ; | |
2502 | ||
2503 | ||
2504 | ||
2505 | /************************************************************** | |
2506 | * IOB mem64 mask register | |
2507 | **************************************************************/ | |
2508 | assign creg_mem64_mask_wr = ncu_man_ucb_buf_acpt_d2 & | |
2509 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mem64_mask_dec; | |
2510 | ||
2511 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_mem64_mask_ff | |
2512 | ( | |
2513 | .scan_in(creg_mem64_mask_ff_scanin), | |
2514 | .scan_out(creg_mem64_mask_ff_scanout), | |
2515 | .dout (mem64_mask[11:0]), | |
2516 | .l1clk (l1clk), | |
2517 | .en (creg_mem64_mask_wr), | |
2518 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2519 | .siclk(siclk), | |
2520 | .soclk(soclk) | |
2521 | ); | |
2522 | ||
2523 | assign creg_mem64_mask[63:0] = {24'b0,4'hf,mem64_mask[11:0],24'b0} ; | |
2524 | ||
2525 | ||
2526 | /************************************************************** | |
2527 | * IOB iocon base register | |
2528 | **************************************************************/ | |
2529 | assign creg_iocon_base_wr = ncu_man_ucb_buf_acpt_d2 & | |
2530 | ncu_man_ucb_c2i_packet_is_wr_req & creg_iocon_base_dec; | |
2531 | ||
2532 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 creg_iocon_en_ff | |
2533 | ( | |
2534 | .scan_in(creg_iocon_en_ff_scanin), | |
2535 | .scan_out(creg_iocon_en_ff_scanout), | |
2536 | .dout (iocon_en), | |
2537 | .l1clk (l1clk), | |
2538 | .en (creg_iocon_base_wr), | |
2539 | .din (ncu_man_ucb_c2i_packet_data[63]), | |
2540 | .siclk(siclk), | |
2541 | .soclk(soclk) | |
2542 | ); | |
2543 | ||
2544 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_iocon_base_ff | |
2545 | ( | |
2546 | .scan_in(creg_iocon_base_ff_scanin), | |
2547 | .scan_out(creg_iocon_base_ff_scanout), | |
2548 | .dout (iocon_base[11:0]), | |
2549 | .l1clk (l1clk), | |
2550 | .en (creg_iocon_base_wr), | |
2551 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2552 | .siclk(siclk), | |
2553 | .soclk(soclk) | |
2554 | ); | |
2555 | ||
2556 | assign creg_iocon_base[63:0] = {iocon_en,27'b0,iocon_base[11:0],24'b0} ; | |
2557 | ||
2558 | ||
2559 | ||
2560 | /************************************************************** | |
2561 | * IOB iocon mask register | |
2562 | **************************************************************/ | |
2563 | assign creg_iocon_mask_wr = ncu_man_ucb_buf_acpt_d2 & | |
2564 | ncu_man_ucb_c2i_packet_is_wr_req & creg_iocon_mask_dec; | |
2565 | ||
2566 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 creg_iocon_mask_ff | |
2567 | ( | |
2568 | .scan_in(creg_iocon_mask_ff_scanin), | |
2569 | .scan_out(creg_iocon_mask_ff_scanout), | |
2570 | .dout (iocon_mask[11:0]), | |
2571 | .l1clk (l1clk), | |
2572 | .en (creg_iocon_mask_wr), | |
2573 | .din (ncu_man_ucb_c2i_packet_data[35:24]), | |
2574 | .siclk(siclk), | |
2575 | .soclk(soclk) | |
2576 | ); | |
2577 | ||
2578 | assign creg_iocon_mask[63:0] = {24'b0,4'hf,iocon_mask[11:0],24'b0} ; | |
2579 | ||
2580 | ||
2581 | ||
2582 | /************************************************************** | |
2583 | * IOB mmufsh register | |
2584 | **************************************************************/ | |
2585 | // mmu_ld is gaurantee to come back in same or next cyc as mmufsh_vld is asserted// | |
2586 | assign creg_mmufsh_wr = ncu_man_ucb_buf_acpt_d2 & | |
2587 | ncu_man_ucb_c2i_packet_is_wr_req & creg_mmufsh_dec; | |
2588 | ||
2589 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 creg_mmufsh_ff | |
2590 | ( | |
2591 | .scan_in(creg_mmufsh_ff_scanin), | |
2592 | .scan_out(creg_mmufsh_ff_scanout), | |
2593 | .dout (mmufsh_data[63:0]), | |
2594 | .l1clk (l1clk), | |
2595 | .en (creg_mmufsh_wr), | |
2596 | .din (ncu_man_ucb_c2i_packet_data[63:0]), | |
2597 | .siclk(siclk), | |
2598 | .soclk(soclk) | |
2599 | ); | |
2600 | ||
2601 | assign mmufsh_vld_next = creg_mmufsh_wr | (mmufsh_vld&~mmu_ld) ; | |
2602 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mmufsh_vld_ff | |
2603 | ( | |
2604 | .scan_in(mmufsh_vld_ff_scanin), | |
2605 | .scan_out(mmufsh_vld_ff_scanout), | |
2606 | .dout (mmufsh_vld), | |
2607 | .l1clk (l1clk), | |
2608 | .din (mmufsh_vld_next), | |
2609 | .siclk(siclk), | |
2610 | .soclk(soclk) | |
2611 | ); | |
2612 | ||
2613 | ||
2614 | ||
2615 | ||
2616 | ||
2617 | /***************************************************************** | |
2618 | * ncu_int_ucb | |
2619 | *****************************************************************/ | |
2620 | // Flop c2i_packet | |
2621 | assign ncu_int_ucb_buf_acpt = c2i_packet_vld & ncu_int_ucb_sel & | |
2622 | ~tap_mondo_acc_outstanding & | |
2623 | ~tap_mondo_acc_outstanding_d1 & | |
2624 | ~ncu_int_ack_vld; | |
2625 | ||
2626 | assign asi_ras_err_steering_wr = ncu_man_ucb_buf_acpt_d2 & asi_ras_err_steering_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
2627 | assign asi_wmr_vec_mask_wr = ncu_man_ucb_buf_acpt_d2 & asi_wmr_vec_mask_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
2628 | assign asi_cmp_tick_enable_wr = ncu_man_ucb_buf_acpt_d2 & asi_cmp_tick_enable_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
2629 | ||
2630 | assign ras_err_steering_n[5:0] = asi_ras_err_steering_wr ? ncu_man_ucb_c2i_packet_data[5:0] : ras_err_steering[5:0]; | |
2631 | assign wmr_vec_mask_n = asi_wmr_vec_mask_wr ? ncu_man_ucb_c2i_packet_data[0] : wmr_vec_mask; | |
2632 | assign cmp_tick_enable_n = asi_cmp_tick_enable_wr ? ncu_man_ucb_c2i_packet_data[0] : cmp_tick_enable; | |
2633 | ||
2634 | assign creg_err_steering[63:0] = {58'b0, ras_err_steering[5:0]}; | |
2635 | assign creg_wmr_vec_mask[63:0] = {63'b0, wmr_vec_mask}; | |
2636 | assign creg_cmp_tick_enable [63:0] = {63'b0, cmp_tick_enable}; | |
2637 | ||
2638 | assign tcu_wmr_vec_mask = wmr_vec_mask; | |
2639 | ||
2640 | ||
2641 | ncu_ctrl_ctl_msff_ctl_macro__width_1 asi_wmr_vec_mask_ff | |
2642 | ( | |
2643 | .scan_in(asi_wmr_vec_mask_ff_scanin), | |
2644 | .scan_out(asi_wmr_vec_mask_ff_scanout), | |
2645 | .dout (wmr_vec_mask), | |
2646 | .l1clk (l1clk), | |
2647 | .siclk (aclk_wmr), | |
2648 | .din (wmr_vec_mask_n), | |
2649 | .soclk(soclk) | |
2650 | ); | |
2651 | ||
2652 | ncu_ctrl_ctl_msff_ctl_macro__width_1 asi_cmp_tick_enable_ff | |
2653 | ( | |
2654 | .scan_in(asi_cmp_tick_enable_ff_scanin), | |
2655 | .scan_out(asi_cmp_tick_enable_ff_scanout), | |
2656 | .dout (cmp_tick_enable), | |
2657 | .l1clk (l1clk), | |
2658 | .siclk (aclk_wmr), | |
2659 | .din (cmp_tick_enable_n), | |
2660 | .soclk(soclk) | |
2661 | ); | |
2662 | ||
2663 | ||
2664 | ncu_ctrl_ctl_msff_ctl_macro__width_6 asi_ras_err_steering_ff | |
2665 | ( | |
2666 | .scan_in(asi_ras_err_steering_ff_scanin), | |
2667 | .scan_out(asi_ras_err_steering_ff_scanout), | |
2668 | .dout (ras_err_steering[5:0]), | |
2669 | .l1clk (l1clk), | |
2670 | .siclk (aclk_wmr), | |
2671 | .din (ras_err_steering_n[5:0]), | |
2672 | .soclk(soclk) | |
2673 | ); | |
2674 | ||
2675 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_24 tap_mondo_acc_addr_39_16_ff | |
2676 | ( | |
2677 | .scan_in(tap_mondo_acc_addr_39_16_ff_scanin), | |
2678 | .scan_out(tap_mondo_acc_addr_39_16_ff_scanout), | |
2679 | .dout (tap_mondo_acc_addr_39_16[23:0]), | |
2680 | .l1clk (l1clk), | |
2681 | .en (ncu_int_ucb_buf_acpt), | |
2682 | .din (c2i_packet[54:31]), | |
2683 | .siclk(siclk), | |
2684 | .soclk(soclk) | |
2685 | ); | |
2686 | ||
2687 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_22 tap_mondo_acc_addr_s_ff | |
2688 | ( | |
2689 | .scan_in(tap_mondo_acc_addr_s_ff_scanin), | |
2690 | .scan_out(tap_mondo_acc_addr_s_ff_scanout), | |
2691 | .dout (tap_mondo_acc_addr_s[21:0]), | |
2692 | .l1clk (l1clk), | |
2693 | .en (ncu_int_ucb_buf_acpt), | |
2694 | .din ({c2i_packet[9:4], c2i_packet[30:15]}), | |
2695 | .siclk(siclk), | |
2696 | .soclk(soclk) | |
2697 | ); | |
2698 | ||
2699 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 tap_mondo_din_s_ff | |
2700 | ( | |
2701 | .scan_in(tap_mondo_din_s_ff_scanin), | |
2702 | .scan_out(tap_mondo_din_s_ff_scanout), | |
2703 | .dout (tap_mondo_din_s[63:0]), | |
2704 | .l1clk (l1clk), | |
2705 | .en (ncu_int_ucb_buf_acpt), | |
2706 | .din (c2i_packet[127:64]), | |
2707 | .siclk(siclk), | |
2708 | .soclk(soclk) | |
2709 | ); | |
2710 | ||
2711 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ncu_int_ucb_c2i_packet_is_rd_req_ff | |
2712 | ( | |
2713 | .scan_in(ncu_int_ucb_c2i_packet_is_rd_req_ff_scanin), | |
2714 | .scan_out(ncu_int_ucb_c2i_packet_is_rd_req_ff_scanout), | |
2715 | .dout (ncu_int_ucb_c2i_packet_is_rd_req), | |
2716 | .l1clk (l1clk), | |
2717 | .en (ncu_int_ucb_buf_acpt), | |
2718 | .din (c2i_packet_is_rd_req), | |
2719 | .siclk(siclk), | |
2720 | .soclk(soclk) | |
2721 | ); | |
2722 | ||
2723 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ncu_int_ucb_c2i_packet_is_wr_req_ff | |
2724 | ( | |
2725 | .scan_in(ncu_int_ucb_c2i_packet_is_wr_req_ff_scanin), | |
2726 | .scan_out(ncu_int_ucb_c2i_packet_is_wr_req_ff_scanout), | |
2727 | .dout (ncu_int_ucb_c2i_packet_is_wr_req), | |
2728 | .l1clk (l1clk), | |
2729 | .en (ncu_int_ucb_buf_acpt), | |
2730 | .din (c2i_packet_is_wr_req), | |
2731 | .siclk(siclk), | |
2732 | .soclk(soclk) | |
2733 | ); | |
2734 | ||
2735 | ||
2736 | // Send interrupt status tbl read/write request to c2i | |
2737 | //assign tap_mondo_acc_addr_s[39:0] = ncu_int_ucb_c2i_packet[54:15]; | |
2738 | ||
2739 | assign tap_mondo_acc_seq_next = ~tap_mondo_acc_seq; | |
2740 | ||
2741 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 tap_mondo_acc_seq_ff | |
2742 | ( | |
2743 | .scan_in(tap_mondo_acc_seq_ff_scanin), | |
2744 | .scan_out(tap_mondo_acc_seq_ff_scanout), | |
2745 | .dout (tap_mondo_acc_seq), | |
2746 | .l1clk (l1clk), | |
2747 | .en (ncu_int_ucb_buf_acpt), | |
2748 | .din (tap_mondo_acc_seq_next), | |
2749 | .siclk(siclk), | |
2750 | .soclk(soclk) | |
2751 | ); | |
2752 | ||
2753 | assign tap_mondo_acc_seq_s = tap_mondo_acc_seq; | |
2754 | ||
2755 | assign tap_mondo_wr_s = ncu_int_ucb_c2i_packet_is_wr_req; | |
2756 | ||
2757 | // Receive interrupt status tbl read/write ack from c2i | |
2758 | ncu_ctrl_ctl_msff_ctl_macro__width_1 tap_mondo_acc_addr_invld_d2_ff | |
2759 | ( | |
2760 | .scan_in(tap_mondo_acc_addr_invld_d2_ff_scanin), | |
2761 | .scan_out(tap_mondo_acc_addr_invld_d2_ff_scanout), | |
2762 | .dout (tap_mondo_acc_addr_invld_d2), | |
2763 | .l1clk (l1clk), | |
2764 | .din (tap_mondo_acc_addr_invld_d2_f), | |
2765 | .siclk(siclk), | |
2766 | .soclk(soclk) | |
2767 | ); | |
2768 | ||
2769 | ncu_ctrl_ctl_msff_ctl_macro__width_1 tap_mondo_acc_seq_d2_ff | |
2770 | ( | |
2771 | .scan_in(tap_mondo_acc_seq_d2_ff_scanin), | |
2772 | .scan_out(tap_mondo_acc_seq_d2_ff_scanout), | |
2773 | .dout (tap_mondo_acc_seq_d2), | |
2774 | .l1clk (l1clk), | |
2775 | .din (tap_mondo_acc_seq_d2_f), | |
2776 | .siclk(siclk), | |
2777 | .soclk(soclk) | |
2778 | ); | |
2779 | ||
2780 | ncu_ctrl_ctl_msff_ctl_macro__width_64 tap_mondo_dout_d2_ff | |
2781 | ( | |
2782 | .scan_in(tap_mondo_dout_d2_ff_scanin), | |
2783 | .scan_out(tap_mondo_dout_d2_ff_scanout), | |
2784 | .dout (tap_mondo_dout_d2[63:0]), | |
2785 | .l1clk (l1clk), | |
2786 | .din (tap_mondo_dout_d2_f[63:0]), | |
2787 | .siclk(siclk), | |
2788 | .soclk(soclk) | |
2789 | ); | |
2790 | ||
2791 | // Detect when the interrupt tbl access is done | |
2792 | assign tap_mondo_acc_outstanding = (tap_mondo_acc_seq != tap_mondo_acc_seq_d2); | |
2793 | ||
2794 | ncu_ctrl_ctl_msff_ctl_macro__width_1 tap_mondo_acc_outstanding_d1_ff | |
2795 | ( | |
2796 | .scan_in(tap_mondo_acc_outstanding_d1_ff_scanin), | |
2797 | .scan_out(tap_mondo_acc_outstanding_d1_ff_scanout), | |
2798 | .dout (tap_mondo_acc_outstanding_d1), | |
2799 | .l1clk (l1clk), | |
2800 | .din (tap_mondo_acc_outstanding), | |
2801 | .siclk(siclk), | |
2802 | .soclk(soclk) | |
2803 | ); | |
2804 | ||
2805 | assign tap_mondo_rd_done = ~tap_mondo_acc_outstanding & | |
2806 | tap_mondo_acc_outstanding_d1 & | |
2807 | ncu_int_ucb_c2i_packet_is_rd_req ; | |
2808 | ||
2809 | // Assemble read result back to UCB packet format | |
2810 | assign ncu_int_ucb_i2c_packet_type[3:0] = tap_mondo_acc_addr_invld_d2 ? | |
2811 | `UCB_READ_NACK : `UCB_READ_ACK ; | |
2812 | ||
2813 | assign ncu_int_ucb_i2c_packet[127:0] = | |
2814 | { tap_mondo_dout_d2[63:0], // data | |
2815 | 9'b0, // reserved | |
2816 | tap_mondo_acc_addr_39_16[23:0], // addr[39:16] | |
2817 | tap_mondo_acc_addr_s[15:0], // addr[15:0] | |
2818 | 3'b0, // size | |
2819 | 2'b01, // buffer ID | |
2820 | 6'b0, // thread ID | |
2821 | ncu_int_ucb_i2c_packet_type[3:0] };// packet type | |
2822 | ||
2823 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 ncu_int_ack_packet_ff | |
2824 | ( | |
2825 | .scan_in(ncu_int_ack_packet_ff_scanin), | |
2826 | .scan_out(ncu_int_ack_packet_ff_scanout), | |
2827 | .dout (ncu_int_ack_packet[127:0]), | |
2828 | .l1clk (l1clk), | |
2829 | .en (tap_mondo_rd_done), | |
2830 | .din (ncu_int_ucb_i2c_packet[127:0]), | |
2831 | .siclk(siclk), | |
2832 | .soclk(soclk) | |
2833 | ); | |
2834 | ||
2835 | assign ncu_int_ack_vld_next = tap_mondo_rd_done | (ncu_int_ack_vld & ~ncu_int_ack_rd); | |
2836 | ||
2837 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_int_ack_vld_ff | |
2838 | ( | |
2839 | .scan_in(ncu_int_ack_vld_ff_scanin), | |
2840 | .scan_out(ncu_int_ack_vld_ff_scanout), | |
2841 | .dout (ncu_int_ack_vld), | |
2842 | .l1clk (l1clk), | |
2843 | .din (ncu_int_ack_vld_next), | |
2844 | .siclk(siclk), | |
2845 | .soclk(soclk) | |
2846 | ); | |
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | /***************************************************************** | |
2853 | * bounce_ucb | |
2854 | *****************************************************************/ | |
2855 | assign bounce_ack_buf_wr = c2i_packet_vld & bounce_ucb_sel & ~bounce_ack_buf_full; | |
2856 | ||
2857 | assign bounce_ucb_buf_acpt = bounce_ack_buf_wr; | |
2858 | ||
2859 | assign bounce_ack_buf_din[127:0] = c2i_packet[127:0]; | |
2860 | //============================================= | |
2861 | //dbl_buf #(128) bounce_ack_buf ( | |
2862 | // .clk(iol2clk), | |
2863 | // .wr(bounce_ack_buf_wr), | |
2864 | // .din(bounce_ack_buf_din[127:0]), | |
2865 | // .vld(bounce_ack_buf_vld), | |
2866 | // .dout(bounce_ack_buf_dout[127:0]), | |
2867 | // .rd(bounce_ack_buf_rd), | |
2868 | // .full(bounce_ack_buf_full) ); */ | |
2869 | //============================================================================= | |
2870 | //============================================================================= | |
2871 | //========================================================== dbl_buf ========== | |
2872 | ||
2873 | // if both entries are empty, write to entry pointed to by the older pointer | |
2874 | assign cc_wr_buf0 = bounce_ack_buf_wr & (cc_buf1_vld | (~cc_buf0_vld & ~cc_buf1_older)); | |
2875 | assign cc_wr_buf1 = bounce_ack_buf_wr & (cc_buf0_vld | (~cc_buf1_vld & cc_buf1_older)); | |
2876 | ||
2877 | // read from the older entry | |
2878 | assign cc_rd_buf0 = bounce_ack_buf_rd & ~cc_buf1_older; | |
2879 | assign cc_rd_buf1 = bounce_ack_buf_rd & cc_buf1_older; | |
2880 | ||
2881 | // flip older pointer when an entry is read | |
2882 | assign cc_rd_buf = bounce_ack_buf_rd & (cc_buf0_vld | cc_buf1_vld); | |
2883 | assign cc_buf1_older_inv = ~cc_buf1_older; | |
2884 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 cc_buf1_older_ff | |
2885 | ( | |
2886 | .scan_in(cc_buf1_older_ff_scanin), | |
2887 | .scan_out(cc_buf1_older_ff_scanout), | |
2888 | .dout (cc_buf1_older), | |
2889 | .l1clk (l1clk), | |
2890 | .en (cc_rd_buf), | |
2891 | .din (cc_buf1_older_inv), | |
2892 | .siclk(siclk), | |
2893 | .soclk(soclk) | |
2894 | ); | |
2895 | ||
2896 | // set valid bit for writes and reset for reads | |
2897 | assign cc_en_vld0 = cc_wr_buf0 | cc_rd_buf0; | |
2898 | assign cc_en_vld1 = cc_wr_buf1 | cc_rd_buf1; | |
2899 | ||
2900 | // the actual buffers | |
2901 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 cc_buf0_vld_ff | |
2902 | ( | |
2903 | .scan_in(cc_buf0_vld_ff_scanin), | |
2904 | .scan_out(cc_buf0_vld_ff_scanout), | |
2905 | .dout (cc_buf0_vld), | |
2906 | .l1clk (l1clk), | |
2907 | .en (cc_en_vld0), | |
2908 | .din (cc_wr_buf0), | |
2909 | .siclk(siclk), | |
2910 | .soclk(soclk) | |
2911 | ); | |
2912 | ||
2913 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 cc_buf1_vld_ff | |
2914 | ( | |
2915 | .scan_in(cc_buf1_vld_ff_scanin), | |
2916 | .scan_out(cc_buf1_vld_ff_scanout), | |
2917 | .dout (cc_buf1_vld), | |
2918 | .l1clk (l1clk), | |
2919 | .en (cc_en_vld1), | |
2920 | .din (cc_wr_buf1), | |
2921 | .siclk(siclk), | |
2922 | .soclk(soclk) | |
2923 | ); | |
2924 | ||
2925 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 cc_buf0_obj_ff | |
2926 | ( | |
2927 | .scan_in(cc_buf0_obj_ff_scanin), | |
2928 | .scan_out(cc_buf0_obj_ff_scanout), | |
2929 | .dout (cc_buf0_obj[127:0]), | |
2930 | .l1clk (l1clk), | |
2931 | .en (cc_wr_buf0), | |
2932 | .din (bounce_ack_buf_din[127:0]), | |
2933 | .siclk(siclk), | |
2934 | .soclk(soclk) | |
2935 | ); | |
2936 | ||
2937 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 cc_buf1_obj_ff | |
2938 | ( | |
2939 | .scan_in(cc_buf1_obj_ff_scanin), | |
2940 | .scan_out(cc_buf1_obj_ff_scanout), | |
2941 | .dout (cc_buf1_obj[127:0]), | |
2942 | .l1clk (l1clk), | |
2943 | .en (cc_wr_buf1), | |
2944 | .din (bounce_ack_buf_din[127:0]), | |
2945 | .siclk(siclk), | |
2946 | .soclk(soclk) | |
2947 | ); | |
2948 | ||
2949 | // mux out the older entry | |
2950 | assign bounce_ack_buf_dout[127:0] = (cc_buf1_older) ? cc_buf1_obj[127:0] : cc_buf0_obj[127:0] ; | |
2951 | ||
2952 | assign bounce_ack_buf_vld = cc_buf0_vld | cc_buf1_vld; | |
2953 | assign bounce_ack_buf_full = cc_buf0_vld & cc_buf1_vld; | |
2954 | //============================================= | |
2955 | assign bounce_ack_vld = bounce_ack_buf_vld; | |
2956 | ||
2957 | assign bounce_ack_packet[127:0] = bounce_ack_buf_dout[127:0]; | |
2958 | ||
2959 | assign bounce_ack_buf_rd = bounce_ack_rd; | |
2960 | //========================================================== dbl_buf ========== | |
2961 | //============================================================================= | |
2962 | //============================================================================= | |
2963 | ||
2964 | ||
2965 | ||
2966 | /***************************************************************** | |
2967 | * rd_nack_ucb | |
2968 | *****************************************************************/ | |
2969 | assign rd_nack_buf_wr = c2i_packet_vld & rd_nack_ucb_sel & ~rd_nack_buf_full; | |
2970 | ||
2971 | assign rd_nack_ucb_buf_acpt = rd_nack_buf_wr; | |
2972 | ||
2973 | assign rd_nack_buf_din[63:0] = c2i_rd_nack_packet[63:0]; | |
2974 | //============================================= | |
2975 | //dbl_buf #(64) rd_nack_buf ( | |
2976 | // .clk(iol2clk), | |
2977 | // .wr(rd_nack_buf_wr), | |
2978 | // .din(rd_nack_buf_din[63:0]), | |
2979 | // .vld(rd_nack_buf_vld), | |
2980 | // .dout(rd_nack_buf_dout[63:0]), | |
2981 | // .rd(rd_nack_buf_rd), | |
2982 | // .full(rd_nack_buf_full) ); */ | |
2983 | //============================================================================= | |
2984 | //============================================================================= | |
2985 | //========================================================== dbl_buf ========== | |
2986 | ||
2987 | // if both entries are empty, write to entry pointed to by the older pointer | |
2988 | assign dd_wr_buf0 = rd_nack_buf_wr & (dd_buf1_vld | (~dd_buf0_vld & ~dd_buf1_older)); | |
2989 | assign dd_wr_buf1 = rd_nack_buf_wr & (dd_buf0_vld | (~dd_buf1_vld & dd_buf1_older)); | |
2990 | ||
2991 | // read from the older entry | |
2992 | assign dd_rd_buf0 = rd_nack_buf_rd & ~dd_buf1_older; | |
2993 | assign dd_rd_buf1 = rd_nack_buf_rd & dd_buf1_older; | |
2994 | ||
2995 | // flip older pointer when an entry is read | |
2996 | assign dd_rd_buf = rd_nack_buf_rd & (dd_buf0_vld | dd_buf1_vld); | |
2997 | assign dd_buf1_older_inv = ~dd_buf1_older; | |
2998 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 dd_buf1_older_ff | |
2999 | ( | |
3000 | .scan_in(dd_buf1_older_ff_scanin), | |
3001 | .scan_out(dd_buf1_older_ff_scanout), | |
3002 | .dout (dd_buf1_older), | |
3003 | .l1clk (l1clk), | |
3004 | .en (dd_rd_buf), | |
3005 | .din (dd_buf1_older_inv), | |
3006 | .siclk(siclk), | |
3007 | .soclk(soclk) | |
3008 | ); | |
3009 | ||
3010 | // set valid bit for writes and reset for reads | |
3011 | assign dd_en_vld0 = dd_wr_buf0 | dd_rd_buf0; | |
3012 | assign dd_en_vld1 = dd_wr_buf1 | dd_rd_buf1; | |
3013 | ||
3014 | // the actual buffers | |
3015 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 dd_buf0_vld_ff | |
3016 | ( | |
3017 | .scan_in(dd_buf0_vld_ff_scanin), | |
3018 | .scan_out(dd_buf0_vld_ff_scanout), | |
3019 | .dout (dd_buf0_vld), | |
3020 | .l1clk (l1clk), | |
3021 | .en (dd_en_vld0), | |
3022 | .din (dd_wr_buf0), | |
3023 | .siclk(siclk), | |
3024 | .soclk(soclk) | |
3025 | ); | |
3026 | ||
3027 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 dd_buf1_vld_ff | |
3028 | ( | |
3029 | .scan_in(dd_buf1_vld_ff_scanin), | |
3030 | .scan_out(dd_buf1_vld_ff_scanout), | |
3031 | .dout (dd_buf1_vld), | |
3032 | .l1clk (l1clk), | |
3033 | .en (dd_en_vld1), | |
3034 | .din (dd_wr_buf1), | |
3035 | .siclk(siclk), | |
3036 | .soclk(soclk) | |
3037 | ); | |
3038 | ||
3039 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 dd_buf0_obj_ff | |
3040 | ( | |
3041 | .scan_in(dd_buf0_obj_ff_scanin), | |
3042 | .scan_out(dd_buf0_obj_ff_scanout), | |
3043 | .dout (dd_buf0_obj[63:0]), | |
3044 | .l1clk (l1clk), | |
3045 | .en (dd_wr_buf0), | |
3046 | .din (rd_nack_buf_din[63:0]), | |
3047 | .siclk(siclk), | |
3048 | .soclk(soclk) | |
3049 | ); | |
3050 | ||
3051 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 dd_buf1_obj_ff | |
3052 | ( | |
3053 | .scan_in(dd_buf1_obj_ff_scanin), | |
3054 | .scan_out(dd_buf1_obj_ff_scanout), | |
3055 | .dout (dd_buf1_obj[63:0]), | |
3056 | .l1clk (l1clk), | |
3057 | .en (dd_wr_buf1), | |
3058 | .din (rd_nack_buf_din[63:0]), | |
3059 | .siclk(siclk), | |
3060 | .soclk(soclk) | |
3061 | ); | |
3062 | ||
3063 | // mux out the older entry | |
3064 | assign rd_nack_buf_dout[63:0] = (dd_buf1_older) ? dd_buf1_obj[63:0] : dd_buf0_obj[63:0] ; | |
3065 | ||
3066 | assign rd_nack_buf_vld = dd_buf0_vld | dd_buf1_vld; | |
3067 | assign rd_nack_buf_full = dd_buf0_vld & dd_buf1_vld; | |
3068 | //============================================= | |
3069 | assign rd_nack_vld = rd_nack_buf_vld; | |
3070 | ||
3071 | assign rd_nack_packet[63:0] = rd_nack_buf_dout[63:0]; | |
3072 | ||
3073 | assign rd_nack_buf_rd = rd_nack_rd; | |
3074 | //========================================================== dbl_buf ========== | |
3075 | //============================================================================= | |
3076 | //============================================================================= | |
3077 | ||
3078 | ||
3079 | //================================ | |
3080 | //=== ASI related registers ==== | |
3081 | //================================ | |
3082 | ||
3083 | ||
3084 | // **************************** | |
3085 | // utility in wmr_protected chain | |
3086 | // **************************** | |
3087 | /* | |
3088 | assign wmr_counter_p1[9:0] = (wmr_counter[9:0]==`WMR_LENGTH_P1) ? `WMR_LENGTH_P1 : wmr_counter[9:0]+10'b1; | |
3089 | ||
3090 | msff_ctl_macro wmr_counter_ff (width=10) | |
3091 | ( | |
3092 | .scan_in(wmr_counter_ff_scanin), | |
3093 | .scan_out(wmr_counter_ff_scanout), | |
3094 | .dout (wmr_counter[9:0]), | |
3095 | .l1clk (l1clk), | |
3096 | .din (wmr_counter_p1[9:0]) | |
3097 | ); | |
3098 | */ | |
3099 | ||
3100 | //assign wmr_upd_en = (wmr_counter[9:0]==`WMR_LENGTH)|~cmp_freeze[2] ; | |
3101 | //assign cmp_freeze_n[2:0] = {1'b1,cmp_freeze[1:0]}; | |
3102 | ||
3103 | ||
3104 | assign wmr_upd_en = ~wmr_protect_d1&wmr_protect_d2 ; // detect deassert of wmr. | |
3105 | ||
3106 | ncu_ctrl_ctl_msff_ctl_macro__width_1 wmr_protect_d1_ff | |
3107 | ( | |
3108 | .scan_in(wmr_protect_d1_ff_scanin), | |
3109 | .scan_out(wmr_protect_d1_ff_scanout), | |
3110 | .dout (wmr_protect_d1), | |
3111 | .l1clk (l1clk), | |
3112 | .siclk (aclk_wmr), | |
3113 | .din (wmr_protect), | |
3114 | .soclk(soclk) | |
3115 | ); | |
3116 | ||
3117 | ncu_ctrl_ctl_msff_ctl_macro__width_1 wmr_protect_d2_ff | |
3118 | ( | |
3119 | .scan_in(wmr_protect_d2_ff_scanin), | |
3120 | .scan_out(wmr_protect_d2_ff_scanout), | |
3121 | .dout (wmr_protect_d2), | |
3122 | .l1clk (l1clk), | |
3123 | .siclk (aclk_wmr), | |
3124 | .din (wmr_protect_d1), | |
3125 | .soclk(soclk) | |
3126 | ); | |
3127 | ||
3128 | assign por_upd_en_next = ~tcu_aclk & ~tcu_bclk & ~tcu_scan_en; // detect deassert of POR | |
3129 | assign por_upd_en = por_upd_en_next & ~por_upd_en_d1 & ~wmr_protect; | |
3130 | ||
3131 | ncu_ctrl_ctl_msff_ctl_macro__width_1 por_upd_en_ff | |
3132 | ( | |
3133 | .scan_in(por_upd_en_ff_scanin), | |
3134 | .scan_out(por_upd_en_ff_scanout), | |
3135 | .dout (por_upd_en_d1), | |
3136 | .l1clk (l1clk), | |
3137 | //.siclk (aclk_wmr), | |
3138 | .din (por_upd_en_next), | |
3139 | .siclk(siclk), | |
3140 | .soclk(soclk) | |
3141 | ); | |
3142 | ||
3143 | ||
3144 | /*************************** | |
3145 | ***** core_available **** | |
3146 | ***************************/ | |
3147 | //// register is from efuse core_available[7:0] | |
3148 | ||
3149 | /*********************** | |
3150 | **** core_enable **** | |
3151 | ***********************/ | |
3152 | always@(coreavail) begin | |
3153 | casex(coreavail[7:0]) | |
3154 | 8'bxxxx_xxx1 : coreavail_lowest_1hot[7:0] = 8'b0000_0001 ; | |
3155 | 8'bxxxx_xx10 : coreavail_lowest_1hot[7:0] = 8'b0000_0010 ; | |
3156 | 8'bxxxx_x100 : coreavail_lowest_1hot[7:0] = 8'b0000_0100 ; | |
3157 | 8'bxxxx_1000 : coreavail_lowest_1hot[7:0] = 8'b0000_1000 ; | |
3158 | 8'bxxx1_0000 : coreavail_lowest_1hot[7:0] = 8'b0001_0000 ; | |
3159 | 8'bxx10_0000 : coreavail_lowest_1hot[7:0] = 8'b0010_0000 ; | |
3160 | 8'bx100_0000 : coreavail_lowest_1hot[7:0] = 8'b0100_0000 ; | |
3161 | 8'b1000_0000 : coreavail_lowest_1hot[7:0] = 8'b1000_0000 ; | |
3162 | default : coreavail_lowest_1hot[7:0] = 8'b0000_0000 ; | |
3163 | endcase | |
3164 | end | |
3165 | ||
3166 | assign core_enable_a0_default[7:0] = ncu_man_ucb_c2i_packet_buf_id[0] ? coreavail_lowest_1hot[7:0] : | |
3167 | 8'b0000_0001 << ncu_man_ucb_c2i_packet_cputhr[5:3] ; | |
3168 | assign c2i_core_en[7:0] = { (&ncu_man_ucb_c2i_packet_data[63:56]), | |
3169 | (&ncu_man_ucb_c2i_packet_data[55:48]), | |
3170 | (&ncu_man_ucb_c2i_packet_data[47:40]), | |
3171 | (&ncu_man_ucb_c2i_packet_data[39:32]), | |
3172 | (&ncu_man_ucb_c2i_packet_data[31:24]), | |
3173 | (&ncu_man_ucb_c2i_packet_data[23:16]), | |
3174 | (&ncu_man_ucb_c2i_packet_data[15:8] ), | |
3175 | (&ncu_man_ucb_c2i_packet_data[7:0] ) } & coreavail[7:0] ; | |
3176 | ||
3177 | assign c2i_core_en_a0 = ~(|c2i_core_en[7:0]) ; | |
3178 | ||
3179 | assign asi_core_en_wr = ncu_man_ucb_buf_acpt_d2 & asi_core_enable_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
3180 | ||
3181 | assign core_enable_next[7:0] = coreavail_done ? coreavail[7:0] : // update with coreavail deassert wmr or por | |
3182 | ~asi_core_en_wr ? core_enable[7:0] : //lock here when no write// | |
3183 | c2i_core_en_a0 ? core_enable_a0_default[7:0] : c2i_core_en[7:0] ; | |
3184 | ||
3185 | assign core_enable_ff_in[7:0] = ~core_enable_next[7:0]; | |
3186 | ncu_ctrl_ctl_msff_ctl_macro__width_8 core_enable_ff | |
3187 | ( | |
3188 | .scan_in(core_enable_ff_scanin), | |
3189 | .scan_out(core_enable_ff_scanout), | |
3190 | .dout (core_enable_ff_out[7:0]), | |
3191 | .l1clk (l1clk), | |
3192 | .siclk (aclk_wmr), | |
3193 | .din (core_enable_ff_in[7:0]), | |
3194 | .soclk(soclk) | |
3195 | ); | |
3196 | assign core_enable[7:0] = ~core_enable_ff_out[7:0]; | |
3197 | ||
3198 | assign creg_core_enable[63:0] = { {8{core_enable[7]}}, {8{core_enable[6]}}, | |
3199 | {8{core_enable[5]}}, {8{core_enable[4]}}, | |
3200 | {8{core_enable[3]}}, {8{core_enable[2]}}, | |
3201 | {8{core_enable[1]}}, {8{core_enable[0]}} }; | |
3202 | ||
3203 | ||
3204 | /*************************** | |
3205 | *** core_enable_status *** | |
3206 | ***************************/ | |
3207 | assign core_enable_status_next[7:0] = coreavail_done ? coreavail[7:0] : | |
3208 | wmr_upd_en ? core_enable[7:0] : core_enable_status[7:0] ; | |
3209 | ||
3210 | assign core_enable_status_ff_in[7:0] = ~core_enable_status_next[7:0]; | |
3211 | ||
3212 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status7_ff | |
3213 | ( | |
3214 | .scan_in(core_enable_status7_ff_scanin), | |
3215 | .scan_out(core_enable_status7_ff_scanout), | |
3216 | .q_l (ncu_spc7_core_enable_status), | |
3217 | .l1clk (l1clk), | |
3218 | .din (core_enable_status_ff_in[7]), | |
3219 | .siclk(siclk), | |
3220 | .soclk(soclk) | |
3221 | ); | |
3222 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status6_ff | |
3223 | ( | |
3224 | .scan_in(core_enable_status6_ff_scanin), | |
3225 | .scan_out(core_enable_status6_ff_scanout), | |
3226 | .q_l (ncu_spc6_core_enable_status), | |
3227 | .l1clk (l1clk), | |
3228 | .din (core_enable_status_ff_in[6]), | |
3229 | .siclk(siclk), | |
3230 | .soclk(soclk) | |
3231 | ); | |
3232 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status5_ff | |
3233 | ( | |
3234 | .scan_in(core_enable_status5_ff_scanin), | |
3235 | .scan_out(core_enable_status5_ff_scanout), | |
3236 | .q_l (ncu_spc5_core_enable_status), | |
3237 | .l1clk (l1clk), | |
3238 | .din (core_enable_status_ff_in[5]), | |
3239 | .siclk(siclk), | |
3240 | .soclk(soclk) | |
3241 | ); | |
3242 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status4_ff | |
3243 | ( | |
3244 | .scan_in(core_enable_status4_ff_scanin), | |
3245 | .scan_out(core_enable_status4_ff_scanout), | |
3246 | .q_l (ncu_spc4_core_enable_status), | |
3247 | .l1clk (l1clk), | |
3248 | .din (core_enable_status_ff_in[4]), | |
3249 | .siclk(siclk), | |
3250 | .soclk(soclk) | |
3251 | ); | |
3252 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status3_ff | |
3253 | ( | |
3254 | .scan_in(core_enable_status3_ff_scanin), | |
3255 | .scan_out(core_enable_status3_ff_scanout), | |
3256 | .q_l (ncu_spc3_core_enable_status), | |
3257 | .l1clk (l1clk), | |
3258 | .din (core_enable_status_ff_in[3]), | |
3259 | .siclk(siclk), | |
3260 | .soclk(soclk) | |
3261 | ); | |
3262 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status2_ff | |
3263 | ( | |
3264 | .scan_in(core_enable_status2_ff_scanin), | |
3265 | .scan_out(core_enable_status2_ff_scanout), | |
3266 | .q_l (ncu_spc2_core_enable_status), | |
3267 | .l1clk (l1clk), | |
3268 | .din (core_enable_status_ff_in[2]), | |
3269 | .siclk(siclk), | |
3270 | .soclk(soclk) | |
3271 | ); | |
3272 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status1_ff | |
3273 | ( | |
3274 | .scan_in(core_enable_status1_ff_scanin), | |
3275 | .scan_out(core_enable_status1_ff_scanout), | |
3276 | .q_l (ncu_spc1_core_enable_status), | |
3277 | .l1clk (l1clk), | |
3278 | .din (core_enable_status_ff_in[1]), | |
3279 | .siclk(siclk), | |
3280 | .soclk(soclk) | |
3281 | ); | |
3282 | ncu_ctrl_ctl_msffi_ctl_macro__width_1 core_enable_status0_ff | |
3283 | ( | |
3284 | .scan_in(core_enable_status0_ff_scanin), | |
3285 | .scan_out(core_enable_status0_ff_scanout), | |
3286 | .q_l (ncu_spc0_core_enable_status), | |
3287 | .l1clk (l1clk), | |
3288 | .din (core_enable_status_ff_in[0]), | |
3289 | .siclk(siclk), | |
3290 | .soclk(soclk) | |
3291 | ); | |
3292 | ||
3293 | //assign core_enable_status[7:0] = ~core_enable_status_ff_out[7:0]; | |
3294 | assign core_enable_status[7:0] = {ncu_spc7_core_enable_status,ncu_spc6_core_enable_status,ncu_spc5_core_enable_status,ncu_spc4_core_enable_status, | |
3295 | ncu_spc3_core_enable_status,ncu_spc2_core_enable_status,ncu_spc1_core_enable_status,ncu_spc0_core_enable_status}; | |
3296 | ||
3297 | assign creg_core_enable_status[63:0] = { {8{core_enable_status[7]}},{8{core_enable_status[6]}}, | |
3298 | {8{core_enable_status[5]}},{8{core_enable_status[4]}}, | |
3299 | {8{core_enable_status[3]}},{8{core_enable_status[2]}}, | |
3300 | {8{core_enable_status[1]}},{8{core_enable_status[0]}} } ; | |
3301 | ||
3302 | ||
3303 | ||
3304 | /************************** | |
3305 | ***** xir_steering ***** | |
3306 | **************************/ | |
3307 | ||
3308 | ncu_ctrl_ctl_msff_ctl_macro__width_1 coreavail_done_d1_ff | |
3309 | ( | |
3310 | .scan_in(coreavail_done_d1_ff_scanin), | |
3311 | .scan_out(coreavail_done_d1_ff_scanout), | |
3312 | .dout (coreavail_done_d1), | |
3313 | .l1clk (l1clk), | |
3314 | .din (coreavail_done), | |
3315 | .siclk(siclk), | |
3316 | .soclk(soclk) | |
3317 | ); | |
3318 | ||
3319 | ||
3320 | ||
3321 | ||
3322 | ////// have same value as core_enable_status after wmr, so take value from core_enable at de-assertion of wmr, | |
3323 | // check/qualify with core_enable_status for further asi_wr. Ok to have 0 value in register// | |
3324 | ||
3325 | assign asi_xir_steering_wr = ncu_man_ucb_buf_acpt_d2 & asi_xir_steering_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
3326 | ||
3327 | //also use by core_running// | |
3328 | assign core_enable_status64[63:0] = { {8{core_enable_status[7]}}, | |
3329 | {8{core_enable_status[6]}}, | |
3330 | {8{core_enable_status[5]}}, | |
3331 | {8{core_enable_status[4]}}, | |
3332 | {8{core_enable_status[3]}}, | |
3333 | {8{core_enable_status[2]}}, | |
3334 | {8{core_enable_status[1]}}, | |
3335 | {8{core_enable_status[0]}} } ; | |
3336 | ||
3337 | assign c2i_data_by_core_enable_status[63:0] = core_enable_status64[63:0]&ncu_man_ucb_c2i_packet_data[63:0] ; | |
3338 | ||
3339 | assign xir_steering_next[63:0] = | |
3340 | coreavail_done_d1 ? creg_coreavail[63:0] : | |
3341 | wmr_upd_en ? creg_core_enable[63:0] : | |
3342 | asi_xir_steering_wr ? c2i_data_by_core_enable_status[63:0] : xir_steering[63:0] ; | |
3343 | ||
3344 | assign xir_snapd_vec_vld = |xir_snapd_vec[55:0] ; | |
3345 | assign xir_snapd_vec_next[55:0] = xir_trigger_d1 ? xir_steering[63:8] : | |
3346 | xir_ld_mini_vec ? {8'b0,xir_snapd_vec[55:8]} : xir_snapd_vec[55:0] ; | |
3347 | ||
3348 | ||
3349 | assign xir_srvcd_mini_vec_vld = |xir_srvcd_mini_vec[7:0] ; | |
3350 | ||
3351 | assign xir_mini_vec_next[7:0] = xir_trigger_d1 ? xir_steering[7:0] : | |
3352 | xir_ld_mini_vec ? xir_snapd_vec[7:0] : | |
3353 | xir_srvc ? xir_srvcd_mini_vec[7:0] : xir_mini_vec[7:0] ; | |
3354 | ||
3355 | //// to ignore any rst_xir comes in during busy //// | |
3356 | assign xir_trigger_d0_next = xir_trigger & ~xir_busy ; | |
3357 | ||
3358 | assign xir_ld_mini_vec = ~xir_srvcd_mini_vec_vld & xir_snapd_vec_vld & ~ncu_man_int_buf_full ; | |
3359 | ||
3360 | assign xir_srvc = ~ncu_man_int_buf_full & xir_mini_vec_vld & ~intvecdisp_int_wr & ~rasper_int_wr ; | |
3361 | ||
3362 | assign xir_int_wr = xir_srvc ; | |
3363 | ||
3364 | ||
3365 | assign xir_cpuid_p1[2:0] = xir_cpuid[2:0]+3'b001 ; | |
3366 | //// set cpuid to 3'd0 when trigger_d1 //// | |
3367 | assign xir_cpuid_next[2:0] = xir_cpuid_p1[2:0] & {3{~xir_trigger_d1}} ; | |
3368 | assign xir_cpuid_inc = xir_ld_mini_vec | xir_trigger_d1 ; | |
3369 | ||
3370 | assign xir_busy_next = xir_trigger_d0 | xir_trigger_d1 | xir_snapd_vec_vld | xir_mini_vec_vld | xir_trigger_d0_next ; | |
3371 | assign xir_busy_falling = ~xir_busy & xir_busy_d1 ; | |
3372 | assign ncu_rst_xir_done_next = rst_ncu_xir_inv ? 1'b0 : xir_busy_falling ? 1'b1 : ncu_rst_xir_done; | |
3373 | //assign ncu_rst_xir_done_next = ~xir_busy & xir_busy_d1 ; | |
3374 | assign xir_trigger_next = ~rst_ncu_xir_inv ; | |
3375 | assign xir_trigger = xir_trigger_next & ~xir_trigger_q; // detect xir_trigger rising edge since rst_xir is no | |
3376 | // longer 1-pulse signal | |
3377 | ||
3378 | assign xir_steering_ff_in[63:0] = ~xir_steering_next[63:0]; | |
3379 | ncu_ctrl_ctl_msff_ctl_macro__width_64 xir_steering_ff | |
3380 | ( | |
3381 | .scan_in(xir_steering_ff_scanin), | |
3382 | .scan_out(xir_steering_ff_scanout), | |
3383 | .dout (xir_steering_ff_out[63:0]), | |
3384 | .l1clk (l1clk), | |
3385 | .din (xir_steering_ff_in[63:0]), | |
3386 | .siclk(siclk), | |
3387 | .soclk(soclk) | |
3388 | ); | |
3389 | assign xir_steering[63:0] = ~xir_steering_ff_out[63:0]; | |
3390 | ||
3391 | ncu_ctrl_ctl_msff_ctl_macro__width_1 xir_trigger_ff | |
3392 | ( | |
3393 | .scan_in(xir_trigger_ff_scanin), | |
3394 | .scan_out(xir_trigger_ff_scanout), | |
3395 | .dout (xir_trigger_q), | |
3396 | .l1clk (l1clk), | |
3397 | .din (xir_trigger_next), | |
3398 | .siclk(siclk), | |
3399 | .soclk(soclk) | |
3400 | ); | |
3401 | ||
3402 | ncu_ctrl_ctl_msff_ctl_macro__width_1 xir_trigger_d0_ff | |
3403 | ( | |
3404 | .scan_in(xir_trigger_d0_ff_scanin), | |
3405 | .scan_out(xir_trigger_d0_ff_scanout), | |
3406 | .dout (xir_trigger_d0), | |
3407 | .l1clk (l1clk), | |
3408 | .din (xir_trigger_d0_next), | |
3409 | .siclk(siclk), | |
3410 | .soclk(soclk) | |
3411 | ); | |
3412 | ||
3413 | ncu_ctrl_ctl_msff_ctl_macro__width_1 xir_trigger_d1_ff | |
3414 | ( | |
3415 | .scan_in(xir_trigger_d1_ff_scanin), | |
3416 | .scan_out(xir_trigger_d1_ff_scanout), | |
3417 | .dout (xir_trigger_d1), | |
3418 | .l1clk (l1clk), | |
3419 | .din (xir_trigger_d0), | |
3420 | .siclk(siclk), | |
3421 | .soclk(soclk) | |
3422 | ); | |
3423 | ||
3424 | ncu_ctrl_ctl_msff_ctl_macro__width_56 xir_snapd_vec_ff | |
3425 | ( | |
3426 | .scan_in(xir_snapd_vec_ff_scanin), | |
3427 | .scan_out(xir_snapd_vec_ff_scanout), | |
3428 | .dout (xir_snapd_vec[55:0]), | |
3429 | .l1clk (l1clk), | |
3430 | .din (xir_snapd_vec_next[55:0]), | |
3431 | .siclk(siclk), | |
3432 | .soclk(soclk) | |
3433 | ); | |
3434 | ||
3435 | ncu_ctrl_ctl_msff_ctl_macro__width_8 xir_mini_vec_ff | |
3436 | ( | |
3437 | .scan_in(xir_mini_vec_ff_scanin), | |
3438 | .scan_out(xir_mini_vec_ff_scanout), | |
3439 | .dout (xir_mini_vec[7:0]), | |
3440 | .l1clk (l1clk), | |
3441 | .din (xir_mini_vec_next[7:0]), | |
3442 | .siclk(siclk), | |
3443 | .soclk(soclk) | |
3444 | ); | |
3445 | ||
3446 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_3 xir_cpuid_ff | |
3447 | ( | |
3448 | .scan_in(xir_cpuid_ff_scanin), | |
3449 | .scan_out(xir_cpuid_ff_scanout), | |
3450 | .dout (xir_cpuid[2:0]), | |
3451 | .l1clk (l1clk), | |
3452 | .en (xir_cpuid_inc), | |
3453 | .din (xir_cpuid_next[2:0]), | |
3454 | .siclk(siclk), | |
3455 | .soclk(soclk) | |
3456 | ); | |
3457 | ||
3458 | ncu_ctrl_ctl_msff_ctl_macro__width_1 xir_busy_ff | |
3459 | ( | |
3460 | .scan_in(xir_busy_ff_scanin), | |
3461 | .scan_out(xir_busy_ff_scanout), | |
3462 | .dout (xir_busy), | |
3463 | .l1clk (l1clk), | |
3464 | .din (xir_busy_next), | |
3465 | .siclk(siclk), | |
3466 | .soclk(soclk) | |
3467 | ); | |
3468 | ||
3469 | ncu_ctrl_ctl_msff_ctl_macro__width_1 xir_busy_d1_ff | |
3470 | ( | |
3471 | .scan_in(xir_busy_d1_ff_scanin), | |
3472 | .scan_out(xir_busy_d1_ff_scanout), | |
3473 | .dout (xir_busy_d1), | |
3474 | .l1clk (l1clk), | |
3475 | .din (xir_busy), | |
3476 | .siclk(siclk), | |
3477 | .soclk(soclk) | |
3478 | ); | |
3479 | ||
3480 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_rst_xir_done_ff | |
3481 | ( | |
3482 | .scan_in(ncu_rst_xir_done_ff_scanin), | |
3483 | .scan_out(ncu_rst_xir_done_ff_scanout), | |
3484 | .dout (ncu_rst_xir_done), | |
3485 | .l1clk (l1clk), | |
3486 | .din (ncu_rst_xir_done_next), | |
3487 | .siclk(siclk), | |
3488 | .soclk(soclk) | |
3489 | ); | |
3490 | ||
3491 | ||
3492 | always@(xir_mini_vec ) begin | |
3493 | casex(xir_mini_vec[7:0]) // 0in case -parallel -full | |
3494 | 8'bxxxx_xxx1 : begin | |
3495 | xir_srvcd_mini_vec[7:0] = 8'b1111_1110 & xir_mini_vec[7:0] ; | |
3496 | xir_mini_thr[2:0] = 3'd0 ; | |
3497 | xir_mini_vec_vld = 1'b1; | |
3498 | end | |
3499 | 8'bxxxx_xx10 : begin | |
3500 | xir_srvcd_mini_vec[7:0] = 8'b1111_1101 & xir_mini_vec[7:0] ; | |
3501 | xir_mini_thr[2:0] = 3'd1 ; | |
3502 | xir_mini_vec_vld = 1'b1; | |
3503 | end | |
3504 | 8'bxxxx_x100 : begin | |
3505 | xir_srvcd_mini_vec[7:0] = 8'b1111_1011 & xir_mini_vec[7:0] ; | |
3506 | xir_mini_thr[2:0] = 3'd2 ; | |
3507 | xir_mini_vec_vld = 1'b1; | |
3508 | end | |
3509 | 8'bxxxx_1000 : begin | |
3510 | xir_srvcd_mini_vec[7:0] = 8'b1111_0111 & xir_mini_vec[7:0] ; | |
3511 | xir_mini_thr[2:0] = 3'd3 ; | |
3512 | xir_mini_vec_vld = 1'b1; | |
3513 | end | |
3514 | 8'bxxx1_0000 : begin | |
3515 | xir_srvcd_mini_vec[7:0] = 8'b1110_1111 & xir_mini_vec[7:0] ; | |
3516 | xir_mini_thr[2:0] = 3'd4 ; | |
3517 | xir_mini_vec_vld = 1'b1; | |
3518 | end | |
3519 | 8'bxx10_0000 : begin | |
3520 | xir_srvcd_mini_vec[7:0] = 8'b1101_1111 & xir_mini_vec[7:0] ; | |
3521 | xir_mini_thr[2:0] = 3'd5 ; | |
3522 | xir_mini_vec_vld = 1'b1; | |
3523 | end | |
3524 | 8'bx100_0000 : begin | |
3525 | xir_srvcd_mini_vec[7:0] = 8'b1011_1111 & xir_mini_vec[7:0] ; | |
3526 | xir_mini_thr[2:0] = 3'd6 ; | |
3527 | xir_mini_vec_vld = 1'b1; | |
3528 | end | |
3529 | 8'b1000_0000 : begin | |
3530 | xir_srvcd_mini_vec[7:0] = 8'b0111_1111 & xir_mini_vec[7:0] ; | |
3531 | xir_mini_thr[2:0] = 3'd7 ; | |
3532 | xir_mini_vec_vld = 1'b1; | |
3533 | end | |
3534 | default : begin //all 0s// | |
3535 | xir_srvcd_mini_vec[7:0] = xir_mini_vec[7:0] ; | |
3536 | xir_mini_thr[2:0] = 3'd0 ; | |
3537 | xir_mini_vec_vld = 1'b0; | |
3538 | end | |
3539 | endcase | |
3540 | end | |
3541 | ||
3542 | /* | |
3543 | assign xir_int_pkt[24:0] = { ////7'b0, //reserved | |
3544 | 6'b00_0011, //XIR int vector //[24:19] | |
3545 | ////32'b0, //reserved | |
3546 | 3'b0, //dummy dev_id | |
3547 | `UCB_RESET_VEC , // interrupt type is reset | |
3548 | 2'b00, | |
3549 | xir_cpuid[2:0],xir_mini_thr[2:0], | |
3550 | `UCB_INT_VEC } ; | |
3551 | */ | |
3552 | ||
3553 | assign xir_int_pkt[24:0] = { ////7'b0, //reserved | |
3554 | 6'b00_0011, //XIR int vector | |
3555 | ////32'b0, //reserved | |
3556 | 9'b0, //dummy dev_id | |
3557 | xir_cpuid[2:0],xir_mini_thr[2:0], | |
3558 | `UCB_RESET_VEC } ; | |
3559 | ||
3560 | ||
3561 | ||
3562 | /************************** | |
3563 | ***** core_running ***** | |
3564 | **************************/ | |
3565 | // when wake_thread, take default value from core_enable_status (which is from core_enable // | |
3566 | // when got out of wmr). core_enable is already senitized by coreavail, so no need to check against coreavail. | |
3567 | // Check against core_enable_staus when asi_wr. | |
3568 | // If write from TCU is all 0, take lowest thread from core_enable_status | |
3569 | // If write from CPU is all 0, keep requester's thread alive // | |
3570 | ||
3571 | always@(core_enable_status) begin | |
3572 | casex(core_enable_status[6:0]) // 0in case -parallel -full | |
3573 | 7'bxxx_xxx1 : enable_status_lowest_1hot[7:0] = 8'b0000_0001 ; | |
3574 | 7'bxxx_xx10 : enable_status_lowest_1hot[7:0] = 8'b0000_0010 ; | |
3575 | 7'bxxx_x100 : enable_status_lowest_1hot[7:0] = 8'b0000_0100 ; | |
3576 | 7'bxxx_1000 : enable_status_lowest_1hot[7:0] = 8'b0000_1000 ; | |
3577 | 7'bxx1_0000 : enable_status_lowest_1hot[7:0] = 8'b0001_0000 ; | |
3578 | 7'bx10_0000 : enable_status_lowest_1hot[7:0] = 8'b0010_0000 ; | |
3579 | 7'b100_0000 : enable_status_lowest_1hot[7:0] = 8'b0100_0000 ; | |
3580 | default : enable_status_lowest_1hot[7:0] = 8'b1000_0000 ; | |
3581 | endcase | |
3582 | end | |
3583 | ||
3584 | assign enable_status_lowest_thr_1hot[63:0] = { 7'b0,enable_status_lowest_1hot[7], | |
3585 | 7'b0,enable_status_lowest_1hot[6], | |
3586 | 7'b0,enable_status_lowest_1hot[5], | |
3587 | 7'b0,enable_status_lowest_1hot[4], | |
3588 | 7'b0,enable_status_lowest_1hot[3], | |
3589 | 7'b0,enable_status_lowest_1hot[2], | |
3590 | 7'b0,enable_status_lowest_1hot[1], | |
3591 | 7'b0,enable_status_lowest_1hot[0] } ; | |
3592 | ||
3593 | //assign core_running_illegal_thr_acc = ~|((64'h0000_0000_0000_0001 << ncu_man_ucb_c2i_packet_cputhr[5:0])& | |
3594 | //core_enable_status64[63:0] ) ; | |
3595 | //assign core_running_a0_default[63:0] = (ncu_man_ucb_c2i_packet_buf_id[0]|core_running_illegal_thr_acc) ? | |
3596 | //assign core_running_a0_default[63:0] = (ncu_man_ucb_c2i_packet_buf_id[0]) ? | |
3597 | // enable_status_lowest_thr_1hot[63:0] : | |
3598 | // 64'h0000_0000_0000_0001 << ncu_man_ucb_c2i_packet_cputhr[5:0] ; | |
3599 | assign core_running_a0_default[63:0] = (ncu_man_ucb_c2i_packet_buf_id[0]) ? 64'h00000000 : | |
3600 | 64'h0000_0000_0000_0001 << ncu_man_ucb_c2i_packet_cputhr[5:0] ; | |
3601 | // when buf_id[1:0] = "01" request is from TCU. TCU request is for | |
3602 | // dg1 only. We can load all "0" to park all thread during debug. | |
3603 | ||
3604 | assign c2i_w1cdata_by_core_running[63:0] = (~ncu_man_ucb_c2i_packet_data[63:0]&core_running[63:0]) ; | |
3605 | ||
3606 | ||
3607 | // filtered by core_enable_status[63:0], and then check if core_running is going to be all 0 // | |
3608 | assign c2i_core_running_a0 = ~(|c2i_data_by_core_enable_status[63:0]); | |
3609 | ||
3610 | assign c2i_core_runningw1c_a0 = ~(|c2i_w1cdata_by_core_running[63:0]); | |
3611 | ||
3612 | // check if resulting all 0. If it is, use a0 default which also check for illegel thr acc // | |
3613 | assign core_runningrw_data[63:0] = c2i_core_running_a0 ? | |
3614 | core_running_a0_default[63:0] : c2i_data_by_core_enable_status[63:0]; | |
3615 | ||
3616 | assign core_runningw1c_data[63:0] = c2i_core_runningw1c_a0 ? | |
3617 | core_running_a0_default[63:0] : c2i_w1cdata_by_core_running[63:0]; | |
3618 | ||
3619 | assign asi_core_running_wr = ncu_man_ucb_buf_acpt_d2 & asi_core_running_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
3620 | assign asi_core_runningw1s_wr = ncu_man_ucb_buf_acpt_d2 & asi_core_runningw1s_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
3621 | assign asi_core_runningw1c_wr = ncu_man_ucb_buf_acpt_d2 & asi_core_runningw1c_dec & ncu_man_ucb_c2i_packet_is_wr_req; | |
3622 | ||
3623 | assign core_running_next[63:0] = wake_thread ? enable_status_lowest_thr_1hot[63:0] : | |
3624 | asi_core_runningw1s_wr ? (c2i_data_by_core_enable_status[63:0]|core_running[63:0]) : | |
3625 | asi_core_running_wr ? core_runningrw_data[63:0] : | |
3626 | asi_core_runningw1c_wr ? core_runningw1c_data[63:0] : core_running[63:0] ; | |
3627 | ||
3628 | ncu_ctrl_ctl_msff_ctl_macro__width_63 core_running_ff | |
3629 | ( | |
3630 | .scan_in(core_running_ff_scanin), | |
3631 | .scan_out(core_running_ff_scanout), | |
3632 | .dout (core_running[63:1]), | |
3633 | .l1clk (l1clk), | |
3634 | .din (core_running_next[63:1]), | |
3635 | .siclk(siclk), | |
3636 | .soclk(soclk) | |
3637 | ); | |
3638 | ||
3639 | assign core_running_ff_in = core_running_next[0]; | |
3640 | ncu_ctrl_ctl_msff_ctl_macro__width_1 core_running0_ff | |
3641 | ( | |
3642 | .scan_in(core_running0_ff_scanin), | |
3643 | .scan_out(core_running0_ff_scanout), | |
3644 | .dout (core_running_ff_out), | |
3645 | .l1clk (l1clk), | |
3646 | .din (core_running_ff_in), | |
3647 | .siclk(siclk), | |
3648 | .soclk(soclk) | |
3649 | ); | |
3650 | assign core_running[0] = core_running_ff_out; | |
3651 | ||
3652 | //// need to make sure only allowing 1 wake thread per warm reset //// | |
3653 | ncu_ctrl_ctl_msff_ctl_macro__width_1 unpark_thread_d1_ff | |
3654 | ( | |
3655 | .scan_in(unpark_thread_d1_ff_scanin), | |
3656 | .scan_out(unpark_thread_d1_ff_scanout), | |
3657 | .dout (unpark_thread_d1), | |
3658 | .l1clk (l1clk), | |
3659 | .din (rst_ncu_unpark_thread), | |
3660 | .siclk(siclk), | |
3661 | .soclk(soclk) | |
3662 | ); | |
3663 | ncu_ctrl_ctl_msff_ctl_macro__width_1 unpark_thread_d2_ff | |
3664 | ( | |
3665 | .scan_in(unpark_thread_d2_ff_scanin), | |
3666 | .scan_out(unpark_thread_d2_ff_scanout), | |
3667 | .dout (unpark_thread_d2), | |
3668 | .l1clk (l1clk), | |
3669 | .din (unpark_thread_d1), | |
3670 | .siclk(siclk), | |
3671 | .soclk(soclk) | |
3672 | ); | |
3673 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 wake_ok__ff | |
3674 | ( | |
3675 | .scan_in(wake_ok__ff_scanin), | |
3676 | .scan_out(wake_ok__ff_scanout), | |
3677 | .dout (wake_ok_inv), | |
3678 | .l1clk (l1clk), | |
3679 | .en (unpark_thread_d1), | |
3680 | .din (1'b1), | |
3681 | .siclk(siclk), | |
3682 | .soclk(soclk) | |
3683 | ); | |
3684 | ||
3685 | assign wake_thread_n = unpark_thread_d1 & ~unpark_thread_d2 & ~wake_ok_inv ; | |
3686 | ||
3687 | ncu_ctrl_ctl_msff_ctl_macro__width_1 wake_thread_ff | |
3688 | ( | |
3689 | .scan_in(wake_thread_ff_scanin), | |
3690 | .scan_out(wake_thread_ff_scanout), | |
3691 | .dout (wake_thread), | |
3692 | .l1clk (l1clk), | |
3693 | .din (wake_thread_n), | |
3694 | .siclk(siclk), | |
3695 | .soclk(soclk) | |
3696 | ); | |
3697 | ||
3698 | ||
3699 | ||
3700 | /********************************* | |
3701 | ***** core_running_status ***** | |
3702 | *********************************/ | |
3703 | ||
3704 | ncu_ctrl_ctl_msff_ctl_macro__width_63 core_running_status_ff | |
3705 | ( | |
3706 | .scan_in(core_running_status_ff_scanin), | |
3707 | .scan_out(core_running_status_ff_scanout), | |
3708 | .dout (creg_core_running_status[63:1]), | |
3709 | .l1clk (l1clk), | |
3710 | .din (core_running_status[63:1]), | |
3711 | .siclk(siclk), | |
3712 | .soclk(soclk) | |
3713 | ); | |
3714 | ||
3715 | assign core_running_status_ff_in = ~core_running_status[0]; | |
3716 | ncu_ctrl_ctl_msff_ctl_macro__width_1 core_running_status0_ff | |
3717 | ( | |
3718 | .scan_in(core_running_status0_ff_scanin), | |
3719 | .scan_out(core_running_status0_ff_scanout), | |
3720 | .dout (core_running_status_ff_out), | |
3721 | .l1clk (l1clk), | |
3722 | .din (core_running_status_ff_in), | |
3723 | .siclk(siclk), | |
3724 | .soclk(soclk) | |
3725 | ); | |
3726 | assign creg_core_running_status[0] = ~core_running_status_ff_out; | |
3727 | ||
3728 | ||
3729 | ||
3730 | ||
3731 | ||
3732 | /********************************* | |
3733 | ***** l2_bank_enable ***** | |
3734 | *********************************/ | |
3735 | reg [7:0] bankavail_lowest_pair; | |
3736 | ||
3737 | assign bankavail_pair[3:0] = {&bankavail[7:6],&bankavail[5:4],&bankavail[3:2],&bankavail[1:0]}; | |
3738 | always@( bankavail_pair ) begin | |
3739 | casex(bankavail_pair[3:0]) | |
3740 | 4'bxxx1 : bankavail_lowest_pair[7:0] = 8'b00_00_00_11; | |
3741 | 4'bxx10 : bankavail_lowest_pair[7:0] = 8'b00_00_11_00; | |
3742 | 4'bx100 : bankavail_lowest_pair[7:0] = 8'b00_11_00_00; | |
3743 | 4'b1000 : bankavail_lowest_pair[7:0] = 8'b11_00_00_00; | |
3744 | default : bankavail_lowest_pair[7:0] = 8'b00_00_00_00; | |
3745 | endcase | |
3746 | end | |
3747 | ||
3748 | assign bank_en_wr = ncu_man_ucb_buf_acpt_d2 & creg_bank_en_dec & ncu_man_ucb_c2i_packet_is_wr_req ; | |
3749 | ||
3750 | assign c2i_bank_en[7:0] = ncu_man_ucb_c2i_packet_data[7:0] & bankavail[7:0] ; | |
3751 | assign c2i_bank_en_a0 = ~(|c2i_bank_en[7:0]) ; | |
3752 | assign bank_en_next[7:0] = bankavail_done ? bankavail[7:0] : //update from bankavail after wmr | |
3753 | ~bank_en_wr ? bank_en[7:0] : //lock here when no write// | |
3754 | c2i_bank_en_a0 ? bankavail_lowest_pair[7:0] : c2i_bank_en[7:0] ; | |
3755 | ||
3756 | assign bank_en_ff_in[7:0] = ~bank_en_next[7:0]; | |
3757 | ncu_ctrl_ctl_msff_ctl_macro__width_8 bank_en_ff | |
3758 | ( | |
3759 | .scan_in(bank_en_ff_scanin), | |
3760 | .scan_out(bank_en_ff_scanout), | |
3761 | .dout (bank_en_ff_out[7:0]), | |
3762 | .l1clk (l1clk), | |
3763 | .siclk (aclk_wmr), | |
3764 | .din (bank_en_ff_in[7:0]), | |
3765 | .soclk(soclk) | |
3766 | ); | |
3767 | assign bank_en[7:0] = ~bank_en_ff_out[7:0]; | |
3768 | ||
3769 | assign creg_bank_en[63:0] = { 56'b0,bank_en[7:0] } ; | |
3770 | ||
3771 | ||
3772 | ||
3773 | /************************************ | |
3774 | ***** l2_bank_enable_status ***** | |
3775 | ************************************/ | |
3776 | ||
3777 | ||
3778 | assign l2pm_en = bankavail_done | wmr_upd_en | por_upd_en; | |
3779 | assign bank_en_full_status[7:0] = bankavail_done ? bankavail[7:0] : bank_en[7:0] ; | |
3780 | assign bank_en_pair_status[3:0] = { &bank_en_full_status[7:6], &bank_en_full_status[5:4], | |
3781 | &bank_en_full_status[3:2], &bank_en_full_status[1:0] } ; | |
3782 | ||
3783 | assign bank_en_final_status[3:0] = | |
3784 | ((^bank_en_pair_status[3:2])&(&bank_en_pair_status[1:0])) ? 4'b0011 : | |
3785 | ((&bank_en_pair_status[3:2])&(^bank_en_pair_status[1:0])) ? 4'b1100 : | |
3786 | bank_en_pair_status[3:0] ; | |
3787 | ||
3788 | assign bank_en_final_status[4] = ~&bank_en_final_status[3:0] ; | |
3789 | assign l2pm_preview_ff_din[4:0] = {~bank_en_final_status[4],bank_en_final_status[3:0]}; | |
3790 | //assign l2pm_ff_din[4:0] = {~bank_en_final_status[4],bank_en_final_status[3:0]} ; | |
3791 | assign l2pm_ff_din[4:0] = {bank_en_final_status[4],bank_en_final_status[3:0]} ; | |
3792 | ||
3793 | ncu_ctrl_ctl_msff_ctl_macro__width_5 l2pm_preview_ff | |
3794 | ( | |
3795 | .scan_in(l2pm_preview_ff_scanin), | |
3796 | .scan_out(l2pm_preview_ff_scanout), | |
3797 | .dout (l2pm_preview_ff_q[4:0]), | |
3798 | .l1clk (l1clk), | |
3799 | .din (l2pm_preview_ff_din[4:0]), | |
3800 | .siclk(siclk), | |
3801 | .soclk(soclk) | |
3802 | ); | |
3803 | ||
3804 | assign l2pm_preview[4:0] = {~l2pm_preview_ff_q[4],l2pm_preview_ff_q[3:0]}; | |
3805 | ||
3806 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_5 l2pm_ff | |
3807 | ( | |
3808 | .scan_in(l2pm_ff_scanin), | |
3809 | .scan_out(l2pm_ff_scanout), | |
3810 | .dout ({ncu_spc_pm,l2pm_ff_q[3:1],ncu_spc_ba01}), | |
3811 | .l1clk (l1clk), | |
3812 | .en (l2pm_en), | |
3813 | .din (l2pm_ff_din[4:0]), | |
3814 | .siclk(siclk), | |
3815 | .soclk(soclk) | |
3816 | ); | |
3817 | ||
3818 | assign l2pm[4:0] = {ncu_spc_pm,l2pm_ff_q[3:1],ncu_spc_ba01}; | |
3819 | //assign l2pm[4:0] = {~l2pm_ff_q[4],l2pm_ff_q[3:0]}; | |
3820 | assign creg_bank_en_status[63:0] = {48'b0,3'b0,l2pm_preview[4:0],3'b0,l2pm[4:0]} ; | |
3821 | ||
3822 | //assign ncu_tcu_bank_en_status[3:0] = creg_bank_en_status[3:0]; | |
3823 | ||
3824 | ||
3825 | /****************************** | |
3826 | *** L2 Index Hash Enable *** | |
3827 | ******************************/ | |
3828 | ||
3829 | assign l2idxhs_en_wr = ncu_man_ucb_buf_acpt_d2 & creg_l2idxhs_en_dec & ncu_man_ucb_c2i_packet_is_wr_req ; | |
3830 | ||
3831 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 l2idxhs_en_ff | |
3832 | ( | |
3833 | .scan_in(l2idxhs_en_ff_scanin), | |
3834 | .scan_out(l2idxhs_en_ff_scanout), | |
3835 | .dout (l2idxhs_en), | |
3836 | .l1clk (l1clk), | |
3837 | .siclk (aclk_wmr), | |
3838 | .en (l2idxhs_en_wr), | |
3839 | .din (ncu_man_ucb_c2i_packet_data[0]), | |
3840 | .soclk(soclk) | |
3841 | ); | |
3842 | ||
3843 | assign creg_l2idxhs_en[63:0] = {63'b0,l2idxhs_en}; | |
3844 | ||
3845 | /*********************************** | |
3846 | *** L2 Index Hash Enable Status *** | |
3847 | ***********************************/ | |
3848 | ||
3849 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 l2idxhs_en_status_ff | |
3850 | ( | |
3851 | .scan_in(l2idxhs_en_status_ff_scanin), | |
3852 | .scan_out(l2idxhs_en_status_ff_scanout), | |
3853 | .dout (l2idxhs_en_status), | |
3854 | .l1clk (l1clk), | |
3855 | .en (wmr_upd_en), | |
3856 | .din (l2idxhs_en), | |
3857 | .siclk(siclk), | |
3858 | .soclk(soclk) | |
3859 | ); | |
3860 | ||
3861 | assign creg_l2idxhs_en_status[63:0] = {63'b0,l2idxhs_en_status} ; | |
3862 | ||
3863 | ||
3864 | ||
3865 | ////////////////////// | |
3866 | //// ESR register //// | |
3867 | ////////////////////// | |
3868 | ||
3869 | assign creg_esr_wr = ncu_man_ucb_buf_acpt_d2 & | |
3870 | ncu_man_ucb_c2i_packet_is_wr_req & creg_esr_dec; | |
3871 | ||
3872 | ncu_ctrl_ctl_msff_ctl_macro__width_1 iobuf_ue_ff | |
3873 | ( | |
3874 | .scan_in(iobuf_ue_ff_scanin), | |
3875 | .scan_out(iobuf_ue_ff_scanout), | |
3876 | .dout (iobuf_ue), | |
3877 | .l1clk (l1clk), | |
3878 | .din (iobuf_ue_f), | |
3879 | .siclk(siclk), | |
3880 | .soclk(soclk) | |
3881 | ); | |
3882 | ||
3883 | ncu_ctrl_ctl_msff_ctl_macro__width_1 intbuf_ue_ff | |
3884 | ( | |
3885 | .scan_in(intbuf_ue_ff_scanin), | |
3886 | .scan_out(intbuf_ue_ff_scanout), | |
3887 | .dout (intbuf_ue), | |
3888 | .l1clk (l1clk), | |
3889 | .din (intbuf_ue_f), | |
3890 | .siclk(siclk), | |
3891 | .soclk(soclk) | |
3892 | ); | |
3893 | ||
3894 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mondotbl_pe_ff | |
3895 | ( | |
3896 | .scan_in(mondotbl_pe_ff_scanin), | |
3897 | .scan_out(mondotbl_pe_ff_scanout), | |
3898 | .dout (mondotbl_pe), | |
3899 | .l1clk (l1clk), | |
3900 | .din (mondotbl_pe_f), | |
3901 | .siclk(siclk), | |
3902 | .soclk(soclk) | |
3903 | ); | |
3904 | ||
3905 | ||
3906 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu3_ncu_ecc_d_ff | |
3907 | ( | |
3908 | .scan_in(mcu3_ncu_ecc_d_ff_scanin), | |
3909 | .scan_out(mcu3_ncu_ecc_d_ff_scanout), | |
3910 | .dout (mcu3_ncu_ecc_d), | |
3911 | .l1clk (l1clk), | |
3912 | .din (mcu3_ncu_ecc), | |
3913 | .siclk(siclk), | |
3914 | .soclk(soclk) | |
3915 | ); | |
3916 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu3_ncu_fbr_d_ff | |
3917 | ( | |
3918 | .scan_in(mcu3_ncu_fbr_d_ff_scanin), | |
3919 | .scan_out(mcu3_ncu_fbr_d_ff_scanout), | |
3920 | .dout (mcu3_ncu_fbr_d), | |
3921 | .l1clk (l1clk), | |
3922 | .din (mcu3_ncu_fbr), | |
3923 | .siclk(siclk), | |
3924 | .soclk(soclk) | |
3925 | ); | |
3926 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu3_ncu_fbu_d_ff | |
3927 | ( | |
3928 | .scan_in(mcu3_ncu_fbu_d_ff_scanin), | |
3929 | .scan_out(mcu3_ncu_fbu_d_ff_scanout), | |
3930 | .dout (mcu3_ncu_fbu_d), | |
3931 | .l1clk (l1clk), | |
3932 | .din (mcu3_ncu_fbu), | |
3933 | .siclk(siclk), | |
3934 | .soclk(soclk) | |
3935 | ); | |
3936 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu2_ncu_ecc_d_ff | |
3937 | ( | |
3938 | .scan_in(mcu2_ncu_ecc_d_ff_scanin), | |
3939 | .scan_out(mcu2_ncu_ecc_d_ff_scanout), | |
3940 | .dout (mcu2_ncu_ecc_d), | |
3941 | .l1clk (l1clk), | |
3942 | .din (mcu2_ncu_ecc), | |
3943 | .siclk(siclk), | |
3944 | .soclk(soclk) | |
3945 | ); | |
3946 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu2_ncu_fbr_d_ff | |
3947 | ( | |
3948 | .scan_in(mcu2_ncu_fbr_d_ff_scanin), | |
3949 | .scan_out(mcu2_ncu_fbr_d_ff_scanout), | |
3950 | .dout (mcu2_ncu_fbr_d), | |
3951 | .l1clk (l1clk), | |
3952 | .din (mcu2_ncu_fbr), | |
3953 | .siclk(siclk), | |
3954 | .soclk(soclk) | |
3955 | ); | |
3956 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu2_ncu_fbu_d_ff | |
3957 | ( | |
3958 | .scan_in(mcu2_ncu_fbu_d_ff_scanin), | |
3959 | .scan_out(mcu2_ncu_fbu_d_ff_scanout), | |
3960 | .dout (mcu2_ncu_fbu_d), | |
3961 | .l1clk (l1clk), | |
3962 | .din (mcu2_ncu_fbu), | |
3963 | .siclk(siclk), | |
3964 | .soclk(soclk) | |
3965 | ); | |
3966 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu1_ncu_ecc_d_ff | |
3967 | ( | |
3968 | .scan_in(mcu1_ncu_ecc_d_ff_scanin), | |
3969 | .scan_out(mcu1_ncu_ecc_d_ff_scanout), | |
3970 | .dout (mcu1_ncu_ecc_d), | |
3971 | .l1clk (l1clk), | |
3972 | .din (mcu1_ncu_ecc), | |
3973 | .siclk(siclk), | |
3974 | .soclk(soclk) | |
3975 | ); | |
3976 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu1_ncu_fbr_d_ff | |
3977 | ( | |
3978 | .scan_in(mcu1_ncu_fbr_d_ff_scanin), | |
3979 | .scan_out(mcu1_ncu_fbr_d_ff_scanout), | |
3980 | .dout (mcu1_ncu_fbr_d), | |
3981 | .l1clk (l1clk), | |
3982 | .din (mcu1_ncu_fbr), | |
3983 | .siclk(siclk), | |
3984 | .soclk(soclk) | |
3985 | ); | |
3986 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu1_ncu_fbu_d_ff | |
3987 | ( | |
3988 | .scan_in(mcu1_ncu_fbu_d_ff_scanin), | |
3989 | .scan_out(mcu1_ncu_fbu_d_ff_scanout), | |
3990 | .dout (mcu1_ncu_fbu_d), | |
3991 | .l1clk (l1clk), | |
3992 | .din (mcu1_ncu_fbu), | |
3993 | .siclk(siclk), | |
3994 | .soclk(soclk) | |
3995 | ); | |
3996 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu0_ncu_ecc_d_ff | |
3997 | ( | |
3998 | .scan_in(mcu0_ncu_ecc_d_ff_scanin), | |
3999 | .scan_out(mcu0_ncu_ecc_d_ff_scanout), | |
4000 | .dout (mcu0_ncu_ecc_d), | |
4001 | .l1clk (l1clk), | |
4002 | .din (mcu0_ncu_ecc), | |
4003 | .siclk(siclk), | |
4004 | .soclk(soclk) | |
4005 | ); | |
4006 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu0_ncu_fbr_d_ff | |
4007 | ( | |
4008 | .scan_in(mcu0_ncu_fbr_d_ff_scanin), | |
4009 | .scan_out(mcu0_ncu_fbr_d_ff_scanout), | |
4010 | .dout (mcu0_ncu_fbr_d), | |
4011 | .l1clk (l1clk), | |
4012 | .din (mcu0_ncu_fbr), | |
4013 | .siclk(siclk), | |
4014 | .soclk(soclk) | |
4015 | ); | |
4016 | ncu_ctrl_ctl_msff_ctl_macro__width_1 mcu0_ncu_fbu_d_ff | |
4017 | ( | |
4018 | .scan_in(mcu0_ncu_fbu_d_ff_scanin), | |
4019 | .scan_out(mcu0_ncu_fbu_d_ff_scanout), | |
4020 | .dout (mcu0_ncu_fbu_d), | |
4021 | .l1clk (l1clk), | |
4022 | .din (mcu0_ncu_fbu), | |
4023 | .siclk(siclk), | |
4024 | .soclk(soclk) | |
4025 | ); | |
4026 | ||
4027 | ncu_ctrl_ctl_msff_ctl_macro__width_1 niu_ncu_d_pe_d_ff | |
4028 | ( | |
4029 | .scan_in(niu_ncu_d_pe_d_ff_scanin), | |
4030 | .scan_out(niu_ncu_d_pe_d_ff_scanout), | |
4031 | .dout (niu_ncu_d_pe_d), | |
4032 | .l1clk (l1clk), | |
4033 | .din (niu_ncu_d_pe), | |
4034 | .siclk(siclk), | |
4035 | .soclk(soclk) | |
4036 | ); | |
4037 | ncu_ctrl_ctl_msff_ctl_macro__width_1 niu_ncu_ctag_ue_d_ff | |
4038 | ( | |
4039 | .scan_in(niu_ncu_ctag_ue_d_ff_scanin), | |
4040 | .scan_out(niu_ncu_ctag_ue_d_ff_scanout), | |
4041 | .dout (niu_ncu_ctag_ue_d), | |
4042 | .l1clk (l1clk), | |
4043 | .din (niu_ncu_ctag_ue), | |
4044 | .siclk(siclk), | |
4045 | .soclk(soclk) | |
4046 | ); | |
4047 | ncu_ctrl_ctl_msff_ctl_macro__width_1 niu_ncu_ctag_ce_d_ff | |
4048 | ( | |
4049 | .scan_in(niu_ncu_ctag_ce_d_ff_scanin), | |
4050 | .scan_out(niu_ncu_ctag_ce_d_ff_scanout), | |
4051 | .dout (niu_ncu_ctag_ce_d), | |
4052 | .l1clk (l1clk), | |
4053 | .din (niu_ncu_ctag_ce), | |
4054 | .siclk(siclk), | |
4055 | .soclk(soclk) | |
4056 | ); | |
4057 | ||
4058 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sio_ncu_ctag_ce_d_ff | |
4059 | ( | |
4060 | .scan_in(sio_ncu_ctag_ce_d_ff_scanin), | |
4061 | .scan_out(sio_ncu_ctag_ce_d_ff_scanout), | |
4062 | .dout (sio_ncu_ctag_ce_d), | |
4063 | .l1clk (l1clk), | |
4064 | .din (sio_ncu_ctag_ce), | |
4065 | .siclk(siclk), | |
4066 | .soclk(soclk) | |
4067 | ); | |
4068 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sio_ncu_ctag_ue_d_ff | |
4069 | ( | |
4070 | .scan_in(sio_ncu_ctag_ue_d_ff_scanin), | |
4071 | .scan_out(sio_ncu_ctag_ue_d_ff_scanout), | |
4072 | .dout (sio_ncu_ctag_ue_d), | |
4073 | .l1clk (l1clk), | |
4074 | .din (sio_ncu_ctag_ue), | |
4075 | .siclk(siclk), | |
4076 | .soclk(soclk) | |
4077 | ); | |
4078 | ||
4079 | /* | |
4080 | msff_ctl_macro sio_ncu_d_pe_d_ff (width=1) | |
4081 | ( | |
4082 | .scan_in(sio_ncu_d_pe_d_ff_scanin), | |
4083 | .scan_out(sio_ncu_d_pe_d_ff_scanout), | |
4084 | .dout (sio_ncu_d_pe_d), | |
4085 | .l1clk (l1clk), | |
4086 | .din (sio_ncu_d_pe) | |
4087 | ); | |
4088 | */ | |
4089 | ||
4090 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_d_pe_d_ff | |
4091 | ( | |
4092 | .scan_in(dmu_ncu_d_pe_d_ff_scanin), | |
4093 | .scan_out(dmu_ncu_d_pe_d_ff_scanout), | |
4094 | .dout (dmu_ncu_d_pe_d), | |
4095 | .l1clk (l1clk), | |
4096 | .din (dmu_ncu_d_pe), | |
4097 | .siclk(siclk), | |
4098 | .soclk(soclk) | |
4099 | ); | |
4100 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_siicr_pe_d_ff | |
4101 | ( | |
4102 | .scan_in(dmu_ncu_siicr_pe_d_ff_scanin), | |
4103 | .scan_out(dmu_ncu_siicr_pe_d_ff_scanout), | |
4104 | .dout (dmu_ncu_siicr_pe_d), | |
4105 | .l1clk (l1clk), | |
4106 | .din (dmu_ncu_siicr_pe), | |
4107 | .siclk(siclk), | |
4108 | .soclk(soclk) | |
4109 | ); | |
4110 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_ctag_ue_d_ff | |
4111 | ( | |
4112 | .scan_in(dmu_ncu_ctag_ue_d_ff_scanin), | |
4113 | .scan_out(dmu_ncu_ctag_ue_d_ff_scanout), | |
4114 | .dout (dmu_ncu_ctag_ue_d), | |
4115 | .l1clk (l1clk), | |
4116 | .din (dmu_ncu_ctag_ue), | |
4117 | .siclk(siclk), | |
4118 | .soclk(soclk) | |
4119 | ); | |
4120 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_ctag_ce_d_ff | |
4121 | ( | |
4122 | .scan_in(dmu_ncu_ctag_ce_d_ff_scanin), | |
4123 | .scan_out(dmu_ncu_ctag_ce_d_ff_scanout), | |
4124 | .dout (dmu_ncu_ctag_ce_d), | |
4125 | .l1clk (l1clk), | |
4126 | .din (dmu_ncu_ctag_ce), | |
4127 | .siclk(siclk), | |
4128 | .soclk(soclk) | |
4129 | ); | |
4130 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_ncucr_pe_d_ff | |
4131 | ( | |
4132 | .scan_in(dmu_ncu_ncucr_pe_d_ff_scanin), | |
4133 | .scan_out(dmu_ncu_ncucr_pe_d_ff_scanout), | |
4134 | .dout (dmu_ncu_ncucr_pe_d), | |
4135 | .l1clk (l1clk), | |
4136 | .din (dmu_ncu_ncucr_pe), | |
4137 | .siclk(siclk), | |
4138 | .soclk(soclk) | |
4139 | ); | |
4140 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dmu_ncu_ie_d_ff | |
4141 | ( | |
4142 | .scan_in(dmu_ncu_ie_d_ff_scanin), | |
4143 | .scan_out(dmu_ncu_ie_d_ff_scanout), | |
4144 | .dout (dmu_ncu_ie_d), | |
4145 | .l1clk (l1clk), | |
4146 | .din (dmu_ncu_ie), | |
4147 | .siclk(siclk), | |
4148 | .soclk(soclk) | |
4149 | ); | |
4150 | ||
4151 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_dmua_pe_d_ff | |
4152 | ( | |
4153 | .scan_in(sii_ncu_dmua_pe_d_ff_scanin), | |
4154 | .scan_out(sii_ncu_dmua_pe_d_ff_scanout), | |
4155 | .dout (sii_ncu_dmua_pe_d), | |
4156 | .l1clk (l1clk), | |
4157 | .din (sii_ncu_dmua_pe ), | |
4158 | .siclk(siclk), | |
4159 | .soclk(soclk) | |
4160 | ); | |
4161 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_niud_pe_d_ff | |
4162 | ( | |
4163 | .scan_in(sii_ncu_niud_pe_d_ff_scanin), | |
4164 | .scan_out(sii_ncu_niud_pe_d_ff_scanout), | |
4165 | .dout (sii_ncu_niud_pe_d), | |
4166 | .l1clk (l1clk), | |
4167 | .din (sii_ncu_niud_pe ), | |
4168 | .siclk(siclk), | |
4169 | .soclk(soclk) | |
4170 | ); | |
4171 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_dmud_pe_d_ff | |
4172 | ( | |
4173 | .scan_in(sii_ncu_dmud_pe_d_ff_scanin), | |
4174 | .scan_out(sii_ncu_dmud_pe_d_ff_scanout), | |
4175 | .dout (sii_ncu_dmud_pe_d), | |
4176 | .l1clk (l1clk), | |
4177 | .din (sii_ncu_dmud_pe ), | |
4178 | .siclk(siclk), | |
4179 | .soclk(soclk) | |
4180 | ); | |
4181 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_niua_pe_d_ff | |
4182 | ( | |
4183 | .scan_in(sii_ncu_niua_pe_d_ff_scanin), | |
4184 | .scan_out(sii_ncu_niua_pe_d_ff_scanout), | |
4185 | .dout (sii_ncu_niua_pe_d), | |
4186 | .l1clk (l1clk), | |
4187 | .din (sii_ncu_niua_pe ), | |
4188 | .siclk(siclk), | |
4189 | .soclk(soclk) | |
4190 | ); | |
4191 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_dmuctag_ce_d_ff | |
4192 | ( | |
4193 | .scan_in(sii_ncu_dmuctag_ce_d_ff_scanin), | |
4194 | .scan_out(sii_ncu_dmuctag_ce_d_ff_scanout), | |
4195 | .dout (sii_ncu_dmuctag_ce_d), | |
4196 | .l1clk (l1clk), | |
4197 | .din (sii_ncu_dmuctag_ce ), | |
4198 | .siclk(siclk), | |
4199 | .soclk(soclk) | |
4200 | ); | |
4201 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_niuctag_ce_d_ff | |
4202 | ( | |
4203 | .scan_in(sii_ncu_niuctag_ce_d_ff_scanin), | |
4204 | .scan_out(sii_ncu_niuctag_ce_d_ff_scanout), | |
4205 | .dout (sii_ncu_niuctag_ce_d), | |
4206 | .l1clk (l1clk), | |
4207 | .din (sii_ncu_niuctag_ce ), | |
4208 | .siclk(siclk), | |
4209 | .soclk(soclk) | |
4210 | ); | |
4211 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_dmuctag_ue_d_ff | |
4212 | ( | |
4213 | .scan_in(sii_ncu_dmuctag_ue_d_ff_scanin), | |
4214 | .scan_out(sii_ncu_dmuctag_ue_d_ff_scanout), | |
4215 | .dout (sii_ncu_dmuctag_ue_d), | |
4216 | .l1clk (l1clk), | |
4217 | .din (sii_ncu_dmuctag_ue ), | |
4218 | .siclk(siclk), | |
4219 | .soclk(soclk) | |
4220 | ); | |
4221 | ncu_ctrl_ctl_msff_ctl_macro__width_1 sii_ncu_niuctag_ue_d_ff | |
4222 | ( | |
4223 | .scan_in(sii_ncu_niuctag_ue_d_ff_scanin), | |
4224 | .scan_out(sii_ncu_niuctag_ue_d_ff_scanout), | |
4225 | .dout (sii_ncu_niuctag_ue_d), | |
4226 | .l1clk (l1clk), | |
4227 | .din (sii_ncu_niuctag_ue ), | |
4228 | .siclk(siclk), | |
4229 | .soclk(soclk) | |
4230 | ); | |
4231 | ||
4232 | ||
4233 | ||
4234 | ||
4235 | assign raserr_in[42:0] = { | |
4236 | dmu_cr_id_rtn_err, //[42] | |
4237 | mcu3_ncu_ecc_d, //[41] | |
4238 | mcu3_ncu_fbr_d, //[40] | |
4239 | mcu3_ncu_fbu_d, //[39] | |
4240 | mcu2_ncu_ecc_d, //[38] | |
4241 | mcu2_ncu_fbr_d, //[37] | |
4242 | mcu2_ncu_fbu_d, //[36] | |
4243 | mcu1_ncu_ecc_d, //[35] | |
4244 | mcu1_ncu_fbr_d, //[34] | |
4245 | mcu1_ncu_fbu_d, //[33] | |
4246 | mcu0_ncu_ecc_d, //[32] | |
4247 | mcu0_ncu_fbr_d, //[31] | |
4248 | mcu0_ncu_fbu_d, //[30] | |
4249 | niu_ncu_d_pe_d, //[29] | |
4250 | niu_ncu_ctag_ue_d, //[28] | |
4251 | niu_ncu_ctag_ce_d, //[27] | |
4252 | sio_ncu_ctag_ce_d, //[26] | |
4253 | sio_ncu_ctag_ue_d, //[25] | |
4254 | 1'b0, | |
4255 | // sio_ncu_d_pe_d, //[24] | |
4256 | ncuctag_ce, //[23] | |
4257 | ncuctag_ue, //[22]* | |
4258 | dmubuf_pue, //[21]* | |
4259 | iobuf_ue, //[20] | |
4260 | cpubuf_ue, //[19]* | |
4261 | cpubuf_pe, //[18]* | |
4262 | intman_pe, //[17]* | |
4263 | intbuf_ue, //[16] | |
4264 | mondotbl_pe, //[15] | |
4265 | ncusiid_pe, //[14]* | |
4266 | dmu_ncu_d_pe_d, //[13] | |
4267 | dmu_ncu_siicr_pe_d, //[12] | |
4268 | dmu_ncu_ctag_ue_d, //[11] | |
4269 | dmu_ncu_ctag_ce_d, //[10] | |
4270 | dmu_ncu_ncucr_pe_d, //[9] | |
4271 | dmu_ncu_ie_d, //[8] | |
4272 | sii_ncu_dmua_pe_d, //[7] | |
4273 | sii_ncu_niud_pe_d, //[6] | |
4274 | sii_ncu_dmud_pe_d, //[5] | |
4275 | sii_ncu_niua_pe_d, //[4] | |
4276 | sii_ncu_dmuctag_ce_d, //[3] | |
4277 | sii_ncu_niuctag_ce_d, //[2] | |
4278 | sii_ncu_dmuctag_ue_d, //[1] | |
4279 | sii_ncu_niuctag_ue_d }; //[0] | |
4280 | ||
4281 | ||
4282 | //bit 30,33,36,39 is guarantee to be 0 already// | |
4283 | assign rasesr_in[42:0] = rasele[42:0] & raserr_in[42:0] ; | |
4284 | ||
4285 | assign rasesr_din[42:0] = creg_esr_wr ?(ncu_man_ucb_c2i_packet_data[42:0]|rasesr_in[42:0]) : | |
4286 | rasesr2per_tgr ? rasesr_in[42:0] : (rasesr_in[42:0]|rasesr[42:0]) ; | |
4287 | ||
4288 | //forcing bit30,33,36.39 to 0, flop is still there but no one can write | |
4289 | //into it -Jimmy 3/25/05 | |
4290 | assign rasesr_n[42:0] = {rasesr_din[42:40], | |
4291 | 1'b0, //[39] | |
4292 | rasesr_din[38:37], | |
4293 | 1'b0, //[36] | |
4294 | rasesr_din[35:34], | |
4295 | 1'b0, //[33] | |
4296 | rasesr_din[32:31], | |
4297 | 1'b0, //[30] | |
4298 | rasesr_din[29:25], | |
4299 | rasesr_din[24:0]}; | |
4300 | ||
4301 | //assign ncu_dbg1_error_event = (|rasesr[42:0]) & wmr_vec_mask; | |
4302 | assign ncu_dbg1_error_event = (|rasesr[42:0]) & dbgtrigen; | |
4303 | ||
4304 | ncu_ctrl_ctl_msff_ctl_macro__width_43 rasesr_ff | |
4305 | ( | |
4306 | .scan_in(rasesr_ff_scanin), | |
4307 | .scan_out(rasesr_ff_scanout), | |
4308 | .dout (rasesr[42:0]), | |
4309 | .l1clk (l1clk), | |
4310 | .siclk (aclk_wmr), | |
4311 | .din (rasesr_n[42:0]), | |
4312 | .soclk(soclk) | |
4313 | ); | |
4314 | ||
4315 | assign rasesr_v_n = rasesr2per_tgr ? (|rasesr_in[42:0]) : (|{rasesr[42:0],rasesr_in[42:0]}) ; | |
4316 | ncu_ctrl_ctl_msff_ctl_macro__width_1 rasesr_v_ff | |
4317 | ( | |
4318 | .scan_in(rasesr_v_ff_scanin), | |
4319 | .scan_out(rasesr_v_ff_scanout), | |
4320 | .dout (rasesr_v), | |
4321 | .l1clk (l1clk), | |
4322 | .siclk (aclk_wmr), | |
4323 | .din (rasesr_v_n), | |
4324 | .soclk(soclk) | |
4325 | ); | |
4326 | ||
4327 | ||
4328 | assign creg_esr [63:0] = { rasesr_v, 20'b0, rasesr[42:0]}; | |
4329 | ||
4330 | ||
4331 | ////////////////////// | |
4332 | //// ELE register //// | |
4333 | ////////////////////// | |
4334 | ||
4335 | assign creg_ele_wr = ncu_man_ucb_buf_acpt_d2 & | |
4336 | ncu_man_ucb_c2i_packet_is_wr_req & creg_ele_dec; | |
4337 | ||
4338 | assign rasele_ff_in[42:0] = ~ncu_man_ucb_c2i_packet_data[42:0]; // add inverters, Jane | |
4339 | ||
4340 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 rasele_ff | |
4341 | ( | |
4342 | // .dout (rasele[42:0]), | |
4343 | .scan_in(rasele_ff_scanin), | |
4344 | .scan_out(rasele_ff_scanout), | |
4345 | .dout (rasele_ff_out[42:0]), | |
4346 | .l1clk (l1clk), | |
4347 | .en (creg_ele_wr), | |
4348 | // .din (ncu_man_ucb_c2i_packet_data[42:0]) | |
4349 | .din (rasele_ff_in[42:0]), | |
4350 | .siclk(siclk), | |
4351 | .soclk(soclk) | |
4352 | ); | |
4353 | ||
4354 | assign rasele[42:0] = ~rasele_ff_out[42:0]; // add inverters, Jane | |
4355 | ||
4356 | assign creg_ele[63:0] = {21'b0,rasele[42:0]}; | |
4357 | ||
4358 | //// sii syndrome filtering //// | |
4359 | //assign siierrsyn_va[5:0] = {6{siierrsyn_done}}&{siierrsyn[1],siierrsyn[5],siierrsyn[2],siierrsyn[4],siierrsyn[0],siierrsyn[3]}; | |
4360 | assign siierrsyn_va[5:0] = {6{siierrsyn_done}}&{siierrsyn[57],siierrsyn[61],siierrsyn[58],siierrsyn[60],siierrsyn[56],siierrsyn[59]}; | |
4361 | assign siierrsyn_vb[5:0] = siierrsyn_va[5:0]&siisynlog_en[5:0] ; | |
4362 | assign siisynlog_en[5:0] = {rasele[7:4],rasele[1:0]}; | |
4363 | ||
4364 | assign siietag[2:0] = siierrsyn_vb[0] ? 3'b000 : | |
4365 | siierrsyn_vb[1] ? 3'b001 : | |
4366 | siierrsyn_vb[2] ? 3'b100 : | |
4367 | siierrsyn_vb[3] ? 3'b101 : | |
4368 | siierrsyn_vb[4] ? 3'b110 : 3'b111 ; | |
4369 | ||
4370 | ||
4371 | //// ncu syndrome filtering //// | |
4372 | assign ncuerrsyn_va[5:0]={rasper[22:21],rasper[19:17],rasper[14]}; | |
4373 | // rasesr_in[22], rasesr_in[14] for format 2, rasesr_in[21] ~ [17] for format 1. | |
4374 | ||
4375 | assign ncuerrsyn_vb = |ncuerrsyn_va[5:0] ; | |
4376 | ||
4377 | ||
4378 | ////////////////////// | |
4379 | //// EIE register //// | |
4380 | ////////////////////// | |
4381 | assign creg_eie_wr = ncu_man_ucb_buf_acpt_d2 & | |
4382 | ncu_man_ucb_c2i_packet_is_wr_req & creg_eie_dec; | |
4383 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 raseie_ff | |
4384 | ( | |
4385 | .scan_in(raseie_ff_scanin), | |
4386 | .scan_out(raseie_ff_scanout), | |
4387 | .dout (raseie[42:0]), | |
4388 | .l1clk (l1clk), | |
4389 | .en (creg_eie_wr), | |
4390 | .din (ncu_man_ucb_c2i_packet_data[42:0]), | |
4391 | .siclk(siclk), | |
4392 | .soclk(soclk) | |
4393 | ); | |
4394 | ||
4395 | assign creg_eie[63:0] = {21'b0,raseie[42:0]}; | |
4396 | ||
4397 | ////////////////////// | |
4398 | //// EJR register //// | |
4399 | ////////////////////// | |
4400 | assign creg_ejr_wr = ncu_man_ucb_buf_acpt_d2 & | |
4401 | ncu_man_ucb_c2i_packet_is_wr_req & creg_ejr_dec; | |
4402 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 rasejr_ff | |
4403 | ( | |
4404 | .scan_in(rasejr_ff_scanin), | |
4405 | .scan_out(rasejr_ff_scanout), | |
4406 | .dout (rasejr[42:0]), | |
4407 | .l1clk (l1clk), | |
4408 | .en (creg_ejr_wr), | |
4409 | .din ({ncu_man_ucb_c2i_packet_data[42:0]}), | |
4410 | .siclk(siclk), | |
4411 | .soclk(soclk) | |
4412 | ); | |
4413 | ||
4414 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bit20_d1_ff | |
4415 | ( | |
4416 | .scan_in(bit20_d1_ff_scanin), | |
4417 | .scan_out(bit20_d1_ff_scanout), | |
4418 | .dout (bit20_d1), | |
4419 | .l1clk (l1clk), | |
4420 | .din (rasejr[20]), | |
4421 | .siclk(siclk), | |
4422 | .soclk(soclk) | |
4423 | ); | |
4424 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bit20_d2_ff | |
4425 | ( | |
4426 | .scan_in(bit20_d2_ff_scanin), | |
4427 | .scan_out(bit20_d2_ff_scanout), | |
4428 | .dout (bit20_d2), | |
4429 | .l1clk (l1clk), | |
4430 | .din (bit20_d1), | |
4431 | .siclk(siclk), | |
4432 | .soclk(soclk) | |
4433 | ); | |
4434 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bit20_d3_ff | |
4435 | ( | |
4436 | .scan_in(bit20_d3_ff_scanin), | |
4437 | .scan_out(bit20_d3_ff_scanout), | |
4438 | .dout (bit20_d3), | |
4439 | .l1clk (l1clk), | |
4440 | .din (bit20_d2), | |
4441 | .siclk(siclk), | |
4442 | .soclk(soclk) | |
4443 | ); | |
4444 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bit20_d4_ff | |
4445 | ( | |
4446 | .scan_in(bit20_d4_ff_scanin), | |
4447 | .scan_out(bit20_d4_ff_scanout), | |
4448 | .dout (bit20_d4), | |
4449 | .l1clk (l1clk), | |
4450 | .din (bit20_d3), | |
4451 | .siclk(siclk), | |
4452 | .soclk(soclk) | |
4453 | ); | |
4454 | ncu_ctrl_ctl_msff_ctl_macro__width_1 bit20_d5_ff | |
4455 | ( | |
4456 | .scan_in(bit20_d5_ff_scanin), | |
4457 | .scan_out(bit20_d5_ff_scanout), | |
4458 | .dout (bit20_d5), | |
4459 | .l1clk (l1clk), | |
4460 | .din (bit20_d4), | |
4461 | .siclk(siclk), | |
4462 | .soclk(soclk) | |
4463 | ); | |
4464 | ||
4465 | assign ncu_dmu_d_pei = ncu_dmu_d_pei_f & tcu_dbr_gateoff; | |
4466 | assign ncu_dmu_siicr_pei = ncu_dmu_siicr_pei_f & tcu_dbr_gateoff; | |
4467 | assign ncu_dmu_ctag_uei = ncu_dmu_ctag_uei_f & tcu_dbr_gateoff; | |
4468 | assign ncu_dmu_ctag_cei = ncu_dmu_ctag_cei_f & tcu_dbr_gateoff; | |
4469 | assign ncu_dmu_ncucr_pei = ncu_dmu_ncucr_pei_f & tcu_dbr_gateoff; | |
4470 | assign ncu_dmu_iei = ncu_dmu_iei_f & tcu_dbr_gateoff; | |
4471 | assign ncu_niu_ctag_cei = ncu_niu_ctag_cei_f & tcu_dbr_gateoff; | |
4472 | assign ncu_niu_ctag_uei = ncu_niu_ctag_uei_f & tcu_dbr_gateoff; | |
4473 | assign ncu_niu_d_pei = ncu_niu_d_pei_f & tcu_dbr_gateoff; | |
4474 | ||
4475 | ||
4476 | assign { | |
4477 | dmu_cr_id_rtn_erri, | |
4478 | ncu_mcu3_ecci, | |
4479 | ncu_mcu3_fbri, | |
4480 | ncu_mcu3_fbui, | |
4481 | ncu_mcu2_ecci, | |
4482 | ncu_mcu2_fbri, | |
4483 | ncu_mcu2_fbui, | |
4484 | ncu_mcu1_ecci, | |
4485 | ncu_mcu1_fbri, | |
4486 | ncu_mcu1_fbui, | |
4487 | ncu_mcu0_ecci, | |
4488 | ncu_mcu0_fbri, | |
4489 | ncu_mcu0_fbui, | |
4490 | ncu_niu_d_pei_f, | |
4491 | ncu_niu_ctag_uei_f, | |
4492 | ncu_niu_ctag_cei_f, | |
4493 | ncu_sio_ctag_cei, | |
4494 | ncu_sio_ctag_uei, | |
4495 | ncu_sio_d_pei, | |
4496 | ncuctag_cei, | |
4497 | ncuctag_uei, | |
4498 | dmubuf_pei, | |
4499 | iobuf_uei, | |
4500 | cpubuf_uei, | |
4501 | cpubuf_pei, | |
4502 | intman_pei, | |
4503 | intbuf_uei, | |
4504 | mondotbl_pei, //// | |
4505 | ncusiid_pei, //// | |
4506 | ncu_dmu_d_pei_f, | |
4507 | ncu_dmu_siicr_pei_f, | |
4508 | ncu_dmu_ctag_uei_f, | |
4509 | ncu_dmu_ctag_cei_f, | |
4510 | ncu_dmu_ncucr_pei_f, | |
4511 | ncu_dmu_iei_f, | |
4512 | ncu_sii_dmua_pei, | |
4513 | ncu_sii_niud_pei, | |
4514 | ncu_sii_dmud_pei, | |
4515 | ncu_sii_niua_pei, | |
4516 | ncu_sii_dmuctag_cei, | |
4517 | ncu_sii_niuctag_cei, | |
4518 | ncu_sii_dmuctag_uei, | |
4519 | ncu_sii_niuctag_uei} = {rasejr[42:21],bit20_d5,rasejr[19:0]}; | |
4520 | ||
4521 | assign creg_ejr[63:0] = {21'b0,rasejr[42:0]}; | |
4522 | ||
4523 | ////////////////////// | |
4524 | //// FEE register //// | |
4525 | ////////////////////// | |
4526 | ||
4527 | assign creg_fee_wr = ncu_man_ucb_buf_acpt_d2 & | |
4528 | ncu_man_ucb_c2i_packet_is_wr_req & creg_fee_dec; | |
4529 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 rasfee_ff | |
4530 | ( | |
4531 | .scan_in(rasfee_ff_scanin), | |
4532 | .scan_out(rasfee_ff_scanout), | |
4533 | .dout (rasfee[42:0]), | |
4534 | .l1clk (l1clk), | |
4535 | .en (creg_fee_wr), | |
4536 | .din (ncu_man_ucb_c2i_packet_data[42:0]), | |
4537 | .siclk(siclk), | |
4538 | .soclk(soclk) | |
4539 | ); | |
4540 | ||
4541 | assign creg_fee[63:0] = {21'b0,rasfee[42:0]}; | |
4542 | ||
4543 | assign ncu_rst_fatal_error_n = |(raserr_in[42:0]&rasfee[42:0]) ; | |
4544 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_rst_fatal_error_ff | |
4545 | ( | |
4546 | .scan_in(ncu_rst_fatal_error_ff_scanin), | |
4547 | .scan_out(ncu_rst_fatal_error_ff_scanout), | |
4548 | .dout (ncu_rst_fatal_error), | |
4549 | .l1clk (l1clk), | |
4550 | .din (ncu_rst_fatal_error_n), | |
4551 | .siclk(siclk), | |
4552 | .soclk(soclk) | |
4553 | ); | |
4554 | ||
4555 | ////////////////////// | |
4556 | //// PER register //// | |
4557 | ////////////////////// | |
4558 | ||
4559 | assign creg_per_wr = ncu_man_ucb_buf_acpt_d2 & | |
4560 | ncu_man_ucb_c2i_packet_is_wr_req & creg_per_dec; | |
4561 | ||
4562 | assign rasper_in[42:0] = rasesr[42:0] & raseie[42:0] ; | |
4563 | assign rasper_in_v = (|rasper_in[42:0]) & rasesr_v ; | |
4564 | assign rasper_n[42:0] = creg_per_wr ? ncu_man_ucb_c2i_packet_data[42:0] : rasper_in[42:0] ; | |
4565 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 rasper_ff | |
4566 | ( | |
4567 | .scan_in(rasper_ff_scanin), | |
4568 | .scan_out(rasper_ff_scanout), | |
4569 | .dout (rasper[42:0]), | |
4570 | .l1clk (l1clk), | |
4571 | .siclk (aclk_wmr), | |
4572 | .en (creg_per_wr|(~rasper_v)), | |
4573 | .din (rasper_n[42:0]), | |
4574 | .soclk(soclk) | |
4575 | ); | |
4576 | ||
4577 | assign rasper_v_n = creg_per_wr ? ncu_man_ucb_c2i_packet_data[63] : rasper_in_v ; | |
4578 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 rasper_v_ff | |
4579 | ( | |
4580 | .scan_in(rasper_v_ff_scanin), | |
4581 | .scan_out(rasper_v_ff_scanout), | |
4582 | .dout (rasper_v), | |
4583 | .l1clk (l1clk), | |
4584 | .siclk (aclk_wmr), | |
4585 | .en (creg_per_wr|(~rasper_v)), | |
4586 | .din (rasper_v_n), | |
4587 | .soclk(soclk) | |
4588 | ); | |
4589 | ||
4590 | assign rasesr2per_tgr = (rasper_in_v&~rasper_v); | |
4591 | ||
4592 | assign rasper_ipg_n = rasper_srvc ? 1'b0 : rasesr2per_tgr|rasper_ipg ; | |
4593 | ncu_ctrl_ctl_msff_ctl_macro__width_1 rasper_ipg_ff | |
4594 | ( | |
4595 | .scan_in(rasper_ipg_ff_scanin), | |
4596 | .scan_out(rasper_ipg_ff_scanout), | |
4597 | .dout (rasper_ipg), | |
4598 | .l1clk (l1clk), | |
4599 | .din (rasper_ipg_n), | |
4600 | .siclk(siclk), | |
4601 | .soclk(soclk) | |
4602 | ); | |
4603 | ncu_ctrl_ctl_msff_ctl_macro__width_1 rasesr2per_tgr_d_ff | |
4604 | ( | |
4605 | .scan_in(rasesr2per_tgr_d_ff_scanin), | |
4606 | .scan_out(rasesr2per_tgr_d_ff_scanout), | |
4607 | .dout (rasesr2per_tgr_d), | |
4608 | .l1clk (l1clk), | |
4609 | .din (rasesr2per_tgr), | |
4610 | .siclk(siclk), | |
4611 | .soclk(soclk) | |
4612 | ); | |
4613 | ||
4614 | assign rasper_srvc = ~ncu_man_int_buf_full & ~intvecdisp_int_wr & rasper_ipg ; | |
4615 | // assert when there is a soc error packet generated for core. | |
4616 | ||
4617 | assign rasper_int_wr = rasper_srvc; | |
4618 | ||
4619 | ncu_ctrl_ctl_msff_ctl_macro__width_1 ncu_tcu_soc_error_ff | |
4620 | ( | |
4621 | .scan_in(ncu_tcu_soc_error_ff_scanin), | |
4622 | .scan_out(ncu_tcu_soc_error_ff_scanout), | |
4623 | .dout (ncu_tcu_soc_error), | |
4624 | .l1clk (l1clk), | |
4625 | .din (rasper_srvc), | |
4626 | .siclk(siclk), | |
4627 | .soclk(soclk) | |
4628 | ); | |
4629 | ||
4630 | ||
4631 | assign raserrce = rasper[41] | rasper[38] | rasper[35] | rasper[32] | rasper[27] | | |
4632 | rasper[26] | rasper[23] | rasper[10] | rasper[3] | rasper[2] | | |
4633 | rasper[31] | rasper[34] | rasper[40] | rasper[37]; | |
4634 | // correctable error | |
4635 | assign raserrue = rasper[25] | rasper[28] | rasper[11] | rasper[1] | rasper[0] | | |
4636 | rasper[4] | rasper[5] | rasper[6] | rasper[7] | rasper[8] | | |
4637 | rasper[9] | rasper[12] | rasper[13] | rasper[14] | rasper[15] | | |
4638 | rasper[16] | rasper[17] | rasper[18] | rasper[19] | rasper[20] | | |
4639 | rasper[21] | rasper[22] | rasper[24] | rasper[29] | rasper[42]; | |
4640 | // uncorrectable error | |
4641 | // all raserr bits are grouped as correctable or uncorrectable except, | |
4642 | // bit 39, 36, 33 and 30, which are Fbdimm uncrecoverable. | |
4643 | ||
4644 | assign ucb_soc_int_type[3:0] = raserrue ? `UCB_INT_SOC_UE : `UCB_INT_SOC_CE ; | |
4645 | ||
4646 | ||
4647 | assign rasper_int_pkt[24:0] = {////7'b0, //reserved | |
4648 | 6'b00_0000, //dummy intvec | |
4649 | ////32'b0, //reserved | |
4650 | 9'b0, //dummy dev_id | |
4651 | // ras_cpuid[2:0],3'b0, | |
4652 | ras_err_steering[5:0], | |
4653 | ucb_soc_int_type[3:0] } ; | |
4654 | ||
4655 | ||
4656 | ||
4657 | ||
4658 | ||
4659 | assign creg_per[63:0] = {rasper_v,20'b0,rasper[42:0]}; | |
4660 | ||
4661 | ||
4662 | ///////////////////////// | |
4663 | //// SIISYN register //// | |
4664 | ///////////////////////// | |
4665 | ||
4666 | assign creg_siisyn_wr = ncu_man_ucb_buf_acpt_d2 & | |
4667 | ncu_man_ucb_c2i_packet_is_wr_req & creg_siisyn_dec; | |
4668 | ||
4669 | assign siisyn_n[58:0] = creg_siisyn_wr ? { ncu_man_ucb_c2i_packet_data[58:0]} : {siietag[2:0],siierrsyn[55:0]} ; | |
4670 | //assign siisyn_n[58:0] = creg_siisyn_wr ? { ncu_man_ucb_c2i_packet_data[58:0]} : {siietag[2:0],siierrsyn[63:8]} ; | |
4671 | ||
4672 | ||
4673 | assign siierrsyn_vc = ~siisyn_v & (|siierrsyn_vb[5:0]); | |
4674 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_59 siisyn_ff | |
4675 | ( | |
4676 | .scan_in(siisyn_ff_scanin), | |
4677 | .scan_out(siisyn_ff_scanout), | |
4678 | .dout (siisyn[58:0]), | |
4679 | .l1clk (l1clk), | |
4680 | .siclk (aclk_wmr), | |
4681 | .en (siierrsyn_vc|creg_siisyn_wr), | |
4682 | .din (siisyn_n[58:0]), | |
4683 | .soclk(soclk) | |
4684 | ); | |
4685 | ||
4686 | assign siisyn_v_n = creg_siisyn_wr ? ncu_man_ucb_c2i_packet_data[63] : 1'b1 ; | |
4687 | ||
4688 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 siisyn_v_ff | |
4689 | ( | |
4690 | .scan_in(siisyn_v_ff_scanin), | |
4691 | .scan_out(siisyn_v_ff_scanout), | |
4692 | .dout (siisyn_v), | |
4693 | .l1clk (l1clk), | |
4694 | .siclk (aclk_wmr), | |
4695 | .en (siierrsyn_vc|creg_siisyn_wr), | |
4696 | .din (siisyn_v_n), | |
4697 | .soclk(soclk) | |
4698 | ); | |
4699 | ||
4700 | assign creg_siisyn[63:0] = {siisyn_v,4'b0,siisyn[58:0]}; | |
4701 | ||
4702 | ||
4703 | ///////////////////////// | |
4704 | //// NCUSYN register //// | |
4705 | ///////////////////////// | |
4706 | ||
4707 | ||
4708 | assign creg_ncusyn_wr = ncu_man_ucb_buf_acpt_d2 & | |
4709 | ncu_man_ucb_c2i_packet_is_wr_req & creg_ncusyn_dec; | |
4710 | ||
4711 | assign creg_ncu_scksel_wr = ncu_man_ucb_buf_acpt_d2 & | |
4712 | ncu_man_ucb_c2i_packet_is_wr_req & creg_ncu_scksel_dec; | |
4713 | ||
4714 | assign creg_dbgtrigen_wr = ncu_man_ucb_buf_acpt_d2 & | |
4715 | ncu_man_ucb_c2i_packet_is_wr_req & creg_dbgtrigen_dec; | |
4716 | ||
4717 | assign intmansyn_n[54:0] = c2i_rd_intman ? | |
4718 | //rtcp ,rqtyp, cputhr ,pa | |
4719 | {4'b1111,5'b0,ncu_man_ucb_c2i_packet_cputhr[5:0],ncu_man_ucb_c2i_packet_addr[39:0]}: | |
4720 | {4'b0110,5'b0,intman_ct_dout[5:0] ,40'b0}; | |
4721 | ||
4722 | ||
4723 | ||
4724 | //assign ncuerrsyn[60:0] = ncuerrsyn_va[4] ? {1'b0,4'b1111,ncu_etag[4:0], dmubufsyn[46:36],`DMU_PIO,dmubufsyn[35:0]} : | |
4725 | // //ncuerrsyn_va[1] ? {5'b0_0110,ncu_etag[4:0], 5'b0,intmansyn[5:0],40'b0} : | |
4726 | // ncuerrsyn_va[1] ? {1'b0,intmansyn[54:51],ncu_etag[4:0],intmansyn[50:0] } : | |
4727 | // (ncuerrsyn_va[5]|ncuerrsyn_va[0]) ? {1'b1,4'b0000,ncu_etag[4:0],5'b0,6'b0,24'b0,ncudpsyn[15:0]} : //f2 | |
4728 | // {1'b0,4'b1111,ncu_etag[4:0],cpubufsyn[50:0]} ; //for [2],[3] | |
4729 | ||
4730 | assign ncuerrsyn[60:0] = ncuerrsyn_va[4] ? {1'b0,4'b1110,ncu_etag[4:0], dmubufsyn[46:36],`DMU_PIO,dmubufsyn[35:0]} : | |
4731 | ncuerrsyn_va[1] ? {1'b0,intmansyn[54:51],ncu_etag[4:0],intmansyn[50:0] } : | |
4732 | (ncuerrsyn_va[5]|ncuerrsyn_va[0]) ? {1'b1,4'b0000,ncu_etag[4:0],5'b0,6'b0,24'b0,ncudpsyn[15:0]} : | |
4733 | ncuerrsyn_va[3] ? {1'b0,4'b1001,ncu_etag[4:0],cpubufsyn[50:46],6'b0,cpubufsyn[39:0]} : //for [3] | |
4734 | {1'b0,4'b0110,ncu_etag[4:0],5'b0,cpubufsyn[45:40],40'b0} ; //for [2] | |
4735 | // ncuerrsyn_va[4] is set, RCTP has to be 4'b1110, since we use offset and PA is not available. | |
4736 | ||
4737 | assign ncusyn_n[60:0] = creg_ncusyn_wr ? | |
4738 | {ncu_man_ucb_c2i_packet_data[62:58], | |
4739 | ncu_man_ucb_c2i_packet_data[55:0]} : ncuerrsyn[60:0] ; | |
4740 | ||
4741 | assign ncuerrsyn_vc = ~ncusyn_v & ncuerrsyn_vb & rasesr2per_tgr_d ; | |
4742 | ||
4743 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_61 ncusyn_ff | |
4744 | ( | |
4745 | .scan_in(ncusyn_ff_scanin), | |
4746 | .scan_out(ncusyn_ff_scanout), | |
4747 | .dout (ncusyn[60:0]), | |
4748 | .l1clk (l1clk), | |
4749 | .siclk (aclk_wmr), | |
4750 | .en (ncuerrsyn_vc|creg_ncusyn_wr), | |
4751 | .din (ncusyn_n[60:0]), | |
4752 | .soclk(soclk) | |
4753 | ); | |
4754 | ||
4755 | assign ncusyn_v_n = creg_ncusyn_wr ? ncu_man_ucb_c2i_packet_data[63] : 1'b1 ; | |
4756 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ncusyn_v_ff | |
4757 | ( | |
4758 | .scan_in(ncusyn_v_ff_scanin), | |
4759 | .scan_out(ncusyn_v_ff_scanout), | |
4760 | .dout (ncusyn_v), | |
4761 | .l1clk (l1clk), | |
4762 | .siclk (aclk_wmr), | |
4763 | .en (ncuerrsyn_vc|creg_ncusyn_wr), | |
4764 | .din (ncusyn_v_n), | |
4765 | .soclk(soclk) | |
4766 | ); | |
4767 | ||
4768 | ||
4769 | assign ncu_scksel_n[1:0] = creg_ncu_scksel_wr ? ncu_man_ucb_c2i_packet_data[1:0] : ncu_scksel[1:0]; | |
4770 | ncu_ctrl_ctl_msff_ctl_macro__width_2 ncu_scksel_ff | |
4771 | ( | |
4772 | .scan_in(ncu_scksel_ff_scanin), | |
4773 | .scan_out(ncu_scksel_ff_scanout), | |
4774 | .dout (ncu_scksel[1:0]), | |
4775 | .l1clk (l1clk), | |
4776 | .siclk (aclk_wmr), | |
4777 | .din (ncu_scksel_n[1:0]), | |
4778 | .soclk(soclk) | |
4779 | ); | |
4780 | assign creg_ncu_scksel[63:0] = {62'b0, ncu_scksel[1:0]}; | |
4781 | ||
4782 | ncu_ctrl_ctl_msff_ctl_macro__en_1__width_2 scksel_sh_ff | |
4783 | ( | |
4784 | .scan_in(scksel_sh_ff_scanin), | |
4785 | .scan_out(scksel_sh_ff_scanout), | |
4786 | .dout (ncu_scksel_sh[1:0]), | |
4787 | .l1clk (l1clk), | |
4788 | .siclk (aclk_wmr), | |
4789 | .en (wmr_upd_en), | |
4790 | .din (ncu_scksel[1:0]), | |
4791 | .soclk(soclk) | |
4792 | ); | |
4793 | ||
4794 | assign dbgtrigen_n = creg_dbgtrigen_wr ? ncu_man_ucb_c2i_packet_data[0] : dbgtrigen; | |
4795 | ncu_ctrl_ctl_msff_ctl_macro__width_1 dbgtrigen_ff | |
4796 | ( | |
4797 | .scan_in(dbgtrigen_ff_scanin), | |
4798 | .scan_out(dbgtrigen_ff_scanout), | |
4799 | .dout (dbgtrigen), | |
4800 | .l1clk (l1clk), | |
4801 | .siclk (aclk_wmr), | |
4802 | .din (dbgtrigen_n), | |
4803 | .soclk(soclk) | |
4804 | ); | |
4805 | assign creg_dbgtrigen[63:0] = {63'b0, dbgtrigen}; | |
4806 | ||
4807 | assign ncu_etag[4:0] = ncuerrsyn_va[0] ? 5'b01110 : // ESR[14] | |
4808 | ncuerrsyn_va[1] ? 5'b10001 : // ESR[17] | |
4809 | ncuerrsyn_va[2] ? 5'b10010 : // ESR[18] | |
4810 | ncuerrsyn_va[3] ? 5'b10011 : // ESR[19] | |
4811 | ncuerrsyn_va[4] ? 5'b10101 : // ESR[21] | |
4812 | ncuerrsyn_va[5] ? 5'b10110 : 5'b0 ; // ESR[22] | |
4813 | ||
4814 | ||
4815 | assign creg_ncusyn[63:0] = {ncusyn_v,ncusyn[60:56],2'b0,ncusyn[55:0]}; | |
4816 | //assign creg_ncusyn[63:0] = {ncusyn_v,ncusyn[55:51],2'b0,ncu_etag[4:0],ncusyn[50:0]}; | |
4817 | ||
4818 | ||
4819 | /**** adding clock header ****/ | |
4820 | ncu_ctrl_ctl_l1clkhdr_ctl_macro clkgen ( | |
4821 | .l2clk (iol2clk), | |
4822 | .l1en (1'b1), | |
4823 | .l1clk (l1clk), | |
4824 | .pce_ov(pce_ov), | |
4825 | .stop(stop), | |
4826 | .se(se) | |
4827 | ); | |
4828 | ||
4829 | ||
4830 | /*** building tcu port ***/ | |
4831 | assign siclk = tcu_aclk; | |
4832 | assign soclk = tcu_bclk; | |
4833 | assign se = tcu_scan_en; | |
4834 | assign pce_ov = tcu_pce_ov; | |
4835 | assign stop = tcu_clk_stop; | |
4836 | ||
4837 | ||
4838 | //// starting warm reset protected scanchain -jimmy 4/3/05 //// | |
4839 | assign sernum0_ff_scanin = scan_in; | |
4840 | assign sernum1_ff_scanin = sernum0_ff_scanout ; | |
4841 | assign sernum2_ff_scanin = sernum1_ff_scanout ; | |
4842 | assign fusestat_ff_scanin = sernum2_ff_scanout ; | |
4843 | assign coreavail_ff_scanin = fusestat_ff_scanout ; | |
4844 | assign bankavail_ff_scanin = coreavail_ff_scanout ; | |
4845 | assign asi_cmp_tick_enable_ff_scanin = bankavail_ff_scanout ; | |
4846 | assign asi_ras_err_steering_ff_scanin = asi_cmp_tick_enable_ff_scanout ; | |
4847 | assign core_enable_ff_scanin = asi_ras_err_steering_ff_scanout ; | |
4848 | assign bank_en_ff_scanin = core_enable_ff_scanout ; | |
4849 | assign l2idxhs_en_ff_scanin = bank_en_ff_scanout ; | |
4850 | assign rasesr_ff_scanin = l2idxhs_en_ff_scanout ; | |
4851 | assign rasesr_v_ff_scanin = rasesr_ff_scanout ; | |
4852 | assign rasper_ff_scanin = rasesr_v_ff_scanout ; | |
4853 | assign rasper_v_ff_scanin = rasper_ff_scanout ; | |
4854 | assign siisyn_ff_scanin = rasper_v_ff_scanout ; | |
4855 | assign siisyn_v_ff_scanin = siisyn_ff_scanout ; | |
4856 | assign ncusyn_ff_scanin = siisyn_v_ff_scanout ; | |
4857 | assign asi_wmr_vec_mask_ff_scanin = ncusyn_ff_scanout; | |
4858 | assign ncu_scksel_ff_scanin = asi_wmr_vec_mask_ff_scanout ; | |
4859 | assign dbgtrigen_ff_scanin = ncu_scksel_ff_scanout; | |
4860 | assign scksel_sh_ff_scanin = dbgtrigen_ff_scanout; | |
4861 | assign wmr_protect_d2_ff_scanin = scksel_sh_ff_scanout; | |
4862 | assign wmr_protect_d1_ff_scanin = wmr_protect_d2_ff_scanout; | |
4863 | assign ncusyn_v_ff_scanin = wmr_protect_d1_ff_scanout ; | |
4864 | assign wmrp_chain_scanout = ~(wmr_protect | ~ncusyn_v_ff_scanout) ; | |
4865 | ||
4866 | // fixscan start: | |
4867 | //assign ncu_man_ucb_buf_acpt_d1_ff_scanin = scan_in ; | |
4868 | assign ncu_man_ucb_buf_acpt_d1_ff_scanin = wmrp_chain_scanout ; | |
4869 | assign ncu_man_ucb_buf_acpt_d2_ff_scanin = ncu_man_ucb_buf_acpt_d1_ff_scanout; | |
4870 | assign ncu_man_ucb_buf_acpt_d3_ff_scanin = ncu_man_ucb_buf_acpt_d2_ff_scanout; | |
4871 | assign ncu_man_ucb_c2i_packet_data_ff_scanin = ncu_man_ucb_buf_acpt_d3_ff_scanout; | |
4872 | assign ncu_man_ucb_c2i_packet_addr_ff_scanin = ncu_man_ucb_c2i_packet_data_ff_scanout; | |
4873 | assign ncu_man_ucb_c2i_packet_buf_id_ff_scanin = ncu_man_ucb_c2i_packet_addr_ff_scanout; | |
4874 | assign ncu_man_ucb_c2i_packet_cputhr_ff_scanin = ncu_man_ucb_c2i_packet_buf_id_ff_scanout; | |
4875 | assign ncu_man_ucb_c2i_packet_is_rd_req_ff_scanin = ncu_man_ucb_c2i_packet_cputhr_ff_scanout; | |
4876 | assign ncu_man_ucb_c2i_packet_is_wr_req_ff_scanin = ncu_man_ucb_c2i_packet_is_rd_req_ff_scanout; | |
4877 | assign aa_buf1_older_ff_scanin = ncu_man_ucb_c2i_packet_is_wr_req_ff_scanout; | |
4878 | assign aa_buf0_vld_ff_scanin = aa_buf1_older_ff_scanout ; | |
4879 | assign aa_buf1_vld_ff_scanin = aa_buf0_vld_ff_scanout ; | |
4880 | assign aa_buf0_obj_ff_scanin = aa_buf1_vld_ff_scanout ; | |
4881 | assign aa_buf1_obj_ff_scanin = aa_buf0_obj_ff_scanout ; | |
4882 | assign bb_buf1_older_ff_scanin = aa_buf1_obj_ff_scanout ; | |
4883 | assign bb_buf0_vld_ff_scanin = bb_buf1_older_ff_scanout ; | |
4884 | assign bb_buf1_vld_ff_scanin = bb_buf0_vld_ff_scanout ; | |
4885 | assign bb_buf0_obj_ff_scanin = bb_buf1_vld_ff_scanout ; | |
4886 | assign bb_buf1_obj_ff_scanin = bb_buf0_obj_ff_scanout ; | |
4887 | assign intman_pe_ff_scanin = bb_buf1_obj_ff_scanout ; | |
4888 | assign intmansyn_ff_scanin = intman_pe_ff_scanout ; | |
4889 | assign fuse_data_d1_ff_scanin = intmansyn_ff_scanout ; | |
4890 | assign coreavail_dshift_d1_ff_scanin = fuse_data_d1_ff_scanout ; | |
4891 | assign coreavail_dshift_d2_ff_scanin = coreavail_dshift_d1_ff_scanout; | |
4892 | assign bankavail_dshift_d1_ff_scanin = coreavail_dshift_d2_ff_scanout; | |
4893 | assign bankavail_dshift_d2_ff_scanin = bankavail_dshift_d1_ff_scanout; | |
4894 | assign fuse_stat_dshift_d1_ff_scanin = bankavail_dshift_d2_ff_scanout; | |
4895 | assign sernum0_dshift_d1_ff_scanin = fuse_stat_dshift_d1_ff_scanout; | |
4896 | assign sernum1_dshift_d1_ff_scanin = sernum0_dshift_d1_ff_scanout; | |
4897 | assign sernum2_dshift_d1_ff_scanin = sernum1_dshift_d1_ff_scanout; | |
4898 | ////assign creg_mondoinvec_ff_scanin = bankavail_ff_scanout ; | |
4899 | assign creg_mondoinvec_ff_scanin = sernum2_dshift_d1_ff_scanout; | |
4900 | assign creg_mem32_en_ff_scanin = creg_mondoinvec_ff_scanout; | |
4901 | assign creg_mem32_base_ff_scanin = creg_mem32_en_ff_scanout ; | |
4902 | assign creg_mem32_mask_ff_scanin = creg_mem32_base_ff_scanout; | |
4903 | assign creg_mem64_en_ff_scanin = creg_mem32_mask_ff_scanout; | |
4904 | assign creg_mem64_base_ff_scanin = creg_mem64_en_ff_scanout ; | |
4905 | assign creg_mem64_mask_ff_scanin = creg_mem64_base_ff_scanout; | |
4906 | assign creg_iocon_en_ff_scanin = creg_mem64_mask_ff_scanout; | |
4907 | assign creg_iocon_base_ff_scanin = creg_iocon_en_ff_scanout ; | |
4908 | assign creg_iocon_mask_ff_scanin = creg_iocon_base_ff_scanout; | |
4909 | assign creg_mmufsh_ff_scanin = creg_iocon_mask_ff_scanout; | |
4910 | assign mmufsh_vld_ff_scanin = creg_mmufsh_ff_scanout ; | |
4911 | //assign asi_wmr_vec_mask_ff_scanin = mmufsh_vld_ff_scanout ; | |
4912 | ////assign tap_mondo_acc_addr_39_16_ff_scanin = asi_ras_err_steering_ff_scanout; | |
4913 | assign tap_mondo_acc_addr_39_16_ff_scanin = mmufsh_vld_ff_scanout; | |
4914 | assign tap_mondo_acc_addr_s_ff_scanin = tap_mondo_acc_addr_39_16_ff_scanout; | |
4915 | assign tap_mondo_din_s_ff_scanin = tap_mondo_acc_addr_s_ff_scanout; | |
4916 | assign ncu_int_ucb_c2i_packet_is_rd_req_ff_scanin = tap_mondo_din_s_ff_scanout; | |
4917 | assign ncu_int_ucb_c2i_packet_is_wr_req_ff_scanin = ncu_int_ucb_c2i_packet_is_rd_req_ff_scanout; | |
4918 | assign tap_mondo_acc_seq_ff_scanin = ncu_int_ucb_c2i_packet_is_wr_req_ff_scanout; | |
4919 | assign tap_mondo_acc_addr_invld_d2_ff_scanin = tap_mondo_acc_seq_ff_scanout; | |
4920 | assign tap_mondo_acc_seq_d2_ff_scanin = tap_mondo_acc_addr_invld_d2_ff_scanout; | |
4921 | assign tap_mondo_dout_d2_ff_scanin = tap_mondo_acc_seq_d2_ff_scanout; | |
4922 | assign tap_mondo_acc_outstanding_d1_ff_scanin = tap_mondo_dout_d2_ff_scanout; | |
4923 | assign ncu_int_ack_packet_ff_scanin = tap_mondo_acc_outstanding_d1_ff_scanout; | |
4924 | assign ncu_int_ack_vld_ff_scanin = ncu_int_ack_packet_ff_scanout; | |
4925 | assign cc_buf1_older_ff_scanin = ncu_int_ack_vld_ff_scanout; | |
4926 | assign cc_buf0_vld_ff_scanin = cc_buf1_older_ff_scanout ; | |
4927 | assign cc_buf1_vld_ff_scanin = cc_buf0_vld_ff_scanout ; | |
4928 | assign cc_buf0_obj_ff_scanin = cc_buf1_vld_ff_scanout ; | |
4929 | assign cc_buf1_obj_ff_scanin = cc_buf0_obj_ff_scanout ; | |
4930 | assign dd_buf1_older_ff_scanin = cc_buf1_obj_ff_scanout ; | |
4931 | assign dd_buf0_vld_ff_scanin = dd_buf1_older_ff_scanout ; | |
4932 | assign dd_buf1_vld_ff_scanin = dd_buf0_vld_ff_scanout ; | |
4933 | assign dd_buf0_obj_ff_scanin = dd_buf1_vld_ff_scanout ; | |
4934 | assign dd_buf1_obj_ff_scanin = dd_buf0_obj_ff_scanout ; | |
4935 | //assign wmr_counter_ff_scanin = dd_buf1_obj_ff_scanout ; | |
4936 | //assign core_enable_status_ff_scanin = core_enable_ff_scanout ; | |
4937 | assign core_enable_status7_ff_scanin = dd_buf1_obj_ff_scanout ; | |
4938 | assign core_enable_status6_ff_scanin = core_enable_status7_ff_scanout; | |
4939 | assign core_enable_status5_ff_scanin = core_enable_status6_ff_scanout; | |
4940 | assign core_enable_status4_ff_scanin = core_enable_status5_ff_scanout; | |
4941 | assign core_enable_status3_ff_scanin = core_enable_status4_ff_scanout; | |
4942 | assign core_enable_status2_ff_scanin = core_enable_status3_ff_scanout; | |
4943 | assign core_enable_status1_ff_scanin = core_enable_status2_ff_scanout; | |
4944 | assign core_enable_status0_ff_scanin = core_enable_status1_ff_scanout; | |
4945 | //assign cmp_freeze_ff_scanin = core_enable_status_ff_scanout; | |
4946 | assign coreavail_done_d1_ff_scanin = core_enable_status0_ff_scanout; | |
4947 | assign xir_steering_ff_scanin = coreavail_done_d1_ff_scanout; | |
4948 | assign xir_trigger_ff_scanin = xir_steering_ff_scanout ; | |
4949 | assign xir_trigger_d0_ff_scanin = xir_trigger_ff_scanout ; | |
4950 | assign xir_trigger_d1_ff_scanin = xir_trigger_d0_ff_scanout; | |
4951 | assign xir_snapd_vec_ff_scanin = xir_trigger_d1_ff_scanout; | |
4952 | assign xir_mini_vec_ff_scanin = xir_snapd_vec_ff_scanout ; | |
4953 | assign xir_cpuid_ff_scanin = xir_mini_vec_ff_scanout ; | |
4954 | assign xir_busy_ff_scanin = xir_cpuid_ff_scanout ; | |
4955 | assign xir_busy_d1_ff_scanin = xir_busy_ff_scanout ; | |
4956 | assign ncu_rst_xir_done_ff_scanin = xir_busy_d1_ff_scanout ; | |
4957 | assign core_running_ff_scanin = ncu_rst_xir_done_ff_scanout; | |
4958 | assign core_running0_ff_scanin = core_running_ff_scanout; | |
4959 | assign unpark_thread_d1_ff_scanin = core_running0_ff_scanout ; | |
4960 | assign unpark_thread_d2_ff_scanin = unpark_thread_d1_ff_scanout; | |
4961 | assign wake_ok__ff_scanin = unpark_thread_d2_ff_scanout; | |
4962 | assign wake_thread_ff_scanin = wake_ok__ff_scanout ; | |
4963 | assign core_running_status_ff_scanin = wake_thread_ff_scanout ; | |
4964 | assign core_running_status0_ff_scanin = core_running_status_ff_scanout ; | |
4965 | assign l2pm_preview_ff_scanin = core_running_status0_ff_scanout; | |
4966 | assign l2pm_ff_scanin = l2pm_preview_ff_scanout ; | |
4967 | ////assign l2idxhs_en_status_ff_scanin = l2idxhs_en_ff_scanout ; | |
4968 | assign l2idxhs_en_status_ff_scanin = l2pm_ff_scanout ; | |
4969 | assign iobuf_ue_ff_scanin = l2idxhs_en_status_ff_scanout; | |
4970 | assign intbuf_ue_ff_scanin = iobuf_ue_ff_scanout ; | |
4971 | assign mondotbl_pe_ff_scanin = intbuf_ue_ff_scanout ; | |
4972 | assign mcu3_ncu_ecc_d_ff_scanin = mondotbl_pe_ff_scanout ; | |
4973 | assign mcu3_ncu_fbr_d_ff_scanin = mcu3_ncu_ecc_d_ff_scanout; | |
4974 | assign mcu3_ncu_fbu_d_ff_scanin = mcu3_ncu_fbr_d_ff_scanout; | |
4975 | assign mcu2_ncu_ecc_d_ff_scanin = mcu3_ncu_fbu_d_ff_scanout; | |
4976 | assign mcu2_ncu_fbr_d_ff_scanin = mcu2_ncu_ecc_d_ff_scanout; | |
4977 | assign mcu2_ncu_fbu_d_ff_scanin = mcu2_ncu_fbr_d_ff_scanout; | |
4978 | assign mcu1_ncu_ecc_d_ff_scanin = mcu2_ncu_fbu_d_ff_scanout; | |
4979 | assign mcu1_ncu_fbr_d_ff_scanin = mcu1_ncu_ecc_d_ff_scanout; | |
4980 | assign mcu1_ncu_fbu_d_ff_scanin = mcu1_ncu_fbr_d_ff_scanout; | |
4981 | assign mcu0_ncu_ecc_d_ff_scanin = mcu1_ncu_fbu_d_ff_scanout; | |
4982 | assign mcu0_ncu_fbr_d_ff_scanin = mcu0_ncu_ecc_d_ff_scanout; | |
4983 | assign mcu0_ncu_fbu_d_ff_scanin = mcu0_ncu_fbr_d_ff_scanout; | |
4984 | assign niu_ncu_d_pe_d_ff_scanin = mcu0_ncu_fbu_d_ff_scanout; | |
4985 | assign niu_ncu_ctag_ue_d_ff_scanin = niu_ncu_d_pe_d_ff_scanout; | |
4986 | assign niu_ncu_ctag_ce_d_ff_scanin = niu_ncu_ctag_ue_d_ff_scanout; | |
4987 | assign sio_ncu_ctag_ce_d_ff_scanin = niu_ncu_ctag_ce_d_ff_scanout; | |
4988 | assign sio_ncu_ctag_ue_d_ff_scanin = sio_ncu_ctag_ce_d_ff_scanout; | |
4989 | //assign sio_ncu_d_pe_d_ff_scanin = sio_ncu_ctag_ue_d_ff_scanout; | |
4990 | assign dmu_ncu_d_pe_d_ff_scanin = sio_ncu_ctag_ue_d_ff_scanout; | |
4991 | assign dmu_ncu_siicr_pe_d_ff_scanin = dmu_ncu_d_pe_d_ff_scanout; | |
4992 | assign dmu_ncu_ctag_ue_d_ff_scanin = dmu_ncu_siicr_pe_d_ff_scanout; | |
4993 | assign dmu_ncu_ctag_ce_d_ff_scanin = dmu_ncu_ctag_ue_d_ff_scanout; | |
4994 | assign dmu_ncu_ncucr_pe_d_ff_scanin = dmu_ncu_ctag_ce_d_ff_scanout; | |
4995 | assign dmu_ncu_ie_d_ff_scanin = dmu_ncu_ncucr_pe_d_ff_scanout; | |
4996 | assign sii_ncu_dmua_pe_d_ff_scanin = dmu_ncu_ie_d_ff_scanout ; | |
4997 | assign sii_ncu_niud_pe_d_ff_scanin = sii_ncu_dmua_pe_d_ff_scanout; | |
4998 | assign sii_ncu_dmud_pe_d_ff_scanin = sii_ncu_niud_pe_d_ff_scanout; | |
4999 | assign sii_ncu_niua_pe_d_ff_scanin = sii_ncu_dmud_pe_d_ff_scanout; | |
5000 | assign sii_ncu_dmuctag_ce_d_ff_scanin = sii_ncu_niua_pe_d_ff_scanout; | |
5001 | assign sii_ncu_niuctag_ce_d_ff_scanin = sii_ncu_dmuctag_ce_d_ff_scanout; | |
5002 | assign sii_ncu_dmuctag_ue_d_ff_scanin = sii_ncu_niuctag_ce_d_ff_scanout; | |
5003 | assign sii_ncu_niuctag_ue_d_ff_scanin = sii_ncu_dmuctag_ue_d_ff_scanout; | |
5004 | //assign rasele_ff_scanin = rasesr_v_ff_scanout ; | |
5005 | assign rasele_ff_scanin = sii_ncu_niuctag_ue_d_ff_scanout; | |
5006 | assign raseie_ff_scanin = rasele_ff_scanout ; | |
5007 | assign rasejr_ff_scanin = raseie_ff_scanout ; | |
5008 | assign bit20_d1_ff_scanin = rasejr_ff_scanout ; | |
5009 | assign bit20_d2_ff_scanin = bit20_d1_ff_scanout ; | |
5010 | assign bit20_d3_ff_scanin = bit20_d2_ff_scanout ; | |
5011 | assign bit20_d4_ff_scanin = bit20_d3_ff_scanout ; | |
5012 | assign bit20_d5_ff_scanin = bit20_d4_ff_scanout ; | |
5013 | assign rasfee_ff_scanin = bit20_d5_ff_scanout ; | |
5014 | assign ncu_rst_fatal_error_ff_scanin = rasfee_ff_scanout ; | |
5015 | assign por_upd_en_ff_scanin = ncu_rst_fatal_error_ff_scanout ; | |
5016 | //assign tcu_aclk_d2_ff_scanin = por_upd_en_ff_scanout; | |
5017 | assign rasper_ipg_ff_scanin = por_upd_en_ff_scanout; | |
5018 | assign rasesr2per_tgr_d_ff_scanin = rasper_ipg_ff_scanout ; | |
5019 | assign ncu_tcu_soc_error_ff_scanin = rasesr2per_tgr_d_ff_scanout ; | |
5020 | ////assign scan_out = ncusyn_v_ff_scanout ; | |
5021 | assign scan_out = ncu_tcu_soc_error_ff_scanout; | |
5022 | // fixscan end: | |
5023 | ||
5024 | ||
5025 | ||
5026 | endmodule // iobdg_ctrl | |
5027 | // Local Variables: | |
5028 | // verilog-auto-sense-defines-constant:t | |
5029 | // End: | |
5030 | ||
5031 | ||
5032 | ||
5033 | ||
5034 | ||
5035 | ||
5036 | ||
5037 | ||
5038 | ||
5039 | ||
5040 | ||
5041 | // any PARAMS parms go into naming of macro | |
5042 | ||
5043 | module ncu_ctrl_ctl_msff_ctl_macro__width_1 ( | |
5044 | din, | |
5045 | l1clk, | |
5046 | scan_in, | |
5047 | siclk, | |
5048 | soclk, | |
5049 | dout, | |
5050 | scan_out); | |
5051 | wire [0:0] fdin; | |
5052 | ||
5053 | input [0:0] din; | |
5054 | input l1clk; | |
5055 | input scan_in; | |
5056 | ||
5057 | ||
5058 | input siclk; | |
5059 | input soclk; | |
5060 | ||
5061 | output [0:0] dout; | |
5062 | output scan_out; | |
5063 | assign fdin[0:0] = din[0:0]; | |
5064 | ||
5065 | ||
5066 | ||
5067 | ||
5068 | ||
5069 | ||
5070 | dff #(1) d0_0 ( | |
5071 | .l1clk(l1clk), | |
5072 | .siclk(siclk), | |
5073 | .soclk(soclk), | |
5074 | .d(fdin[0:0]), | |
5075 | .si(scan_in), | |
5076 | .so(scan_out), | |
5077 | .q(dout[0:0]) | |
5078 | ); | |
5079 | ||
5080 | ||
5081 | ||
5082 | ||
5083 | ||
5084 | ||
5085 | ||
5086 | ||
5087 | ||
5088 | ||
5089 | ||
5090 | ||
5091 | endmodule | |
5092 | ||
5093 | ||
5094 | ||
5095 | ||
5096 | ||
5097 | ||
5098 | ||
5099 | ||
5100 | ||
5101 | ||
5102 | ||
5103 | ||
5104 | ||
5105 | // any PARAMS parms go into naming of macro | |
5106 | ||
5107 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_64 ( | |
5108 | din, | |
5109 | en, | |
5110 | l1clk, | |
5111 | scan_in, | |
5112 | siclk, | |
5113 | soclk, | |
5114 | dout, | |
5115 | scan_out); | |
5116 | wire [63:0] fdin; | |
5117 | wire [62:0] so; | |
5118 | ||
5119 | input [63:0] din; | |
5120 | input en; | |
5121 | input l1clk; | |
5122 | input scan_in; | |
5123 | ||
5124 | ||
5125 | input siclk; | |
5126 | input soclk; | |
5127 | ||
5128 | output [63:0] dout; | |
5129 | output scan_out; | |
5130 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); | |
5131 | ||
5132 | ||
5133 | ||
5134 | ||
5135 | ||
5136 | ||
5137 | dff #(64) d0_0 ( | |
5138 | .l1clk(l1clk), | |
5139 | .siclk(siclk), | |
5140 | .soclk(soclk), | |
5141 | .d(fdin[63:0]), | |
5142 | .si({scan_in,so[62:0]}), | |
5143 | .so({so[62:0],scan_out}), | |
5144 | .q(dout[63:0]) | |
5145 | ); | |
5146 | ||
5147 | ||
5148 | ||
5149 | ||
5150 | ||
5151 | ||
5152 | ||
5153 | ||
5154 | ||
5155 | ||
5156 | ||
5157 | ||
5158 | endmodule | |
5159 | ||
5160 | ||
5161 | ||
5162 | ||
5163 | ||
5164 | ||
5165 | ||
5166 | ||
5167 | ||
5168 | ||
5169 | ||
5170 | ||
5171 | ||
5172 | // any PARAMS parms go into naming of macro | |
5173 | ||
5174 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_40 ( | |
5175 | din, | |
5176 | en, | |
5177 | l1clk, | |
5178 | scan_in, | |
5179 | siclk, | |
5180 | soclk, | |
5181 | dout, | |
5182 | scan_out); | |
5183 | wire [39:0] fdin; | |
5184 | wire [38:0] so; | |
5185 | ||
5186 | input [39:0] din; | |
5187 | input en; | |
5188 | input l1clk; | |
5189 | input scan_in; | |
5190 | ||
5191 | ||
5192 | input siclk; | |
5193 | input soclk; | |
5194 | ||
5195 | output [39:0] dout; | |
5196 | output scan_out; | |
5197 | assign fdin[39:0] = (din[39:0] & {40{en}}) | (dout[39:0] & ~{40{en}}); | |
5198 | ||
5199 | ||
5200 | ||
5201 | ||
5202 | ||
5203 | ||
5204 | dff #(40) d0_0 ( | |
5205 | .l1clk(l1clk), | |
5206 | .siclk(siclk), | |
5207 | .soclk(soclk), | |
5208 | .d(fdin[39:0]), | |
5209 | .si({scan_in,so[38:0]}), | |
5210 | .so({so[38:0],scan_out}), | |
5211 | .q(dout[39:0]) | |
5212 | ); | |
5213 | ||
5214 | ||
5215 | ||
5216 | ||
5217 | ||
5218 | ||
5219 | ||
5220 | ||
5221 | ||
5222 | ||
5223 | ||
5224 | ||
5225 | endmodule | |
5226 | ||
5227 | ||
5228 | ||
5229 | ||
5230 | ||
5231 | ||
5232 | ||
5233 | ||
5234 | ||
5235 | ||
5236 | ||
5237 | ||
5238 | ||
5239 | // any PARAMS parms go into naming of macro | |
5240 | ||
5241 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_2 ( | |
5242 | din, | |
5243 | en, | |
5244 | l1clk, | |
5245 | scan_in, | |
5246 | siclk, | |
5247 | soclk, | |
5248 | dout, | |
5249 | scan_out); | |
5250 | wire [1:0] fdin; | |
5251 | wire [0:0] so; | |
5252 | ||
5253 | input [1:0] din; | |
5254 | input en; | |
5255 | input l1clk; | |
5256 | input scan_in; | |
5257 | ||
5258 | ||
5259 | input siclk; | |
5260 | input soclk; | |
5261 | ||
5262 | output [1:0] dout; | |
5263 | output scan_out; | |
5264 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
5265 | ||
5266 | ||
5267 | ||
5268 | ||
5269 | ||
5270 | ||
5271 | dff #(2) d0_0 ( | |
5272 | .l1clk(l1clk), | |
5273 | .siclk(siclk), | |
5274 | .soclk(soclk), | |
5275 | .d(fdin[1:0]), | |
5276 | .si({scan_in,so[0:0]}), | |
5277 | .so({so[0:0],scan_out}), | |
5278 | .q(dout[1:0]) | |
5279 | ); | |
5280 | ||
5281 | ||
5282 | ||
5283 | ||
5284 | ||
5285 | ||
5286 | ||
5287 | ||
5288 | ||
5289 | ||
5290 | ||
5291 | ||
5292 | endmodule | |
5293 | ||
5294 | ||
5295 | ||
5296 | ||
5297 | ||
5298 | ||
5299 | ||
5300 | ||
5301 | ||
5302 | ||
5303 | ||
5304 | ||
5305 | ||
5306 | // any PARAMS parms go into naming of macro | |
5307 | ||
5308 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_6 ( | |
5309 | din, | |
5310 | en, | |
5311 | l1clk, | |
5312 | scan_in, | |
5313 | siclk, | |
5314 | soclk, | |
5315 | dout, | |
5316 | scan_out); | |
5317 | wire [5:0] fdin; | |
5318 | wire [4:0] so; | |
5319 | ||
5320 | input [5:0] din; | |
5321 | input en; | |
5322 | input l1clk; | |
5323 | input scan_in; | |
5324 | ||
5325 | ||
5326 | input siclk; | |
5327 | input soclk; | |
5328 | ||
5329 | output [5:0] dout; | |
5330 | output scan_out; | |
5331 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); | |
5332 | ||
5333 | ||
5334 | ||
5335 | ||
5336 | ||
5337 | ||
5338 | dff #(6) d0_0 ( | |
5339 | .l1clk(l1clk), | |
5340 | .siclk(siclk), | |
5341 | .soclk(soclk), | |
5342 | .d(fdin[5:0]), | |
5343 | .si({scan_in,so[4:0]}), | |
5344 | .so({so[4:0],scan_out}), | |
5345 | .q(dout[5:0]) | |
5346 | ); | |
5347 | ||
5348 | ||
5349 | ||
5350 | ||
5351 | ||
5352 | ||
5353 | ||
5354 | ||
5355 | ||
5356 | ||
5357 | ||
5358 | ||
5359 | endmodule | |
5360 | ||
5361 | ||
5362 | ||
5363 | ||
5364 | ||
5365 | ||
5366 | ||
5367 | ||
5368 | ||
5369 | ||
5370 | ||
5371 | ||
5372 | ||
5373 | // any PARAMS parms go into naming of macro | |
5374 | ||
5375 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_1 ( | |
5376 | din, | |
5377 | en, | |
5378 | l1clk, | |
5379 | scan_in, | |
5380 | siclk, | |
5381 | soclk, | |
5382 | dout, | |
5383 | scan_out); | |
5384 | wire [0:0] fdin; | |
5385 | ||
5386 | input [0:0] din; | |
5387 | input en; | |
5388 | input l1clk; | |
5389 | input scan_in; | |
5390 | ||
5391 | ||
5392 | input siclk; | |
5393 | input soclk; | |
5394 | ||
5395 | output [0:0] dout; | |
5396 | output scan_out; | |
5397 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
5398 | ||
5399 | ||
5400 | ||
5401 | ||
5402 | ||
5403 | ||
5404 | dff #(1) d0_0 ( | |
5405 | .l1clk(l1clk), | |
5406 | .siclk(siclk), | |
5407 | .soclk(soclk), | |
5408 | .d(fdin[0:0]), | |
5409 | .si(scan_in), | |
5410 | .so(scan_out), | |
5411 | .q(dout[0:0]) | |
5412 | ); | |
5413 | ||
5414 | ||
5415 | ||
5416 | ||
5417 | ||
5418 | ||
5419 | ||
5420 | ||
5421 | ||
5422 | ||
5423 | ||
5424 | ||
5425 | endmodule | |
5426 | ||
5427 | ||
5428 | ||
5429 | ||
5430 | ||
5431 | ||
5432 | ||
5433 | ||
5434 | ||
5435 | ||
5436 | ||
5437 | ||
5438 | ||
5439 | // any PARAMS parms go into naming of macro | |
5440 | ||
5441 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_25 ( | |
5442 | din, | |
5443 | en, | |
5444 | l1clk, | |
5445 | scan_in, | |
5446 | siclk, | |
5447 | soclk, | |
5448 | dout, | |
5449 | scan_out); | |
5450 | wire [24:0] fdin; | |
5451 | wire [23:0] so; | |
5452 | ||
5453 | input [24:0] din; | |
5454 | input en; | |
5455 | input l1clk; | |
5456 | input scan_in; | |
5457 | ||
5458 | ||
5459 | input siclk; | |
5460 | input soclk; | |
5461 | ||
5462 | output [24:0] dout; | |
5463 | output scan_out; | |
5464 | assign fdin[24:0] = (din[24:0] & {25{en}}) | (dout[24:0] & ~{25{en}}); | |
5465 | ||
5466 | ||
5467 | ||
5468 | ||
5469 | ||
5470 | ||
5471 | dff #(25) d0_0 ( | |
5472 | .l1clk(l1clk), | |
5473 | .siclk(siclk), | |
5474 | .soclk(soclk), | |
5475 | .d(fdin[24:0]), | |
5476 | .si({scan_in,so[23:0]}), | |
5477 | .so({so[23:0],scan_out}), | |
5478 | .q(dout[24:0]) | |
5479 | ); | |
5480 | ||
5481 | ||
5482 | ||
5483 | ||
5484 | ||
5485 | ||
5486 | ||
5487 | ||
5488 | ||
5489 | ||
5490 | ||
5491 | ||
5492 | endmodule | |
5493 | ||
5494 | ||
5495 | ||
5496 | ||
5497 | ||
5498 | ||
5499 | ||
5500 | ||
5501 | ||
5502 | ||
5503 | ||
5504 | ||
5505 | ||
5506 | // any PARAMS parms go into naming of macro | |
5507 | ||
5508 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_128 ( | |
5509 | din, | |
5510 | en, | |
5511 | l1clk, | |
5512 | scan_in, | |
5513 | siclk, | |
5514 | soclk, | |
5515 | dout, | |
5516 | scan_out); | |
5517 | wire [127:0] fdin; | |
5518 | wire [126:0] so; | |
5519 | ||
5520 | input [127:0] din; | |
5521 | input en; | |
5522 | input l1clk; | |
5523 | input scan_in; | |
5524 | ||
5525 | ||
5526 | input siclk; | |
5527 | input soclk; | |
5528 | ||
5529 | output [127:0] dout; | |
5530 | output scan_out; | |
5531 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); | |
5532 | ||
5533 | ||
5534 | ||
5535 | ||
5536 | ||
5537 | ||
5538 | dff #(128) d0_0 ( | |
5539 | .l1clk(l1clk), | |
5540 | .siclk(siclk), | |
5541 | .soclk(soclk), | |
5542 | .d(fdin[127:0]), | |
5543 | .si({scan_in,so[126:0]}), | |
5544 | .so({so[126:0],scan_out}), | |
5545 | .q(dout[127:0]) | |
5546 | ); | |
5547 | ||
5548 | ||
5549 | ||
5550 | ||
5551 | ||
5552 | ||
5553 | ||
5554 | ||
5555 | ||
5556 | ||
5557 | ||
5558 | ||
5559 | endmodule | |
5560 | ||
5561 | ||
5562 | ||
5563 | ||
5564 | ||
5565 | ||
5566 | ||
5567 | ||
5568 | ||
5569 | ||
5570 | ||
5571 | ||
5572 | ||
5573 | // any PARAMS parms go into naming of macro | |
5574 | ||
5575 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_55 ( | |
5576 | din, | |
5577 | en, | |
5578 | l1clk, | |
5579 | scan_in, | |
5580 | siclk, | |
5581 | soclk, | |
5582 | dout, | |
5583 | scan_out); | |
5584 | wire [54:0] fdin; | |
5585 | wire [53:0] so; | |
5586 | ||
5587 | input [54:0] din; | |
5588 | input en; | |
5589 | input l1clk; | |
5590 | input scan_in; | |
5591 | ||
5592 | ||
5593 | input siclk; | |
5594 | input soclk; | |
5595 | ||
5596 | output [54:0] dout; | |
5597 | output scan_out; | |
5598 | assign fdin[54:0] = (din[54:0] & {55{en}}) | (dout[54:0] & ~{55{en}}); | |
5599 | ||
5600 | ||
5601 | ||
5602 | ||
5603 | ||
5604 | ||
5605 | dff #(55) d0_0 ( | |
5606 | .l1clk(l1clk), | |
5607 | .siclk(siclk), | |
5608 | .soclk(soclk), | |
5609 | .d(fdin[54:0]), | |
5610 | .si({scan_in,so[53:0]}), | |
5611 | .so({so[53:0],scan_out}), | |
5612 | .q(dout[54:0]) | |
5613 | ); | |
5614 | ||
5615 | ||
5616 | ||
5617 | ||
5618 | ||
5619 | ||
5620 | ||
5621 | ||
5622 | ||
5623 | ||
5624 | ||
5625 | ||
5626 | endmodule | |
5627 | ||
5628 | ||
5629 | ||
5630 | ||
5631 | ||
5632 | ||
5633 | ||
5634 | ||
5635 | ||
5636 | ||
5637 | ||
5638 | ||
5639 | ||
5640 | // any PARAMS parms go into naming of macro | |
5641 | ||
5642 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_22 ( | |
5643 | din, | |
5644 | en, | |
5645 | l1clk, | |
5646 | scan_in, | |
5647 | siclk, | |
5648 | soclk, | |
5649 | dout, | |
5650 | scan_out); | |
5651 | wire [21:0] fdin; | |
5652 | wire [20:0] so; | |
5653 | ||
5654 | input [21:0] din; | |
5655 | input en; | |
5656 | input l1clk; | |
5657 | input scan_in; | |
5658 | ||
5659 | ||
5660 | input siclk; | |
5661 | input soclk; | |
5662 | ||
5663 | output [21:0] dout; | |
5664 | output scan_out; | |
5665 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); | |
5666 | ||
5667 | ||
5668 | ||
5669 | ||
5670 | ||
5671 | ||
5672 | dff #(22) d0_0 ( | |
5673 | .l1clk(l1clk), | |
5674 | .siclk(siclk), | |
5675 | .soclk(soclk), | |
5676 | .d(fdin[21:0]), | |
5677 | .si({scan_in,so[20:0]}), | |
5678 | .so({so[20:0],scan_out}), | |
5679 | .q(dout[21:0]) | |
5680 | ); | |
5681 | ||
5682 | ||
5683 | ||
5684 | ||
5685 | ||
5686 | ||
5687 | ||
5688 | ||
5689 | ||
5690 | ||
5691 | ||
5692 | ||
5693 | endmodule | |
5694 | ||
5695 | ||
5696 | ||
5697 | ||
5698 | ||
5699 | ||
5700 | ||
5701 | ||
5702 | ||
5703 | ||
5704 | ||
5705 | ||
5706 | ||
5707 | // any PARAMS parms go into naming of macro | |
5708 | ||
5709 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_20 ( | |
5710 | din, | |
5711 | en, | |
5712 | l1clk, | |
5713 | scan_in, | |
5714 | siclk, | |
5715 | soclk, | |
5716 | dout, | |
5717 | scan_out); | |
5718 | wire [19:0] fdin; | |
5719 | wire [18:0] so; | |
5720 | ||
5721 | input [19:0] din; | |
5722 | input en; | |
5723 | input l1clk; | |
5724 | input scan_in; | |
5725 | ||
5726 | ||
5727 | input siclk; | |
5728 | input soclk; | |
5729 | ||
5730 | output [19:0] dout; | |
5731 | output scan_out; | |
5732 | assign fdin[19:0] = (din[19:0] & {20{en}}) | (dout[19:0] & ~{20{en}}); | |
5733 | ||
5734 | ||
5735 | ||
5736 | ||
5737 | ||
5738 | ||
5739 | dff #(20) d0_0 ( | |
5740 | .l1clk(l1clk), | |
5741 | .siclk(siclk), | |
5742 | .soclk(soclk), | |
5743 | .d(fdin[19:0]), | |
5744 | .si({scan_in,so[18:0]}), | |
5745 | .so({so[18:0],scan_out}), | |
5746 | .q(dout[19:0]) | |
5747 | ); | |
5748 | ||
5749 | ||
5750 | ||
5751 | ||
5752 | ||
5753 | ||
5754 | ||
5755 | ||
5756 | ||
5757 | ||
5758 | ||
5759 | ||
5760 | endmodule | |
5761 | ||
5762 | ||
5763 | ||
5764 | ||
5765 | ||
5766 | ||
5767 | ||
5768 | ||
5769 | ||
5770 | ||
5771 | ||
5772 | ||
5773 | ||
5774 | // any PARAMS parms go into naming of macro | |
5775 | ||
5776 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_8 ( | |
5777 | din, | |
5778 | en, | |
5779 | l1clk, | |
5780 | scan_in, | |
5781 | siclk, | |
5782 | soclk, | |
5783 | dout, | |
5784 | scan_out); | |
5785 | wire [7:0] fdin; | |
5786 | wire [6:0] so; | |
5787 | ||
5788 | input [7:0] din; | |
5789 | input en; | |
5790 | input l1clk; | |
5791 | input scan_in; | |
5792 | ||
5793 | ||
5794 | input siclk; | |
5795 | input soclk; | |
5796 | ||
5797 | output [7:0] dout; | |
5798 | output scan_out; | |
5799 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
5800 | ||
5801 | ||
5802 | ||
5803 | ||
5804 | ||
5805 | ||
5806 | dff #(8) d0_0 ( | |
5807 | .l1clk(l1clk), | |
5808 | .siclk(siclk), | |
5809 | .soclk(soclk), | |
5810 | .d(fdin[7:0]), | |
5811 | .si({scan_in,so[6:0]}), | |
5812 | .so({so[6:0],scan_out}), | |
5813 | .q(dout[7:0]) | |
5814 | ); | |
5815 | ||
5816 | ||
5817 | ||
5818 | ||
5819 | ||
5820 | ||
5821 | ||
5822 | ||
5823 | ||
5824 | ||
5825 | ||
5826 | ||
5827 | endmodule | |
5828 | ||
5829 | ||
5830 | ||
5831 | ||
5832 | ||
5833 | ||
5834 | ||
5835 | ||
5836 | ||
5837 | ||
5838 | ||
5839 | ||
5840 | ||
5841 | // any PARAMS parms go into naming of macro | |
5842 | ||
5843 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_12 ( | |
5844 | din, | |
5845 | en, | |
5846 | l1clk, | |
5847 | scan_in, | |
5848 | siclk, | |
5849 | soclk, | |
5850 | dout, | |
5851 | scan_out); | |
5852 | wire [11:0] fdin; | |
5853 | wire [10:0] so; | |
5854 | ||
5855 | input [11:0] din; | |
5856 | input en; | |
5857 | input l1clk; | |
5858 | input scan_in; | |
5859 | ||
5860 | ||
5861 | input siclk; | |
5862 | input soclk; | |
5863 | ||
5864 | output [11:0] dout; | |
5865 | output scan_out; | |
5866 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
5867 | ||
5868 | ||
5869 | ||
5870 | ||
5871 | ||
5872 | ||
5873 | dff #(12) d0_0 ( | |
5874 | .l1clk(l1clk), | |
5875 | .siclk(siclk), | |
5876 | .soclk(soclk), | |
5877 | .d(fdin[11:0]), | |
5878 | .si({scan_in,so[10:0]}), | |
5879 | .so({so[10:0],scan_out}), | |
5880 | .q(dout[11:0]) | |
5881 | ); | |
5882 | ||
5883 | ||
5884 | ||
5885 | ||
5886 | ||
5887 | ||
5888 | ||
5889 | ||
5890 | ||
5891 | ||
5892 | ||
5893 | ||
5894 | endmodule | |
5895 | ||
5896 | ||
5897 | ||
5898 | ||
5899 | ||
5900 | ||
5901 | ||
5902 | ||
5903 | ||
5904 | ||
5905 | ||
5906 | ||
5907 | ||
5908 | // any PARAMS parms go into naming of macro | |
5909 | ||
5910 | module ncu_ctrl_ctl_msff_ctl_macro__width_6 ( | |
5911 | din, | |
5912 | l1clk, | |
5913 | scan_in, | |
5914 | siclk, | |
5915 | soclk, | |
5916 | dout, | |
5917 | scan_out); | |
5918 | wire [5:0] fdin; | |
5919 | wire [4:0] so; | |
5920 | ||
5921 | input [5:0] din; | |
5922 | input l1clk; | |
5923 | input scan_in; | |
5924 | ||
5925 | ||
5926 | input siclk; | |
5927 | input soclk; | |
5928 | ||
5929 | output [5:0] dout; | |
5930 | output scan_out; | |
5931 | assign fdin[5:0] = din[5:0]; | |
5932 | ||
5933 | ||
5934 | ||
5935 | ||
5936 | ||
5937 | ||
5938 | dff #(6) d0_0 ( | |
5939 | .l1clk(l1clk), | |
5940 | .siclk(siclk), | |
5941 | .soclk(soclk), | |
5942 | .d(fdin[5:0]), | |
5943 | .si({scan_in,so[4:0]}), | |
5944 | .so({so[4:0],scan_out}), | |
5945 | .q(dout[5:0]) | |
5946 | ); | |
5947 | ||
5948 | ||
5949 | ||
5950 | ||
5951 | ||
5952 | ||
5953 | ||
5954 | ||
5955 | ||
5956 | ||
5957 | ||
5958 | ||
5959 | endmodule | |
5960 | ||
5961 | ||
5962 | ||
5963 | ||
5964 | ||
5965 | ||
5966 | ||
5967 | ||
5968 | ||
5969 | ||
5970 | ||
5971 | ||
5972 | ||
5973 | // any PARAMS parms go into naming of macro | |
5974 | ||
5975 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_24 ( | |
5976 | din, | |
5977 | en, | |
5978 | l1clk, | |
5979 | scan_in, | |
5980 | siclk, | |
5981 | soclk, | |
5982 | dout, | |
5983 | scan_out); | |
5984 | wire [23:0] fdin; | |
5985 | wire [22:0] so; | |
5986 | ||
5987 | input [23:0] din; | |
5988 | input en; | |
5989 | input l1clk; | |
5990 | input scan_in; | |
5991 | ||
5992 | ||
5993 | input siclk; | |
5994 | input soclk; | |
5995 | ||
5996 | output [23:0] dout; | |
5997 | output scan_out; | |
5998 | assign fdin[23:0] = (din[23:0] & {24{en}}) | (dout[23:0] & ~{24{en}}); | |
5999 | ||
6000 | ||
6001 | ||
6002 | ||
6003 | ||
6004 | ||
6005 | dff #(24) d0_0 ( | |
6006 | .l1clk(l1clk), | |
6007 | .siclk(siclk), | |
6008 | .soclk(soclk), | |
6009 | .d(fdin[23:0]), | |
6010 | .si({scan_in,so[22:0]}), | |
6011 | .so({so[22:0],scan_out}), | |
6012 | .q(dout[23:0]) | |
6013 | ); | |
6014 | ||
6015 | ||
6016 | ||
6017 | ||
6018 | ||
6019 | ||
6020 | ||
6021 | ||
6022 | ||
6023 | ||
6024 | ||
6025 | ||
6026 | endmodule | |
6027 | ||
6028 | ||
6029 | ||
6030 | ||
6031 | ||
6032 | ||
6033 | ||
6034 | ||
6035 | ||
6036 | ||
6037 | ||
6038 | ||
6039 | ||
6040 | // any PARAMS parms go into naming of macro | |
6041 | ||
6042 | module ncu_ctrl_ctl_msff_ctl_macro__width_64 ( | |
6043 | din, | |
6044 | l1clk, | |
6045 | scan_in, | |
6046 | siclk, | |
6047 | soclk, | |
6048 | dout, | |
6049 | scan_out); | |
6050 | wire [63:0] fdin; | |
6051 | wire [62:0] so; | |
6052 | ||
6053 | input [63:0] din; | |
6054 | input l1clk; | |
6055 | input scan_in; | |
6056 | ||
6057 | ||
6058 | input siclk; | |
6059 | input soclk; | |
6060 | ||
6061 | output [63:0] dout; | |
6062 | output scan_out; | |
6063 | assign fdin[63:0] = din[63:0]; | |
6064 | ||
6065 | ||
6066 | ||
6067 | ||
6068 | ||
6069 | ||
6070 | dff #(64) d0_0 ( | |
6071 | .l1clk(l1clk), | |
6072 | .siclk(siclk), | |
6073 | .soclk(soclk), | |
6074 | .d(fdin[63:0]), | |
6075 | .si({scan_in,so[62:0]}), | |
6076 | .so({so[62:0],scan_out}), | |
6077 | .q(dout[63:0]) | |
6078 | ); | |
6079 | ||
6080 | ||
6081 | ||
6082 | ||
6083 | ||
6084 | ||
6085 | ||
6086 | ||
6087 | ||
6088 | ||
6089 | ||
6090 | ||
6091 | endmodule | |
6092 | ||
6093 | ||
6094 | ||
6095 | ||
6096 | ||
6097 | ||
6098 | ||
6099 | ||
6100 | ||
6101 | ||
6102 | ||
6103 | ||
6104 | ||
6105 | // any PARAMS parms go into naming of macro | |
6106 | ||
6107 | module ncu_ctrl_ctl_msff_ctl_macro__width_8 ( | |
6108 | din, | |
6109 | l1clk, | |
6110 | scan_in, | |
6111 | siclk, | |
6112 | soclk, | |
6113 | dout, | |
6114 | scan_out); | |
6115 | wire [7:0] fdin; | |
6116 | wire [6:0] so; | |
6117 | ||
6118 | input [7:0] din; | |
6119 | input l1clk; | |
6120 | input scan_in; | |
6121 | ||
6122 | ||
6123 | input siclk; | |
6124 | input soclk; | |
6125 | ||
6126 | output [7:0] dout; | |
6127 | output scan_out; | |
6128 | assign fdin[7:0] = din[7:0]; | |
6129 | ||
6130 | ||
6131 | ||
6132 | ||
6133 | ||
6134 | ||
6135 | dff #(8) d0_0 ( | |
6136 | .l1clk(l1clk), | |
6137 | .siclk(siclk), | |
6138 | .soclk(soclk), | |
6139 | .d(fdin[7:0]), | |
6140 | .si({scan_in,so[6:0]}), | |
6141 | .so({so[6:0],scan_out}), | |
6142 | .q(dout[7:0]) | |
6143 | ); | |
6144 | ||
6145 | ||
6146 | ||
6147 | ||
6148 | ||
6149 | ||
6150 | ||
6151 | ||
6152 | ||
6153 | ||
6154 | ||
6155 | ||
6156 | endmodule | |
6157 | ||
6158 | ||
6159 | ||
6160 | ||
6161 | ||
6162 | ||
6163 | ||
6164 | ||
6165 | ||
6166 | ||
6167 | ||
6168 | ||
6169 | ||
6170 | // any PARAMS parms go into naming of macro | |
6171 | ||
6172 | module ncu_ctrl_ctl_msffi_ctl_macro__width_1 ( | |
6173 | din, | |
6174 | l1clk, | |
6175 | scan_in, | |
6176 | siclk, | |
6177 | soclk, | |
6178 | q_l, | |
6179 | scan_out); | |
6180 | input [0:0] din; | |
6181 | input l1clk; | |
6182 | input scan_in; | |
6183 | ||
6184 | ||
6185 | input siclk; | |
6186 | input soclk; | |
6187 | ||
6188 | output [0:0] q_l; | |
6189 | output scan_out; | |
6190 | ||
6191 | ||
6192 | ||
6193 | ||
6194 | ||
6195 | ||
6196 | msffi #(1) d0_0 ( | |
6197 | .l1clk(l1clk), | |
6198 | .siclk(siclk), | |
6199 | .soclk(soclk), | |
6200 | .d(din[0:0]), | |
6201 | .si(scan_in), | |
6202 | .so(scan_out), | |
6203 | .q_l(q_l[0:0]) | |
6204 | ); | |
6205 | ||
6206 | ||
6207 | ||
6208 | ||
6209 | ||
6210 | ||
6211 | ||
6212 | ||
6213 | ||
6214 | ||
6215 | ||
6216 | ||
6217 | endmodule | |
6218 | ||
6219 | ||
6220 | ||
6221 | ||
6222 | ||
6223 | ||
6224 | ||
6225 | ||
6226 | ||
6227 | ||
6228 | ||
6229 | ||
6230 | ||
6231 | // any PARAMS parms go into naming of macro | |
6232 | ||
6233 | module ncu_ctrl_ctl_msff_ctl_macro__width_56 ( | |
6234 | din, | |
6235 | l1clk, | |
6236 | scan_in, | |
6237 | siclk, | |
6238 | soclk, | |
6239 | dout, | |
6240 | scan_out); | |
6241 | wire [55:0] fdin; | |
6242 | wire [54:0] so; | |
6243 | ||
6244 | input [55:0] din; | |
6245 | input l1clk; | |
6246 | input scan_in; | |
6247 | ||
6248 | ||
6249 | input siclk; | |
6250 | input soclk; | |
6251 | ||
6252 | output [55:0] dout; | |
6253 | output scan_out; | |
6254 | assign fdin[55:0] = din[55:0]; | |
6255 | ||
6256 | ||
6257 | ||
6258 | ||
6259 | ||
6260 | ||
6261 | dff #(56) d0_0 ( | |
6262 | .l1clk(l1clk), | |
6263 | .siclk(siclk), | |
6264 | .soclk(soclk), | |
6265 | .d(fdin[55:0]), | |
6266 | .si({scan_in,so[54:0]}), | |
6267 | .so({so[54:0],scan_out}), | |
6268 | .q(dout[55:0]) | |
6269 | ); | |
6270 | ||
6271 | ||
6272 | ||
6273 | ||
6274 | ||
6275 | ||
6276 | ||
6277 | ||
6278 | ||
6279 | ||
6280 | ||
6281 | ||
6282 | endmodule | |
6283 | ||
6284 | ||
6285 | ||
6286 | ||
6287 | ||
6288 | ||
6289 | ||
6290 | ||
6291 | ||
6292 | ||
6293 | ||
6294 | ||
6295 | ||
6296 | // any PARAMS parms go into naming of macro | |
6297 | ||
6298 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_3 ( | |
6299 | din, | |
6300 | en, | |
6301 | l1clk, | |
6302 | scan_in, | |
6303 | siclk, | |
6304 | soclk, | |
6305 | dout, | |
6306 | scan_out); | |
6307 | wire [2:0] fdin; | |
6308 | wire [1:0] so; | |
6309 | ||
6310 | input [2:0] din; | |
6311 | input en; | |
6312 | input l1clk; | |
6313 | input scan_in; | |
6314 | ||
6315 | ||
6316 | input siclk; | |
6317 | input soclk; | |
6318 | ||
6319 | output [2:0] dout; | |
6320 | output scan_out; | |
6321 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
6322 | ||
6323 | ||
6324 | ||
6325 | ||
6326 | ||
6327 | ||
6328 | dff #(3) d0_0 ( | |
6329 | .l1clk(l1clk), | |
6330 | .siclk(siclk), | |
6331 | .soclk(soclk), | |
6332 | .d(fdin[2:0]), | |
6333 | .si({scan_in,so[1:0]}), | |
6334 | .so({so[1:0],scan_out}), | |
6335 | .q(dout[2:0]) | |
6336 | ); | |
6337 | ||
6338 | ||
6339 | ||
6340 | ||
6341 | ||
6342 | ||
6343 | ||
6344 | ||
6345 | ||
6346 | ||
6347 | ||
6348 | ||
6349 | endmodule | |
6350 | ||
6351 | ||
6352 | ||
6353 | ||
6354 | ||
6355 | ||
6356 | ||
6357 | ||
6358 | ||
6359 | ||
6360 | ||
6361 | ||
6362 | ||
6363 | // any PARAMS parms go into naming of macro | |
6364 | ||
6365 | module ncu_ctrl_ctl_msff_ctl_macro__width_63 ( | |
6366 | din, | |
6367 | l1clk, | |
6368 | scan_in, | |
6369 | siclk, | |
6370 | soclk, | |
6371 | dout, | |
6372 | scan_out); | |
6373 | wire [62:0] fdin; | |
6374 | wire [61:0] so; | |
6375 | ||
6376 | input [62:0] din; | |
6377 | input l1clk; | |
6378 | input scan_in; | |
6379 | ||
6380 | ||
6381 | input siclk; | |
6382 | input soclk; | |
6383 | ||
6384 | output [62:0] dout; | |
6385 | output scan_out; | |
6386 | assign fdin[62:0] = din[62:0]; | |
6387 | ||
6388 | ||
6389 | ||
6390 | ||
6391 | ||
6392 | ||
6393 | dff #(63) d0_0 ( | |
6394 | .l1clk(l1clk), | |
6395 | .siclk(siclk), | |
6396 | .soclk(soclk), | |
6397 | .d(fdin[62:0]), | |
6398 | .si({scan_in,so[61:0]}), | |
6399 | .so({so[61:0],scan_out}), | |
6400 | .q(dout[62:0]) | |
6401 | ); | |
6402 | ||
6403 | ||
6404 | ||
6405 | ||
6406 | ||
6407 | ||
6408 | ||
6409 | ||
6410 | ||
6411 | ||
6412 | ||
6413 | ||
6414 | endmodule | |
6415 | ||
6416 | ||
6417 | ||
6418 | ||
6419 | ||
6420 | ||
6421 | ||
6422 | ||
6423 | ||
6424 | ||
6425 | ||
6426 | ||
6427 | ||
6428 | // any PARAMS parms go into naming of macro | |
6429 | ||
6430 | module ncu_ctrl_ctl_msff_ctl_macro__width_5 ( | |
6431 | din, | |
6432 | l1clk, | |
6433 | scan_in, | |
6434 | siclk, | |
6435 | soclk, | |
6436 | dout, | |
6437 | scan_out); | |
6438 | wire [4:0] fdin; | |
6439 | wire [3:0] so; | |
6440 | ||
6441 | input [4:0] din; | |
6442 | input l1clk; | |
6443 | input scan_in; | |
6444 | ||
6445 | ||
6446 | input siclk; | |
6447 | input soclk; | |
6448 | ||
6449 | output [4:0] dout; | |
6450 | output scan_out; | |
6451 | assign fdin[4:0] = din[4:0]; | |
6452 | ||
6453 | ||
6454 | ||
6455 | ||
6456 | ||
6457 | ||
6458 | dff #(5) d0_0 ( | |
6459 | .l1clk(l1clk), | |
6460 | .siclk(siclk), | |
6461 | .soclk(soclk), | |
6462 | .d(fdin[4:0]), | |
6463 | .si({scan_in,so[3:0]}), | |
6464 | .so({so[3:0],scan_out}), | |
6465 | .q(dout[4:0]) | |
6466 | ); | |
6467 | ||
6468 | ||
6469 | ||
6470 | ||
6471 | ||
6472 | ||
6473 | ||
6474 | ||
6475 | ||
6476 | ||
6477 | ||
6478 | ||
6479 | endmodule | |
6480 | ||
6481 | ||
6482 | ||
6483 | ||
6484 | ||
6485 | ||
6486 | ||
6487 | ||
6488 | ||
6489 | ||
6490 | ||
6491 | ||
6492 | ||
6493 | // any PARAMS parms go into naming of macro | |
6494 | ||
6495 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_5 ( | |
6496 | din, | |
6497 | en, | |
6498 | l1clk, | |
6499 | scan_in, | |
6500 | siclk, | |
6501 | soclk, | |
6502 | dout, | |
6503 | scan_out); | |
6504 | wire [4:0] fdin; | |
6505 | wire [3:0] so; | |
6506 | ||
6507 | input [4:0] din; | |
6508 | input en; | |
6509 | input l1clk; | |
6510 | input scan_in; | |
6511 | ||
6512 | ||
6513 | input siclk; | |
6514 | input soclk; | |
6515 | ||
6516 | output [4:0] dout; | |
6517 | output scan_out; | |
6518 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
6519 | ||
6520 | ||
6521 | ||
6522 | ||
6523 | ||
6524 | ||
6525 | dff #(5) d0_0 ( | |
6526 | .l1clk(l1clk), | |
6527 | .siclk(siclk), | |
6528 | .soclk(soclk), | |
6529 | .d(fdin[4:0]), | |
6530 | .si({scan_in,so[3:0]}), | |
6531 | .so({so[3:0],scan_out}), | |
6532 | .q(dout[4:0]) | |
6533 | ); | |
6534 | ||
6535 | ||
6536 | ||
6537 | ||
6538 | ||
6539 | ||
6540 | ||
6541 | ||
6542 | ||
6543 | ||
6544 | ||
6545 | ||
6546 | endmodule | |
6547 | ||
6548 | ||
6549 | ||
6550 | ||
6551 | ||
6552 | ||
6553 | ||
6554 | ||
6555 | ||
6556 | ||
6557 | ||
6558 | ||
6559 | ||
6560 | // any PARAMS parms go into naming of macro | |
6561 | ||
6562 | module ncu_ctrl_ctl_msff_ctl_macro__width_43 ( | |
6563 | din, | |
6564 | l1clk, | |
6565 | scan_in, | |
6566 | siclk, | |
6567 | soclk, | |
6568 | dout, | |
6569 | scan_out); | |
6570 | wire [42:0] fdin; | |
6571 | wire [41:0] so; | |
6572 | ||
6573 | input [42:0] din; | |
6574 | input l1clk; | |
6575 | input scan_in; | |
6576 | ||
6577 | ||
6578 | input siclk; | |
6579 | input soclk; | |
6580 | ||
6581 | output [42:0] dout; | |
6582 | output scan_out; | |
6583 | assign fdin[42:0] = din[42:0]; | |
6584 | ||
6585 | ||
6586 | ||
6587 | ||
6588 | ||
6589 | ||
6590 | dff #(43) d0_0 ( | |
6591 | .l1clk(l1clk), | |
6592 | .siclk(siclk), | |
6593 | .soclk(soclk), | |
6594 | .d(fdin[42:0]), | |
6595 | .si({scan_in,so[41:0]}), | |
6596 | .so({so[41:0],scan_out}), | |
6597 | .q(dout[42:0]) | |
6598 | ); | |
6599 | ||
6600 | ||
6601 | ||
6602 | ||
6603 | ||
6604 | ||
6605 | ||
6606 | ||
6607 | ||
6608 | ||
6609 | ||
6610 | ||
6611 | endmodule | |
6612 | ||
6613 | ||
6614 | ||
6615 | ||
6616 | ||
6617 | ||
6618 | ||
6619 | ||
6620 | ||
6621 | ||
6622 | ||
6623 | ||
6624 | ||
6625 | // any PARAMS parms go into naming of macro | |
6626 | ||
6627 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_43 ( | |
6628 | din, | |
6629 | en, | |
6630 | l1clk, | |
6631 | scan_in, | |
6632 | siclk, | |
6633 | soclk, | |
6634 | dout, | |
6635 | scan_out); | |
6636 | wire [42:0] fdin; | |
6637 | wire [41:0] so; | |
6638 | ||
6639 | input [42:0] din; | |
6640 | input en; | |
6641 | input l1clk; | |
6642 | input scan_in; | |
6643 | ||
6644 | ||
6645 | input siclk; | |
6646 | input soclk; | |
6647 | ||
6648 | output [42:0] dout; | |
6649 | output scan_out; | |
6650 | assign fdin[42:0] = (din[42:0] & {43{en}}) | (dout[42:0] & ~{43{en}}); | |
6651 | ||
6652 | ||
6653 | ||
6654 | ||
6655 | ||
6656 | ||
6657 | dff #(43) d0_0 ( | |
6658 | .l1clk(l1clk), | |
6659 | .siclk(siclk), | |
6660 | .soclk(soclk), | |
6661 | .d(fdin[42:0]), | |
6662 | .si({scan_in,so[41:0]}), | |
6663 | .so({so[41:0],scan_out}), | |
6664 | .q(dout[42:0]) | |
6665 | ); | |
6666 | ||
6667 | ||
6668 | ||
6669 | ||
6670 | ||
6671 | ||
6672 | ||
6673 | ||
6674 | ||
6675 | ||
6676 | ||
6677 | ||
6678 | endmodule | |
6679 | ||
6680 | ||
6681 | ||
6682 | ||
6683 | ||
6684 | ||
6685 | ||
6686 | ||
6687 | ||
6688 | ||
6689 | ||
6690 | ||
6691 | ||
6692 | // any PARAMS parms go into naming of macro | |
6693 | ||
6694 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_59 ( | |
6695 | din, | |
6696 | en, | |
6697 | l1clk, | |
6698 | scan_in, | |
6699 | siclk, | |
6700 | soclk, | |
6701 | dout, | |
6702 | scan_out); | |
6703 | wire [58:0] fdin; | |
6704 | wire [57:0] so; | |
6705 | ||
6706 | input [58:0] din; | |
6707 | input en; | |
6708 | input l1clk; | |
6709 | input scan_in; | |
6710 | ||
6711 | ||
6712 | input siclk; | |
6713 | input soclk; | |
6714 | ||
6715 | output [58:0] dout; | |
6716 | output scan_out; | |
6717 | assign fdin[58:0] = (din[58:0] & {59{en}}) | (dout[58:0] & ~{59{en}}); | |
6718 | ||
6719 | ||
6720 | ||
6721 | ||
6722 | ||
6723 | ||
6724 | dff #(59) d0_0 ( | |
6725 | .l1clk(l1clk), | |
6726 | .siclk(siclk), | |
6727 | .soclk(soclk), | |
6728 | .d(fdin[58:0]), | |
6729 | .si({scan_in,so[57:0]}), | |
6730 | .so({so[57:0],scan_out}), | |
6731 | .q(dout[58:0]) | |
6732 | ); | |
6733 | ||
6734 | ||
6735 | ||
6736 | ||
6737 | ||
6738 | ||
6739 | ||
6740 | ||
6741 | ||
6742 | ||
6743 | ||
6744 | ||
6745 | endmodule | |
6746 | ||
6747 | ||
6748 | ||
6749 | ||
6750 | ||
6751 | ||
6752 | ||
6753 | ||
6754 | ||
6755 | ||
6756 | ||
6757 | ||
6758 | ||
6759 | // any PARAMS parms go into naming of macro | |
6760 | ||
6761 | module ncu_ctrl_ctl_msff_ctl_macro__en_1__width_61 ( | |
6762 | din, | |
6763 | en, | |
6764 | l1clk, | |
6765 | scan_in, | |
6766 | siclk, | |
6767 | soclk, | |
6768 | dout, | |
6769 | scan_out); | |
6770 | wire [60:0] fdin; | |
6771 | wire [59:0] so; | |
6772 | ||
6773 | input [60:0] din; | |
6774 | input en; | |
6775 | input l1clk; | |
6776 | input scan_in; | |
6777 | ||
6778 | ||
6779 | input siclk; | |
6780 | input soclk; | |
6781 | ||
6782 | output [60:0] dout; | |
6783 | output scan_out; | |
6784 | assign fdin[60:0] = (din[60:0] & {61{en}}) | (dout[60:0] & ~{61{en}}); | |
6785 | ||
6786 | ||
6787 | ||
6788 | ||
6789 | ||
6790 | ||
6791 | dff #(61) d0_0 ( | |
6792 | .l1clk(l1clk), | |
6793 | .siclk(siclk), | |
6794 | .soclk(soclk), | |
6795 | .d(fdin[60:0]), | |
6796 | .si({scan_in,so[59:0]}), | |
6797 | .so({so[59:0],scan_out}), | |
6798 | .q(dout[60:0]) | |
6799 | ); | |
6800 | ||
6801 | ||
6802 | ||
6803 | ||
6804 | ||
6805 | ||
6806 | ||
6807 | ||
6808 | ||
6809 | ||
6810 | ||
6811 | ||
6812 | endmodule | |
6813 | ||
6814 | ||
6815 | ||
6816 | ||
6817 | ||
6818 | ||
6819 | ||
6820 | ||
6821 | ||
6822 | ||
6823 | ||
6824 | ||
6825 | ||
6826 | // any PARAMS parms go into naming of macro | |
6827 | ||
6828 | module ncu_ctrl_ctl_msff_ctl_macro__width_2 ( | |
6829 | din, | |
6830 | l1clk, | |
6831 | scan_in, | |
6832 | siclk, | |
6833 | soclk, | |
6834 | dout, | |
6835 | scan_out); | |
6836 | wire [1:0] fdin; | |
6837 | wire [0:0] so; | |
6838 | ||
6839 | input [1:0] din; | |
6840 | input l1clk; | |
6841 | input scan_in; | |
6842 | ||
6843 | ||
6844 | input siclk; | |
6845 | input soclk; | |
6846 | ||
6847 | output [1:0] dout; | |
6848 | output scan_out; | |
6849 | assign fdin[1:0] = din[1:0]; | |
6850 | ||
6851 | ||
6852 | ||
6853 | ||
6854 | ||
6855 | ||
6856 | dff #(2) d0_0 ( | |
6857 | .l1clk(l1clk), | |
6858 | .siclk(siclk), | |
6859 | .soclk(soclk), | |
6860 | .d(fdin[1:0]), | |
6861 | .si({scan_in,so[0:0]}), | |
6862 | .so({so[0:0],scan_out}), | |
6863 | .q(dout[1:0]) | |
6864 | ); | |
6865 | ||
6866 | ||
6867 | ||
6868 | ||
6869 | ||
6870 | ||
6871 | ||
6872 | ||
6873 | ||
6874 | ||
6875 | ||
6876 | ||
6877 | endmodule | |
6878 | ||
6879 | ||
6880 | ||
6881 | ||
6882 | ||
6883 | ||
6884 | ||
6885 | ||
6886 | ||
6887 | ||
6888 | ||
6889 | ||
6890 | ||
6891 | // any PARAMS parms go into naming of macro | |
6892 | ||
6893 | module ncu_ctrl_ctl_l1clkhdr_ctl_macro ( | |
6894 | l2clk, | |
6895 | l1en, | |
6896 | pce_ov, | |
6897 | stop, | |
6898 | se, | |
6899 | l1clk); | |
6900 | ||
6901 | ||
6902 | input l2clk; | |
6903 | input l1en; | |
6904 | input pce_ov; | |
6905 | input stop; | |
6906 | input se; | |
6907 | output l1clk; | |
6908 | ||
6909 | ||
6910 | ||
6911 | ||
6912 | ||
6913 | cl_sc1_l1hdr_8x c_0 ( | |
6914 | ||
6915 | ||
6916 | .l2clk(l2clk), | |
6917 | .pce(l1en), | |
6918 | .l1clk(l1clk), | |
6919 | .se(se), | |
6920 | .pce_ov(pce_ov), | |
6921 | .stop(stop) | |
6922 | ); | |
6923 | ||
6924 | ||
6925 | ||
6926 | endmodule | |
6927 | ||
6928 | ||
6929 | ||
6930 | ||
6931 | ||
6932 | ||
6933 | ||
6934 |