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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_i2cbuftcu_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define RF_RDEN_OFFSTATE 1'b1 | |
36 | ||
37 | //==================================== | |
38 | `define NCU_INTMANRF_DEPTH 128 | |
39 | `define NCU_INTMANRF_DATAWIDTH 16 | |
40 | `define NCU_INTMANRF_ADDRWIDTH 7 | |
41 | //==================================== | |
42 | ||
43 | //==================================== | |
44 | `define NCU_MONDORF_DEPTH 64 | |
45 | `define NCU_MONDORF_DATAWIDTH 72 | |
46 | `define NCU_MONDORF_ADDRWIDTH 6 | |
47 | //==================================== | |
48 | ||
49 | //==================================== | |
50 | `define NCU_CPUBUFRF_DEPTH 32 | |
51 | `define NCU_CPUBUFRF_DATAWIDTH 144 | |
52 | `define NCU_CPUBUFRF_ADDRWIDTH 5 | |
53 | //==================================== | |
54 | ||
55 | //==================================== | |
56 | `define NCU_IOBUFRF_DEPTH 32 | |
57 | `define NCU_IOBUFRF_DATAWIDTH 144 | |
58 | `define NCU_IOBUFRF_ADDRWIDTH 5 | |
59 | //==================================== | |
60 | ||
61 | //==================================== | |
62 | `define NCU_IOBUF1RF_DEPTH 32 | |
63 | `define NCU_IOBUF1RF_DATAWIDTH 32 | |
64 | `define NCU_IOBUF1RF_ADDRWIDTH 5 | |
65 | //==================================== | |
66 | ||
67 | //==================================== | |
68 | `define NCU_INTBUFRF_DEPTH 32 | |
69 | `define NCU_INTBUFRF_DATAWIDTH 144 | |
70 | `define NCU_INTBUFRF_ADDRWIDTH 5 | |
71 | //==================================== | |
72 | ||
73 | //== fix me : need to remove when warm // | |
74 | //== becomes available // | |
75 | `define WMR_LENGTH 10'd999 | |
76 | `define WMR_LENGTH_P1 10'd1000 | |
77 | ||
78 | //// NCU CSR_MAN address 80_0000_xxxx //// | |
79 | `define NCU_CSR_MAN 16'h0000 | |
80 | `define NCU_CREG_INTMAN 16'h0000 | |
81 | //`define NCU_CREG_INTVECDISP 16'h0800 | |
82 | `define NCU_CREG_MONDOINVEC 16'h0a00 | |
83 | `define NCU_CREG_SERNUM 16'h1000 | |
84 | `define NCU_CREG_FUSESTAT 16'h1008 | |
85 | `define NCU_CREG_COREAVAIL 16'h1010 | |
86 | `define NCU_CREG_BANKAVAIL 16'h1018 | |
87 | `define NCU_CREG_BANK_ENABLE 16'h1020 | |
88 | `define NCU_CREG_BANK_ENABLE_STATUS 16'h1028 | |
89 | `define NCU_CREG_L2_HASH_ENABLE 16'h1030 | |
90 | `define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038 | |
91 | ||
92 | ||
93 | `define NCU_CREG_MEM32_BASE 16'h2000 | |
94 | `define NCU_CREG_MEM32_MASK 16'h2008 | |
95 | `define NCU_CREG_MEM64_BASE 16'h2010 | |
96 | `define NCU_CREG_MEM64_MASK 16'h2018 | |
97 | `define NCU_CREG_IOCON_BASE 16'h2020 | |
98 | `define NCU_CREG_IOCON_MASK 16'h2028 | |
99 | `define NCU_CREG_MMUFSH 16'h2030 | |
100 | ||
101 | `define NCU_CREG_ESR 16'h3000 | |
102 | `define NCU_CREG_ELE 16'h3008 | |
103 | `define NCU_CREG_EIE 16'h3010 | |
104 | `define NCU_CREG_EJR 16'h3018 | |
105 | `define NCU_CREG_FEE 16'h3020 | |
106 | `define NCU_CREG_PER 16'h3028 | |
107 | `define NCU_CREG_SIISYN 16'h3030 | |
108 | `define NCU_CREG_NCUSYN 16'h3038 | |
109 | `define NCU_CREG_SCKSEL 16'h3040 | |
110 | `define NCU_CREG_DBGTRIG_EN 16'h4000 | |
111 | ||
112 | //// NUC CSR_MONDO address 80_0004_xxxx //// | |
113 | `define NCU_CSR_MONDO 16'h0004 | |
114 | `define NCU_CREG_MDATA0 16'h0000 | |
115 | `define NCU_CREG_MDATA1 16'h0200 | |
116 | `define NCU_CREG_MDATA0_ALIAS 16'h0400 | |
117 | `define NCU_CREG_MDATA1_ALIAS 16'h0600 | |
118 | `define NCU_CREG_MBUSY 16'h0800 | |
119 | `define NCU_CREG_MBUSY_ALIAS 16'h0a00 | |
120 | ||
121 | ||
122 | ||
123 | // ASI shared reg 90_xxxx_xxxx// | |
124 | `define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x" | |
125 | `define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x" | |
126 | `define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x" | |
127 | `define NCU_ASI_COREAVAIL 16'h0000 | |
128 | `define NCU_ASI_CORE_ENABLE_STATUS 16'h0010 | |
129 | `define NCU_ASI_CORE_ENABLE 16'h0020 | |
130 | `define NCU_ASI_XIR_STEERING 16'h0030 | |
131 | `define NCU_ASI_CORE_RUNNINGRW 16'h0050 | |
132 | `define NCU_ASI_CORE_RUNNING_STATUS 16'h0058 | |
133 | `define NCU_ASI_CORE_RUNNING_W1S 16'h0060 | |
134 | `define NCU_ASI_CORE_RUNNING_W1C 16'h0068 | |
135 | `define NCU_ASI_INTVECDISP 16'h0000 | |
136 | `define NCU_ASI_ERR_STR 16'h1000 | |
137 | `define NCU_ASI_WMR_VEC_MASK 16'h0018 | |
138 | `define NCU_ASI_CMP_TICK_ENABLE 16'h0038 | |
139 | ||
140 | ||
141 | //// UCB packet type //// | |
142 | `define UCB_READ_NACK 4'b0000 // ack/nack types | |
143 | `define UCB_READ_ACK 4'b0001 | |
144 | `define UCB_WRITE_ACK 4'b0010 | |
145 | `define UCB_IFILL_ACK 4'b0011 | |
146 | `define UCB_IFILL_NACK 4'b0111 | |
147 | ||
148 | `define UCB_READ_REQ 4'b0100 // req types | |
149 | `define UCB_WRITE_REQ 4'b0101 | |
150 | `define UCB_IFILL_REQ 4'b0110 | |
151 | ||
152 | `define UCB_INT 4'b1000 // plain interrupt | |
153 | `define UCB_INT_VEC 4'b1100 // interrupt with vector | |
154 | `define UCB_INT_SOC_UE 4'b1001 // soc interrup ue | |
155 | `define UCB_INT_SOC_CE 4'b1010 // soc interrup ce | |
156 | `define UCB_RESET_VEC 4'b0101 // reset with vector | |
157 | `define UCB_IDLE_VEC 4'b1110 // idle with vector | |
158 | `define UCB_RESUME_VEC 4'b1111 // resume with vector | |
159 | ||
160 | `define UCB_INT_SOC 4'b1101 // soc interrup ce | |
161 | ||
162 | ||
163 | //// PCX packet type //// | |
164 | `define PCX_LOAD_RQ 5'b00000 | |
165 | `define PCX_IMISS_RQ 5'b10000 | |
166 | `define PCX_STORE_RQ 5'b00001 | |
167 | `define PCX_FWD_RQs 5'b01101 | |
168 | `define PCX_FWD_RPYs 5'b01110 | |
169 | ||
170 | //// CPX packet type //// | |
171 | //`define CPX_LOAD_RET 4'b0000 | |
172 | `define CPX_LOAD_RET 4'b1000 | |
173 | `define CPX_ST_ACK 4'b0100 | |
174 | //`define CPX_IFILL_RET 4'b0001 | |
175 | `define CPX_IFILL_RET 4'b1001 | |
176 | `define CPX_INT_RET 4'b0111 | |
177 | `define CPX_INT_SOC 4'b1101 | |
178 | //`define CPX_FWD_RQ_RET 4'b1010 | |
179 | //`define CPX_FWD_RPY_RET 4'b1011 | |
180 | ||
181 | ||
182 | ||
183 | ||
184 | //// Global CSR decode //// | |
185 | `define NCU_CSR 8'h80 | |
186 | `define NIU_CSR 8'h81 | |
187 | //`define RNG_CSR 8'h82 | |
188 | `define DBG1_CSR 8'h86 | |
189 | `define CCU_CSR 8'h83 | |
190 | `define MCU_CSR 8'h84 | |
191 | `define TCU_CSR 8'h85 | |
192 | `define DMU_CSR 8'h88 | |
193 | `define RCU_CSR 8'h89 | |
194 | `define NCU_ASI 8'h90 | |
195 | /////8'h91 ~ 9F reserved | |
196 | /////8'hA0 ~ BF L2 CSR//// | |
197 | `define DMU_PIO 4'hC // C0 ~ CF | |
198 | /////8'hB0 ~ FE reserved | |
199 | `define SSI_CSR 8'hFF | |
200 | ||
201 | ||
202 | //// NCU_SSI //// | |
203 | `define SSI_ADDR 12'hFF_F | |
204 | `define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088 | |
205 | `define SSI_ADDR_LOG_REG 40'hFF_0000_0018 | |
206 | ||
207 | `define IF_IDLE 2'b00 | |
208 | `define IF_ACPT 2'b01 | |
209 | `define IF_DROP 2'b10 | |
210 | ||
211 | `define SSI_IDLE 3'b000 | |
212 | `define SSI_REQ 3'b001 | |
213 | `define SSI_WDATA 3'b011 | |
214 | `define SSI_REQ_PAR 3'b101 | |
215 | `define SSI_ACK 3'b111 | |
216 | `define SSI_RDATA 3'b110 | |
217 | `define SSI_ACK_PAR 3'b010 | |
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | ||
228 | module ncu_i2cbuftcu_ctl ( | |
229 | iol2clk, | |
230 | scan_in, | |
231 | scan_out, | |
232 | tcu_pce_ov, | |
233 | tcu_clk_stop, | |
234 | tcu_scan_en, | |
235 | tcu_aclk, | |
236 | tcu_bclk, | |
237 | vld, | |
238 | data, | |
239 | stall, | |
240 | tap_iob_busy, | |
241 | iob_tap_packet, | |
242 | iob_tap_packet_vld) ; | |
243 | wire buf_obj_ff_scanin; | |
244 | wire buf_obj_ff_scanout; | |
245 | wire [127:0] buf_obj; | |
246 | wire l1clk; | |
247 | wire buf_obj_vld_ff_scanin; | |
248 | wire buf_obj_vld_ff_scanout; | |
249 | wire buf_obj_vld; | |
250 | wire buf_obj_vld_next; | |
251 | wire outdata_buf_busy; | |
252 | wire [15:0] outdata_vec_in; | |
253 | wire [15:0] outdata_vec; | |
254 | wire [127:0] outdata_buf; | |
255 | wire rdy0_ff_scanin; | |
256 | wire rdy0_ff_scanout; | |
257 | wire rdy0; | |
258 | wire rdy1_ff_scanin; | |
259 | wire rdy1_ff_scanout; | |
260 | wire rdy1; | |
261 | wire stall_d1_ff_scanin; | |
262 | wire stall_d1_ff_scanout; | |
263 | wire stall_d1; | |
264 | wire load_outdata; | |
265 | wire shift_outdata; | |
266 | wire [15:0] outdata_vec_next; | |
267 | wire outdata_vec_ff_scanin; | |
268 | wire outdata_vec_ff_scanout; | |
269 | wire [127:0] outdata_buf_next; | |
270 | wire outdata_buf_ff_scanin; | |
271 | wire outdata_buf_ff_scanout; | |
272 | wire siclk; | |
273 | wire soclk; | |
274 | wire se; | |
275 | wire pce_ov; | |
276 | wire stop; | |
277 | ||
278 | ||
279 | // Globals | |
280 | input iol2clk; | |
281 | input scan_in; | |
282 | output scan_out; | |
283 | input tcu_pce_ov; | |
284 | input tcu_clk_stop; | |
285 | input tcu_scan_en; | |
286 | input tcu_aclk; | |
287 | input tcu_bclk; | |
288 | ||
289 | // UCB bus interface | |
290 | output vld; | |
291 | output [7 :0] data; | |
292 | input stall; | |
293 | ||
294 | // Local interface | |
295 | output tap_iob_busy; | |
296 | input [127:0] iob_tap_packet; | |
297 | input iob_tap_packet_vld; | |
298 | ||
299 | // Local signals | |
300 | ||
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | ||
308 | ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_128 buf_obj_ff | |
309 | ( | |
310 | .scan_in(buf_obj_ff_scanin), | |
311 | .scan_out(buf_obj_ff_scanout), | |
312 | .dout (buf_obj[127:0] ), | |
313 | .l1clk (l1clk), | |
314 | .en (iob_tap_packet_vld), | |
315 | .din (iob_tap_packet[127:0]), | |
316 | .siclk(siclk), | |
317 | .soclk(soclk) | |
318 | ); | |
319 | ||
320 | ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 buf_obj_vld_ff | |
321 | ( | |
322 | .scan_in(buf_obj_vld_ff_scanin), | |
323 | .scan_out(buf_obj_vld_ff_scanout), | |
324 | .dout (buf_obj_vld), | |
325 | .l1clk (l1clk), | |
326 | .din (buf_obj_vld_next), | |
327 | .siclk(siclk), | |
328 | .soclk(soclk) | |
329 | ); | |
330 | ||
331 | ||
332 | assign buf_obj_vld_next = buf_obj_vld ? outdata_buf_busy : iob_tap_packet_vld ; | |
333 | assign tap_iob_busy = buf_obj_vld; | |
334 | ||
335 | assign outdata_vec_in[15:0] = (buf_obj[3:0]==`UCB_READ_NACK) ? 16'h00ff : 16'hffff ; | |
336 | ||
337 | //////////////////////////////////////////////////////////////////////// | |
338 | // Code starts here | |
339 | //////////////////////////////////////////////////////////////////////// | |
340 | /************************************************************ | |
341 | * UCB bus interface flops | |
342 | ************************************************************/ | |
343 | assign vld = outdata_vec[0]; | |
344 | assign data[7 :0] = outdata_buf[7 :0]; | |
345 | ||
346 | ||
347 | ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 rdy0_ff | |
348 | ( | |
349 | .scan_in(rdy0_ff_scanin), | |
350 | .scan_out(rdy0_ff_scanout), | |
351 | .dout (rdy0), | |
352 | .l1clk (l1clk), | |
353 | .din (1'b1), | |
354 | .siclk(siclk), | |
355 | .soclk(soclk) | |
356 | ); | |
357 | ||
358 | ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 rdy1_ff | |
359 | ( | |
360 | .scan_in(rdy1_ff_scanin), | |
361 | .scan_out(rdy1_ff_scanout), | |
362 | .dout (rdy1), | |
363 | .l1clk (l1clk), | |
364 | .din (rdy0), | |
365 | .siclk(siclk), | |
366 | .soclk(soclk) | |
367 | ); | |
368 | ||
369 | ||
370 | ||
371 | ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_1 stall_d1_ff | |
372 | ( | |
373 | .scan_in(stall_d1_ff_scanin), | |
374 | .scan_out(stall_d1_ff_scanout), | |
375 | .dout (stall_d1), | |
376 | .l1clk (l1clk), | |
377 | .en (rdy1), | |
378 | .din (stall), | |
379 | .siclk(siclk), | |
380 | .soclk(soclk) | |
381 | ); | |
382 | ||
383 | /************************************************************ | |
384 | * Outbound Data | |
385 | ************************************************************/ | |
386 | // accept new data only if there is none being processed | |
387 | //assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
388 | assign load_outdata = buf_obj_vld & ~outdata_buf_busy; | |
389 | ||
390 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
391 | ||
392 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
393 | ||
394 | assign outdata_vec_next[15 :0] = load_outdata ? outdata_vec_in[15 :0] : | |
395 | shift_outdata ? {1'b0,outdata_vec[15 :1]} : | |
396 | outdata_vec[15 :0] ; | |
397 | ||
398 | ncu_i2cbuftcu_ctl_msff_ctl_macro__width_16 outdata_vec_ff | |
399 | ( | |
400 | .scan_in(outdata_vec_ff_scanin), | |
401 | .scan_out(outdata_vec_ff_scanout), | |
402 | .dout (outdata_vec[15 :0]), | |
403 | .l1clk (l1clk), | |
404 | .din (outdata_vec_next[15 :0]), | |
405 | .siclk(siclk), | |
406 | .soclk(soclk) | |
407 | ); | |
408 | ||
409 | assign outdata_buf_next[127:0] = load_outdata ? buf_obj[127:0] : | |
410 | shift_outdata ? (outdata_buf[127:0] >> 8 ) : | |
411 | outdata_buf[127:0] ; | |
412 | ||
413 | ncu_i2cbuftcu_ctl_msff_ctl_macro__width_128 outdata_buf_ff | |
414 | ( | |
415 | .scan_in(outdata_buf_ff_scanin), | |
416 | .scan_out(outdata_buf_ff_scanout), | |
417 | .dout (outdata_buf[127:0]), | |
418 | .l1clk (l1clk), | |
419 | .din (outdata_buf_next[127:0]), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk) | |
422 | ); | |
423 | ||
424 | ||
425 | ||
426 | /**** adding clock header ****/ | |
427 | ncu_i2cbuftcu_ctl_l1clkhdr_ctl_macro clkgen ( | |
428 | .l2clk (iol2clk), | |
429 | .l1en (1'b1), | |
430 | .l1clk (l1clk), | |
431 | .pce_ov(pce_ov), | |
432 | .stop(stop), | |
433 | .se(se) | |
434 | ); | |
435 | ||
436 | /*** building tcu port ***/ | |
437 | assign siclk = tcu_aclk; | |
438 | assign soclk = tcu_bclk; | |
439 | assign se = tcu_scan_en; | |
440 | assign pce_ov = tcu_pce_ov; | |
441 | assign stop = tcu_clk_stop; | |
442 | ||
443 | // fixscan start: | |
444 | assign buf_obj_ff_scanin = scan_in ; | |
445 | assign buf_obj_vld_ff_scanin = buf_obj_ff_scanout ; | |
446 | assign rdy0_ff_scanin = buf_obj_vld_ff_scanout ; | |
447 | assign rdy1_ff_scanin = rdy0_ff_scanout ; | |
448 | assign stall_d1_ff_scanin = rdy1_ff_scanout ; | |
449 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; | |
450 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; | |
451 | assign scan_out = outdata_buf_ff_scanout ; | |
452 | // fixscan end: | |
453 | endmodule // ncu_i2cbuftcu_ctl | |
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | // any PARAMS parms go into naming of macro | |
467 | ||
468 | module ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_128 ( | |
469 | din, | |
470 | en, | |
471 | l1clk, | |
472 | scan_in, | |
473 | siclk, | |
474 | soclk, | |
475 | dout, | |
476 | scan_out); | |
477 | wire [127:0] fdin; | |
478 | wire [126:0] so; | |
479 | ||
480 | input [127:0] din; | |
481 | input en; | |
482 | input l1clk; | |
483 | input scan_in; | |
484 | ||
485 | ||
486 | input siclk; | |
487 | input soclk; | |
488 | ||
489 | output [127:0] dout; | |
490 | output scan_out; | |
491 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); | |
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | dff #(128) d0_0 ( | |
499 | .l1clk(l1clk), | |
500 | .siclk(siclk), | |
501 | .soclk(soclk), | |
502 | .d(fdin[127:0]), | |
503 | .si({scan_in,so[126:0]}), | |
504 | .so({so[126:0],scan_out}), | |
505 | .q(dout[127:0]) | |
506 | ); | |
507 | ||
508 | ||
509 | ||
510 | ||
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | endmodule | |
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | // any PARAMS parms go into naming of macro | |
534 | ||
535 | module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 ( | |
536 | din, | |
537 | l1clk, | |
538 | scan_in, | |
539 | siclk, | |
540 | soclk, | |
541 | dout, | |
542 | scan_out); | |
543 | wire [0:0] fdin; | |
544 | ||
545 | input [0:0] din; | |
546 | input l1clk; | |
547 | input scan_in; | |
548 | ||
549 | ||
550 | input siclk; | |
551 | input soclk; | |
552 | ||
553 | output [0:0] dout; | |
554 | output scan_out; | |
555 | assign fdin[0:0] = din[0:0]; | |
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | ||
562 | dff #(1) d0_0 ( | |
563 | .l1clk(l1clk), | |
564 | .siclk(siclk), | |
565 | .soclk(soclk), | |
566 | .d(fdin[0:0]), | |
567 | .si(scan_in), | |
568 | .so(scan_out), | |
569 | .q(dout[0:0]) | |
570 | ); | |
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | endmodule | |
584 | ||
585 | ||
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | // any PARAMS parms go into naming of macro | |
598 | ||
599 | module ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_1 ( | |
600 | din, | |
601 | en, | |
602 | l1clk, | |
603 | scan_in, | |
604 | siclk, | |
605 | soclk, | |
606 | dout, | |
607 | scan_out); | |
608 | wire [0:0] fdin; | |
609 | ||
610 | input [0:0] din; | |
611 | input en; | |
612 | input l1clk; | |
613 | input scan_in; | |
614 | ||
615 | ||
616 | input siclk; | |
617 | input soclk; | |
618 | ||
619 | output [0:0] dout; | |
620 | output scan_out; | |
621 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | dff #(1) d0_0 ( | |
629 | .l1clk(l1clk), | |
630 | .siclk(siclk), | |
631 | .soclk(soclk), | |
632 | .d(fdin[0:0]), | |
633 | .si(scan_in), | |
634 | .so(scan_out), | |
635 | .q(dout[0:0]) | |
636 | ); | |
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | ||
648 | ||
649 | endmodule | |
650 | ||
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | // any PARAMS parms go into naming of macro | |
664 | ||
665 | module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_16 ( | |
666 | din, | |
667 | l1clk, | |
668 | scan_in, | |
669 | siclk, | |
670 | soclk, | |
671 | dout, | |
672 | scan_out); | |
673 | wire [15:0] fdin; | |
674 | wire [14:0] so; | |
675 | ||
676 | input [15:0] din; | |
677 | input l1clk; | |
678 | input scan_in; | |
679 | ||
680 | ||
681 | input siclk; | |
682 | input soclk; | |
683 | ||
684 | output [15:0] dout; | |
685 | output scan_out; | |
686 | assign fdin[15:0] = din[15:0]; | |
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | dff #(16) d0_0 ( | |
694 | .l1clk(l1clk), | |
695 | .siclk(siclk), | |
696 | .soclk(soclk), | |
697 | .d(fdin[15:0]), | |
698 | .si({scan_in,so[14:0]}), | |
699 | .so({so[14:0],scan_out}), | |
700 | .q(dout[15:0]) | |
701 | ); | |
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | endmodule | |
715 | ||
716 | ||
717 | ||
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | // any PARAMS parms go into naming of macro | |
729 | ||
730 | module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_128 ( | |
731 | din, | |
732 | l1clk, | |
733 | scan_in, | |
734 | siclk, | |
735 | soclk, | |
736 | dout, | |
737 | scan_out); | |
738 | wire [127:0] fdin; | |
739 | wire [126:0] so; | |
740 | ||
741 | input [127:0] din; | |
742 | input l1clk; | |
743 | input scan_in; | |
744 | ||
745 | ||
746 | input siclk; | |
747 | input soclk; | |
748 | ||
749 | output [127:0] dout; | |
750 | output scan_out; | |
751 | assign fdin[127:0] = din[127:0]; | |
752 | ||
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | dff #(128) d0_0 ( | |
759 | .l1clk(l1clk), | |
760 | .siclk(siclk), | |
761 | .soclk(soclk), | |
762 | .d(fdin[127:0]), | |
763 | .si({scan_in,so[126:0]}), | |
764 | .so({so[126:0],scan_out}), | |
765 | .q(dout[127:0]) | |
766 | ); | |
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | endmodule | |
780 | ||
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | ||
792 | ||
793 | // any PARAMS parms go into naming of macro | |
794 | ||
795 | module ncu_i2cbuftcu_ctl_l1clkhdr_ctl_macro ( | |
796 | l2clk, | |
797 | l1en, | |
798 | pce_ov, | |
799 | stop, | |
800 | se, | |
801 | l1clk); | |
802 | ||
803 | ||
804 | input l2clk; | |
805 | input l1en; | |
806 | input pce_ov; | |
807 | input stop; | |
808 | input se; | |
809 | output l1clk; | |
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | cl_sc1_l1hdr_8x c_0 ( | |
816 | ||
817 | ||
818 | .l2clk(l2clk), | |
819 | .pce(l1en), | |
820 | .l1clk(l1clk), | |
821 | .se(se), | |
822 | .pce_ov(pce_ov), | |
823 | .stop(stop) | |
824 | ); | |
825 | ||
826 | ||
827 | ||
828 | endmodule | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 |