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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ncu / rtl / ncu_scd_ctl.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ncu_scd_ctl.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module ncu_scd_ctl (
36 ccu_ncu_data,
37 ccu_ncu_stall,
38 ccu_ncu_vld,
39 core_running_status,
40 cpubuf_dout,
41 cpubuf_tail_f,
42 dmu_ncu_data,
43 dmu_ncu_stall,
44 dmu_ncu_vld,
45 dmu_ncu_wrack_tag,
46 dmu_ncu_wrack_vld,
47 dmu_ncu_wrack_par,
48 efu_ncu_bankavail_dshift,
49 efu_ncu_coreavail_dshift,
50 efu_ncu_fuse_data,
51 efu_ncu_fusestat_dshift,
52 efu_ncu_sernum0_dshift,
53 efu_ncu_sernum1_dshift,
54 efu_ncu_sernum2_dshift,
55 intman_tbl_dout,
56 iobuf_head_f,
57 iol2clk,
58 mcu0_ncu_data,
59 mcu0_ncu_stall,
60 mcu0_ncu_vld,
61 mcu1_ncu_data,
62 mcu1_ncu_stall,
63 mcu1_ncu_vld,
64 mcu2_ncu_data,
65 mcu2_ncu_stall,
66 mcu2_ncu_vld,
67 mcu3_ncu_data,
68 mcu3_ncu_stall,
69 mcu3_ncu_vld,
70 mondo_busy_vec_f,
71 niu_ncu_data,
72 niu_ncu_stall,
73 niu_ncu_vld,
74 rcu_ncu_data,
75 rcu_ncu_stall,
76 rcu_ncu_vld,
77 dbg1_ncu_data,
78 dbg1_ncu_stall,
79 dbg1_ncu_vld,
80 rst_ncu_unpark_thread,
81 rst_ncu_xir_,
82 scan_in,
83 sii_ncu_data,
84 sii_ncu_req,
85 sii_ncu_dparity,
86 ssi_ncu_data,
87 ssi_ncu_stall,
88 ssi_ncu_vld,
89 tap_mondo_acc_addr_invld_d2_f,
90 tap_mondo_acc_seq_d2_f,
91 tap_mondo_dout_d2_f,
92 tcu_clk_stop,
93 tcu_ncu_data,
94 tcu_ncu_stall,
95 tcu_ncu_vld,
96 tcu_pce_ov,
97 tcu_scan_en,
98 tcu_aclk,
99 tcu_bclk,
100 dmubuf0_dout,
101 dmubuf1_dout,
102 mb0_run,
103 mb0_iobuf_wr_en,
104 mb0_addr,
105 mb0_wdata,
106 tcu_dbr_gateoff,
107 tcu_mbist_bisi_en,
108 mb1_run,
109 mb1_addr,
110 mb1_wdata,
111 mb1_cpubuf_wr_en,
112 mb1_scanout,
113 mb1_done,
114 mb1_fail,
115 mb1_start,
116 mb1_scanin,
117 tcu_mbist_user_mode,
118 ncu_spc_pm,
119 ncu_spc_ba67,
120 ncu_spc_ba45,
121 ncu_spc_ba23,
122 ncu_spc_ba01,
123 ncu_spc_l2_idx_hash_en,
124 ncu_sii_pm,
125 ncu_sii_ba67,
126 ncu_sii_ba45,
127 ncu_sii_ba23,
128 ncu_sii_ba01,
129 ncu_sii_l2_idx_hash_en,
130 ncu_l2t_pm,
131 ncu_l2t_ba67,
132 ncu_l2t_ba45,
133 ncu_l2t_ba23,
134 ncu_l2t_ba01,
135 ncu_mcu_pm,
136 ncu_mcu_ba67,
137 ncu_mcu_ba45,
138 ncu_mcu_ba23,
139 ncu_mcu_ba01,
140 cpubuf_mb0_data,
141 ncu_spc7_core_enable_status,
142 ncu_spc6_core_enable_status,
143 ncu_spc5_core_enable_status,
144 ncu_spc4_core_enable_status,
145 ncu_spc3_core_enable_status,
146 ncu_spc2_core_enable_status,
147 ncu_spc1_core_enable_status,
148 ncu_spc0_core_enable_status,
149 core_running,
150 coreavail,
151 cpubuf_head_ptr,
152 cpubuf_head_s,
153 cpubuf_rden,
154 intman_tbl_raddr,
155 intman_tbl_waddr,
156 intman_tbl_din,
157 intman_tbl_rden,
158 intman_tbl_wr,
159 iobuf_din,
160 iobuf_tail_ptr,
161 iobuf_tail_s,
162 iobuf_wr,
163 io_mondo_data0_din_s,
164 io_mondo_data1_din_s,
165 io_mondo_data_wr_addr_s,
166 io_mondo_data_wr_s,
167 ncu_ccu_data,
168 ncu_ccu_stall,
169 ncu_ccu_vld,
170 ncu_dmu_data,
171 ncu_dmu_mmu_addr_vld,
172 ncu_dmu_mondo_ack,
173 ncu_dmu_mondo_id,
174 ncu_dmu_mondo_id_par,
175 ncu_dmu_mondo_nack,
176 ncu_dmu_dpar,
177 ncu_dmu_pio_data,
178 ncu_dmu_pio_hdr_vld,
179 ncu_dmu_stall,
180 ncu_dmu_vld,
181 ncu_mcu0_data,
182 ncu_mcu0_stall,
183 ncu_mcu0_vld,
184 ncu_mcu1_data,
185 ncu_mcu1_stall,
186 ncu_mcu1_vld,
187 ncu_mcu2_data,
188 ncu_mcu2_stall,
189 ncu_mcu2_vld,
190 ncu_mcu3_data,
191 ncu_mcu3_stall,
192 ncu_mcu3_vld,
193 ncu_niu_data,
194 ncu_niu_stall,
195 ncu_niu_vld,
196 ncu_rcu_data,
197 ncu_rcu_stall,
198 ncu_rcu_vld,
199 ncu_dbg1_data,
200 ncu_dbg1_stall,
201 ncu_dbg1_vld,
202 ncu_rst_xir_done,
203 ncu_sii_gnt,
204 ncu_ssi_data,
205 ncu_ssi_stall,
206 ncu_ssi_vld,
207 ncu_tcu_data,
208 ncu_tcu_stall,
209 ncu_tcu_vld,
210 scan_out,
211 tap_mondo_acc_addr_s,
212 tap_mondo_acc_seq_s,
213 tap_mondo_din_s,
214 tap_mondo_wr_s,
215 dmubuf_din,
216 dmubuf_raddr,
217 dmubuf_waddr,
218 dmubuf0_wr,
219 dmubuf1_wr,
220 dmubuf_rden,
221 aclk_wmr,
222 wmr_protect,
223 dmu_ncu_d_pe,
224 ncu_dmu_d_pei,
225 dmu_ncu_siicr_pe,
226 ncu_dmu_siicr_pei,
227 dmu_ncu_ctag_ue,
228 ncu_dmu_ctag_uei,
229 dmu_ncu_ctag_ce,
230 ncu_dmu_ctag_cei,
231 dmu_ncu_ncucr_pe,
232 ncu_dmu_ncucr_pei,
233 dmu_ncu_ie,
234 ncu_dmu_iei,
235 niu_ncu_d_pe,
236 ncu_niu_d_pei,
237 niu_ncu_ctag_ue,
238 ncu_niu_ctag_uei,
239 niu_ncu_ctag_ce,
240 ncu_niu_ctag_cei,
241 sio_ncu_ctag_ce,
242 ncu_sio_ctag_cei,
243 sio_ncu_ctag_ue,
244 ncu_sio_ctag_uei,
245 ncu_sio_d_pei,
246 mcu0_ncu_ecc,
247 ncu_mcu0_ecci,
248 mcu0_ncu_fbr,
249 ncu_mcu0_fbri,
250 mcu0_ncu_fbu,
251 ncu_mcu0_fbui,
252 mcu1_ncu_ecc,
253 ncu_mcu1_ecci,
254 mcu1_ncu_fbr,
255 ncu_mcu1_fbri,
256 mcu1_ncu_fbu,
257 ncu_mcu1_fbui,
258 mcu2_ncu_ecc,
259 ncu_mcu2_ecci,
260 mcu2_ncu_fbr,
261 ncu_mcu2_fbri,
262 mcu2_ncu_fbu,
263 ncu_mcu2_fbui,
264 mcu3_ncu_ecc,
265 ncu_mcu3_ecci,
266 mcu3_ncu_fbr,
267 ncu_mcu3_fbri,
268 mcu3_ncu_fbu,
269 ncu_mcu3_fbui,
270 sii_ncu_syn_data,
271 sii_ncu_syn_vld,
272 sii_ncu_dmuctag_ce,
273 ncu_sii_dmuctag_cei,
274 sii_ncu_dmuctag_ue,
275 ncu_sii_dmuctag_uei,
276 sii_ncu_dmua_pe,
277 ncu_sii_dmua_pei,
278 sii_ncu_dmud_pe,
279 ncu_sii_dmud_pei,
280 sii_ncu_niuctag_ce,
281 ncu_sii_niuctag_cei,
282 sii_ncu_niuctag_ue,
283 ncu_sii_niuctag_uei,
284 sii_ncu_niua_pe,
285 ncu_sii_niua_pei,
286 sii_ncu_niud_pe,
287 ncu_sii_niud_pei,
288 ncu_rst_fatal_error,
289 ncu_tcu_soc_error,
290 ncu_tcu_bank_avail,
291 iobuf_ue_f,
292 iobuf_uei,
293 intbuf_ue_f,
294 intbuf_uei,
295 mondotbl_pe_f,
296 mondotbl_pei,
297 ncu_dbg1_error_event,
298 cmp_tick_enable,
299 tcu_wmr_vec_mask,
300 ncu_scksel) ;
301wire [4:0] l2pm;
302wire l2idxhs_en_status;
303wire tcu_dbr_gateoff_i;
304wire raserrce;
305wire raserrue;
306wire ncuctag_uei;
307wire ncuctag_cei;
308wire ncusiid_pei;
309wire [127:0] bounce_ack_packet;
310wire bounce_ack_vld;
311wire lhs_intman_acc;
312wire [5:0] mondoinvec;
313wire [127:0] ncu_int_ack_packet;
314wire ncu_int_ack_vld;
315wire [127:0] ncu_man_ack_packet;
316wire ncu_man_ack_vld;
317wire [24:0] ncu_man_int_packet;
318wire ncu_man_int_vld;
319wire [63:0] rd_nack_packet;
320wire rd_nack_vld;
321wire srvc_wr_ack;
322wire [152:0] wr_ack_iopkt;
323wire [152:0] dmupio_wack_iopkt;
324wire dmupio_srvc_wack;
325wire bounce_ack_rd;
326wire intman_pchkf2i2c;
327wire iobuf_avail;
328wire [6:0] io_intman_addr;
329wire ncu_c2iscd_ctl_scanin;
330wire ncu_c2iscd_ctl_scanout;
331wire ncu_int_ack_rd;
332wire ncu_man_ack_rd;
333wire ncu_man_int_rd;
334wire rd_nack_rd;
335wire [3:0] sii_cr_id_rtn;
336wire sii_cr_id_rtn_vld;
337wire [63:0] siierrsyn;
338wire siierrsyn_done;
339wire io_rd_intman_d2;
340wire ncuctag_ue;
341wire ncuctag_ce;
342wire ncusiid_pe;
343wire [15:0] ncudpsyn;
344wire ncu_i2cscd_ctl_scanin;
345wire ncu_i2cscd_ctl_scanout;
346
347
348input [3:0] ccu_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
349input ccu_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
350input ccu_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
351input [63:0] core_running_status; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
352input [143:0] cpubuf_dout; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
353input [5:0] cpubuf_tail_f; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
354input [31:0] dmu_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
355input dmu_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
356input dmu_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
357input [3:0] dmu_ncu_wrack_tag; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
358input dmu_ncu_wrack_vld; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
359input dmu_ncu_wrack_par; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
360input efu_ncu_bankavail_dshift;// To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
361input efu_ncu_coreavail_dshift;// To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
362//input efu_ncu_fuse_clk1; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
363input efu_ncu_fuse_data; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
364input efu_ncu_fusestat_dshift;// To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
365input efu_ncu_sernum0_dshift; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
366input efu_ncu_sernum1_dshift; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
367input efu_ncu_sernum2_dshift; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
368input [15:0] intman_tbl_dout; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
369input [5:0] iobuf_head_f; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
370input iol2clk; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
371input [3:0] mcu0_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
372input mcu0_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
373input mcu0_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
374input [3:0] mcu1_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
375input mcu1_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
376input mcu1_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
377input [3:0] mcu2_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
378input mcu2_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
379input mcu2_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
380input [3:0] mcu3_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
381input mcu3_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
382input mcu3_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
383input [63:0] mondo_busy_vec_f; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
384input [31:0] niu_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
385input niu_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
386input niu_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
387input [3:0] rcu_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
388input rcu_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
389input rcu_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
390//input [3:0] rng_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
391input [3:0] dbg1_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
392input dbg1_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
393input dbg1_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
394//input rng_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
395//input rng_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
396input rst_ncu_unpark_thread; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
397input rst_ncu_xir_; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
398input scan_in; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
399input [31:0] sii_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
400input sii_ncu_req; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
401input [1:0] sii_ncu_dparity;
402input [3:0] ssi_ncu_data; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
403input ssi_ncu_stall; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
404input ssi_ncu_vld; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
405input tap_mondo_acc_addr_invld_d2_f;// To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
406input tap_mondo_acc_seq_d2_f; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
407input [63:0] tap_mondo_dout_d2_f; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
408input tcu_clk_stop; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
409input [7:0] tcu_ncu_data; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
410input tcu_ncu_stall; // To ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
411input tcu_ncu_vld; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
412input tcu_pce_ov; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
413input tcu_scan_en; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
414input tcu_aclk; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
415input tcu_bclk; // To ncu_c2iscd_ctl of ncu_c2iscd_ctl.v, ...
416input [143:0] dmubuf0_dout;
417input [143:0] dmubuf1_dout;
418input mb0_run;
419input mb0_iobuf_wr_en;
420input [5:0] mb0_addr;
421input [7:0] mb0_wdata;
422input tcu_dbr_gateoff;
423input tcu_mbist_bisi_en;
424output mb1_run;
425output [6:0] mb1_addr;
426output [7:0] mb1_wdata;
427output mb1_cpubuf_wr_en;
428
429//mb1 tcu connection//
430output mb1_scanout;
431output mb1_done;
432output mb1_fail;
433input mb1_start;
434input mb1_scanin;
435input tcu_mbist_user_mode;
436
437output ncu_spc_pm;
438output ncu_spc_ba67;
439output ncu_spc_ba45;
440output ncu_spc_ba23;
441output ncu_spc_ba01;
442output ncu_spc_l2_idx_hash_en;
443output ncu_sii_pm;
444output ncu_sii_ba67;
445output ncu_sii_ba45;
446output ncu_sii_ba23;
447output ncu_sii_ba01;
448output ncu_sii_l2_idx_hash_en;
449output ncu_l2t_pm;
450output ncu_l2t_ba67;
451output ncu_l2t_ba45;
452output ncu_l2t_ba23;
453output ncu_l2t_ba01;
454output ncu_mcu_pm ;
455output ncu_mcu_ba67;
456output ncu_mcu_ba45;
457output ncu_mcu_ba23;
458output ncu_mcu_ba01;
459
460
461output [7:0] cpubuf_mb0_data;
462//output [7:0] core_enable_status; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
463output ncu_spc7_core_enable_status;
464output ncu_spc6_core_enable_status;
465output ncu_spc5_core_enable_status;
466output ncu_spc4_core_enable_status;
467output ncu_spc3_core_enable_status;
468output ncu_spc2_core_enable_status;
469output ncu_spc1_core_enable_status;
470output ncu_spc0_core_enable_status;
471
472output [63:0] core_running; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
473output [7:0] coreavail; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
474output [4:0] cpubuf_head_ptr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
475output [5:0] cpubuf_head_s; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
476output cpubuf_rden; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
477output [6:0] intman_tbl_raddr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
478output [6:0] intman_tbl_waddr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
479output [15:0] intman_tbl_din; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
480output intman_tbl_rden; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
481output intman_tbl_wr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
482output [175:0] iobuf_din; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
483output [4:0] iobuf_tail_ptr; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
484output [5:0] iobuf_tail_s; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
485output iobuf_wr; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
486output [63:0] io_mondo_data0_din_s; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
487output [63:0] io_mondo_data1_din_s; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
488output [5:0] io_mondo_data_wr_addr_s;// From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
489output io_mondo_data_wr_s; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
490//output [4:0] l2pm; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
491//output l2idxhs_en_status;
492output [3:0] ncu_ccu_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
493output ncu_ccu_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
494output ncu_ccu_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
495output [31:0] ncu_dmu_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
496output ncu_dmu_mmu_addr_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
497output ncu_dmu_mondo_ack; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
498output [5:0] ncu_dmu_mondo_id; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
499output ncu_dmu_mondo_id_par;
500output ncu_dmu_mondo_nack; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
501output [1:0] ncu_dmu_dpar; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
502output [63:0] ncu_dmu_pio_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
503output ncu_dmu_pio_hdr_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
504output ncu_dmu_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
505output ncu_dmu_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
506output [3:0] ncu_mcu0_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
507output ncu_mcu0_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
508output ncu_mcu0_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
509output [3:0] ncu_mcu1_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
510output ncu_mcu1_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
511output ncu_mcu1_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
512output [3:0] ncu_mcu2_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
513output ncu_mcu2_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
514output ncu_mcu2_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
515output [3:0] ncu_mcu3_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
516output ncu_mcu3_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
517output ncu_mcu3_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
518output [31:0] ncu_niu_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
519output ncu_niu_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
520output ncu_niu_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
521output [3:0] ncu_rcu_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
522output ncu_rcu_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
523output ncu_rcu_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
524//output [3:0] ncu_rng_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
525//output ncu_rng_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
526//output ncu_rng_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
527output [3:0] ncu_dbg1_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
528output ncu_dbg1_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
529output ncu_dbg1_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
530output ncu_rst_xir_done; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
531output ncu_sii_gnt; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
532output [3:0] ncu_ssi_data; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
533output ncu_ssi_stall; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
534output ncu_ssi_vld; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
535output [7:0] ncu_tcu_data; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
536output ncu_tcu_stall; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
537output ncu_tcu_vld; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
538output scan_out; // From ncu_i2cscd_ctl of ncu_i2cscd_ctl.v
539output [21:0] tap_mondo_acc_addr_s; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
540output tap_mondo_acc_seq_s; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
541output [63:0] tap_mondo_din_s; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
542output tap_mondo_wr_s; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
543output [143:0] dmubuf_din; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
544output [4:0] dmubuf_raddr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
545output [4:0] dmubuf_waddr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
546output dmubuf0_wr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
547output dmubuf1_wr; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
548output dmubuf_rden; // From ncu_c2iscd_ctl of ncu_c2iscd_ctl.v
549
550//err ecc//
551input aclk_wmr;
552input wmr_protect;
553input dmu_ncu_d_pe;
554output ncu_dmu_d_pei;
555input dmu_ncu_siicr_pe;
556output ncu_dmu_siicr_pei;
557input dmu_ncu_ctag_ue;
558output ncu_dmu_ctag_uei;
559input dmu_ncu_ctag_ce;
560output ncu_dmu_ctag_cei;
561input dmu_ncu_ncucr_pe;
562output ncu_dmu_ncucr_pei;
563input dmu_ncu_ie;
564output ncu_dmu_iei;
565
566input niu_ncu_d_pe;
567output ncu_niu_d_pei;
568input niu_ncu_ctag_ue;
569output ncu_niu_ctag_uei;
570input niu_ncu_ctag_ce;
571output ncu_niu_ctag_cei;
572
573input sio_ncu_ctag_ce;
574output ncu_sio_ctag_cei;
575input sio_ncu_ctag_ue;
576output ncu_sio_ctag_uei;
577//input sio_ncu_d_pe;
578output ncu_sio_d_pei;
579
580input mcu0_ncu_ecc;
581output ncu_mcu0_ecci;
582input mcu0_ncu_fbr;
583output ncu_mcu0_fbri;
584input mcu0_ncu_fbu;
585output ncu_mcu0_fbui;
586
587input mcu1_ncu_ecc;
588output ncu_mcu1_ecci;
589input mcu1_ncu_fbr;
590output ncu_mcu1_fbri;
591input mcu1_ncu_fbu;
592output ncu_mcu1_fbui;
593
594input mcu2_ncu_ecc;
595output ncu_mcu2_ecci;
596input mcu2_ncu_fbr;
597output ncu_mcu2_fbri;
598input mcu2_ncu_fbu;
599output ncu_mcu2_fbui;
600
601input mcu3_ncu_ecc;
602output ncu_mcu3_ecci;
603input mcu3_ncu_fbr;
604output ncu_mcu3_fbri;
605input mcu3_ncu_fbu;
606output ncu_mcu3_fbui;
607
608
609input [3:0] sii_ncu_syn_data;
610input sii_ncu_syn_vld;
611input sii_ncu_dmuctag_ce;
612output ncu_sii_dmuctag_cei;
613input sii_ncu_dmuctag_ue;
614output ncu_sii_dmuctag_uei;
615input sii_ncu_dmua_pe;
616output ncu_sii_dmua_pei;
617input sii_ncu_dmud_pe;
618output ncu_sii_dmud_pei;
619input sii_ncu_niuctag_ce;
620output ncu_sii_niuctag_cei;
621input sii_ncu_niuctag_ue;
622output ncu_sii_niuctag_uei;
623input sii_ncu_niua_pe;
624output ncu_sii_niua_pei;
625input sii_ncu_niud_pe;
626output ncu_sii_niud_pei;
627
628output ncu_rst_fatal_error;
629output ncu_tcu_soc_error;
630output [7:0] ncu_tcu_bank_avail;
631//output [3:0] ncu_tcu_bank_en_status;
632
633input iobuf_ue_f;
634output iobuf_uei;
635input intbuf_ue_f;
636output intbuf_uei;
637input mondotbl_pe_f;
638output mondotbl_pei;
639output ncu_dbg1_error_event;
640output cmp_tick_enable;
641output tcu_wmr_vec_mask;
642output[1:0] ncu_scksel;
643
644/*AUTOWIRE*/
645// Beginning of automatic wires (for undeclared instantiated-module outputs)
646// End of automatics
647//
648//assign ncu_spc_pm = l2pm[4];
649assign ncu_spc_ba67 = l2pm[3];
650assign ncu_spc_ba45 = l2pm[2];
651assign ncu_spc_ba23 = l2pm[1];
652//assign ncu_spc_ba01 = l2pm[0];
653assign ncu_spc_l2_idx_hash_en = l2idxhs_en_status;
654//// sii ////
655assign ncu_sii_pm = l2pm[4];
656assign ncu_sii_ba67 = l2pm[3];
657assign ncu_sii_ba45 = l2pm[2];
658assign ncu_sii_ba23 = l2pm[1];
659assign ncu_sii_ba01 = l2pm[0];
660assign ncu_sii_l2_idx_hash_en = l2idxhs_en_status;
661//// l2t ////
662assign ncu_l2t_pm = l2pm[4];
663assign ncu_l2t_ba67 = l2pm[3];
664assign ncu_l2t_ba45 = l2pm[2];
665assign ncu_l2t_ba23 = l2pm[1];
666assign ncu_l2t_ba01 = l2pm[0];
667//// mcu ////
668assign ncu_mcu_pm = l2pm[4];
669assign ncu_mcu_ba67 = l2pm[3];
670assign ncu_mcu_ba45 = l2pm[2];
671assign ncu_mcu_ba23 = l2pm[1];
672assign ncu_mcu_ba01 = l2pm[0];
673
674assign tcu_dbr_gateoff_i = ~tcu_dbr_gateoff;
675
676///*ncu_c2iscd_ctl auto_template (
677// .scan_out( ) ); */
678ncu_c2iscd_ctl ncu_c2iscd_ctl ( /*AUTOINST*/
679 // Outputs
680 .mb1_run(mb1_run),
681 .mb1_scanout(mb1_scanout),
682 .mb1_fail(mb1_fail),
683 .mb1_done(mb1_done),
684 .mb1_addr(mb1_addr[6:0]),
685 .mb1_wdata(mb1_wdata[7:0]),
686 .ncu_rst_fatal_error(ncu_rst_fatal_error),
687 .ncu_tcu_soc_error(ncu_tcu_soc_error),
688 .raserrce(raserrce),
689 .raserrue(raserrue),
690 .ncu_dmu_d_pei(ncu_dmu_d_pei),
691 .ncu_dmu_siicr_pei(ncu_dmu_siicr_pei),
692 .ncu_dmu_ctag_uei(ncu_dmu_ctag_uei),
693 .ncu_dmu_ctag_cei(ncu_dmu_ctag_cei),
694 .ncu_dmu_ncucr_pei(ncu_dmu_ncucr_pei),
695 .ncu_dmu_iei(ncu_dmu_iei),
696 .ncu_niu_d_pei(ncu_niu_d_pei),
697 .ncu_niu_ctag_uei(ncu_niu_ctag_uei),
698 .ncu_niu_ctag_cei(ncu_niu_ctag_cei),
699 .ncu_sio_ctag_cei(ncu_sio_ctag_cei),
700 .ncu_sio_ctag_uei(ncu_sio_ctag_uei),
701 .ncu_sio_d_pei(ncu_sio_d_pei),
702 .ncu_sii_dmuctag_cei(ncu_sii_dmuctag_cei),
703 .ncu_sii_dmuctag_uei(ncu_sii_dmuctag_uei),
704 .ncu_sii_dmua_pei(ncu_sii_dmua_pei),
705 .ncu_sii_dmud_pei(ncu_sii_dmud_pei),
706 .ncu_sii_niuctag_cei(ncu_sii_niuctag_cei),
707 .ncu_sii_niuctag_uei(ncu_sii_niuctag_uei),
708 .ncu_sii_niua_pei(ncu_sii_niua_pei),
709 .ncu_sii_niud_pei(ncu_sii_niud_pei),
710 .ncu_mcu0_ecci(ncu_mcu0_ecci),
711 .ncu_mcu0_fbri(ncu_mcu0_fbri),
712 .ncu_mcu0_fbui(ncu_mcu0_fbui),
713 .ncu_mcu1_ecci(ncu_mcu1_ecci),
714 .ncu_mcu1_fbri(ncu_mcu1_fbri),
715 .ncu_mcu1_fbui(ncu_mcu1_fbui),
716 .ncu_mcu2_ecci(ncu_mcu2_ecci),
717 .ncu_mcu2_fbri(ncu_mcu2_fbri),
718 .ncu_mcu2_fbui(ncu_mcu2_fbui),
719 .ncu_mcu3_ecci(ncu_mcu3_ecci),
720 .ncu_mcu3_fbri(ncu_mcu3_fbri),
721 .ncu_mcu3_fbui(ncu_mcu3_fbui),
722 .ncuctag_uei(ncuctag_uei),
723 .ncuctag_cei(ncuctag_cei),
724 .ncusiid_pei(ncusiid_pei),
725 .iobuf_uei(iobuf_uei),
726 .intbuf_uei(intbuf_uei),
727 .mondotbl_pei(mondotbl_pei),
728 .bounce_ack_packet(bounce_ack_packet[127:0]),
729 .bounce_ack_vld(bounce_ack_vld),
730 //.core_enable_status(core_enable_status[7:0]),
731 .ncu_spc7_core_enable_status(ncu_spc7_core_enable_status),
732 .ncu_spc6_core_enable_status(ncu_spc6_core_enable_status),
733 .ncu_spc5_core_enable_status(ncu_spc5_core_enable_status),
734 .ncu_spc4_core_enable_status(ncu_spc4_core_enable_status),
735 .ncu_spc3_core_enable_status(ncu_spc3_core_enable_status),
736 .ncu_spc2_core_enable_status(ncu_spc2_core_enable_status),
737 .ncu_spc1_core_enable_status(ncu_spc1_core_enable_status),
738 .ncu_spc0_core_enable_status(ncu_spc0_core_enable_status),
739 .core_running(core_running[63:0]),
740 .coreavail(coreavail[7:0]),
741 .cpubuf_head_ptr(cpubuf_head_ptr[4:0]),
742 .cpubuf_head_s(cpubuf_head_s[5:0]),
743 .cpubuf_rden(cpubuf_rden),
744 .intman_tbl_raddr(intman_tbl_raddr[6:0]),
745 .intman_tbl_waddr(intman_tbl_waddr[6:0]),
746 .intman_tbl_din(intman_tbl_din[15:0]),
747 .intman_tbl_rden(intman_tbl_rden),
748 .intman_tbl_wr(intman_tbl_wr),
749 .dmubuf_din(dmubuf_din[143:0]),
750 .dmubuf_raddr(dmubuf_raddr[4:0]),
751 .dmubuf_waddr(dmubuf_waddr[4:0]),
752 .dmubuf_rden(dmubuf_rden),
753 .dmubuf0_wr(dmubuf0_wr),
754 .dmubuf1_wr(dmubuf1_wr),
755 .l2pm (l2pm[4:0]),
756 .ncu_spc_pm(ncu_spc_pm),
757 .ncu_spc_ba01(ncu_spc_ba01),
758 .l2idxhs_en_status(l2idxhs_en_status),
759 .lhs_intman_acc(lhs_intman_acc),
760 .mondoinvec(mondoinvec[5:0]),
761 .ncu_ccu_data(ncu_ccu_data[3:0]),
762 .ncu_ccu_vld(ncu_ccu_vld),
763 .ncu_dmu_data(ncu_dmu_data[31:0]),
764 .ncu_dmu_mmu_addr_vld(ncu_dmu_mmu_addr_vld),
765 .ncu_dmu_dpar(ncu_dmu_dpar[1:0]),
766 .ncu_dmu_pio_data(ncu_dmu_pio_data[63:0]),
767 .ncu_dmu_pio_hdr_vld(ncu_dmu_pio_hdr_vld),
768 .ncu_dmu_vld(ncu_dmu_vld),
769 .ncu_int_ack_packet(ncu_int_ack_packet[127:0]),
770 .ncu_int_ack_vld(ncu_int_ack_vld),
771 .ncu_man_ack_packet(ncu_man_ack_packet[127:0]),
772 .ncu_man_ack_vld(ncu_man_ack_vld),
773 .ncu_man_int_packet(ncu_man_int_packet[24:0]),
774 .ncu_man_int_vld(ncu_man_int_vld),
775 .ncu_mcu0_data(ncu_mcu0_data[3:0]),
776 .ncu_mcu0_vld(ncu_mcu0_vld),
777 .ncu_mcu1_data(ncu_mcu1_data[3:0]),
778 .ncu_mcu1_vld(ncu_mcu1_vld),
779 .ncu_mcu2_data(ncu_mcu2_data[3:0]),
780 .ncu_mcu2_vld(ncu_mcu2_vld),
781 .ncu_mcu3_data(ncu_mcu3_data[3:0]),
782 .ncu_mcu3_vld(ncu_mcu3_vld),
783 .ncu_niu_data(ncu_niu_data[31:0]),
784 .ncu_niu_vld(ncu_niu_vld),
785 .ncu_rcu_data(ncu_rcu_data[3:0]),
786 .ncu_rcu_vld(ncu_rcu_vld),
787 .ncu_dbg1_data(ncu_dbg1_data[3:0]),
788 .ncu_dbg1_vld(ncu_dbg1_vld),
789 .ncu_rst_xir_done(ncu_rst_xir_done),
790 .ncu_ssi_data(ncu_ssi_data[3:0]),
791 .ncu_ssi_vld(ncu_ssi_vld),
792 .ncu_tcu_stall(ncu_tcu_stall),
793 .ncu_tcu_bank_avail(ncu_tcu_bank_avail[7:0]),
794 //.ncu_tcu_bank_en_status(ncu_tcu_bank_en_status[3:0]),
795 .rd_nack_packet(rd_nack_packet[63:0]),
796 .rd_nack_vld(rd_nack_vld),
797 .srvc_wr_ack(srvc_wr_ack),
798 .tap_mondo_acc_addr_s(tap_mondo_acc_addr_s[21:0]),
799 .tap_mondo_acc_seq_s(tap_mondo_acc_seq_s),
800 .tap_mondo_din_s(tap_mondo_din_s[63:0]),
801 .tap_mondo_wr_s(tap_mondo_wr_s),
802 .wr_ack_iopkt(wr_ack_iopkt[152:0]),
803 .cpubuf_mb0_data(cpubuf_mb0_data[7:0]),
804 .dmupio_wack_iopkt(dmupio_wack_iopkt[152:0]),
805 .dmupio_srvc_wack(dmupio_srvc_wack),
806 .cmp_tick_enable(cmp_tick_enable),
807 .tcu_wmr_vec_mask(tcu_wmr_vec_mask),
808 .ncu_dbg1_error_event(ncu_dbg1_error_event),
809 .ncu_scksel(ncu_scksel[1:0]),
810 // Inputs
811 .tcu_dbr_gateoff(tcu_dbr_gateoff_i),
812 .aclk_wmr(aclk_wmr),
813 .wmr_protect(wmr_protect),
814 .mb1_scanin(mb1_scanin),
815 .tcu_mbist_user_mode(tcu_mbist_user_mode),
816 .mb1_start(mb1_start),
817 .tcu_mbist_bisi_en(tcu_mbist_bisi_en),
818 .bounce_ack_rd(bounce_ack_rd),
819 .ccu_ncu_stall(ccu_ncu_stall),
820 .core_running_status(core_running_status[63:0]),
821 .cpubuf_dout(cpubuf_dout[143:0]),
822 .cpubuf_tail_f(cpubuf_tail_f[5:0]),
823 .dmu_ncu_stall(dmu_ncu_stall),
824 .dmu_ncu_wrack_tag(dmu_ncu_wrack_tag[3:0]),
825 .dmu_ncu_wrack_vld(dmu_ncu_wrack_vld),
826 .dmu_ncu_wrack_par(dmu_ncu_wrack_par),
827 .efu_ncu_bankavail_dshift(efu_ncu_bankavail_dshift),
828 .efu_ncu_coreavail_dshift(efu_ncu_coreavail_dshift),
829 //.efu_ncu_fuse_clk1(efu_ncu_fuse_clk1),
830 .efu_ncu_fuse_data(efu_ncu_fuse_data),
831 .efu_ncu_fusestat_dshift(efu_ncu_fusestat_dshift),
832 .efu_ncu_sernum0_dshift(efu_ncu_sernum0_dshift),
833 .efu_ncu_sernum1_dshift(efu_ncu_sernum1_dshift),
834 .efu_ncu_sernum2_dshift(efu_ncu_sernum2_dshift),
835 .intman_pchkf2i2c(intman_pchkf2i2c),
836 .intman_tbl_dout(intman_tbl_dout[15:0]),
837 .dmubuf0_dout(dmubuf0_dout[143:0]),
838 .dmubuf1_dout(dmubuf1_dout[143:0]),
839 .iobuf_avail(iobuf_avail),
840 .io_intman_addr(io_intman_addr[6:0]),
841 .scan_in(ncu_c2iscd_ctl_scanin),
842 .scan_out(ncu_c2iscd_ctl_scanout),
843 .iol2clk (iol2clk),
844 .mcu0_ncu_stall(mcu0_ncu_stall),
845 .mcu1_ncu_stall(mcu1_ncu_stall),
846 .mcu2_ncu_stall(mcu2_ncu_stall),
847 .mcu3_ncu_stall(mcu3_ncu_stall),
848 .ncu_int_ack_rd(ncu_int_ack_rd),
849 .ncu_man_ack_rd(ncu_man_ack_rd),
850 .ncu_man_int_rd(ncu_man_int_rd),
851 .niu_ncu_stall(niu_ncu_stall),
852 .rcu_ncu_stall(rcu_ncu_stall),
853 .rd_nack_rd(rd_nack_rd),
854 .dbg1_ncu_stall(dbg1_ncu_stall),
855 .rst_ncu_unpark_thread(rst_ncu_unpark_thread),
856 .rst_ncu_xir_(rst_ncu_xir_),
857 .sii_cr_id_rtn(sii_cr_id_rtn[3:0]),
858 .sii_cr_id_rtn_vld(sii_cr_id_rtn_vld),
859 .ssi_ncu_stall(ssi_ncu_stall),
860 .tap_mondo_acc_addr_invld_d2_f(tap_mondo_acc_addr_invld_d2_f),
861 .tap_mondo_acc_seq_d2_f(tap_mondo_acc_seq_d2_f),
862 .tap_mondo_dout_d2_f(tap_mondo_dout_d2_f[63:0]),
863 .tcu_aclk(tcu_aclk),
864 .tcu_bclk(tcu_bclk),
865 .tcu_clk_stop(tcu_clk_stop),
866 .tcu_ncu_data(tcu_ncu_data[7:0]),
867 .tcu_ncu_vld(tcu_ncu_vld),
868 .tcu_pce_ov(tcu_pce_ov),
869 .tcu_scan_en(tcu_scan_en),
870 //.mb0_raddr(mb0_addr[5:0]),
871 //.mb0_iobuf_wr_en(mb0_iobuf_wr_en),
872 .dmu_ncu_d_pe(dmu_ncu_d_pe),
873 .dmu_ncu_siicr_pe(dmu_ncu_siicr_pe),
874 .dmu_ncu_ctag_ue(dmu_ncu_ctag_ue),
875 .dmu_ncu_ctag_ce(dmu_ncu_ctag_ce),
876 .dmu_ncu_ncucr_pe(dmu_ncu_ncucr_pe),
877 .dmu_ncu_ie(dmu_ncu_ie),
878 .niu_ncu_d_pe(niu_ncu_d_pe),
879 .niu_ncu_ctag_ue(niu_ncu_ctag_ue),
880 .niu_ncu_ctag_ce(niu_ncu_ctag_ce),
881 .sio_ncu_ctag_ce(sio_ncu_ctag_ce),
882 .sio_ncu_ctag_ue(sio_ncu_ctag_ue),
883 //.sio_ncu_d_pe(sio_ncu_d_pe),
884 .sii_ncu_dmuctag_ce(sii_ncu_dmuctag_ce),
885 .sii_ncu_dmuctag_ue(sii_ncu_dmuctag_ue),
886 .sii_ncu_dmua_pe(sii_ncu_dmua_pe),
887 .sii_ncu_dmud_pe(sii_ncu_dmud_pe),
888 .sii_ncu_niuctag_ce(sii_ncu_niuctag_ce),
889 .sii_ncu_niuctag_ue(sii_ncu_niuctag_ue),
890 .sii_ncu_niua_pe(sii_ncu_niua_pe),
891 .sii_ncu_niud_pe(sii_ncu_niud_pe),
892 .mcu0_ncu_ecc(mcu0_ncu_ecc),
893 .mcu0_ncu_fbr(mcu0_ncu_fbr),
894 .mcu0_ncu_fbu(mcu0_ncu_fbu),
895 .mcu1_ncu_ecc(mcu1_ncu_ecc),
896 .mcu1_ncu_fbr(mcu1_ncu_fbr),
897 .mcu1_ncu_fbu(mcu1_ncu_fbu),
898 .mcu2_ncu_ecc(mcu2_ncu_ecc),
899 .mcu2_ncu_fbr(mcu2_ncu_fbr),
900 .mcu2_ncu_fbu(mcu2_ncu_fbu),
901 .mcu3_ncu_ecc(mcu3_ncu_ecc),
902 .mcu3_ncu_fbr(mcu3_ncu_fbr),
903 .mcu3_ncu_fbu(mcu3_ncu_fbu),
904 .siierrsyn(siierrsyn[63:0]),
905 .siierrsyn_done(siierrsyn_done),
906 .io_rd_intman_d2(io_rd_intman_d2),
907 .ncuctag_ue(ncuctag_ue),
908 .ncuctag_ce(ncuctag_ce),
909 .ncusiid_pe(ncusiid_pe),
910 .ncudpsyn(ncudpsyn[15:0]),
911 .iobuf_ue_f(iobuf_ue_f),
912 .intbuf_ue_f(intbuf_ue_f),
913 .mondotbl_pe_f(mondotbl_pe_f),
914 .mb0_addr(mb0_addr[5:0]),
915 .mb0_wdata(mb0_wdata[7:0]),
916 .mb0_run(mb0_run),
917 .mb0_iobuf_wr_en(mb0_iobuf_wr_en),
918 .mb1_cpubuf_wr_en(mb1_cpubuf_wr_en));
919 // outputs
920
921
922
923///*ncu_i2cscd_ctl auto_template (
924// .scan_out( ) ); */
925ncu_i2cscd_ctl ncu_i2cscd_ctl ( /*AUTOINST*/
926 // Outputs
927 .bounce_ack_rd(bounce_ack_rd),
928 .iobuf_avail(iobuf_avail),
929 .iobuf_din(iobuf_din[175:0]),
930 .iobuf_tail_ptr(iobuf_tail_ptr[4:0]),
931 .iobuf_tail_s(iobuf_tail_s[5:0]),
932 .iobuf_wr(iobuf_wr),
933 .io_intman_addr(io_intman_addr[6:0]),
934 .io_mondo_data0_din_s(io_mondo_data0_din_s[63:0]),
935 .io_mondo_data1_din_s(io_mondo_data1_din_s[63:0]),
936 .io_mondo_data_wr_addr_s(io_mondo_data_wr_addr_s[5:0]),
937 .io_mondo_data_wr_s(io_mondo_data_wr_s),
938 .intman_pchkf2i2c(intman_pchkf2i2c),
939 .ncu_ccu_stall(ncu_ccu_stall),
940 .ncu_dmu_mondo_ack(ncu_dmu_mondo_ack),
941 .ncu_dmu_mondo_id(ncu_dmu_mondo_id[5:0]),
942 .ncu_dmu_mondo_id_par(ncu_dmu_mondo_id_par),
943 .ncu_dmu_mondo_nack(ncu_dmu_mondo_nack),
944 .ncu_dmu_stall(ncu_dmu_stall),
945 .ncu_int_ack_rd(ncu_int_ack_rd),
946 .ncu_man_ack_rd(ncu_man_ack_rd),
947 .ncu_man_int_rd(ncu_man_int_rd),
948 .ncu_mcu0_stall(ncu_mcu0_stall),
949 .ncu_mcu1_stall(ncu_mcu1_stall),
950 .ncu_mcu2_stall(ncu_mcu2_stall),
951 .ncu_mcu3_stall(ncu_mcu3_stall),
952 .ncu_niu_stall(ncu_niu_stall),
953 .ncu_rcu_stall(ncu_rcu_stall),
954 .ncu_dbg1_stall(ncu_dbg1_stall),
955 .ncu_sii_gnt(ncu_sii_gnt),
956 .ncu_ssi_stall(ncu_ssi_stall),
957 .ncu_tcu_data(ncu_tcu_data[7:0]),
958 .ncu_tcu_vld(ncu_tcu_vld),
959 .rd_nack_rd(rd_nack_rd),
960 .sii_cr_id_rtn(sii_cr_id_rtn[3:0]),
961 .sii_cr_id_rtn_vld(sii_cr_id_rtn_vld),
962 .io_rd_intman_d2(io_rd_intman_d2),
963 .siierrsyn(siierrsyn[63:0]),
964 .siierrsyn_done(siierrsyn_done),
965 .ncudpsyn(ncudpsyn[15:0]),
966 .ncuctag_ue(ncuctag_ue),
967 .ncuctag_ce(ncuctag_ce),
968 .ncusiid_pe(ncusiid_pe),
969 // Inputs
970 .tcu_dbr_gateoff(tcu_dbr_gateoff_i),
971 .bounce_ack_packet(bounce_ack_packet[127:0]),
972 .bounce_ack_vld(bounce_ack_vld),
973 .ccu_ncu_data(ccu_ncu_data[3:0]),
974 .ccu_ncu_vld(ccu_ncu_vld),
975 .dmu_ncu_data(dmu_ncu_data[31:0]),
976 .dmu_ncu_vld(dmu_ncu_vld),
977 .intman_tbl_dout(intman_tbl_dout[11:0]),
978 .iobuf_head_f(iobuf_head_f[5:0]),
979 .scan_in(ncu_i2cscd_ctl_scanin),
980 .scan_out(ncu_i2cscd_ctl_scanout),
981 .iol2clk (iol2clk),
982 .lhs_intman_acc(lhs_intman_acc),
983 .mcu0_ncu_data(mcu0_ncu_data[3:0]),
984 .mcu0_ncu_vld(mcu0_ncu_vld),
985 .mcu1_ncu_data(mcu1_ncu_data[3:0]),
986 .mcu1_ncu_vld(mcu1_ncu_vld),
987 .mcu2_ncu_data(mcu2_ncu_data[3:0]),
988 .mcu2_ncu_vld(mcu2_ncu_vld),
989 .mcu3_ncu_data(mcu3_ncu_data[3:0]),
990 .mcu3_ncu_vld(mcu3_ncu_vld),
991 .mondo_busy_vec_f(mondo_busy_vec_f[63:0]),
992 .mondoinvec(mondoinvec[5:0]),
993 .ncu_int_ack_packet(ncu_int_ack_packet[127:0]),
994 .ncu_int_ack_vld(ncu_int_ack_vld),
995 .ncu_man_ack_packet(ncu_man_ack_packet[127:0]),
996 .ncu_man_ack_vld(ncu_man_ack_vld),
997 .ncu_man_int_packet(ncu_man_int_packet[24:0]),
998 .ncu_man_int_vld(ncu_man_int_vld),
999 .niu_ncu_data(niu_ncu_data[31:0]),
1000 .niu_ncu_vld(niu_ncu_vld),
1001 .rcu_ncu_data(rcu_ncu_data[3:0]),
1002 .rcu_ncu_vld(rcu_ncu_vld),
1003 .rd_nack_packet(rd_nack_packet[63:0]),
1004 .rd_nack_vld(rd_nack_vld),
1005 .dbg1_ncu_data(dbg1_ncu_data[3:0]),
1006 .dbg1_ncu_vld(dbg1_ncu_vld),
1007 .sii_ncu_dparity(sii_ncu_dparity[1:0]),
1008 .sii_ncu_data(sii_ncu_data[31:0]),
1009 .sii_ncu_req(sii_ncu_req),
1010 .sii_ncu_syn_data(sii_ncu_syn_data[3:0]),
1011 .sii_ncu_syn_vld(sii_ncu_syn_vld),
1012 .srvc_wr_ack(srvc_wr_ack),
1013 .ssi_ncu_data(ssi_ncu_data[3:0]),
1014 .ssi_ncu_vld(ssi_ncu_vld),
1015 .tcu_clk_stop(tcu_clk_stop),
1016 .tcu_ncu_stall(tcu_ncu_stall),
1017 .tcu_pce_ov(tcu_pce_ov),
1018 .tcu_scan_en(tcu_scan_en),
1019 .tcu_aclk(tcu_aclk),
1020 .tcu_bclk(tcu_bclk),
1021 .wr_ack_iopkt(wr_ack_iopkt[152:0]),
1022 .raserrce(raserrce),
1023 .raserrue(raserrue),
1024 .mb0_addr(mb0_addr[5:0]),
1025 .mb0_wdata(mb0_wdata[7:0]),
1026 .mb0_run(mb0_run),
1027 .mb0_iobuf_wr_en(mb0_iobuf_wr_en),
1028 .dmupio_wack_iopkt(dmupio_wack_iopkt[152:0]),
1029 .dmupio_srvc_wack(dmupio_srvc_wack),
1030 .ncuctag_uei(ncuctag_uei),
1031 .ncuctag_cei(ncuctag_cei),
1032 .ncusiid_pei(ncusiid_pei));
1033
1034/* spare gate, 58957 cells/450 = 132 spare gate */
1035
1036/*
1037spare_ctl_macro spares (num=132) (
1038 .scan_in(spares_scanin),
1039 .scan_out(spares_scanout),
1040 .l1clk (l1clk)
1041 );
1042*/
1043
1044
1045// fixscan start:
1046assign ncu_c2iscd_ctl_scanin = scan_in ;
1047assign ncu_i2cscd_ctl_scanin = ncu_c2iscd_ctl_scanout ;
1048//assign spares_scanin = ncu_i2cscd_ctl_scanout ;
1049//assign scan_out = spares_scanout ;
1050assign scan_out = ncu_i2cscd_ctl_scanout ;
1051// fixscan end:
1052endmodule
1053
1054
1055
1056
1057
1058// any PARAMS parms go into naming of macro
1059
1060module ncu_scd_ctl_msff_ctl_macro__width_6 (
1061 din,
1062 l1clk,
1063 scan_in,
1064 siclk,
1065 soclk,
1066 dout,
1067 scan_out);
1068wire [5:0] fdin;
1069wire [4:0] so;
1070
1071 input [5:0] din;
1072 input l1clk;
1073 input scan_in;
1074
1075
1076 input siclk;
1077 input soclk;
1078
1079 output [5:0] dout;
1080 output scan_out;
1081assign fdin[5:0] = din[5:0];
1082
1083
1084
1085
1086
1087
1088dff #(6) d0_0 (
1089.l1clk(l1clk),
1090.siclk(siclk),
1091.soclk(soclk),
1092.d(fdin[5:0]),
1093.si({scan_in,so[4:0]}),
1094.so({so[4:0],scan_out}),
1095.q(dout[5:0])
1096);
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109endmodule
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123// any PARAMS parms go into naming of macro
1124
1125module ncu_scd_ctl_msff_ctl_macro__width_1 (
1126 din,
1127 l1clk,
1128 scan_in,
1129 siclk,
1130 soclk,
1131 dout,
1132 scan_out);
1133wire [0:0] fdin;
1134
1135 input [0:0] din;
1136 input l1clk;
1137 input scan_in;
1138
1139
1140 input siclk;
1141 input soclk;
1142
1143 output [0:0] dout;
1144 output scan_out;
1145assign fdin[0:0] = din[0:0];
1146
1147
1148
1149
1150
1151
1152dff #(1) d0_0 (
1153.l1clk(l1clk),
1154.siclk(siclk),
1155.soclk(soclk),
1156.d(fdin[0:0]),
1157.si(scan_in),
1158.so(scan_out),
1159.q(dout[0:0])
1160);
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173endmodule
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187// any PARAMS parms go into naming of macro
1188
1189module ncu_scd_ctl_msff_ctl_macro__en_1__width_1 (
1190 din,
1191 en,
1192 l1clk,
1193 scan_in,
1194 siclk,
1195 soclk,
1196 dout,
1197 scan_out);
1198wire [0:0] fdin;
1199
1200 input [0:0] din;
1201 input en;
1202 input l1clk;
1203 input scan_in;
1204
1205
1206 input siclk;
1207 input soclk;
1208
1209 output [0:0] dout;
1210 output scan_out;
1211assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
1212
1213
1214
1215
1216
1217
1218dff #(1) d0_0 (
1219.l1clk(l1clk),
1220.siclk(siclk),
1221.soclk(soclk),
1222.d(fdin[0:0]),
1223.si(scan_in),
1224.so(scan_out),
1225.q(dout[0:0])
1226);
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239endmodule
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253// any PARAMS parms go into naming of macro
1254
1255module ncu_scd_ctl_l1clkhdr_ctl_macro (
1256 l2clk,
1257 l1en,
1258 pce_ov,
1259 stop,
1260 se,
1261 l1clk);
1262
1263
1264 input l2clk;
1265 input l1en;
1266 input pce_ov;
1267 input stop;
1268 input se;
1269 output l1clk;
1270
1271
1272
1273
1274
1275cl_sc1_l1hdr_8x c_0 (
1276
1277
1278 .l2clk(l2clk),
1279 .pce(l1en),
1280 .l1clk(l1clk),
1281 .se(se),
1282 .pce_ov(pce_ov),
1283 .stop(stop)
1284);
1285
1286
1287
1288endmodule
1289
1290
1291
1292
1293// any PARAMS parms go into naming of macro
1294
1295module ncu_scd_ctl_msff_ctl_macro__en_1__width_64 (
1296 din,
1297 en,
1298 l1clk,
1299 scan_in,
1300 siclk,
1301 soclk,
1302 dout,
1303 scan_out);
1304wire [63:0] fdin;
1305wire [62:0] so;
1306
1307 input [63:0] din;
1308 input en;
1309 input l1clk;
1310 input scan_in;
1311
1312
1313 input siclk;
1314 input soclk;
1315
1316 output [63:0] dout;
1317 output scan_out;
1318assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}});
1319
1320
1321
1322
1323
1324
1325dff #(64) d0_0 (
1326.l1clk(l1clk),
1327.siclk(siclk),
1328.soclk(soclk),
1329.d(fdin[63:0]),
1330.si({scan_in,so[62:0]}),
1331.so({so[62:0],scan_out}),
1332.q(dout[63:0])
1333);
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346endmodule
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360// any PARAMS parms go into naming of macro
1361
1362module ncu_scd_ctl_msff_ctl_macro__en_1__width_40 (
1363 din,
1364 en,
1365 l1clk,
1366 scan_in,
1367 siclk,
1368 soclk,
1369 dout,
1370 scan_out);
1371wire [39:0] fdin;
1372wire [38:0] so;
1373
1374 input [39:0] din;
1375 input en;
1376 input l1clk;
1377 input scan_in;
1378
1379
1380 input siclk;
1381 input soclk;
1382
1383 output [39:0] dout;
1384 output scan_out;
1385assign fdin[39:0] = (din[39:0] & {40{en}}) | (dout[39:0] & ~{40{en}});
1386
1387
1388
1389
1390
1391
1392dff #(40) d0_0 (
1393.l1clk(l1clk),
1394.siclk(siclk),
1395.soclk(soclk),
1396.d(fdin[39:0]),
1397.si({scan_in,so[38:0]}),
1398.so({so[38:0],scan_out}),
1399.q(dout[39:0])
1400);
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413endmodule
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427// any PARAMS parms go into naming of macro
1428
1429module ncu_scd_ctl_msff_ctl_macro__en_1__width_2 (
1430 din,
1431 en,
1432 l1clk,
1433 scan_in,
1434 siclk,
1435 soclk,
1436 dout,
1437 scan_out);
1438wire [1:0] fdin;
1439wire [0:0] so;
1440
1441 input [1:0] din;
1442 input en;
1443 input l1clk;
1444 input scan_in;
1445
1446
1447 input siclk;
1448 input soclk;
1449
1450 output [1:0] dout;
1451 output scan_out;
1452assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}});
1453
1454
1455
1456
1457
1458
1459dff #(2) d0_0 (
1460.l1clk(l1clk),
1461.siclk(siclk),
1462.soclk(soclk),
1463.d(fdin[1:0]),
1464.si({scan_in,so[0:0]}),
1465.so({so[0:0],scan_out}),
1466.q(dout[1:0])
1467);
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480endmodule
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494// any PARAMS parms go into naming of macro
1495
1496module ncu_scd_ctl_msff_ctl_macro__en_1__width_6 (
1497 din,
1498 en,
1499 l1clk,
1500 scan_in,
1501 siclk,
1502 soclk,
1503 dout,
1504 scan_out);
1505wire [5:0] fdin;
1506wire [4:0] so;
1507
1508 input [5:0] din;
1509 input en;
1510 input l1clk;
1511 input scan_in;
1512
1513
1514 input siclk;
1515 input soclk;
1516
1517 output [5:0] dout;
1518 output scan_out;
1519assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}});
1520
1521
1522
1523
1524
1525
1526dff #(6) d0_0 (
1527.l1clk(l1clk),
1528.siclk(siclk),
1529.soclk(soclk),
1530.d(fdin[5:0]),
1531.si({scan_in,so[4:0]}),
1532.so({so[4:0],scan_out}),
1533.q(dout[5:0])
1534);
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547endmodule
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561// any PARAMS parms go into naming of macro
1562
1563module ncu_scd_ctl_msff_ctl_macro__en_1__width_25 (
1564 din,
1565 en,
1566 l1clk,
1567 scan_in,
1568 siclk,
1569 soclk,
1570 dout,
1571 scan_out);
1572wire [24:0] fdin;
1573wire [23:0] so;
1574
1575 input [24:0] din;
1576 input en;
1577 input l1clk;
1578 input scan_in;
1579
1580
1581 input siclk;
1582 input soclk;
1583
1584 output [24:0] dout;
1585 output scan_out;
1586assign fdin[24:0] = (din[24:0] & {25{en}}) | (dout[24:0] & ~{25{en}});
1587
1588
1589
1590
1591
1592
1593dff #(25) d0_0 (
1594.l1clk(l1clk),
1595.siclk(siclk),
1596.soclk(soclk),
1597.d(fdin[24:0]),
1598.si({scan_in,so[23:0]}),
1599.so({so[23:0],scan_out}),
1600.q(dout[24:0])
1601);
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614endmodule
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628// any PARAMS parms go into naming of macro
1629
1630module ncu_scd_ctl_msff_ctl_macro__en_1__width_128 (
1631 din,
1632 en,
1633 l1clk,
1634 scan_in,
1635 siclk,
1636 soclk,
1637 dout,
1638 scan_out);
1639wire [127:0] fdin;
1640wire [126:0] so;
1641
1642 input [127:0] din;
1643 input en;
1644 input l1clk;
1645 input scan_in;
1646
1647
1648 input siclk;
1649 input soclk;
1650
1651 output [127:0] dout;
1652 output scan_out;
1653assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}});
1654
1655
1656
1657
1658
1659
1660dff #(128) d0_0 (
1661.l1clk(l1clk),
1662.siclk(siclk),
1663.soclk(soclk),
1664.d(fdin[127:0]),
1665.si({scan_in,so[126:0]}),
1666.so({so[126:0],scan_out}),
1667.q(dout[127:0])
1668);
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681endmodule
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695// any PARAMS parms go into naming of macro
1696
1697module ncu_scd_ctl_msff_ctl_macro__en_1__width_55 (
1698 din,
1699 en,
1700 l1clk,
1701 scan_in,
1702 siclk,
1703 soclk,
1704 dout,
1705 scan_out);
1706wire [54:0] fdin;
1707wire [53:0] so;
1708
1709 input [54:0] din;
1710 input en;
1711 input l1clk;
1712 input scan_in;
1713
1714
1715 input siclk;
1716 input soclk;
1717
1718 output [54:0] dout;
1719 output scan_out;
1720assign fdin[54:0] = (din[54:0] & {55{en}}) | (dout[54:0] & ~{55{en}});
1721
1722
1723
1724
1725
1726
1727dff #(55) d0_0 (
1728.l1clk(l1clk),
1729.siclk(siclk),
1730.soclk(soclk),
1731.d(fdin[54:0]),
1732.si({scan_in,so[53:0]}),
1733.so({so[53:0],scan_out}),
1734.q(dout[54:0])
1735);
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748endmodule
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762// any PARAMS parms go into naming of macro
1763
1764module ncu_scd_ctl_msff_ctl_macro__en_1__width_22 (
1765 din,
1766 en,
1767 l1clk,
1768 scan_in,
1769 siclk,
1770 soclk,
1771 dout,
1772 scan_out);
1773wire [21:0] fdin;
1774wire [20:0] so;
1775
1776 input [21:0] din;
1777 input en;
1778 input l1clk;
1779 input scan_in;
1780
1781
1782 input siclk;
1783 input soclk;
1784
1785 output [21:0] dout;
1786 output scan_out;
1787assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}});
1788
1789
1790
1791
1792
1793
1794dff #(22) d0_0 (
1795.l1clk(l1clk),
1796.siclk(siclk),
1797.soclk(soclk),
1798.d(fdin[21:0]),
1799.si({scan_in,so[20:0]}),
1800.so({so[20:0],scan_out}),
1801.q(dout[21:0])
1802);
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815endmodule
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829// any PARAMS parms go into naming of macro
1830
1831module ncu_scd_ctl_msff_ctl_macro__en_1__width_20 (
1832 din,
1833 en,
1834 l1clk,
1835 scan_in,
1836 siclk,
1837 soclk,
1838 dout,
1839 scan_out);
1840wire [19:0] fdin;
1841wire [18:0] so;
1842
1843 input [19:0] din;
1844 input en;
1845 input l1clk;
1846 input scan_in;
1847
1848
1849 input siclk;
1850 input soclk;
1851
1852 output [19:0] dout;
1853 output scan_out;
1854assign fdin[19:0] = (din[19:0] & {20{en}}) | (dout[19:0] & ~{20{en}});
1855
1856
1857
1858
1859
1860
1861dff #(20) d0_0 (
1862.l1clk(l1clk),
1863.siclk(siclk),
1864.soclk(soclk),
1865.d(fdin[19:0]),
1866.si({scan_in,so[18:0]}),
1867.so({so[18:0],scan_out}),
1868.q(dout[19:0])
1869);
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882endmodule
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896// any PARAMS parms go into naming of macro
1897
1898module ncu_scd_ctl_msff_ctl_macro__en_1__width_8 (
1899 din,
1900 en,
1901 l1clk,
1902 scan_in,
1903 siclk,
1904 soclk,
1905 dout,
1906 scan_out);
1907wire [7:0] fdin;
1908wire [6:0] so;
1909
1910 input [7:0] din;
1911 input en;
1912 input l1clk;
1913 input scan_in;
1914
1915
1916 input siclk;
1917 input soclk;
1918
1919 output [7:0] dout;
1920 output scan_out;
1921assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}});
1922
1923
1924
1925
1926
1927
1928dff #(8) d0_0 (
1929.l1clk(l1clk),
1930.siclk(siclk),
1931.soclk(soclk),
1932.d(fdin[7:0]),
1933.si({scan_in,so[6:0]}),
1934.so({so[6:0],scan_out}),
1935.q(dout[7:0])
1936);
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949endmodule
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963// any PARAMS parms go into naming of macro
1964
1965module ncu_scd_ctl_msff_ctl_macro__en_1__width_12 (
1966 din,
1967 en,
1968 l1clk,
1969 scan_in,
1970 siclk,
1971 soclk,
1972 dout,
1973 scan_out);
1974wire [11:0] fdin;
1975wire [10:0] so;
1976
1977 input [11:0] din;
1978 input en;
1979 input l1clk;
1980 input scan_in;
1981
1982
1983 input siclk;
1984 input soclk;
1985
1986 output [11:0] dout;
1987 output scan_out;
1988assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}});
1989
1990
1991
1992
1993
1994
1995dff #(12) d0_0 (
1996.l1clk(l1clk),
1997.siclk(siclk),
1998.soclk(soclk),
1999.d(fdin[11:0]),
2000.si({scan_in,so[10:0]}),
2001.so({so[10:0],scan_out}),
2002.q(dout[11:0])
2003);
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016endmodule
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030// any PARAMS parms go into naming of macro
2031
2032module ncu_scd_ctl_msff_ctl_macro__en_1__width_24 (
2033 din,
2034 en,
2035 l1clk,
2036 scan_in,
2037 siclk,
2038 soclk,
2039 dout,
2040 scan_out);
2041wire [23:0] fdin;
2042wire [22:0] so;
2043
2044 input [23:0] din;
2045 input en;
2046 input l1clk;
2047 input scan_in;
2048
2049
2050 input siclk;
2051 input soclk;
2052
2053 output [23:0] dout;
2054 output scan_out;
2055assign fdin[23:0] = (din[23:0] & {24{en}}) | (dout[23:0] & ~{24{en}});
2056
2057
2058
2059
2060
2061
2062dff #(24) d0_0 (
2063.l1clk(l1clk),
2064.siclk(siclk),
2065.soclk(soclk),
2066.d(fdin[23:0]),
2067.si({scan_in,so[22:0]}),
2068.so({so[22:0],scan_out}),
2069.q(dout[23:0])
2070);
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083endmodule
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097// any PARAMS parms go into naming of macro
2098
2099module ncu_scd_ctl_msff_ctl_macro__width_64 (
2100 din,
2101 l1clk,
2102 scan_in,
2103 siclk,
2104 soclk,
2105 dout,
2106 scan_out);
2107wire [63:0] fdin;
2108wire [62:0] so;
2109
2110 input [63:0] din;
2111 input l1clk;
2112 input scan_in;
2113
2114
2115 input siclk;
2116 input soclk;
2117
2118 output [63:0] dout;
2119 output scan_out;
2120assign fdin[63:0] = din[63:0];
2121
2122
2123
2124
2125
2126
2127dff #(64) d0_0 (
2128.l1clk(l1clk),
2129.siclk(siclk),
2130.soclk(soclk),
2131.d(fdin[63:0]),
2132.si({scan_in,so[62:0]}),
2133.so({so[62:0],scan_out}),
2134.q(dout[63:0])
2135);
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148endmodule
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162// any PARAMS parms go into naming of macro
2163
2164module ncu_scd_ctl_msff_ctl_macro__width_8 (
2165 din,
2166 l1clk,
2167 scan_in,
2168 siclk,
2169 soclk,
2170 dout,
2171 scan_out);
2172wire [7:0] fdin;
2173wire [6:0] so;
2174
2175 input [7:0] din;
2176 input l1clk;
2177 input scan_in;
2178
2179
2180 input siclk;
2181 input soclk;
2182
2183 output [7:0] dout;
2184 output scan_out;
2185assign fdin[7:0] = din[7:0];
2186
2187
2188
2189
2190
2191
2192dff #(8) d0_0 (
2193.l1clk(l1clk),
2194.siclk(siclk),
2195.soclk(soclk),
2196.d(fdin[7:0]),
2197.si({scan_in,so[6:0]}),
2198.so({so[6:0],scan_out}),
2199.q(dout[7:0])
2200);
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213endmodule
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227// any PARAMS parms go into naming of macro
2228
2229module ncu_scd_ctl_msffi_ctl_macro__width_1 (
2230 din,
2231 l1clk,
2232 scan_in,
2233 siclk,
2234 soclk,
2235 q_l,
2236 scan_out);
2237 input [0:0] din;
2238 input l1clk;
2239 input scan_in;
2240
2241
2242 input siclk;
2243 input soclk;
2244
2245 output [0:0] q_l;
2246 output scan_out;
2247
2248
2249
2250
2251
2252
2253msffi #(1) d0_0 (
2254.l1clk(l1clk),
2255.siclk(siclk),
2256.soclk(soclk),
2257.d(din[0:0]),
2258.si(scan_in),
2259.so(scan_out),
2260.q_l(q_l[0:0])
2261);
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274endmodule
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288// any PARAMS parms go into naming of macro
2289
2290module ncu_scd_ctl_msff_ctl_macro__width_56 (
2291 din,
2292 l1clk,
2293 scan_in,
2294 siclk,
2295 soclk,
2296 dout,
2297 scan_out);
2298wire [55:0] fdin;
2299wire [54:0] so;
2300
2301 input [55:0] din;
2302 input l1clk;
2303 input scan_in;
2304
2305
2306 input siclk;
2307 input soclk;
2308
2309 output [55:0] dout;
2310 output scan_out;
2311assign fdin[55:0] = din[55:0];
2312
2313
2314
2315
2316
2317
2318dff #(56) d0_0 (
2319.l1clk(l1clk),
2320.siclk(siclk),
2321.soclk(soclk),
2322.d(fdin[55:0]),
2323.si({scan_in,so[54:0]}),
2324.so({so[54:0],scan_out}),
2325.q(dout[55:0])
2326);
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339endmodule
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353// any PARAMS parms go into naming of macro
2354
2355module ncu_scd_ctl_msff_ctl_macro__en_1__width_3 (
2356 din,
2357 en,
2358 l1clk,
2359 scan_in,
2360 siclk,
2361 soclk,
2362 dout,
2363 scan_out);
2364wire [2:0] fdin;
2365wire [1:0] so;
2366
2367 input [2:0] din;
2368 input en;
2369 input l1clk;
2370 input scan_in;
2371
2372
2373 input siclk;
2374 input soclk;
2375
2376 output [2:0] dout;
2377 output scan_out;
2378assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}});
2379
2380
2381
2382
2383
2384
2385dff #(3) d0_0 (
2386.l1clk(l1clk),
2387.siclk(siclk),
2388.soclk(soclk),
2389.d(fdin[2:0]),
2390.si({scan_in,so[1:0]}),
2391.so({so[1:0],scan_out}),
2392.q(dout[2:0])
2393);
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406endmodule
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420// any PARAMS parms go into naming of macro
2421
2422module ncu_scd_ctl_msff_ctl_macro__width_63 (
2423 din,
2424 l1clk,
2425 scan_in,
2426 siclk,
2427 soclk,
2428 dout,
2429 scan_out);
2430wire [62:0] fdin;
2431wire [61:0] so;
2432
2433 input [62:0] din;
2434 input l1clk;
2435 input scan_in;
2436
2437
2438 input siclk;
2439 input soclk;
2440
2441 output [62:0] dout;
2442 output scan_out;
2443assign fdin[62:0] = din[62:0];
2444
2445
2446
2447
2448
2449
2450dff #(63) d0_0 (
2451.l1clk(l1clk),
2452.siclk(siclk),
2453.soclk(soclk),
2454.d(fdin[62:0]),
2455.si({scan_in,so[61:0]}),
2456.so({so[61:0],scan_out}),
2457.q(dout[62:0])
2458);
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471endmodule
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485// any PARAMS parms go into naming of macro
2486
2487module ncu_scd_ctl_msff_ctl_macro__width_5 (
2488 din,
2489 l1clk,
2490 scan_in,
2491 siclk,
2492 soclk,
2493 dout,
2494 scan_out);
2495wire [4:0] fdin;
2496wire [3:0] so;
2497
2498 input [4:0] din;
2499 input l1clk;
2500 input scan_in;
2501
2502
2503 input siclk;
2504 input soclk;
2505
2506 output [4:0] dout;
2507 output scan_out;
2508assign fdin[4:0] = din[4:0];
2509
2510
2511
2512
2513
2514
2515dff #(5) d0_0 (
2516.l1clk(l1clk),
2517.siclk(siclk),
2518.soclk(soclk),
2519.d(fdin[4:0]),
2520.si({scan_in,so[3:0]}),
2521.so({so[3:0],scan_out}),
2522.q(dout[4:0])
2523);
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536endmodule
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550// any PARAMS parms go into naming of macro
2551
2552module ncu_scd_ctl_msff_ctl_macro__en_1__width_5 (
2553 din,
2554 en,
2555 l1clk,
2556 scan_in,
2557 siclk,
2558 soclk,
2559 dout,
2560 scan_out);
2561wire [4:0] fdin;
2562wire [3:0] so;
2563
2564 input [4:0] din;
2565 input en;
2566 input l1clk;
2567 input scan_in;
2568
2569
2570 input siclk;
2571 input soclk;
2572
2573 output [4:0] dout;
2574 output scan_out;
2575assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}});
2576
2577
2578
2579
2580
2581
2582dff #(5) d0_0 (
2583.l1clk(l1clk),
2584.siclk(siclk),
2585.soclk(soclk),
2586.d(fdin[4:0]),
2587.si({scan_in,so[3:0]}),
2588.so({so[3:0],scan_out}),
2589.q(dout[4:0])
2590);
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603endmodule
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617// any PARAMS parms go into naming of macro
2618
2619module ncu_scd_ctl_msff_ctl_macro__width_43 (
2620 din,
2621 l1clk,
2622 scan_in,
2623 siclk,
2624 soclk,
2625 dout,
2626 scan_out);
2627wire [42:0] fdin;
2628wire [41:0] so;
2629
2630 input [42:0] din;
2631 input l1clk;
2632 input scan_in;
2633
2634
2635 input siclk;
2636 input soclk;
2637
2638 output [42:0] dout;
2639 output scan_out;
2640assign fdin[42:0] = din[42:0];
2641
2642
2643
2644
2645
2646
2647dff #(43) d0_0 (
2648.l1clk(l1clk),
2649.siclk(siclk),
2650.soclk(soclk),
2651.d(fdin[42:0]),
2652.si({scan_in,so[41:0]}),
2653.so({so[41:0],scan_out}),
2654.q(dout[42:0])
2655);
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668endmodule
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682// any PARAMS parms go into naming of macro
2683
2684module ncu_scd_ctl_msff_ctl_macro__en_1__width_43 (
2685 din,
2686 en,
2687 l1clk,
2688 scan_in,
2689 siclk,
2690 soclk,
2691 dout,
2692 scan_out);
2693wire [42:0] fdin;
2694wire [41:0] so;
2695
2696 input [42:0] din;
2697 input en;
2698 input l1clk;
2699 input scan_in;
2700
2701
2702 input siclk;
2703 input soclk;
2704
2705 output [42:0] dout;
2706 output scan_out;
2707assign fdin[42:0] = (din[42:0] & {43{en}}) | (dout[42:0] & ~{43{en}});
2708
2709
2710
2711
2712
2713
2714dff #(43) d0_0 (
2715.l1clk(l1clk),
2716.siclk(siclk),
2717.soclk(soclk),
2718.d(fdin[42:0]),
2719.si({scan_in,so[41:0]}),
2720.so({so[41:0],scan_out}),
2721.q(dout[42:0])
2722);
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735endmodule
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749// any PARAMS parms go into naming of macro
2750
2751module ncu_scd_ctl_msff_ctl_macro__en_1__width_59 (
2752 din,
2753 en,
2754 l1clk,
2755 scan_in,
2756 siclk,
2757 soclk,
2758 dout,
2759 scan_out);
2760wire [58:0] fdin;
2761wire [57:0] so;
2762
2763 input [58:0] din;
2764 input en;
2765 input l1clk;
2766 input scan_in;
2767
2768
2769 input siclk;
2770 input soclk;
2771
2772 output [58:0] dout;
2773 output scan_out;
2774assign fdin[58:0] = (din[58:0] & {59{en}}) | (dout[58:0] & ~{59{en}});
2775
2776
2777
2778
2779
2780
2781dff #(59) d0_0 (
2782.l1clk(l1clk),
2783.siclk(siclk),
2784.soclk(soclk),
2785.d(fdin[58:0]),
2786.si({scan_in,so[57:0]}),
2787.so({so[57:0],scan_out}),
2788.q(dout[58:0])
2789);
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802endmodule
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816// any PARAMS parms go into naming of macro
2817
2818module ncu_scd_ctl_msff_ctl_macro__en_1__width_61 (
2819 din,
2820 en,
2821 l1clk,
2822 scan_in,
2823 siclk,
2824 soclk,
2825 dout,
2826 scan_out);
2827wire [60:0] fdin;
2828wire [59:0] so;
2829
2830 input [60:0] din;
2831 input en;
2832 input l1clk;
2833 input scan_in;
2834
2835
2836 input siclk;
2837 input soclk;
2838
2839 output [60:0] dout;
2840 output scan_out;
2841assign fdin[60:0] = (din[60:0] & {61{en}}) | (dout[60:0] & ~{61{en}});
2842
2843
2844
2845
2846
2847
2848dff #(61) d0_0 (
2849.l1clk(l1clk),
2850.siclk(siclk),
2851.soclk(soclk),
2852.d(fdin[60:0]),
2853.si({scan_in,so[59:0]}),
2854.so({so[59:0],scan_out}),
2855.q(dout[60:0])
2856);
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869endmodule
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883// any PARAMS parms go into naming of macro
2884
2885module ncu_scd_ctl_msff_ctl_macro__width_2 (
2886 din,
2887 l1clk,
2888 scan_in,
2889 siclk,
2890 soclk,
2891 dout,
2892 scan_out);
2893wire [1:0] fdin;
2894wire [0:0] so;
2895
2896 input [1:0] din;
2897 input l1clk;
2898 input scan_in;
2899
2900
2901 input siclk;
2902 input soclk;
2903
2904 output [1:0] dout;
2905 output scan_out;
2906assign fdin[1:0] = din[1:0];
2907
2908
2909
2910
2911
2912
2913dff #(2) d0_0 (
2914.l1clk(l1clk),
2915.siclk(siclk),
2916.soclk(soclk),
2917.d(fdin[1:0]),
2918.si({scan_in,so[0:0]}),
2919.so({so[0:0],scan_out}),
2920.q(dout[1:0])
2921);
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934endmodule
2935
2936
2937
2938
2939// any PARAMS parms go into naming of macro
2940
2941module ncu_scd_ctl_msff_ctl_macro__width_9 (
2942 din,
2943 l1clk,
2944 scan_in,
2945 siclk,
2946 soclk,
2947 dout,
2948 scan_out);
2949wire [8:0] fdin;
2950wire [7:0] so;
2951
2952 input [8:0] din;
2953 input l1clk;
2954 input scan_in;
2955
2956
2957 input siclk;
2958 input soclk;
2959
2960 output [8:0] dout;
2961 output scan_out;
2962assign fdin[8:0] = din[8:0];
2963
2964
2965
2966
2967
2968
2969dff #(9) d0_0 (
2970.l1clk(l1clk),
2971.siclk(siclk),
2972.soclk(soclk),
2973.d(fdin[8:0]),
2974.si({scan_in,so[7:0]}),
2975.so({so[7:0],scan_out}),
2976.q(dout[8:0])
2977);
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990endmodule
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004// any PARAMS parms go into naming of macro
3005
3006module ncu_scd_ctl_msff_ctl_macro__width_7 (
3007 din,
3008 l1clk,
3009 scan_in,
3010 siclk,
3011 soclk,
3012 dout,
3013 scan_out);
3014wire [6:0] fdin;
3015wire [5:0] so;
3016
3017 input [6:0] din;
3018 input l1clk;
3019 input scan_in;
3020
3021
3022 input siclk;
3023 input soclk;
3024
3025 output [6:0] dout;
3026 output scan_out;
3027assign fdin[6:0] = din[6:0];
3028
3029
3030
3031
3032
3033
3034dff #(7) d0_0 (
3035.l1clk(l1clk),
3036.siclk(siclk),
3037.soclk(soclk),
3038.d(fdin[6:0]),
3039.si({scan_in,so[5:0]}),
3040.so({so[5:0],scan_out}),
3041.q(dout[6:0])
3042);
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055endmodule
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069// any PARAMS parms go into naming of macro
3070
3071module ncu_scd_ctl_msff_ctl_macro__width_4 (
3072 din,
3073 l1clk,
3074 scan_in,
3075 siclk,
3076 soclk,
3077 dout,
3078 scan_out);
3079wire [3:0] fdin;
3080wire [2:0] so;
3081
3082 input [3:0] din;
3083 input l1clk;
3084 input scan_in;
3085
3086
3087 input siclk;
3088 input soclk;
3089
3090 output [3:0] dout;
3091 output scan_out;
3092assign fdin[3:0] = din[3:0];
3093
3094
3095
3096
3097
3098
3099dff #(4) d0_0 (
3100.l1clk(l1clk),
3101.siclk(siclk),
3102.soclk(soclk),
3103.d(fdin[3:0]),
3104.si({scan_in,so[2:0]}),
3105.so({so[2:0],scan_out}),
3106.q(dout[3:0])
3107);
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120endmodule
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134// any PARAMS parms go into naming of macro
3135
3136module ncu_scd_ctl_msff_ctl_macro__width_40 (
3137 din,
3138 l1clk,
3139 scan_in,
3140 siclk,
3141 soclk,
3142 dout,
3143 scan_out);
3144wire [39:0] fdin;
3145wire [38:0] so;
3146
3147 input [39:0] din;
3148 input l1clk;
3149 input scan_in;
3150
3151
3152 input siclk;
3153 input soclk;
3154
3155 output [39:0] dout;
3156 output scan_out;
3157assign fdin[39:0] = din[39:0];
3158
3159
3160
3161
3162
3163
3164dff #(40) d0_0 (
3165.l1clk(l1clk),
3166.siclk(siclk),
3167.soclk(soclk),
3168.d(fdin[39:0]),
3169.si({scan_in,so[38:0]}),
3170.so({so[38:0],scan_out}),
3171.q(dout[39:0])
3172);
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185endmodule
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199// any PARAMS parms go into naming of macro
3200
3201module ncu_scd_ctl_msff_ctl_macro__width_23 (
3202 din,
3203 l1clk,
3204 scan_in,
3205 siclk,
3206 soclk,
3207 dout,
3208 scan_out);
3209wire [22:0] fdin;
3210wire [21:0] so;
3211
3212 input [22:0] din;
3213 input l1clk;
3214 input scan_in;
3215
3216
3217 input siclk;
3218 input soclk;
3219
3220 output [22:0] dout;
3221 output scan_out;
3222assign fdin[22:0] = din[22:0];
3223
3224
3225
3226
3227
3228
3229dff #(23) d0_0 (
3230.l1clk(l1clk),
3231.siclk(siclk),
3232.soclk(soclk),
3233.d(fdin[22:0]),
3234.si({scan_in,so[21:0]}),
3235.so({so[21:0],scan_out}),
3236.q(dout[22:0])
3237);
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250endmodule
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264// any PARAMS parms go into naming of macro
3265
3266module ncu_scd_ctl_msff_ctl_macro__width_3 (
3267 din,
3268 l1clk,
3269 scan_in,
3270 siclk,
3271 soclk,
3272 dout,
3273 scan_out);
3274wire [2:0] fdin;
3275wire [1:0] so;
3276
3277 input [2:0] din;
3278 input l1clk;
3279 input scan_in;
3280
3281
3282 input siclk;
3283 input soclk;
3284
3285 output [2:0] dout;
3286 output scan_out;
3287assign fdin[2:0] = din[2:0];
3288
3289
3290
3291
3292
3293
3294dff #(3) d0_0 (
3295.l1clk(l1clk),
3296.siclk(siclk),
3297.soclk(soclk),
3298.d(fdin[2:0]),
3299.si({scan_in,so[1:0]}),
3300.so({so[1:0],scan_out}),
3301.q(dout[2:0])
3302);
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315endmodule
3316
3317
3318
3319
3320// Local Variables:
3321// verilog-auto-sense-defines-constant:t
3322// End:
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332// any PARAMS parms go into naming of macro
3333
3334module ncu_scd_ctl_msff_ctl_macro__en_1__width_144 (
3335 din,
3336 en,
3337 l1clk,
3338 scan_in,
3339 siclk,
3340 soclk,
3341 dout,
3342 scan_out);
3343wire [143:0] fdin;
3344wire [142:0] so;
3345
3346 input [143:0] din;
3347 input en;
3348 input l1clk;
3349 input scan_in;
3350
3351
3352 input siclk;
3353 input soclk;
3354
3355 output [143:0] dout;
3356 output scan_out;
3357assign fdin[143:0] = (din[143:0] & {144{en}}) | (dout[143:0] & ~{144{en}});
3358
3359
3360
3361
3362
3363
3364dff #(144) d0_0 (
3365.l1clk(l1clk),
3366.siclk(siclk),
3367.soclk(soclk),
3368.d(fdin[143:0]),
3369.si({scan_in,so[142:0]}),
3370.so({so[142:0],scan_out}),
3371.q(dout[143:0])
3372);
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385endmodule
3386
3387
3388
3389
3390
3391
3392
3393
3394// any PARAMS parms go into naming of macro
3395
3396module ncu_scd_ctl_msff_ctl_macro__en_1__width_129 (
3397 din,
3398 en,
3399 l1clk,
3400 scan_in,
3401 siclk,
3402 soclk,
3403 dout,
3404 scan_out);
3405wire [128:0] fdin;
3406wire [127:0] so;
3407
3408 input [128:0] din;
3409 input en;
3410 input l1clk;
3411 input scan_in;
3412
3413
3414 input siclk;
3415 input soclk;
3416
3417 output [128:0] dout;
3418 output scan_out;
3419assign fdin[128:0] = (din[128:0] & {129{en}}) | (dout[128:0] & ~{129{en}});
3420
3421
3422
3423
3424
3425
3426dff #(129) d0_0 (
3427.l1clk(l1clk),
3428.siclk(siclk),
3429.soclk(soclk),
3430.d(fdin[128:0]),
3431.si({scan_in,so[127:0]}),
3432.so({so[127:0],scan_out}),
3433.q(dout[128:0])
3434);
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447endmodule
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461// any PARAMS parms go into naming of macro
3462
3463module ncu_scd_ctl_msff_ctl_macro__en_1__width_51 (
3464 din,
3465 en,
3466 l1clk,
3467 scan_in,
3468 siclk,
3469 soclk,
3470 dout,
3471 scan_out);
3472wire [50:0] fdin;
3473wire [49:0] so;
3474
3475 input [50:0] din;
3476 input en;
3477 input l1clk;
3478 input scan_in;
3479
3480
3481 input siclk;
3482 input soclk;
3483
3484 output [50:0] dout;
3485 output scan_out;
3486assign fdin[50:0] = (din[50:0] & {51{en}}) | (dout[50:0] & ~{51{en}});
3487
3488
3489
3490
3491
3492
3493dff #(51) d0_0 (
3494.l1clk(l1clk),
3495.siclk(siclk),
3496.soclk(soclk),
3497.d(fdin[50:0]),
3498.si({scan_in,so[49:0]}),
3499.so({so[49:0],scan_out}),
3500.q(dout[50:0])
3501);
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514endmodule
3515
3516
3517
3518
3519
3520
3521// any PARAMS parms go into naming of macro
3522
3523module ncu_scd_ctl_msff_ctl_macro__en_1__width_127 (
3524 din,
3525 en,
3526 l1clk,
3527 scan_in,
3528 siclk,
3529 soclk,
3530 dout,
3531 scan_out);
3532wire [126:0] fdin;
3533wire [125:0] so;
3534
3535 input [126:0] din;
3536 input en;
3537 input l1clk;
3538 input scan_in;
3539
3540
3541 input siclk;
3542 input soclk;
3543
3544 output [126:0] dout;
3545 output scan_out;
3546assign fdin[126:0] = (din[126:0] & {127{en}}) | (dout[126:0] & ~{127{en}});
3547
3548
3549
3550
3551
3552
3553dff #(127) d0_0 (
3554.l1clk(l1clk),
3555.siclk(siclk),
3556.soclk(soclk),
3557.d(fdin[126:0]),
3558.si({scan_in,so[125:0]}),
3559.so({so[125:0],scan_out}),
3560.q(dout[126:0])
3561);
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574endmodule
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588// any PARAMS parms go into naming of macro
3589
3590module ncu_scd_ctl_msff_ctl_macro__en_1__width_47 (
3591 din,
3592 en,
3593 l1clk,
3594 scan_in,
3595 siclk,
3596 soclk,
3597 dout,
3598 scan_out);
3599wire [46:0] fdin;
3600wire [45:0] so;
3601
3602 input [46:0] din;
3603 input en;
3604 input l1clk;
3605 input scan_in;
3606
3607
3608 input siclk;
3609 input soclk;
3610
3611 output [46:0] dout;
3612 output scan_out;
3613assign fdin[46:0] = (din[46:0] & {47{en}}) | (dout[46:0] & ~{47{en}});
3614
3615
3616
3617
3618
3619
3620dff #(47) d0_0 (
3621.l1clk(l1clk),
3622.siclk(siclk),
3623.soclk(soclk),
3624.d(fdin[46:0]),
3625.si({scan_in,so[45:0]}),
3626.so({so[45:0],scan_out}),
3627.q(dout[46:0])
3628);
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641endmodule
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655// any PARAMS parms go into naming of macro
3656
3657module ncu_scd_ctl_msff_ctl_macro__width_16 (
3658 din,
3659 l1clk,
3660 scan_in,
3661 siclk,
3662 soclk,
3663 dout,
3664 scan_out);
3665wire [15:0] fdin;
3666wire [14:0] so;
3667
3668 input [15:0] din;
3669 input l1clk;
3670 input scan_in;
3671
3672
3673 input siclk;
3674 input soclk;
3675
3676 output [15:0] dout;
3677 output scan_out;
3678assign fdin[15:0] = din[15:0];
3679
3680
3681
3682
3683
3684
3685dff #(16) d0_0 (
3686.l1clk(l1clk),
3687.siclk(siclk),
3688.soclk(soclk),
3689.d(fdin[15:0]),
3690.si({scan_in,so[14:0]}),
3691.so({so[14:0],scan_out}),
3692.q(dout[15:0])
3693);
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706endmodule
3707
3708
3709
3710
3711// any PARAMS parms go into naming of macro
3712
3713module ncu_scd_ctl_msff_ctl_macro__width_128 (
3714 din,
3715 l1clk,
3716 scan_in,
3717 siclk,
3718 soclk,
3719 dout,
3720 scan_out);
3721wire [127:0] fdin;
3722wire [126:0] so;
3723
3724 input [127:0] din;
3725 input l1clk;
3726 input scan_in;
3727
3728
3729 input siclk;
3730 input soclk;
3731
3732 output [127:0] dout;
3733 output scan_out;
3734assign fdin[127:0] = din[127:0];
3735
3736
3737
3738
3739
3740
3741dff #(128) d0_0 (
3742.l1clk(l1clk),
3743.siclk(siclk),
3744.soclk(soclk),
3745.d(fdin[127:0]),
3746.si({scan_in,so[126:0]}),
3747.so({so[126:0],scan_out}),
3748.q(dout[127:0])
3749);
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762endmodule
3763
3764
3765
3766
3767// any PARAMS parms go into naming of macro
3768
3769module ncu_scd_ctl_msff_ctl_macro__width_32 (
3770 din,
3771 l1clk,
3772 scan_in,
3773 siclk,
3774 soclk,
3775 dout,
3776 scan_out);
3777wire [31:0] fdin;
3778wire [30:0] so;
3779
3780 input [31:0] din;
3781 input l1clk;
3782 input scan_in;
3783
3784
3785 input siclk;
3786 input soclk;
3787
3788 output [31:0] dout;
3789 output scan_out;
3790assign fdin[31:0] = din[31:0];
3791
3792
3793
3794
3795
3796
3797dff #(32) d0_0 (
3798.l1clk(l1clk),
3799.siclk(siclk),
3800.soclk(soclk),
3801.d(fdin[31:0]),
3802.si({scan_in,so[30:0]}),
3803.so({so[30:0],scan_out}),
3804.q(dout[31:0])
3805);
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818endmodule
3819
3820
3821
3822
3823
3824// any PARAMS parms go into naming of macro
3825
3826module ncu_scd_ctl_msff_ctl_macro__en_1__width_16 (
3827 din,
3828 en,
3829 l1clk,
3830 scan_in,
3831 siclk,
3832 soclk,
3833 dout,
3834 scan_out);
3835wire [15:0] fdin;
3836wire [14:0] so;
3837
3838 input [15:0] din;
3839 input en;
3840 input l1clk;
3841 input scan_in;
3842
3843
3844 input siclk;
3845 input soclk;
3846
3847 output [15:0] dout;
3848 output scan_out;
3849assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}});
3850
3851
3852
3853
3854
3855
3856dff #(16) d0_0 (
3857.l1clk(l1clk),
3858.siclk(siclk),
3859.soclk(soclk),
3860.d(fdin[15:0]),
3861.si({scan_in,so[14:0]}),
3862.so({so[14:0],scan_out}),
3863.q(dout[15:0])
3864);
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877endmodule
3878
3879
3880// Local Variables:
3881// verilog-auto-sense-defines-constant:t
3882// End:
3883
3884
3885
3886
3887
3888
3889// any PARAMS parms go into naming of macro
3890
3891module ncu_scd_ctl_msff_ctl_macro__width_15 (
3892 din,
3893 l1clk,
3894 scan_in,
3895 siclk,
3896 soclk,
3897 dout,
3898 scan_out);
3899wire [14:0] fdin;
3900wire [13:0] so;
3901
3902 input [14:0] din;
3903 input l1clk;
3904 input scan_in;
3905
3906
3907 input siclk;
3908 input soclk;
3909
3910 output [14:0] dout;
3911 output scan_out;
3912assign fdin[14:0] = din[14:0];
3913
3914
3915
3916
3917
3918
3919dff #(15) d0_0 (
3920.l1clk(l1clk),
3921.siclk(siclk),
3922.soclk(soclk),
3923.d(fdin[14:0]),
3924.si({scan_in,so[13:0]}),
3925.so({so[13:0],scan_out}),
3926.q(dout[14:0])
3927);
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940endmodule
3941
3942
3943
3944
3945
3946// Description: Spare gate macro for control blocks
3947//
3948// Param num controls the number of times the macro is added
3949// flops=0 can be used to use only combination spare logic
3950
3951
3952module ncu_scd_ctl_spare_ctl_macro__num_11 (
3953 l1clk,
3954 scan_in,
3955 siclk,
3956 soclk,
3957 scan_out);
3958wire si_0;
3959wire so_0;
3960wire spare0_flop_unused;
3961wire spare0_buf_32x_unused;
3962wire spare0_nand3_8x_unused;
3963wire spare0_inv_8x_unused;
3964wire spare0_aoi22_4x_unused;
3965wire spare0_buf_8x_unused;
3966wire spare0_oai22_4x_unused;
3967wire spare0_inv_16x_unused;
3968wire spare0_nand2_16x_unused;
3969wire spare0_nor3_4x_unused;
3970wire spare0_nand2_8x_unused;
3971wire spare0_buf_16x_unused;
3972wire spare0_nor2_16x_unused;
3973wire spare0_inv_32x_unused;
3974wire si_1;
3975wire so_1;
3976wire spare1_flop_unused;
3977wire spare1_buf_32x_unused;
3978wire spare1_nand3_8x_unused;
3979wire spare1_inv_8x_unused;
3980wire spare1_aoi22_4x_unused;
3981wire spare1_buf_8x_unused;
3982wire spare1_oai22_4x_unused;
3983wire spare1_inv_16x_unused;
3984wire spare1_nand2_16x_unused;
3985wire spare1_nor3_4x_unused;
3986wire spare1_nand2_8x_unused;
3987wire spare1_buf_16x_unused;
3988wire spare1_nor2_16x_unused;
3989wire spare1_inv_32x_unused;
3990wire si_2;
3991wire so_2;
3992wire spare2_flop_unused;
3993wire spare2_buf_32x_unused;
3994wire spare2_nand3_8x_unused;
3995wire spare2_inv_8x_unused;
3996wire spare2_aoi22_4x_unused;
3997wire spare2_buf_8x_unused;
3998wire spare2_oai22_4x_unused;
3999wire spare2_inv_16x_unused;
4000wire spare2_nand2_16x_unused;
4001wire spare2_nor3_4x_unused;
4002wire spare2_nand2_8x_unused;
4003wire spare2_buf_16x_unused;
4004wire spare2_nor2_16x_unused;
4005wire spare2_inv_32x_unused;
4006wire si_3;
4007wire so_3;
4008wire spare3_flop_unused;
4009wire spare3_buf_32x_unused;
4010wire spare3_nand3_8x_unused;
4011wire spare3_inv_8x_unused;
4012wire spare3_aoi22_4x_unused;
4013wire spare3_buf_8x_unused;
4014wire spare3_oai22_4x_unused;
4015wire spare3_inv_16x_unused;
4016wire spare3_nand2_16x_unused;
4017wire spare3_nor3_4x_unused;
4018wire spare3_nand2_8x_unused;
4019wire spare3_buf_16x_unused;
4020wire spare3_nor2_16x_unused;
4021wire spare3_inv_32x_unused;
4022wire si_4;
4023wire so_4;
4024wire spare4_flop_unused;
4025wire spare4_buf_32x_unused;
4026wire spare4_nand3_8x_unused;
4027wire spare4_inv_8x_unused;
4028wire spare4_aoi22_4x_unused;
4029wire spare4_buf_8x_unused;
4030wire spare4_oai22_4x_unused;
4031wire spare4_inv_16x_unused;
4032wire spare4_nand2_16x_unused;
4033wire spare4_nor3_4x_unused;
4034wire spare4_nand2_8x_unused;
4035wire spare4_buf_16x_unused;
4036wire spare4_nor2_16x_unused;
4037wire spare4_inv_32x_unused;
4038wire si_5;
4039wire so_5;
4040wire spare5_flop_unused;
4041wire spare5_buf_32x_unused;
4042wire spare5_nand3_8x_unused;
4043wire spare5_inv_8x_unused;
4044wire spare5_aoi22_4x_unused;
4045wire spare5_buf_8x_unused;
4046wire spare5_oai22_4x_unused;
4047wire spare5_inv_16x_unused;
4048wire spare5_nand2_16x_unused;
4049wire spare5_nor3_4x_unused;
4050wire spare5_nand2_8x_unused;
4051wire spare5_buf_16x_unused;
4052wire spare5_nor2_16x_unused;
4053wire spare5_inv_32x_unused;
4054wire si_6;
4055wire so_6;
4056wire spare6_flop_unused;
4057wire spare6_buf_32x_unused;
4058wire spare6_nand3_8x_unused;
4059wire spare6_inv_8x_unused;
4060wire spare6_aoi22_4x_unused;
4061wire spare6_buf_8x_unused;
4062wire spare6_oai22_4x_unused;
4063wire spare6_inv_16x_unused;
4064wire spare6_nand2_16x_unused;
4065wire spare6_nor3_4x_unused;
4066wire spare6_nand2_8x_unused;
4067wire spare6_buf_16x_unused;
4068wire spare6_nor2_16x_unused;
4069wire spare6_inv_32x_unused;
4070wire si_7;
4071wire so_7;
4072wire spare7_flop_unused;
4073wire spare7_buf_32x_unused;
4074wire spare7_nand3_8x_unused;
4075wire spare7_inv_8x_unused;
4076wire spare7_aoi22_4x_unused;
4077wire spare7_buf_8x_unused;
4078wire spare7_oai22_4x_unused;
4079wire spare7_inv_16x_unused;
4080wire spare7_nand2_16x_unused;
4081wire spare7_nor3_4x_unused;
4082wire spare7_nand2_8x_unused;
4083wire spare7_buf_16x_unused;
4084wire spare7_nor2_16x_unused;
4085wire spare7_inv_32x_unused;
4086wire si_8;
4087wire so_8;
4088wire spare8_flop_unused;
4089wire spare8_buf_32x_unused;
4090wire spare8_nand3_8x_unused;
4091wire spare8_inv_8x_unused;
4092wire spare8_aoi22_4x_unused;
4093wire spare8_buf_8x_unused;
4094wire spare8_oai22_4x_unused;
4095wire spare8_inv_16x_unused;
4096wire spare8_nand2_16x_unused;
4097wire spare8_nor3_4x_unused;
4098wire spare8_nand2_8x_unused;
4099wire spare8_buf_16x_unused;
4100wire spare8_nor2_16x_unused;
4101wire spare8_inv_32x_unused;
4102wire si_9;
4103wire so_9;
4104wire spare9_flop_unused;
4105wire spare9_buf_32x_unused;
4106wire spare9_nand3_8x_unused;
4107wire spare9_inv_8x_unused;
4108wire spare9_aoi22_4x_unused;
4109wire spare9_buf_8x_unused;
4110wire spare9_oai22_4x_unused;
4111wire spare9_inv_16x_unused;
4112wire spare9_nand2_16x_unused;
4113wire spare9_nor3_4x_unused;
4114wire spare9_nand2_8x_unused;
4115wire spare9_buf_16x_unused;
4116wire spare9_nor2_16x_unused;
4117wire spare9_inv_32x_unused;
4118wire si_10;
4119wire so_10;
4120wire spare10_flop_unused;
4121wire spare10_buf_32x_unused;
4122wire spare10_nand3_8x_unused;
4123wire spare10_inv_8x_unused;
4124wire spare10_aoi22_4x_unused;
4125wire spare10_buf_8x_unused;
4126wire spare10_oai22_4x_unused;
4127wire spare10_inv_16x_unused;
4128wire spare10_nand2_16x_unused;
4129wire spare10_nor3_4x_unused;
4130wire spare10_nand2_8x_unused;
4131wire spare10_buf_16x_unused;
4132wire spare10_nor2_16x_unused;
4133wire spare10_inv_32x_unused;
4134
4135
4136input l1clk;
4137input scan_in;
4138input siclk;
4139input soclk;
4140output scan_out;
4141
4142cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
4143 .siclk(siclk),
4144 .soclk(soclk),
4145 .si(si_0),
4146 .so(so_0),
4147 .d(1'b0),
4148 .q(spare0_flop_unused));
4149assign si_0 = scan_in;
4150
4151cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
4152 .out(spare0_buf_32x_unused));
4153cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
4154 .in1(1'b1),
4155 .in2(1'b1),
4156 .out(spare0_nand3_8x_unused));
4157cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
4158 .out(spare0_inv_8x_unused));
4159cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
4160 .in01(1'b1),
4161 .in10(1'b1),
4162 .in11(1'b1),
4163 .out(spare0_aoi22_4x_unused));
4164cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
4165 .out(spare0_buf_8x_unused));
4166cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
4167 .in01(1'b1),
4168 .in10(1'b1),
4169 .in11(1'b1),
4170 .out(spare0_oai22_4x_unused));
4171cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
4172 .out(spare0_inv_16x_unused));
4173cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
4174 .in1(1'b1),
4175 .out(spare0_nand2_16x_unused));
4176cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
4177 .in1(1'b0),
4178 .in2(1'b0),
4179 .out(spare0_nor3_4x_unused));
4180cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
4181 .in1(1'b1),
4182 .out(spare0_nand2_8x_unused));
4183cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
4184 .out(spare0_buf_16x_unused));
4185cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
4186 .in1(1'b0),
4187 .out(spare0_nor2_16x_unused));
4188cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
4189 .out(spare0_inv_32x_unused));
4190
4191cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
4192 .siclk(siclk),
4193 .soclk(soclk),
4194 .si(si_1),
4195 .so(so_1),
4196 .d(1'b0),
4197 .q(spare1_flop_unused));
4198assign si_1 = so_0;
4199
4200cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
4201 .out(spare1_buf_32x_unused));
4202cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
4203 .in1(1'b1),
4204 .in2(1'b1),
4205 .out(spare1_nand3_8x_unused));
4206cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
4207 .out(spare1_inv_8x_unused));
4208cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
4209 .in01(1'b1),
4210 .in10(1'b1),
4211 .in11(1'b1),
4212 .out(spare1_aoi22_4x_unused));
4213cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
4214 .out(spare1_buf_8x_unused));
4215cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
4216 .in01(1'b1),
4217 .in10(1'b1),
4218 .in11(1'b1),
4219 .out(spare1_oai22_4x_unused));
4220cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
4221 .out(spare1_inv_16x_unused));
4222cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
4223 .in1(1'b1),
4224 .out(spare1_nand2_16x_unused));
4225cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
4226 .in1(1'b0),
4227 .in2(1'b0),
4228 .out(spare1_nor3_4x_unused));
4229cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
4230 .in1(1'b1),
4231 .out(spare1_nand2_8x_unused));
4232cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
4233 .out(spare1_buf_16x_unused));
4234cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
4235 .in1(1'b0),
4236 .out(spare1_nor2_16x_unused));
4237cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
4238 .out(spare1_inv_32x_unused));
4239
4240cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
4241 .siclk(siclk),
4242 .soclk(soclk),
4243 .si(si_2),
4244 .so(so_2),
4245 .d(1'b0),
4246 .q(spare2_flop_unused));
4247assign si_2 = so_1;
4248
4249cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
4250 .out(spare2_buf_32x_unused));
4251cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
4252 .in1(1'b1),
4253 .in2(1'b1),
4254 .out(spare2_nand3_8x_unused));
4255cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
4256 .out(spare2_inv_8x_unused));
4257cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
4258 .in01(1'b1),
4259 .in10(1'b1),
4260 .in11(1'b1),
4261 .out(spare2_aoi22_4x_unused));
4262cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
4263 .out(spare2_buf_8x_unused));
4264cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
4265 .in01(1'b1),
4266 .in10(1'b1),
4267 .in11(1'b1),
4268 .out(spare2_oai22_4x_unused));
4269cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
4270 .out(spare2_inv_16x_unused));
4271cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
4272 .in1(1'b1),
4273 .out(spare2_nand2_16x_unused));
4274cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
4275 .in1(1'b0),
4276 .in2(1'b0),
4277 .out(spare2_nor3_4x_unused));
4278cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
4279 .in1(1'b1),
4280 .out(spare2_nand2_8x_unused));
4281cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
4282 .out(spare2_buf_16x_unused));
4283cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
4284 .in1(1'b0),
4285 .out(spare2_nor2_16x_unused));
4286cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
4287 .out(spare2_inv_32x_unused));
4288
4289cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
4290 .siclk(siclk),
4291 .soclk(soclk),
4292 .si(si_3),
4293 .so(so_3),
4294 .d(1'b0),
4295 .q(spare3_flop_unused));
4296assign si_3 = so_2;
4297
4298cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
4299 .out(spare3_buf_32x_unused));
4300cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
4301 .in1(1'b1),
4302 .in2(1'b1),
4303 .out(spare3_nand3_8x_unused));
4304cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
4305 .out(spare3_inv_8x_unused));
4306cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
4307 .in01(1'b1),
4308 .in10(1'b1),
4309 .in11(1'b1),
4310 .out(spare3_aoi22_4x_unused));
4311cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
4312 .out(spare3_buf_8x_unused));
4313cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
4314 .in01(1'b1),
4315 .in10(1'b1),
4316 .in11(1'b1),
4317 .out(spare3_oai22_4x_unused));
4318cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
4319 .out(spare3_inv_16x_unused));
4320cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
4321 .in1(1'b1),
4322 .out(spare3_nand2_16x_unused));
4323cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
4324 .in1(1'b0),
4325 .in2(1'b0),
4326 .out(spare3_nor3_4x_unused));
4327cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
4328 .in1(1'b1),
4329 .out(spare3_nand2_8x_unused));
4330cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
4331 .out(spare3_buf_16x_unused));
4332cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
4333 .in1(1'b0),
4334 .out(spare3_nor2_16x_unused));
4335cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
4336 .out(spare3_inv_32x_unused));
4337
4338cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
4339 .siclk(siclk),
4340 .soclk(soclk),
4341 .si(si_4),
4342 .so(so_4),
4343 .d(1'b0),
4344 .q(spare4_flop_unused));
4345assign si_4 = so_3;
4346
4347cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
4348 .out(spare4_buf_32x_unused));
4349cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
4350 .in1(1'b1),
4351 .in2(1'b1),
4352 .out(spare4_nand3_8x_unused));
4353cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
4354 .out(spare4_inv_8x_unused));
4355cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
4356 .in01(1'b1),
4357 .in10(1'b1),
4358 .in11(1'b1),
4359 .out(spare4_aoi22_4x_unused));
4360cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
4361 .out(spare4_buf_8x_unused));
4362cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
4363 .in01(1'b1),
4364 .in10(1'b1),
4365 .in11(1'b1),
4366 .out(spare4_oai22_4x_unused));
4367cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
4368 .out(spare4_inv_16x_unused));
4369cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
4370 .in1(1'b1),
4371 .out(spare4_nand2_16x_unused));
4372cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
4373 .in1(1'b0),
4374 .in2(1'b0),
4375 .out(spare4_nor3_4x_unused));
4376cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
4377 .in1(1'b1),
4378 .out(spare4_nand2_8x_unused));
4379cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
4380 .out(spare4_buf_16x_unused));
4381cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
4382 .in1(1'b0),
4383 .out(spare4_nor2_16x_unused));
4384cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
4385 .out(spare4_inv_32x_unused));
4386
4387cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
4388 .siclk(siclk),
4389 .soclk(soclk),
4390 .si(si_5),
4391 .so(so_5),
4392 .d(1'b0),
4393 .q(spare5_flop_unused));
4394assign si_5 = so_4;
4395
4396cl_u1_buf_32x spare5_buf_32x (.in(1'b1),
4397 .out(spare5_buf_32x_unused));
4398cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
4399 .in1(1'b1),
4400 .in2(1'b1),
4401 .out(spare5_nand3_8x_unused));
4402cl_u1_inv_8x spare5_inv_8x (.in(1'b1),
4403 .out(spare5_inv_8x_unused));
4404cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
4405 .in01(1'b1),
4406 .in10(1'b1),
4407 .in11(1'b1),
4408 .out(spare5_aoi22_4x_unused));
4409cl_u1_buf_8x spare5_buf_8x (.in(1'b1),
4410 .out(spare5_buf_8x_unused));
4411cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
4412 .in01(1'b1),
4413 .in10(1'b1),
4414 .in11(1'b1),
4415 .out(spare5_oai22_4x_unused));
4416cl_u1_inv_16x spare5_inv_16x (.in(1'b1),
4417 .out(spare5_inv_16x_unused));
4418cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
4419 .in1(1'b1),
4420 .out(spare5_nand2_16x_unused));
4421cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
4422 .in1(1'b0),
4423 .in2(1'b0),
4424 .out(spare5_nor3_4x_unused));
4425cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
4426 .in1(1'b1),
4427 .out(spare5_nand2_8x_unused));
4428cl_u1_buf_16x spare5_buf_16x (.in(1'b1),
4429 .out(spare5_buf_16x_unused));
4430cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
4431 .in1(1'b0),
4432 .out(spare5_nor2_16x_unused));
4433cl_u1_inv_32x spare5_inv_32x (.in(1'b1),
4434 .out(spare5_inv_32x_unused));
4435
4436cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
4437 .siclk(siclk),
4438 .soclk(soclk),
4439 .si(si_6),
4440 .so(so_6),
4441 .d(1'b0),
4442 .q(spare6_flop_unused));
4443assign si_6 = so_5;
4444
4445cl_u1_buf_32x spare6_buf_32x (.in(1'b1),
4446 .out(spare6_buf_32x_unused));
4447cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
4448 .in1(1'b1),
4449 .in2(1'b1),
4450 .out(spare6_nand3_8x_unused));
4451cl_u1_inv_8x spare6_inv_8x (.in(1'b1),
4452 .out(spare6_inv_8x_unused));
4453cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
4454 .in01(1'b1),
4455 .in10(1'b1),
4456 .in11(1'b1),
4457 .out(spare6_aoi22_4x_unused));
4458cl_u1_buf_8x spare6_buf_8x (.in(1'b1),
4459 .out(spare6_buf_8x_unused));
4460cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
4461 .in01(1'b1),
4462 .in10(1'b1),
4463 .in11(1'b1),
4464 .out(spare6_oai22_4x_unused));
4465cl_u1_inv_16x spare6_inv_16x (.in(1'b1),
4466 .out(spare6_inv_16x_unused));
4467cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
4468 .in1(1'b1),
4469 .out(spare6_nand2_16x_unused));
4470cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
4471 .in1(1'b0),
4472 .in2(1'b0),
4473 .out(spare6_nor3_4x_unused));
4474cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
4475 .in1(1'b1),
4476 .out(spare6_nand2_8x_unused));
4477cl_u1_buf_16x spare6_buf_16x (.in(1'b1),
4478 .out(spare6_buf_16x_unused));
4479cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
4480 .in1(1'b0),
4481 .out(spare6_nor2_16x_unused));
4482cl_u1_inv_32x spare6_inv_32x (.in(1'b1),
4483 .out(spare6_inv_32x_unused));
4484
4485cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
4486 .siclk(siclk),
4487 .soclk(soclk),
4488 .si(si_7),
4489 .so(so_7),
4490 .d(1'b0),
4491 .q(spare7_flop_unused));
4492assign si_7 = so_6;
4493
4494cl_u1_buf_32x spare7_buf_32x (.in(1'b1),
4495 .out(spare7_buf_32x_unused));
4496cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
4497 .in1(1'b1),
4498 .in2(1'b1),
4499 .out(spare7_nand3_8x_unused));
4500cl_u1_inv_8x spare7_inv_8x (.in(1'b1),
4501 .out(spare7_inv_8x_unused));
4502cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
4503 .in01(1'b1),
4504 .in10(1'b1),
4505 .in11(1'b1),
4506 .out(spare7_aoi22_4x_unused));
4507cl_u1_buf_8x spare7_buf_8x (.in(1'b1),
4508 .out(spare7_buf_8x_unused));
4509cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
4510 .in01(1'b1),
4511 .in10(1'b1),
4512 .in11(1'b1),
4513 .out(spare7_oai22_4x_unused));
4514cl_u1_inv_16x spare7_inv_16x (.in(1'b1),
4515 .out(spare7_inv_16x_unused));
4516cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
4517 .in1(1'b1),
4518 .out(spare7_nand2_16x_unused));
4519cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
4520 .in1(1'b0),
4521 .in2(1'b0),
4522 .out(spare7_nor3_4x_unused));
4523cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
4524 .in1(1'b1),
4525 .out(spare7_nand2_8x_unused));
4526cl_u1_buf_16x spare7_buf_16x (.in(1'b1),
4527 .out(spare7_buf_16x_unused));
4528cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
4529 .in1(1'b0),
4530 .out(spare7_nor2_16x_unused));
4531cl_u1_inv_32x spare7_inv_32x (.in(1'b1),
4532 .out(spare7_inv_32x_unused));
4533
4534cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
4535 .siclk(siclk),
4536 .soclk(soclk),
4537 .si(si_8),
4538 .so(so_8),
4539 .d(1'b0),
4540 .q(spare8_flop_unused));
4541assign si_8 = so_7;
4542
4543cl_u1_buf_32x spare8_buf_32x (.in(1'b1),
4544 .out(spare8_buf_32x_unused));
4545cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
4546 .in1(1'b1),
4547 .in2(1'b1),
4548 .out(spare8_nand3_8x_unused));
4549cl_u1_inv_8x spare8_inv_8x (.in(1'b1),
4550 .out(spare8_inv_8x_unused));
4551cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
4552 .in01(1'b1),
4553 .in10(1'b1),
4554 .in11(1'b1),
4555 .out(spare8_aoi22_4x_unused));
4556cl_u1_buf_8x spare8_buf_8x (.in(1'b1),
4557 .out(spare8_buf_8x_unused));
4558cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
4559 .in01(1'b1),
4560 .in10(1'b1),
4561 .in11(1'b1),
4562 .out(spare8_oai22_4x_unused));
4563cl_u1_inv_16x spare8_inv_16x (.in(1'b1),
4564 .out(spare8_inv_16x_unused));
4565cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
4566 .in1(1'b1),
4567 .out(spare8_nand2_16x_unused));
4568cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
4569 .in1(1'b0),
4570 .in2(1'b0),
4571 .out(spare8_nor3_4x_unused));
4572cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
4573 .in1(1'b1),
4574 .out(spare8_nand2_8x_unused));
4575cl_u1_buf_16x spare8_buf_16x (.in(1'b1),
4576 .out(spare8_buf_16x_unused));
4577cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
4578 .in1(1'b0),
4579 .out(spare8_nor2_16x_unused));
4580cl_u1_inv_32x spare8_inv_32x (.in(1'b1),
4581 .out(spare8_inv_32x_unused));
4582
4583cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
4584 .siclk(siclk),
4585 .soclk(soclk),
4586 .si(si_9),
4587 .so(so_9),
4588 .d(1'b0),
4589 .q(spare9_flop_unused));
4590assign si_9 = so_8;
4591
4592cl_u1_buf_32x spare9_buf_32x (.in(1'b1),
4593 .out(spare9_buf_32x_unused));
4594cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
4595 .in1(1'b1),
4596 .in2(1'b1),
4597 .out(spare9_nand3_8x_unused));
4598cl_u1_inv_8x spare9_inv_8x (.in(1'b1),
4599 .out(spare9_inv_8x_unused));
4600cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
4601 .in01(1'b1),
4602 .in10(1'b1),
4603 .in11(1'b1),
4604 .out(spare9_aoi22_4x_unused));
4605cl_u1_buf_8x spare9_buf_8x (.in(1'b1),
4606 .out(spare9_buf_8x_unused));
4607cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
4608 .in01(1'b1),
4609 .in10(1'b1),
4610 .in11(1'b1),
4611 .out(spare9_oai22_4x_unused));
4612cl_u1_inv_16x spare9_inv_16x (.in(1'b1),
4613 .out(spare9_inv_16x_unused));
4614cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
4615 .in1(1'b1),
4616 .out(spare9_nand2_16x_unused));
4617cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
4618 .in1(1'b0),
4619 .in2(1'b0),
4620 .out(spare9_nor3_4x_unused));
4621cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
4622 .in1(1'b1),
4623 .out(spare9_nand2_8x_unused));
4624cl_u1_buf_16x spare9_buf_16x (.in(1'b1),
4625 .out(spare9_buf_16x_unused));
4626cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
4627 .in1(1'b0),
4628 .out(spare9_nor2_16x_unused));
4629cl_u1_inv_32x spare9_inv_32x (.in(1'b1),
4630 .out(spare9_inv_32x_unused));
4631
4632cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
4633 .siclk(siclk),
4634 .soclk(soclk),
4635 .si(si_10),
4636 .so(so_10),
4637 .d(1'b0),
4638 .q(spare10_flop_unused));
4639assign si_10 = so_9;
4640
4641cl_u1_buf_32x spare10_buf_32x (.in(1'b1),
4642 .out(spare10_buf_32x_unused));
4643cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
4644 .in1(1'b1),
4645 .in2(1'b1),
4646 .out(spare10_nand3_8x_unused));
4647cl_u1_inv_8x spare10_inv_8x (.in(1'b1),
4648 .out(spare10_inv_8x_unused));
4649cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
4650 .in01(1'b1),
4651 .in10(1'b1),
4652 .in11(1'b1),
4653 .out(spare10_aoi22_4x_unused));
4654cl_u1_buf_8x spare10_buf_8x (.in(1'b1),
4655 .out(spare10_buf_8x_unused));
4656cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
4657 .in01(1'b1),
4658 .in10(1'b1),
4659 .in11(1'b1),
4660 .out(spare10_oai22_4x_unused));
4661cl_u1_inv_16x spare10_inv_16x (.in(1'b1),
4662 .out(spare10_inv_16x_unused));
4663cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
4664 .in1(1'b1),
4665 .out(spare10_nand2_16x_unused));
4666cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
4667 .in1(1'b0),
4668 .in2(1'b0),
4669 .out(spare10_nor3_4x_unused));
4670cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
4671 .in1(1'b1),
4672 .out(spare10_nand2_8x_unused));
4673cl_u1_buf_16x spare10_buf_16x (.in(1'b1),
4674 .out(spare10_buf_16x_unused));
4675cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
4676 .in1(1'b0),
4677 .out(spare10_nor2_16x_unused));
4678cl_u1_inv_32x spare10_inv_32x (.in(1'b1),
4679 .out(spare10_inv_32x_unused));
4680assign scan_out = so_10;
4681
4682
4683
4684endmodule
4685
4686
4687
4688
4689// any PARAMS parms go into naming of macro
4690
4691module ncu_scd_ctl_msff_ctl_macro__en_1__width_32 (
4692 din,
4693 en,
4694 l1clk,
4695 scan_in,
4696 siclk,
4697 soclk,
4698 dout,
4699 scan_out);
4700wire [31:0] fdin;
4701wire [30:0] so;
4702
4703 input [31:0] din;
4704 input en;
4705 input l1clk;
4706 input scan_in;
4707
4708
4709 input siclk;
4710 input soclk;
4711
4712 output [31:0] dout;
4713 output scan_out;
4714assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}});
4715
4716
4717
4718
4719
4720
4721dff #(32) d0_0 (
4722.l1clk(l1clk),
4723.siclk(siclk),
4724.soclk(soclk),
4725.d(fdin[31:0]),
4726.si({scan_in,so[30:0]}),
4727.so({so[30:0],scan_out}),
4728.q(dout[31:0])
4729);
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742endmodule
4743
4744
4745
4746
4747// any PARAMS parms go into naming of macro
4748
4749module ncu_scd_ctl_msff_ctl_macro__en_1__width_140 (
4750 din,
4751 en,
4752 l1clk,
4753 scan_in,
4754 siclk,
4755 soclk,
4756 dout,
4757 scan_out);
4758wire [139:0] fdin;
4759wire [138:0] so;
4760
4761 input [139:0] din;
4762 input en;
4763 input l1clk;
4764 input scan_in;
4765
4766
4767 input siclk;
4768 input soclk;
4769
4770 output [139:0] dout;
4771 output scan_out;
4772assign fdin[139:0] = (din[139:0] & {140{en}}) | (dout[139:0] & ~{140{en}});
4773
4774
4775
4776
4777
4778
4779dff #(140) d0_0 (
4780.l1clk(l1clk),
4781.siclk(siclk),
4782.soclk(soclk),
4783.d(fdin[139:0]),
4784.si({scan_in,so[138:0]}),
4785.so({so[138:0],scan_out}),
4786.q(dout[139:0])
4787);
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800endmodule
4801
4802
4803
4804
4805
4806
4807// any PARAMS parms go into naming of macro
4808
4809module ncu_scd_ctl_msff_ctl_macro__en_1__width_4 (
4810 din,
4811 en,
4812 l1clk,
4813 scan_in,
4814 siclk,
4815 soclk,
4816 dout,
4817 scan_out);
4818wire [3:0] fdin;
4819wire [2:0] so;
4820
4821 input [3:0] din;
4822 input en;
4823 input l1clk;
4824 input scan_in;
4825
4826
4827 input siclk;
4828 input soclk;
4829
4830 output [3:0] dout;
4831 output scan_out;
4832assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}});
4833
4834
4835
4836
4837
4838
4839dff #(4) d0_0 (
4840.l1clk(l1clk),
4841.siclk(siclk),
4842.soclk(soclk),
4843.d(fdin[3:0]),
4844.si({scan_in,so[2:0]}),
4845.so({so[2:0],scan_out}),
4846.q(dout[3:0])
4847);
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860endmodule
4861
Full OpenSPARC design & verification tarball including full HDL.