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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_ssisrg8_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_ssisrg8_ctl ( | |
36 | iol2clk, | |
37 | tcu_pce_ov, | |
38 | tcu_clk_stop, | |
39 | tcu_scan_en, | |
40 | tcu_aclk, | |
41 | tcu_bclk, | |
42 | scan_in, | |
43 | scan_out, | |
44 | s_in, | |
45 | p_in, | |
46 | shift_n, | |
47 | load_n, | |
48 | p_out) ; | |
49 | wire p_out_ff_scanin; | |
50 | wire p_out_ff_scanout; | |
51 | wire l1clk; | |
52 | wire siclk; | |
53 | wire soclk; | |
54 | wire se; | |
55 | wire pce_ov; | |
56 | wire stop; | |
57 | ||
58 | ||
59 | input iol2clk; | |
60 | input tcu_pce_ov; | |
61 | input tcu_clk_stop; | |
62 | input tcu_scan_en; | |
63 | input tcu_aclk; | |
64 | input tcu_bclk; | |
65 | input scan_in; | |
66 | output scan_out; | |
67 | input s_in; | |
68 | input [7:0] p_in; | |
69 | input shift_n; | |
70 | input load_n; | |
71 | output [7:0] p_out; | |
72 | ||
73 | reg [7:0] p_out_n; | |
74 | ||
75 | always@(p_in or s_in or load_n or shift_n or p_out) begin | |
76 | case({load_n,shift_n}) | |
77 | 2'b01 : p_out_n[7:0] = p_in[7:0] ; | |
78 | 2'b10 : p_out_n[7:0] = {p_out[6:0],s_in} ; | |
79 | default : p_out_n[7:0] = p_out[7:0] ; | |
80 | endcase | |
81 | end | |
82 | ||
83 | ncu_ssisrg8_ctl_msff_ctl_macro__width_8 p_out_ff | |
84 | ( | |
85 | .scan_in(p_out_ff_scanin), | |
86 | .scan_out(p_out_ff_scanout), | |
87 | .dout (p_out[7:0]), | |
88 | .l1clk (l1clk), | |
89 | .din (p_out_n[7:0]), | |
90 | .siclk(siclk), | |
91 | .soclk(soclk) | |
92 | ); | |
93 | ||
94 | ||
95 | ||
96 | /**** adding clock header ****/ | |
97 | ncu_ssisrg8_ctl_l1clkhdr_ctl_macro clkgen ( | |
98 | .l2clk (iol2clk), | |
99 | .l1en (1'b1), | |
100 | .l1clk (l1clk), | |
101 | .pce_ov(pce_ov), | |
102 | .stop(stop), | |
103 | .se(se) | |
104 | ); | |
105 | ||
106 | /*** building tcu port ***/ | |
107 | assign siclk = tcu_aclk; | |
108 | assign soclk = tcu_bclk; | |
109 | assign se = tcu_scan_en; | |
110 | assign pce_ov = tcu_pce_ov; | |
111 | assign stop = tcu_clk_stop; | |
112 | ||
113 | // fixscan start: | |
114 | assign p_out_ff_scanin = scan_in ; | |
115 | assign scan_out = p_out_ff_scanout ; | |
116 | // fixscan end: | |
117 | endmodule | |
118 | ||
119 | ||
120 | ||
121 | ||
122 | ||
123 | ||
124 | ||
125 | ||
126 | // any PARAMS parms go into naming of macro | |
127 | ||
128 | module ncu_ssisrg8_ctl_msff_ctl_macro__width_8 ( | |
129 | din, | |
130 | l1clk, | |
131 | scan_in, | |
132 | siclk, | |
133 | soclk, | |
134 | dout, | |
135 | scan_out); | |
136 | wire [7:0] fdin; | |
137 | wire [6:0] so; | |
138 | ||
139 | input [7:0] din; | |
140 | input l1clk; | |
141 | input scan_in; | |
142 | ||
143 | ||
144 | input siclk; | |
145 | input soclk; | |
146 | ||
147 | output [7:0] dout; | |
148 | output scan_out; | |
149 | assign fdin[7:0] = din[7:0]; | |
150 | ||
151 | ||
152 | ||
153 | ||
154 | ||
155 | ||
156 | dff #(8) d0_0 ( | |
157 | .l1clk(l1clk), | |
158 | .siclk(siclk), | |
159 | .soclk(soclk), | |
160 | .d(fdin[7:0]), | |
161 | .si({scan_in,so[6:0]}), | |
162 | .so({so[6:0],scan_out}), | |
163 | .q(dout[7:0]) | |
164 | ); | |
165 | ||
166 | ||
167 | ||
168 | ||
169 | ||
170 | ||
171 | ||
172 | ||
173 | ||
174 | ||
175 | ||
176 | ||
177 | endmodule | |
178 | ||
179 | ||
180 | ||
181 | ||
182 | ||
183 | ||
184 | ||
185 | ||
186 | ||
187 | ||
188 | ||
189 | ||
190 | ||
191 | // any PARAMS parms go into naming of macro | |
192 | ||
193 | module ncu_ssisrg8_ctl_l1clkhdr_ctl_macro ( | |
194 | l2clk, | |
195 | l1en, | |
196 | pce_ov, | |
197 | stop, | |
198 | se, | |
199 | l1clk); | |
200 | ||
201 | ||
202 | input l2clk; | |
203 | input l1en; | |
204 | input pce_ov; | |
205 | input stop; | |
206 | input se; | |
207 | output l1clk; | |
208 | ||
209 | ||
210 | ||
211 | ||
212 | ||
213 | cl_sc1_l1hdr_8x c_0 ( | |
214 | ||
215 | ||
216 | .l2clk(l2clk), | |
217 | .pce(l1en), | |
218 | .l1clk(l1clk), | |
219 | .se(se), | |
220 | .pce_ov(pce_ov), | |
221 | .stop(stop) | |
222 | ); | |
223 | ||
224 | ||
225 | ||
226 | endmodule | |
227 | ||
228 | ||
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 |