Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_ssitop_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_ssitop_ctl ( | |
36 | iol2clk, | |
37 | tcu_pce_ov, | |
38 | tcu_clk_stop, | |
39 | tcu_scan_en, | |
40 | tcu_aclk, | |
41 | tcu_bclk, | |
42 | ncu_scksel, | |
43 | scan_in, | |
44 | scan_out, | |
45 | jbi_io_ssi_mosi, | |
46 | io_jbi_ssi_miso, | |
47 | jbi_io_ssi_sck, | |
48 | io_jbi_ext_int_l, | |
49 | iob_jbi_spi_vld, | |
50 | iob_jbi_spi_data, | |
51 | iob_jbi_spi_stall, | |
52 | jbi_iob_spi_vld, | |
53 | jbi_iob_spi_data, | |
54 | jbi_iob_spi_stall, | |
55 | tcu_sck_bypass) ; | |
56 | wire ucb_ucbif_rd_req_vld; | |
57 | wire ucb_ucbif_wr_req_vld; | |
58 | wire ucb_ucbif_ifill_req_vld; | |
59 | wire [5:0] ucb_ucbif_thr_id_in; | |
60 | wire [1:0] ucb_ucbif_buf_id_in; | |
61 | wire [2:0] ucb_ucbif_size_in; | |
62 | wire [39:0] ucb_ucbif_addr_in; | |
63 | wire [63:0] ucb_ucbif_data_in; | |
64 | wire ucb_ucbif_ack_busy; | |
65 | wire ucb_ucbif_int_busy; | |
66 | wire ncu_ssiflow_ctl_scanin; | |
67 | wire ncu_ssiflow_ctl_scanout; | |
68 | wire ucbif_ucb_req_acpted; | |
69 | wire ucbif_ucb_rd_ack_vld; | |
70 | wire ucbif_ucb_rd_nack_vld; | |
71 | wire ucbif_ucb_ifill_ack_vld; | |
72 | wire ucbif_ucb_ifill_nack_vld; | |
73 | wire [5:0] ucbif_ucb_thr_id_out; | |
74 | wire [1:0] ucbif_ucb_buf_id_out; | |
75 | wire [63:0] ucbif_ucb_data_out; | |
76 | wire ucbif_ucb_int_vld; | |
77 | wire [3:0] ucbif_ucb_int_type; | |
78 | wire [8:0] ucbif_ucb_dev_id; | |
79 | wire sck_cntexp; | |
80 | wire ucbif_sif_vld; | |
81 | wire ucbif_sif_rw; | |
82 | wire [1:0] ucbif_sif_size; | |
83 | wire [27:0] ucbif_sif_addr; | |
84 | wire [63:0] ucbif_sif_wdata; | |
85 | wire ucbif_sif_rdata_accpt; | |
86 | wire ucbif_sif_timeout_accpt; | |
87 | wire [23:0] ucbif_sif_timeval; | |
88 | wire ncu_ssiuif_ctl_scanin; | |
89 | wire ncu_ssiuif_ctl_scanout; | |
90 | wire sif_ucbif_busy; | |
91 | wire [63:0] sif_ucbif_rdata; | |
92 | wire sif_ucbif_rdata_vld; | |
93 | wire sif_ucbif_timeout; | |
94 | wire sif_ucbif_timeout_rw; | |
95 | wire sif_ucbif_par_err; | |
96 | wire ncu_ssisif_ctl_scanin; | |
97 | wire ncu_ssisif_ctl_scanout; | |
98 | ||
99 | ||
100 | input iol2clk; | |
101 | input tcu_pce_ov; | |
102 | input tcu_clk_stop; | |
103 | input tcu_scan_en; | |
104 | input tcu_aclk; | |
105 | input tcu_bclk; | |
106 | input [1:0] ncu_scksel; | |
107 | input scan_in; | |
108 | output scan_out; | |
109 | ||
110 | // IO Pads | |
111 | output jbi_io_ssi_mosi; // Master out slave in to pad. | |
112 | input io_jbi_ssi_miso; // Master in slave out from pad. | |
113 | output jbi_io_ssi_sck; // Serial clock to pad. | |
114 | input io_jbi_ext_int_l; | |
115 | ||
116 | //IOB Interface | |
117 | input iob_jbi_spi_vld; // Valid packet from IOB. | |
118 | input [3:0] iob_jbi_spi_data; // Packet data from IOB. | |
119 | input iob_jbi_spi_stall; // Flow control to stop data. | |
120 | output jbi_iob_spi_vld; // Valid packet from UCB. | |
121 | output [3:0] jbi_iob_spi_data; // Packet data from UCB. | |
122 | output jbi_iob_spi_stall; // Flow control to stop data. | |
123 | input tcu_sck_bypass; // from TCU | |
124 | ||
125 | ||
126 | /*AUTOWIRE*/ | |
127 | // Beginning of automatic wires (for undeclared instantiated-module outputs) | |
128 | // End of automatics | |
129 | ||
130 | ||
131 | ncu_ssiflow_ctl ncu_ssiflow_ctl ( | |
132 | // Outputs | |
133 | .ucb_iob_stall(jbi_iob_spi_stall), // Templated | |
134 | .rd_req_vld (ucb_ucbif_rd_req_vld), // Templated | |
135 | .wr_req_vld (ucb_ucbif_wr_req_vld), // Templated | |
136 | .ifill_req_vld(ucb_ucbif_ifill_req_vld), // Templated | |
137 | .thr_id_in (ucb_ucbif_thr_id_in[5:0]), // Templated | |
138 | .buf_id_in (ucb_ucbif_buf_id_in[1:0]), // Templated | |
139 | .size_in (ucb_ucbif_size_in[2:0]), // Templated | |
140 | .addr_in (ucb_ucbif_addr_in[39:0]), // Templated | |
141 | .data_in (ucb_ucbif_data_in[63:0]), // Templated | |
142 | .ack_busy (ucb_ucbif_ack_busy), // Templated | |
143 | .int_busy (ucb_ucbif_int_busy), // Templated | |
144 | .ucb_iob_vld (jbi_iob_spi_vld), // Templated | |
145 | .ucb_iob_data(jbi_iob_spi_data[3:0]), // Templated | |
146 | // Inputs | |
147 | .scan_in(ncu_ssiflow_ctl_scanin), | |
148 | .scan_out(ncu_ssiflow_ctl_scanout), | |
149 | .iol2clk (iol2clk), | |
150 | .tcu_pce_ov(tcu_pce_ov), | |
151 | .tcu_clk_stop(tcu_clk_stop), | |
152 | .tcu_aclk(tcu_aclk), | |
153 | .tcu_bclk(tcu_bclk), | |
154 | .tcu_scan_en(tcu_scan_en), | |
155 | .iob_ucb_vld (iob_jbi_spi_vld), // Templated | |
156 | .iob_ucb_data(iob_jbi_spi_data[3:0]), // Templated | |
157 | .req_acpted (ucbif_ucb_req_acpted), // Templated | |
158 | .rd_ack_vld (ucbif_ucb_rd_ack_vld), // Templated | |
159 | .rd_nack_vld (ucbif_ucb_rd_nack_vld), // Templated | |
160 | .ifill_ack_vld(ucbif_ucb_ifill_ack_vld), // Templated | |
161 | .ifill_nack_vld(ucbif_ucb_ifill_nack_vld), // Templated | |
162 | .thr_id_out (ucbif_ucb_thr_id_out[5:0]), // Templated | |
163 | .buf_id_out (ucbif_ucb_buf_id_out[1:0]), // Templated | |
164 | .data_out (ucbif_ucb_data_out[63:0]), // Templated | |
165 | .int_vld (ucbif_ucb_int_vld), // Templated | |
166 | .int_typ (ucbif_ucb_int_type[3:0]), // Templated | |
167 | .int_thr_id (6'b0), // Templated | |
168 | .dev_id (ucbif_ucb_dev_id[8:0]), // Templated | |
169 | .int_stat (32'b0), // Templated | |
170 | .int_vec (6'b0), // Templated | |
171 | .sck_cntexp(sck_cntexp), | |
172 | .iob_ucb_stall(iob_jbi_spi_stall)); // Templated | |
173 | ||
174 | ncu_ssiuif_ctl ncu_ssiuif_ctl (/*AUTOINST*/ | |
175 | // Outputs | |
176 | .ucbif_ucb_req_acpted(ucbif_ucb_req_acpted), | |
177 | .ucbif_ucb_rd_ack_vld(ucbif_ucb_rd_ack_vld), | |
178 | .ucbif_ucb_rd_nack_vld(ucbif_ucb_rd_nack_vld), | |
179 | .ucbif_ucb_ifill_ack_vld(ucbif_ucb_ifill_ack_vld), | |
180 | .ucbif_ucb_ifill_nack_vld(ucbif_ucb_ifill_nack_vld), | |
181 | .ucbif_ucb_thr_id_out(ucbif_ucb_thr_id_out[5:0]), | |
182 | .ucbif_ucb_buf_id_out(ucbif_ucb_buf_id_out[1:0]), | |
183 | .ucbif_ucb_data_out(ucbif_ucb_data_out[63:0]), | |
184 | .ucbif_ucb_int_vld(ucbif_ucb_int_vld), | |
185 | .ucbif_ucb_int_type(ucbif_ucb_int_type[3:0]), | |
186 | .ucbif_ucb_dev_id(ucbif_ucb_dev_id[8:0]), | |
187 | .ucbif_sif_vld (ucbif_sif_vld), | |
188 | .ucbif_sif_rw (ucbif_sif_rw), | |
189 | .ucbif_sif_size (ucbif_sif_size[1:0]), | |
190 | .ucbif_sif_addr (ucbif_sif_addr[27:0]), | |
191 | .ucbif_sif_wdata(ucbif_sif_wdata[63:0]), | |
192 | .ucbif_sif_rdata_accpt(ucbif_sif_rdata_accpt), | |
193 | .ucbif_sif_timeout_accpt(ucbif_sif_timeout_accpt), | |
194 | .ucbif_sif_timeval(ucbif_sif_timeval[23:0]), | |
195 | // Inputs | |
196 | .scan_in(ncu_ssiuif_ctl_scanin), | |
197 | .scan_out(ncu_ssiuif_ctl_scanout), | |
198 | .iol2clk (iol2clk), | |
199 | .tcu_pce_ov(tcu_pce_ov), | |
200 | .tcu_clk_stop(tcu_clk_stop), | |
201 | .tcu_aclk(tcu_aclk), | |
202 | .tcu_bclk(tcu_bclk), | |
203 | .tcu_scan_en(tcu_scan_en), | |
204 | .io_jbi_ext_int_l(io_jbi_ext_int_l), | |
205 | .ucb_ucbif_rd_req_vld(ucb_ucbif_rd_req_vld), | |
206 | .ucb_ucbif_ifill_req_vld(ucb_ucbif_ifill_req_vld), | |
207 | .ucb_ucbif_wr_req_vld(ucb_ucbif_wr_req_vld), | |
208 | .ucb_ucbif_thr_id_in(ucb_ucbif_thr_id_in[5:0]), | |
209 | .ucb_ucbif_buf_id_in(ucb_ucbif_buf_id_in[1:0]), | |
210 | .ucb_ucbif_size_in(ucb_ucbif_size_in[2:0]), | |
211 | .ucb_ucbif_addr_in(ucb_ucbif_addr_in[39:0]), | |
212 | .ucb_ucbif_data_in(ucb_ucbif_data_in[63:0]), | |
213 | .ucb_ucbif_ack_busy(ucb_ucbif_ack_busy), | |
214 | .ucb_ucbif_int_busy(ucb_ucbif_int_busy), | |
215 | .sif_ucbif_busy (sif_ucbif_busy), | |
216 | .sif_ucbif_rdata(sif_ucbif_rdata[63:0]), | |
217 | .sif_ucbif_rdata_vld(sif_ucbif_rdata_vld), | |
218 | .sif_ucbif_timeout(sif_ucbif_timeout), | |
219 | .sif_ucbif_timeout_rw(sif_ucbif_timeout_rw), | |
220 | .sif_ucbif_par_err(sif_ucbif_par_err)); | |
221 | ||
222 | ncu_ssisif_ctl ncu_ssisif_ctl (/*AUTOINST*/ | |
223 | // Outputs | |
224 | .sif_ucbif_timeout (sif_ucbif_timeout), | |
225 | .sif_ucbif_timeout_rw(sif_ucbif_timeout_rw), | |
226 | .sif_ucbif_par_err (sif_ucbif_par_err), | |
227 | .sif_ucbif_busy (sif_ucbif_busy), | |
228 | .sif_ucbif_rdata (sif_ucbif_rdata[63:0]), | |
229 | .sif_ucbif_rdata_vld (sif_ucbif_rdata_vld), | |
230 | .jbi_io_ssi_mosi (jbi_io_ssi_mosi), | |
231 | .jbi_io_ssi_sck (jbi_io_ssi_sck), | |
232 | .sck_cntexp(sck_cntexp), | |
233 | // Inputs | |
234 | .scan_in(ncu_ssisif_ctl_scanin), | |
235 | .scan_out(ncu_ssisif_ctl_scanout), | |
236 | .iol2clk(iol2clk), | |
237 | .ncu_scksel(ncu_scksel[1:0]), | |
238 | .tcu_pce_ov(tcu_pce_ov), | |
239 | .tcu_clk_stop(tcu_clk_stop), | |
240 | .tcu_aclk(tcu_aclk), | |
241 | .tcu_bclk(tcu_bclk), | |
242 | .tcu_scan_en(tcu_scan_en), | |
243 | .tcu_sck_bypass(tcu_sck_bypass), | |
244 | .ucbif_sif_timeval (ucbif_sif_timeval[23:0]), | |
245 | .ucbif_sif_timeout_accpt(ucbif_sif_timeout_accpt), | |
246 | .ucbif_sif_vld (ucbif_sif_vld), | |
247 | .ucbif_sif_rw (ucbif_sif_rw), | |
248 | .ucbif_sif_size (ucbif_sif_size[1:0]), | |
249 | .ucbif_sif_addr (ucbif_sif_addr[27:0]), | |
250 | .ucbif_sif_wdata (ucbif_sif_wdata[63:0]), | |
251 | .ucbif_sif_rdata_accpt(ucbif_sif_rdata_accpt), | |
252 | .io_jbi_ssi_miso (io_jbi_ssi_miso)); | |
253 | ||
254 | /* | |
255 | spare_ctl_macro spares (num=11) ( | |
256 | .scan_in(spares_scanin), | |
257 | .scan_out(spares_scanout), | |
258 | .l1clk (l1clk) | |
259 | ); | |
260 | */ | |
261 | ||
262 | // fixscan start: | |
263 | assign ncu_ssiflow_ctl_scanin = scan_in ; | |
264 | assign ncu_ssiuif_ctl_scanin = ncu_ssiflow_ctl_scanout ; | |
265 | assign ncu_ssisif_ctl_scanin = ncu_ssiuif_ctl_scanout ; | |
266 | //assign spares_scanin = ncu_ssisif_ctl_scanout ; | |
267 | //assign scan_out = spares_scanout ; | |
268 | assign scan_out = ncu_ssisif_ctl_scanout ; | |
269 | // fixscan end: | |
270 | endmodule | |
271 | ||
272 | // Local Variables: | |
273 | // verilog-library-directories:("." "../../../common/rtl/") | |
274 | // verilog-auto-sense-defines-constant:t | |
275 | // End: | |
276 | ||
277 | ||
278 | ||
279 | ||
280 | // any PARAMS parms go into naming of macro | |
281 | ||
282 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_1 ( | |
283 | din, | |
284 | en, | |
285 | l1clk, | |
286 | scan_in, | |
287 | siclk, | |
288 | soclk, | |
289 | dout, | |
290 | scan_out); | |
291 | wire [0:0] fdin; | |
292 | ||
293 | input [0:0] din; | |
294 | input en; | |
295 | input l1clk; | |
296 | input scan_in; | |
297 | ||
298 | ||
299 | input siclk; | |
300 | input soclk; | |
301 | ||
302 | output [0:0] dout; | |
303 | output scan_out; | |
304 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
305 | ||
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | dff #(1) d0_0 ( | |
312 | .l1clk(l1clk), | |
313 | .siclk(siclk), | |
314 | .soclk(soclk), | |
315 | .d(fdin[0:0]), | |
316 | .si(scan_in), | |
317 | .so(scan_out), | |
318 | .q(dout[0:0]) | |
319 | ); | |
320 | ||
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | ||
330 | ||
331 | ||
332 | endmodule | |
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | ||
339 | ||
340 | ||
341 | ||
342 | ||
343 | ||
344 | ||
345 | ||
346 | // any PARAMS parms go into naming of macro | |
347 | ||
348 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_4 ( | |
349 | din, | |
350 | en, | |
351 | l1clk, | |
352 | scan_in, | |
353 | siclk, | |
354 | soclk, | |
355 | dout, | |
356 | scan_out); | |
357 | wire [3:0] fdin; | |
358 | wire [2:0] so; | |
359 | ||
360 | input [3:0] din; | |
361 | input en; | |
362 | input l1clk; | |
363 | input scan_in; | |
364 | ||
365 | ||
366 | input siclk; | |
367 | input soclk; | |
368 | ||
369 | output [3:0] dout; | |
370 | output scan_out; | |
371 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
372 | ||
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | dff #(4) d0_0 ( | |
379 | .l1clk(l1clk), | |
380 | .siclk(siclk), | |
381 | .soclk(soclk), | |
382 | .d(fdin[3:0]), | |
383 | .si({scan_in,so[2:0]}), | |
384 | .so({so[2:0],scan_out}), | |
385 | .q(dout[3:0]) | |
386 | ); | |
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 | ||
399 | endmodule | |
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | // any PARAMS parms go into naming of macro | |
414 | ||
415 | module ncu_ssitop_ctl_msff_ctl_macro__width_1 ( | |
416 | din, | |
417 | l1clk, | |
418 | scan_in, | |
419 | siclk, | |
420 | soclk, | |
421 | dout, | |
422 | scan_out); | |
423 | wire [0:0] fdin; | |
424 | ||
425 | input [0:0] din; | |
426 | input l1clk; | |
427 | input scan_in; | |
428 | ||
429 | ||
430 | input siclk; | |
431 | input soclk; | |
432 | ||
433 | output [0:0] dout; | |
434 | output scan_out; | |
435 | assign fdin[0:0] = din[0:0]; | |
436 | ||
437 | ||
438 | ||
439 | ||
440 | ||
441 | ||
442 | dff #(1) d0_0 ( | |
443 | .l1clk(l1clk), | |
444 | .siclk(siclk), | |
445 | .soclk(soclk), | |
446 | .d(fdin[0:0]), | |
447 | .si(scan_in), | |
448 | .so(scan_out), | |
449 | .q(dout[0:0]) | |
450 | ); | |
451 | ||
452 | ||
453 | ||
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | endmodule | |
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | // any PARAMS parms go into naming of macro | |
478 | ||
479 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_32 ( | |
480 | din, | |
481 | en, | |
482 | l1clk, | |
483 | scan_in, | |
484 | siclk, | |
485 | soclk, | |
486 | dout, | |
487 | scan_out); | |
488 | wire [31:0] fdin; | |
489 | wire [30:0] so; | |
490 | ||
491 | input [31:0] din; | |
492 | input en; | |
493 | input l1clk; | |
494 | input scan_in; | |
495 | ||
496 | ||
497 | input siclk; | |
498 | input soclk; | |
499 | ||
500 | output [31:0] dout; | |
501 | output scan_out; | |
502 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); | |
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | dff #(32) d0_0 ( | |
510 | .l1clk(l1clk), | |
511 | .siclk(siclk), | |
512 | .soclk(soclk), | |
513 | .d(fdin[31:0]), | |
514 | .si({scan_in,so[30:0]}), | |
515 | .so({so[30:0],scan_out}), | |
516 | .q(dout[31:0]) | |
517 | ); | |
518 | ||
519 | ||
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | endmodule | |
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | // any PARAMS parms go into naming of macro | |
545 | ||
546 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_128 ( | |
547 | din, | |
548 | en, | |
549 | l1clk, | |
550 | scan_in, | |
551 | siclk, | |
552 | soclk, | |
553 | dout, | |
554 | scan_out); | |
555 | wire [127:0] fdin; | |
556 | wire [126:0] so; | |
557 | ||
558 | input [127:0] din; | |
559 | input en; | |
560 | input l1clk; | |
561 | input scan_in; | |
562 | ||
563 | ||
564 | input siclk; | |
565 | input soclk; | |
566 | ||
567 | output [127:0] dout; | |
568 | output scan_out; | |
569 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); | |
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | dff #(128) d0_0 ( | |
577 | .l1clk(l1clk), | |
578 | .siclk(siclk), | |
579 | .soclk(soclk), | |
580 | .d(fdin[127:0]), | |
581 | .si({scan_in,so[126:0]}), | |
582 | .so({so[126:0],scan_out}), | |
583 | .q(dout[127:0]) | |
584 | ); | |
585 | ||
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | endmodule | |
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | // any PARAMS parms go into naming of macro | |
612 | ||
613 | module ncu_ssitop_ctl_l1clkhdr_ctl_macro ( | |
614 | l2clk, | |
615 | l1en, | |
616 | pce_ov, | |
617 | stop, | |
618 | se, | |
619 | l1clk); | |
620 | ||
621 | ||
622 | input l2clk; | |
623 | input l1en; | |
624 | input pce_ov; | |
625 | input stop; | |
626 | input se; | |
627 | output l1clk; | |
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | cl_sc1_l1hdr_8x c_0 ( | |
634 | ||
635 | ||
636 | .l2clk(l2clk), | |
637 | .pce(l1en), | |
638 | .l1clk(l1clk), | |
639 | .se(se), | |
640 | .pce_ov(pce_ov), | |
641 | .stop(stop) | |
642 | ); | |
643 | ||
644 | ||
645 | ||
646 | endmodule | |
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | // any PARAMS parms go into naming of macro | |
661 | ||
662 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_118 ( | |
663 | din, | |
664 | en, | |
665 | l1clk, | |
666 | scan_in, | |
667 | siclk, | |
668 | soclk, | |
669 | dout, | |
670 | scan_out); | |
671 | wire [117:0] fdin; | |
672 | wire [116:0] so; | |
673 | ||
674 | input [117:0] din; | |
675 | input en; | |
676 | input l1clk; | |
677 | input scan_in; | |
678 | ||
679 | ||
680 | input siclk; | |
681 | input soclk; | |
682 | ||
683 | output [117:0] dout; | |
684 | output scan_out; | |
685 | assign fdin[117:0] = (din[117:0] & {118{en}}) | (dout[117:0] & ~{118{en}}); | |
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | dff #(118) d0_0 ( | |
693 | .l1clk(l1clk), | |
694 | .siclk(siclk), | |
695 | .soclk(soclk), | |
696 | .d(fdin[117:0]), | |
697 | .si({scan_in,so[116:0]}), | |
698 | .so({so[116:0],scan_out}), | |
699 | .q(dout[117:0]) | |
700 | ); | |
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | endmodule | |
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | // any PARAMS parms go into naming of macro | |
728 | ||
729 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_76 ( | |
730 | din, | |
731 | en, | |
732 | l1clk, | |
733 | scan_in, | |
734 | siclk, | |
735 | soclk, | |
736 | dout, | |
737 | scan_out); | |
738 | wire [75:0] fdin; | |
739 | wire [74:0] so; | |
740 | ||
741 | input [75:0] din; | |
742 | input en; | |
743 | input l1clk; | |
744 | input scan_in; | |
745 | ||
746 | ||
747 | input siclk; | |
748 | input soclk; | |
749 | ||
750 | output [75:0] dout; | |
751 | output scan_out; | |
752 | assign fdin[75:0] = (din[75:0] & {76{en}}) | (dout[75:0] & ~{76{en}}); | |
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | dff #(76) d0_0 ( | |
760 | .l1clk(l1clk), | |
761 | .siclk(siclk), | |
762 | .soclk(soclk), | |
763 | .d(fdin[75:0]), | |
764 | .si({scan_in,so[74:0]}), | |
765 | .so({so[74:0],scan_out}), | |
766 | .q(dout[75:0]) | |
767 | ); | |
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | endmodule | |
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | ||
792 | ||
793 | ||
794 | // any PARAMS parms go into naming of macro | |
795 | ||
796 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_57 ( | |
797 | din, | |
798 | en, | |
799 | l1clk, | |
800 | scan_in, | |
801 | siclk, | |
802 | soclk, | |
803 | dout, | |
804 | scan_out); | |
805 | wire [56:0] fdin; | |
806 | wire [55:0] so; | |
807 | ||
808 | input [56:0] din; | |
809 | input en; | |
810 | input l1clk; | |
811 | input scan_in; | |
812 | ||
813 | ||
814 | input siclk; | |
815 | input soclk; | |
816 | ||
817 | output [56:0] dout; | |
818 | output scan_out; | |
819 | assign fdin[56:0] = (din[56:0] & {57{en}}) | (dout[56:0] & ~{57{en}}); | |
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | dff #(57) d0_0 ( | |
827 | .l1clk(l1clk), | |
828 | .siclk(siclk), | |
829 | .soclk(soclk), | |
830 | .d(fdin[56:0]), | |
831 | .si({scan_in,so[55:0]}), | |
832 | .so({so[55:0],scan_out}), | |
833 | .q(dout[56:0]) | |
834 | ); | |
835 | ||
836 | ||
837 | ||
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | ||
847 | endmodule | |
848 | ||
849 | ||
850 | ||
851 | ||
852 | ||
853 | // any PARAMS parms go into naming of macro | |
854 | ||
855 | module ncu_ssitop_ctl_msff_ctl_macro__width_32 ( | |
856 | din, | |
857 | l1clk, | |
858 | scan_in, | |
859 | siclk, | |
860 | soclk, | |
861 | dout, | |
862 | scan_out); | |
863 | wire [31:0] fdin; | |
864 | wire [30:0] so; | |
865 | ||
866 | input [31:0] din; | |
867 | input l1clk; | |
868 | input scan_in; | |
869 | ||
870 | ||
871 | input siclk; | |
872 | input soclk; | |
873 | ||
874 | output [31:0] dout; | |
875 | output scan_out; | |
876 | assign fdin[31:0] = din[31:0]; | |
877 | ||
878 | ||
879 | ||
880 | ||
881 | ||
882 | ||
883 | dff #(32) d0_0 ( | |
884 | .l1clk(l1clk), | |
885 | .siclk(siclk), | |
886 | .soclk(soclk), | |
887 | .d(fdin[31:0]), | |
888 | .si({scan_in,so[30:0]}), | |
889 | .so({so[30:0],scan_out}), | |
890 | .q(dout[31:0]) | |
891 | ); | |
892 | ||
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | endmodule | |
905 | ||
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | // any PARAMS parms go into naming of macro | |
919 | ||
920 | module ncu_ssitop_ctl_msff_ctl_macro__width_128 ( | |
921 | din, | |
922 | l1clk, | |
923 | scan_in, | |
924 | siclk, | |
925 | soclk, | |
926 | dout, | |
927 | scan_out); | |
928 | wire [127:0] fdin; | |
929 | wire [126:0] so; | |
930 | ||
931 | input [127:0] din; | |
932 | input l1clk; | |
933 | input scan_in; | |
934 | ||
935 | ||
936 | input siclk; | |
937 | input soclk; | |
938 | ||
939 | output [127:0] dout; | |
940 | output scan_out; | |
941 | assign fdin[127:0] = din[127:0]; | |
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | dff #(128) d0_0 ( | |
949 | .l1clk(l1clk), | |
950 | .siclk(siclk), | |
951 | .soclk(soclk), | |
952 | .d(fdin[127:0]), | |
953 | .si({scan_in,so[126:0]}), | |
954 | .so({so[126:0],scan_out}), | |
955 | .q(dout[127:0]) | |
956 | ); | |
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | endmodule | |
970 | ||
971 | ||
972 | ||
973 | // any PARAMS parms go into naming of macro | |
974 | ||
975 | module ncu_ssitop_ctl_msff_ctl_macro__width_25 ( | |
976 | din, | |
977 | l1clk, | |
978 | scan_in, | |
979 | siclk, | |
980 | soclk, | |
981 | dout, | |
982 | scan_out); | |
983 | wire [24:0] fdin; | |
984 | wire [23:0] so; | |
985 | ||
986 | input [24:0] din; | |
987 | input l1clk; | |
988 | input scan_in; | |
989 | ||
990 | ||
991 | input siclk; | |
992 | input soclk; | |
993 | ||
994 | output [24:0] dout; | |
995 | output scan_out; | |
996 | assign fdin[24:0] = din[24:0]; | |
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | dff #(25) d0_0 ( | |
1004 | .l1clk(l1clk), | |
1005 | .siclk(siclk), | |
1006 | .soclk(soclk), | |
1007 | .d(fdin[24:0]), | |
1008 | .si({scan_in,so[23:0]}), | |
1009 | .so({so[23:0],scan_out}), | |
1010 | .q(dout[24:0]) | |
1011 | ); | |
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | endmodule | |
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | ||
1038 | // any PARAMS parms go into naming of macro | |
1039 | ||
1040 | module ncu_ssitop_ctl_msff_ctl_macro__width_2 ( | |
1041 | din, | |
1042 | l1clk, | |
1043 | scan_in, | |
1044 | siclk, | |
1045 | soclk, | |
1046 | dout, | |
1047 | scan_out); | |
1048 | wire [1:0] fdin; | |
1049 | wire [0:0] so; | |
1050 | ||
1051 | input [1:0] din; | |
1052 | input l1clk; | |
1053 | input scan_in; | |
1054 | ||
1055 | ||
1056 | input siclk; | |
1057 | input soclk; | |
1058 | ||
1059 | output [1:0] dout; | |
1060 | output scan_out; | |
1061 | assign fdin[1:0] = din[1:0]; | |
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | dff #(2) d0_0 ( | |
1069 | .l1clk(l1clk), | |
1070 | .siclk(siclk), | |
1071 | .soclk(soclk), | |
1072 | .d(fdin[1:0]), | |
1073 | .si({scan_in,so[0:0]}), | |
1074 | .so({so[0:0],scan_out}), | |
1075 | .q(dout[1:0]) | |
1076 | ); | |
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | endmodule | |
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | ||
1095 | ||
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | // any PARAMS parms go into naming of macro | |
1104 | ||
1105 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_6 ( | |
1106 | din, | |
1107 | en, | |
1108 | l1clk, | |
1109 | scan_in, | |
1110 | siclk, | |
1111 | soclk, | |
1112 | dout, | |
1113 | scan_out); | |
1114 | wire [5:0] fdin; | |
1115 | wire [4:0] so; | |
1116 | ||
1117 | input [5:0] din; | |
1118 | input en; | |
1119 | input l1clk; | |
1120 | input scan_in; | |
1121 | ||
1122 | ||
1123 | input siclk; | |
1124 | input soclk; | |
1125 | ||
1126 | output [5:0] dout; | |
1127 | output scan_out; | |
1128 | assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}}); | |
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | dff #(6) d0_0 ( | |
1136 | .l1clk(l1clk), | |
1137 | .siclk(siclk), | |
1138 | .soclk(soclk), | |
1139 | .d(fdin[5:0]), | |
1140 | .si({scan_in,so[4:0]}), | |
1141 | .so({so[4:0],scan_out}), | |
1142 | .q(dout[5:0]) | |
1143 | ); | |
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | endmodule | |
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | // any PARAMS parms go into naming of macro | |
1171 | ||
1172 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_2 ( | |
1173 | din, | |
1174 | en, | |
1175 | l1clk, | |
1176 | scan_in, | |
1177 | siclk, | |
1178 | soclk, | |
1179 | dout, | |
1180 | scan_out); | |
1181 | wire [1:0] fdin; | |
1182 | wire [0:0] so; | |
1183 | ||
1184 | input [1:0] din; | |
1185 | input en; | |
1186 | input l1clk; | |
1187 | input scan_in; | |
1188 | ||
1189 | ||
1190 | input siclk; | |
1191 | input soclk; | |
1192 | ||
1193 | output [1:0] dout; | |
1194 | output scan_out; | |
1195 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | dff #(2) d0_0 ( | |
1203 | .l1clk(l1clk), | |
1204 | .siclk(siclk), | |
1205 | .soclk(soclk), | |
1206 | .d(fdin[1:0]), | |
1207 | .si({scan_in,so[0:0]}), | |
1208 | .so({so[0:0],scan_out}), | |
1209 | .q(dout[1:0]) | |
1210 | ); | |
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | ||
1223 | endmodule | |
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | // any PARAMS parms go into naming of macro | |
1229 | ||
1230 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_64 ( | |
1231 | din, | |
1232 | en, | |
1233 | l1clk, | |
1234 | scan_in, | |
1235 | siclk, | |
1236 | soclk, | |
1237 | dout, | |
1238 | scan_out); | |
1239 | wire [63:0] fdin; | |
1240 | wire [62:0] so; | |
1241 | ||
1242 | input [63:0] din; | |
1243 | input en; | |
1244 | input l1clk; | |
1245 | input scan_in; | |
1246 | ||
1247 | ||
1248 | input siclk; | |
1249 | input soclk; | |
1250 | ||
1251 | output [63:0] dout; | |
1252 | output scan_out; | |
1253 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); | |
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | dff #(64) d0_0 ( | |
1261 | .l1clk(l1clk), | |
1262 | .siclk(siclk), | |
1263 | .soclk(soclk), | |
1264 | .d(fdin[63:0]), | |
1265 | .si({scan_in,so[62:0]}), | |
1266 | .so({so[62:0],scan_out}), | |
1267 | .q(dout[63:0]) | |
1268 | ); | |
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | endmodule | |
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | // any PARAMS parms go into naming of macro | |
1296 | ||
1297 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_3 ( | |
1298 | din, | |
1299 | en, | |
1300 | l1clk, | |
1301 | scan_in, | |
1302 | siclk, | |
1303 | soclk, | |
1304 | dout, | |
1305 | scan_out); | |
1306 | wire [2:0] fdin; | |
1307 | wire [1:0] so; | |
1308 | ||
1309 | input [2:0] din; | |
1310 | input en; | |
1311 | input l1clk; | |
1312 | input scan_in; | |
1313 | ||
1314 | ||
1315 | input siclk; | |
1316 | input soclk; | |
1317 | ||
1318 | output [2:0] dout; | |
1319 | output scan_out; | |
1320 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | dff #(3) d0_0 ( | |
1328 | .l1clk(l1clk), | |
1329 | .siclk(siclk), | |
1330 | .soclk(soclk), | |
1331 | .d(fdin[2:0]), | |
1332 | .si({scan_in,so[1:0]}), | |
1333 | .so({so[1:0],scan_out}), | |
1334 | .q(dout[2:0]) | |
1335 | ); | |
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | endmodule | |
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | // any PARAMS parms go into naming of macro | |
1363 | ||
1364 | module ncu_ssitop_ctl_msff_ctl_macro__en_1__width_24 ( | |
1365 | din, | |
1366 | en, | |
1367 | l1clk, | |
1368 | scan_in, | |
1369 | siclk, | |
1370 | soclk, | |
1371 | dout, | |
1372 | scan_out); | |
1373 | wire [23:0] fdin; | |
1374 | wire [22:0] so; | |
1375 | ||
1376 | input [23:0] din; | |
1377 | input en; | |
1378 | input l1clk; | |
1379 | input scan_in; | |
1380 | ||
1381 | ||
1382 | input siclk; | |
1383 | input soclk; | |
1384 | ||
1385 | output [23:0] dout; | |
1386 | output scan_out; | |
1387 | assign fdin[23:0] = (din[23:0] & {24{en}}) | (dout[23:0] & ~{24{en}}); | |
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | dff #(24) d0_0 ( | |
1395 | .l1clk(l1clk), | |
1396 | .siclk(siclk), | |
1397 | .soclk(soclk), | |
1398 | .d(fdin[23:0]), | |
1399 | .si({scan_in,so[22:0]}), | |
1400 | .so({so[22:0],scan_out}), | |
1401 | .q(dout[23:0]) | |
1402 | ); | |
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | endmodule | |
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | // any PARAMS parms go into naming of macro | |
1424 | ||
1425 | module ncu_ssitop_ctl_msff_ctl_macro__width_8 ( | |
1426 | din, | |
1427 | l1clk, | |
1428 | scan_in, | |
1429 | siclk, | |
1430 | soclk, | |
1431 | dout, | |
1432 | scan_out); | |
1433 | wire [7:0] fdin; | |
1434 | wire [6:0] so; | |
1435 | ||
1436 | input [7:0] din; | |
1437 | input l1clk; | |
1438 | input scan_in; | |
1439 | ||
1440 | ||
1441 | input siclk; | |
1442 | input soclk; | |
1443 | ||
1444 | output [7:0] dout; | |
1445 | output scan_out; | |
1446 | assign fdin[7:0] = din[7:0]; | |
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | dff #(8) d0_0 ( | |
1454 | .l1clk(l1clk), | |
1455 | .siclk(siclk), | |
1456 | .soclk(soclk), | |
1457 | .d(fdin[7:0]), | |
1458 | .si({scan_in,so[6:0]}), | |
1459 | .so({so[6:0],scan_out}), | |
1460 | .q(dout[7:0]) | |
1461 | ); | |
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | endmodule | |
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | ||
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | // any PARAMS parms go into naming of macro | |
1489 | ||
1490 | module ncu_ssitop_ctl_msff_ctl_macro__width_64 ( | |
1491 | din, | |
1492 | l1clk, | |
1493 | scan_in, | |
1494 | siclk, | |
1495 | soclk, | |
1496 | dout, | |
1497 | scan_out); | |
1498 | wire [63:0] fdin; | |
1499 | wire [62:0] so; | |
1500 | ||
1501 | input [63:0] din; | |
1502 | input l1clk; | |
1503 | input scan_in; | |
1504 | ||
1505 | ||
1506 | input siclk; | |
1507 | input soclk; | |
1508 | ||
1509 | output [63:0] dout; | |
1510 | output scan_out; | |
1511 | assign fdin[63:0] = din[63:0]; | |
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | dff #(64) d0_0 ( | |
1519 | .l1clk(l1clk), | |
1520 | .siclk(siclk), | |
1521 | .soclk(soclk), | |
1522 | .d(fdin[63:0]), | |
1523 | .si({scan_in,so[62:0]}), | |
1524 | .so({so[62:0],scan_out}), | |
1525 | .q(dout[63:0]) | |
1526 | ); | |
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | endmodule | |
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | // any PARAMS parms go into naming of macro | |
1554 | ||
1555 | module ncu_ssitop_ctl_msff_ctl_macro__width_3 ( | |
1556 | din, | |
1557 | l1clk, | |
1558 | scan_in, | |
1559 | siclk, | |
1560 | soclk, | |
1561 | dout, | |
1562 | scan_out); | |
1563 | wire [2:0] fdin; | |
1564 | wire [1:0] so; | |
1565 | ||
1566 | input [2:0] din; | |
1567 | input l1clk; | |
1568 | input scan_in; | |
1569 | ||
1570 | ||
1571 | input siclk; | |
1572 | input soclk; | |
1573 | ||
1574 | output [2:0] dout; | |
1575 | output scan_out; | |
1576 | assign fdin[2:0] = din[2:0]; | |
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | dff #(3) d0_0 ( | |
1584 | .l1clk(l1clk), | |
1585 | .siclk(siclk), | |
1586 | .soclk(soclk), | |
1587 | .d(fdin[2:0]), | |
1588 | .si({scan_in,so[1:0]}), | |
1589 | .so({so[1:0],scan_out}), | |
1590 | .q(dout[2:0]) | |
1591 | ); | |
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | endmodule | |
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | // any PARAMS parms go into naming of macro | |
1619 | ||
1620 | module ncu_ssitop_ctl_msff_ctl_macro__width_7 ( | |
1621 | din, | |
1622 | l1clk, | |
1623 | scan_in, | |
1624 | siclk, | |
1625 | soclk, | |
1626 | dout, | |
1627 | scan_out); | |
1628 | wire [6:0] fdin; | |
1629 | wire [5:0] so; | |
1630 | ||
1631 | input [6:0] din; | |
1632 | input l1clk; | |
1633 | input scan_in; | |
1634 | ||
1635 | ||
1636 | input siclk; | |
1637 | input soclk; | |
1638 | ||
1639 | output [6:0] dout; | |
1640 | output scan_out; | |
1641 | assign fdin[6:0] = din[6:0]; | |
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | dff #(7) d0_0 ( | |
1649 | .l1clk(l1clk), | |
1650 | .siclk(siclk), | |
1651 | .soclk(soclk), | |
1652 | .d(fdin[6:0]), | |
1653 | .si({scan_in,so[5:0]}), | |
1654 | .so({so[5:0],scan_out}), | |
1655 | .q(dout[6:0]) | |
1656 | ); | |
1657 | ||
1658 | ||
1659 | ||
1660 | ||
1661 | ||
1662 | ||
1663 | ||
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | endmodule | |
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | // any PARAMS parms go into naming of macro | |
1684 | ||
1685 | module ncu_ssitop_ctl_msff_ctl_macro__width_18 ( | |
1686 | din, | |
1687 | l1clk, | |
1688 | scan_in, | |
1689 | siclk, | |
1690 | soclk, | |
1691 | dout, | |
1692 | scan_out); | |
1693 | wire [17:0] fdin; | |
1694 | wire [16:0] so; | |
1695 | ||
1696 | input [17:0] din; | |
1697 | input l1clk; | |
1698 | input scan_in; | |
1699 | ||
1700 | ||
1701 | input siclk; | |
1702 | input soclk; | |
1703 | ||
1704 | output [17:0] dout; | |
1705 | output scan_out; | |
1706 | assign fdin[17:0] = din[17:0]; | |
1707 | ||
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | dff #(18) d0_0 ( | |
1714 | .l1clk(l1clk), | |
1715 | .siclk(siclk), | |
1716 | .soclk(soclk), | |
1717 | .d(fdin[17:0]), | |
1718 | .si({scan_in,so[16:0]}), | |
1719 | .so({so[16:0],scan_out}), | |
1720 | .q(dout[17:0]) | |
1721 | ); | |
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | ||
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | endmodule | |
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | ||
1743 | ||
1744 | // Description: Spare gate macro for control blocks | |
1745 | // | |
1746 | // Param num controls the number of times the macro is added | |
1747 | // flops=0 can be used to use only combination spare logic | |
1748 | ||
1749 | ||
1750 | module ncu_ssitop_ctl_spare_ctl_macro__num_11 ( | |
1751 | l1clk, | |
1752 | scan_in, | |
1753 | siclk, | |
1754 | soclk, | |
1755 | scan_out); | |
1756 | wire si_0; | |
1757 | wire so_0; | |
1758 | wire spare0_flop_unused; | |
1759 | wire spare0_buf_32x_unused; | |
1760 | wire spare0_nand3_8x_unused; | |
1761 | wire spare0_inv_8x_unused; | |
1762 | wire spare0_aoi22_4x_unused; | |
1763 | wire spare0_buf_8x_unused; | |
1764 | wire spare0_oai22_4x_unused; | |
1765 | wire spare0_inv_16x_unused; | |
1766 | wire spare0_nand2_16x_unused; | |
1767 | wire spare0_nor3_4x_unused; | |
1768 | wire spare0_nand2_8x_unused; | |
1769 | wire spare0_buf_16x_unused; | |
1770 | wire spare0_nor2_16x_unused; | |
1771 | wire spare0_inv_32x_unused; | |
1772 | wire si_1; | |
1773 | wire so_1; | |
1774 | wire spare1_flop_unused; | |
1775 | wire spare1_buf_32x_unused; | |
1776 | wire spare1_nand3_8x_unused; | |
1777 | wire spare1_inv_8x_unused; | |
1778 | wire spare1_aoi22_4x_unused; | |
1779 | wire spare1_buf_8x_unused; | |
1780 | wire spare1_oai22_4x_unused; | |
1781 | wire spare1_inv_16x_unused; | |
1782 | wire spare1_nand2_16x_unused; | |
1783 | wire spare1_nor3_4x_unused; | |
1784 | wire spare1_nand2_8x_unused; | |
1785 | wire spare1_buf_16x_unused; | |
1786 | wire spare1_nor2_16x_unused; | |
1787 | wire spare1_inv_32x_unused; | |
1788 | wire si_2; | |
1789 | wire so_2; | |
1790 | wire spare2_flop_unused; | |
1791 | wire spare2_buf_32x_unused; | |
1792 | wire spare2_nand3_8x_unused; | |
1793 | wire spare2_inv_8x_unused; | |
1794 | wire spare2_aoi22_4x_unused; | |
1795 | wire spare2_buf_8x_unused; | |
1796 | wire spare2_oai22_4x_unused; | |
1797 | wire spare2_inv_16x_unused; | |
1798 | wire spare2_nand2_16x_unused; | |
1799 | wire spare2_nor3_4x_unused; | |
1800 | wire spare2_nand2_8x_unused; | |
1801 | wire spare2_buf_16x_unused; | |
1802 | wire spare2_nor2_16x_unused; | |
1803 | wire spare2_inv_32x_unused; | |
1804 | wire si_3; | |
1805 | wire so_3; | |
1806 | wire spare3_flop_unused; | |
1807 | wire spare3_buf_32x_unused; | |
1808 | wire spare3_nand3_8x_unused; | |
1809 | wire spare3_inv_8x_unused; | |
1810 | wire spare3_aoi22_4x_unused; | |
1811 | wire spare3_buf_8x_unused; | |
1812 | wire spare3_oai22_4x_unused; | |
1813 | wire spare3_inv_16x_unused; | |
1814 | wire spare3_nand2_16x_unused; | |
1815 | wire spare3_nor3_4x_unused; | |
1816 | wire spare3_nand2_8x_unused; | |
1817 | wire spare3_buf_16x_unused; | |
1818 | wire spare3_nor2_16x_unused; | |
1819 | wire spare3_inv_32x_unused; | |
1820 | wire si_4; | |
1821 | wire so_4; | |
1822 | wire spare4_flop_unused; | |
1823 | wire spare4_buf_32x_unused; | |
1824 | wire spare4_nand3_8x_unused; | |
1825 | wire spare4_inv_8x_unused; | |
1826 | wire spare4_aoi22_4x_unused; | |
1827 | wire spare4_buf_8x_unused; | |
1828 | wire spare4_oai22_4x_unused; | |
1829 | wire spare4_inv_16x_unused; | |
1830 | wire spare4_nand2_16x_unused; | |
1831 | wire spare4_nor3_4x_unused; | |
1832 | wire spare4_nand2_8x_unused; | |
1833 | wire spare4_buf_16x_unused; | |
1834 | wire spare4_nor2_16x_unused; | |
1835 | wire spare4_inv_32x_unused; | |
1836 | wire si_5; | |
1837 | wire so_5; | |
1838 | wire spare5_flop_unused; | |
1839 | wire spare5_buf_32x_unused; | |
1840 | wire spare5_nand3_8x_unused; | |
1841 | wire spare5_inv_8x_unused; | |
1842 | wire spare5_aoi22_4x_unused; | |
1843 | wire spare5_buf_8x_unused; | |
1844 | wire spare5_oai22_4x_unused; | |
1845 | wire spare5_inv_16x_unused; | |
1846 | wire spare5_nand2_16x_unused; | |
1847 | wire spare5_nor3_4x_unused; | |
1848 | wire spare5_nand2_8x_unused; | |
1849 | wire spare5_buf_16x_unused; | |
1850 | wire spare5_nor2_16x_unused; | |
1851 | wire spare5_inv_32x_unused; | |
1852 | wire si_6; | |
1853 | wire so_6; | |
1854 | wire spare6_flop_unused; | |
1855 | wire spare6_buf_32x_unused; | |
1856 | wire spare6_nand3_8x_unused; | |
1857 | wire spare6_inv_8x_unused; | |
1858 | wire spare6_aoi22_4x_unused; | |
1859 | wire spare6_buf_8x_unused; | |
1860 | wire spare6_oai22_4x_unused; | |
1861 | wire spare6_inv_16x_unused; | |
1862 | wire spare6_nand2_16x_unused; | |
1863 | wire spare6_nor3_4x_unused; | |
1864 | wire spare6_nand2_8x_unused; | |
1865 | wire spare6_buf_16x_unused; | |
1866 | wire spare6_nor2_16x_unused; | |
1867 | wire spare6_inv_32x_unused; | |
1868 | wire si_7; | |
1869 | wire so_7; | |
1870 | wire spare7_flop_unused; | |
1871 | wire spare7_buf_32x_unused; | |
1872 | wire spare7_nand3_8x_unused; | |
1873 | wire spare7_inv_8x_unused; | |
1874 | wire spare7_aoi22_4x_unused; | |
1875 | wire spare7_buf_8x_unused; | |
1876 | wire spare7_oai22_4x_unused; | |
1877 | wire spare7_inv_16x_unused; | |
1878 | wire spare7_nand2_16x_unused; | |
1879 | wire spare7_nor3_4x_unused; | |
1880 | wire spare7_nand2_8x_unused; | |
1881 | wire spare7_buf_16x_unused; | |
1882 | wire spare7_nor2_16x_unused; | |
1883 | wire spare7_inv_32x_unused; | |
1884 | wire si_8; | |
1885 | wire so_8; | |
1886 | wire spare8_flop_unused; | |
1887 | wire spare8_buf_32x_unused; | |
1888 | wire spare8_nand3_8x_unused; | |
1889 | wire spare8_inv_8x_unused; | |
1890 | wire spare8_aoi22_4x_unused; | |
1891 | wire spare8_buf_8x_unused; | |
1892 | wire spare8_oai22_4x_unused; | |
1893 | wire spare8_inv_16x_unused; | |
1894 | wire spare8_nand2_16x_unused; | |
1895 | wire spare8_nor3_4x_unused; | |
1896 | wire spare8_nand2_8x_unused; | |
1897 | wire spare8_buf_16x_unused; | |
1898 | wire spare8_nor2_16x_unused; | |
1899 | wire spare8_inv_32x_unused; | |
1900 | wire si_9; | |
1901 | wire so_9; | |
1902 | wire spare9_flop_unused; | |
1903 | wire spare9_buf_32x_unused; | |
1904 | wire spare9_nand3_8x_unused; | |
1905 | wire spare9_inv_8x_unused; | |
1906 | wire spare9_aoi22_4x_unused; | |
1907 | wire spare9_buf_8x_unused; | |
1908 | wire spare9_oai22_4x_unused; | |
1909 | wire spare9_inv_16x_unused; | |
1910 | wire spare9_nand2_16x_unused; | |
1911 | wire spare9_nor3_4x_unused; | |
1912 | wire spare9_nand2_8x_unused; | |
1913 | wire spare9_buf_16x_unused; | |
1914 | wire spare9_nor2_16x_unused; | |
1915 | wire spare9_inv_32x_unused; | |
1916 | wire si_10; | |
1917 | wire so_10; | |
1918 | wire spare10_flop_unused; | |
1919 | wire spare10_buf_32x_unused; | |
1920 | wire spare10_nand3_8x_unused; | |
1921 | wire spare10_inv_8x_unused; | |
1922 | wire spare10_aoi22_4x_unused; | |
1923 | wire spare10_buf_8x_unused; | |
1924 | wire spare10_oai22_4x_unused; | |
1925 | wire spare10_inv_16x_unused; | |
1926 | wire spare10_nand2_16x_unused; | |
1927 | wire spare10_nor3_4x_unused; | |
1928 | wire spare10_nand2_8x_unused; | |
1929 | wire spare10_buf_16x_unused; | |
1930 | wire spare10_nor2_16x_unused; | |
1931 | wire spare10_inv_32x_unused; | |
1932 | ||
1933 | ||
1934 | input l1clk; | |
1935 | input scan_in; | |
1936 | input siclk; | |
1937 | input soclk; | |
1938 | output scan_out; | |
1939 | ||
1940 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1941 | .siclk(siclk), | |
1942 | .soclk(soclk), | |
1943 | .si(si_0), | |
1944 | .so(so_0), | |
1945 | .d(1'b0), | |
1946 | .q(spare0_flop_unused)); | |
1947 | assign si_0 = scan_in; | |
1948 | ||
1949 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1950 | .out(spare0_buf_32x_unused)); | |
1951 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1952 | .in1(1'b1), | |
1953 | .in2(1'b1), | |
1954 | .out(spare0_nand3_8x_unused)); | |
1955 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1956 | .out(spare0_inv_8x_unused)); | |
1957 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1958 | .in01(1'b1), | |
1959 | .in10(1'b1), | |
1960 | .in11(1'b1), | |
1961 | .out(spare0_aoi22_4x_unused)); | |
1962 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1963 | .out(spare0_buf_8x_unused)); | |
1964 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1965 | .in01(1'b1), | |
1966 | .in10(1'b1), | |
1967 | .in11(1'b1), | |
1968 | .out(spare0_oai22_4x_unused)); | |
1969 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1970 | .out(spare0_inv_16x_unused)); | |
1971 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1972 | .in1(1'b1), | |
1973 | .out(spare0_nand2_16x_unused)); | |
1974 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1975 | .in1(1'b0), | |
1976 | .in2(1'b0), | |
1977 | .out(spare0_nor3_4x_unused)); | |
1978 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1979 | .in1(1'b1), | |
1980 | .out(spare0_nand2_8x_unused)); | |
1981 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1982 | .out(spare0_buf_16x_unused)); | |
1983 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1984 | .in1(1'b0), | |
1985 | .out(spare0_nor2_16x_unused)); | |
1986 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1987 | .out(spare0_inv_32x_unused)); | |
1988 | ||
1989 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1990 | .siclk(siclk), | |
1991 | .soclk(soclk), | |
1992 | .si(si_1), | |
1993 | .so(so_1), | |
1994 | .d(1'b0), | |
1995 | .q(spare1_flop_unused)); | |
1996 | assign si_1 = so_0; | |
1997 | ||
1998 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1999 | .out(spare1_buf_32x_unused)); | |
2000 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
2001 | .in1(1'b1), | |
2002 | .in2(1'b1), | |
2003 | .out(spare1_nand3_8x_unused)); | |
2004 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
2005 | .out(spare1_inv_8x_unused)); | |
2006 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
2007 | .in01(1'b1), | |
2008 | .in10(1'b1), | |
2009 | .in11(1'b1), | |
2010 | .out(spare1_aoi22_4x_unused)); | |
2011 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
2012 | .out(spare1_buf_8x_unused)); | |
2013 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
2014 | .in01(1'b1), | |
2015 | .in10(1'b1), | |
2016 | .in11(1'b1), | |
2017 | .out(spare1_oai22_4x_unused)); | |
2018 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
2019 | .out(spare1_inv_16x_unused)); | |
2020 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
2021 | .in1(1'b1), | |
2022 | .out(spare1_nand2_16x_unused)); | |
2023 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
2024 | .in1(1'b0), | |
2025 | .in2(1'b0), | |
2026 | .out(spare1_nor3_4x_unused)); | |
2027 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
2028 | .in1(1'b1), | |
2029 | .out(spare1_nand2_8x_unused)); | |
2030 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
2031 | .out(spare1_buf_16x_unused)); | |
2032 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
2033 | .in1(1'b0), | |
2034 | .out(spare1_nor2_16x_unused)); | |
2035 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
2036 | .out(spare1_inv_32x_unused)); | |
2037 | ||
2038 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
2039 | .siclk(siclk), | |
2040 | .soclk(soclk), | |
2041 | .si(si_2), | |
2042 | .so(so_2), | |
2043 | .d(1'b0), | |
2044 | .q(spare2_flop_unused)); | |
2045 | assign si_2 = so_1; | |
2046 | ||
2047 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
2048 | .out(spare2_buf_32x_unused)); | |
2049 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
2050 | .in1(1'b1), | |
2051 | .in2(1'b1), | |
2052 | .out(spare2_nand3_8x_unused)); | |
2053 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
2054 | .out(spare2_inv_8x_unused)); | |
2055 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
2056 | .in01(1'b1), | |
2057 | .in10(1'b1), | |
2058 | .in11(1'b1), | |
2059 | .out(spare2_aoi22_4x_unused)); | |
2060 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
2061 | .out(spare2_buf_8x_unused)); | |
2062 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
2063 | .in01(1'b1), | |
2064 | .in10(1'b1), | |
2065 | .in11(1'b1), | |
2066 | .out(spare2_oai22_4x_unused)); | |
2067 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
2068 | .out(spare2_inv_16x_unused)); | |
2069 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
2070 | .in1(1'b1), | |
2071 | .out(spare2_nand2_16x_unused)); | |
2072 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
2073 | .in1(1'b0), | |
2074 | .in2(1'b0), | |
2075 | .out(spare2_nor3_4x_unused)); | |
2076 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
2077 | .in1(1'b1), | |
2078 | .out(spare2_nand2_8x_unused)); | |
2079 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
2080 | .out(spare2_buf_16x_unused)); | |
2081 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
2082 | .in1(1'b0), | |
2083 | .out(spare2_nor2_16x_unused)); | |
2084 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
2085 | .out(spare2_inv_32x_unused)); | |
2086 | ||
2087 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
2088 | .siclk(siclk), | |
2089 | .soclk(soclk), | |
2090 | .si(si_3), | |
2091 | .so(so_3), | |
2092 | .d(1'b0), | |
2093 | .q(spare3_flop_unused)); | |
2094 | assign si_3 = so_2; | |
2095 | ||
2096 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
2097 | .out(spare3_buf_32x_unused)); | |
2098 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
2099 | .in1(1'b1), | |
2100 | .in2(1'b1), | |
2101 | .out(spare3_nand3_8x_unused)); | |
2102 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
2103 | .out(spare3_inv_8x_unused)); | |
2104 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
2105 | .in01(1'b1), | |
2106 | .in10(1'b1), | |
2107 | .in11(1'b1), | |
2108 | .out(spare3_aoi22_4x_unused)); | |
2109 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
2110 | .out(spare3_buf_8x_unused)); | |
2111 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
2112 | .in01(1'b1), | |
2113 | .in10(1'b1), | |
2114 | .in11(1'b1), | |
2115 | .out(spare3_oai22_4x_unused)); | |
2116 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
2117 | .out(spare3_inv_16x_unused)); | |
2118 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
2119 | .in1(1'b1), | |
2120 | .out(spare3_nand2_16x_unused)); | |
2121 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
2122 | .in1(1'b0), | |
2123 | .in2(1'b0), | |
2124 | .out(spare3_nor3_4x_unused)); | |
2125 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
2126 | .in1(1'b1), | |
2127 | .out(spare3_nand2_8x_unused)); | |
2128 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
2129 | .out(spare3_buf_16x_unused)); | |
2130 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
2131 | .in1(1'b0), | |
2132 | .out(spare3_nor2_16x_unused)); | |
2133 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
2134 | .out(spare3_inv_32x_unused)); | |
2135 | ||
2136 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
2137 | .siclk(siclk), | |
2138 | .soclk(soclk), | |
2139 | .si(si_4), | |
2140 | .so(so_4), | |
2141 | .d(1'b0), | |
2142 | .q(spare4_flop_unused)); | |
2143 | assign si_4 = so_3; | |
2144 | ||
2145 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
2146 | .out(spare4_buf_32x_unused)); | |
2147 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
2148 | .in1(1'b1), | |
2149 | .in2(1'b1), | |
2150 | .out(spare4_nand3_8x_unused)); | |
2151 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
2152 | .out(spare4_inv_8x_unused)); | |
2153 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
2154 | .in01(1'b1), | |
2155 | .in10(1'b1), | |
2156 | .in11(1'b1), | |
2157 | .out(spare4_aoi22_4x_unused)); | |
2158 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
2159 | .out(spare4_buf_8x_unused)); | |
2160 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
2161 | .in01(1'b1), | |
2162 | .in10(1'b1), | |
2163 | .in11(1'b1), | |
2164 | .out(spare4_oai22_4x_unused)); | |
2165 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
2166 | .out(spare4_inv_16x_unused)); | |
2167 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
2168 | .in1(1'b1), | |
2169 | .out(spare4_nand2_16x_unused)); | |
2170 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
2171 | .in1(1'b0), | |
2172 | .in2(1'b0), | |
2173 | .out(spare4_nor3_4x_unused)); | |
2174 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
2175 | .in1(1'b1), | |
2176 | .out(spare4_nand2_8x_unused)); | |
2177 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
2178 | .out(spare4_buf_16x_unused)); | |
2179 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
2180 | .in1(1'b0), | |
2181 | .out(spare4_nor2_16x_unused)); | |
2182 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
2183 | .out(spare4_inv_32x_unused)); | |
2184 | ||
2185 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
2186 | .siclk(siclk), | |
2187 | .soclk(soclk), | |
2188 | .si(si_5), | |
2189 | .so(so_5), | |
2190 | .d(1'b0), | |
2191 | .q(spare5_flop_unused)); | |
2192 | assign si_5 = so_4; | |
2193 | ||
2194 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
2195 | .out(spare5_buf_32x_unused)); | |
2196 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
2197 | .in1(1'b1), | |
2198 | .in2(1'b1), | |
2199 | .out(spare5_nand3_8x_unused)); | |
2200 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
2201 | .out(spare5_inv_8x_unused)); | |
2202 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
2203 | .in01(1'b1), | |
2204 | .in10(1'b1), | |
2205 | .in11(1'b1), | |
2206 | .out(spare5_aoi22_4x_unused)); | |
2207 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
2208 | .out(spare5_buf_8x_unused)); | |
2209 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
2210 | .in01(1'b1), | |
2211 | .in10(1'b1), | |
2212 | .in11(1'b1), | |
2213 | .out(spare5_oai22_4x_unused)); | |
2214 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
2215 | .out(spare5_inv_16x_unused)); | |
2216 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
2217 | .in1(1'b1), | |
2218 | .out(spare5_nand2_16x_unused)); | |
2219 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
2220 | .in1(1'b0), | |
2221 | .in2(1'b0), | |
2222 | .out(spare5_nor3_4x_unused)); | |
2223 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
2224 | .in1(1'b1), | |
2225 | .out(spare5_nand2_8x_unused)); | |
2226 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
2227 | .out(spare5_buf_16x_unused)); | |
2228 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
2229 | .in1(1'b0), | |
2230 | .out(spare5_nor2_16x_unused)); | |
2231 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
2232 | .out(spare5_inv_32x_unused)); | |
2233 | ||
2234 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), | |
2235 | .siclk(siclk), | |
2236 | .soclk(soclk), | |
2237 | .si(si_6), | |
2238 | .so(so_6), | |
2239 | .d(1'b0), | |
2240 | .q(spare6_flop_unused)); | |
2241 | assign si_6 = so_5; | |
2242 | ||
2243 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
2244 | .out(spare6_buf_32x_unused)); | |
2245 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
2246 | .in1(1'b1), | |
2247 | .in2(1'b1), | |
2248 | .out(spare6_nand3_8x_unused)); | |
2249 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
2250 | .out(spare6_inv_8x_unused)); | |
2251 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
2252 | .in01(1'b1), | |
2253 | .in10(1'b1), | |
2254 | .in11(1'b1), | |
2255 | .out(spare6_aoi22_4x_unused)); | |
2256 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
2257 | .out(spare6_buf_8x_unused)); | |
2258 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
2259 | .in01(1'b1), | |
2260 | .in10(1'b1), | |
2261 | .in11(1'b1), | |
2262 | .out(spare6_oai22_4x_unused)); | |
2263 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
2264 | .out(spare6_inv_16x_unused)); | |
2265 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
2266 | .in1(1'b1), | |
2267 | .out(spare6_nand2_16x_unused)); | |
2268 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
2269 | .in1(1'b0), | |
2270 | .in2(1'b0), | |
2271 | .out(spare6_nor3_4x_unused)); | |
2272 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
2273 | .in1(1'b1), | |
2274 | .out(spare6_nand2_8x_unused)); | |
2275 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
2276 | .out(spare6_buf_16x_unused)); | |
2277 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
2278 | .in1(1'b0), | |
2279 | .out(spare6_nor2_16x_unused)); | |
2280 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
2281 | .out(spare6_inv_32x_unused)); | |
2282 | ||
2283 | cl_sc1_msff_8x spare7_flop (.l1clk(l1clk), | |
2284 | .siclk(siclk), | |
2285 | .soclk(soclk), | |
2286 | .si(si_7), | |
2287 | .so(so_7), | |
2288 | .d(1'b0), | |
2289 | .q(spare7_flop_unused)); | |
2290 | assign si_7 = so_6; | |
2291 | ||
2292 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
2293 | .out(spare7_buf_32x_unused)); | |
2294 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
2295 | .in1(1'b1), | |
2296 | .in2(1'b1), | |
2297 | .out(spare7_nand3_8x_unused)); | |
2298 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
2299 | .out(spare7_inv_8x_unused)); | |
2300 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
2301 | .in01(1'b1), | |
2302 | .in10(1'b1), | |
2303 | .in11(1'b1), | |
2304 | .out(spare7_aoi22_4x_unused)); | |
2305 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
2306 | .out(spare7_buf_8x_unused)); | |
2307 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
2308 | .in01(1'b1), | |
2309 | .in10(1'b1), | |
2310 | .in11(1'b1), | |
2311 | .out(spare7_oai22_4x_unused)); | |
2312 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
2313 | .out(spare7_inv_16x_unused)); | |
2314 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
2315 | .in1(1'b1), | |
2316 | .out(spare7_nand2_16x_unused)); | |
2317 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
2318 | .in1(1'b0), | |
2319 | .in2(1'b0), | |
2320 | .out(spare7_nor3_4x_unused)); | |
2321 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
2322 | .in1(1'b1), | |
2323 | .out(spare7_nand2_8x_unused)); | |
2324 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
2325 | .out(spare7_buf_16x_unused)); | |
2326 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
2327 | .in1(1'b0), | |
2328 | .out(spare7_nor2_16x_unused)); | |
2329 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
2330 | .out(spare7_inv_32x_unused)); | |
2331 | ||
2332 | cl_sc1_msff_8x spare8_flop (.l1clk(l1clk), | |
2333 | .siclk(siclk), | |
2334 | .soclk(soclk), | |
2335 | .si(si_8), | |
2336 | .so(so_8), | |
2337 | .d(1'b0), | |
2338 | .q(spare8_flop_unused)); | |
2339 | assign si_8 = so_7; | |
2340 | ||
2341 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
2342 | .out(spare8_buf_32x_unused)); | |
2343 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
2344 | .in1(1'b1), | |
2345 | .in2(1'b1), | |
2346 | .out(spare8_nand3_8x_unused)); | |
2347 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
2348 | .out(spare8_inv_8x_unused)); | |
2349 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
2350 | .in01(1'b1), | |
2351 | .in10(1'b1), | |
2352 | .in11(1'b1), | |
2353 | .out(spare8_aoi22_4x_unused)); | |
2354 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
2355 | .out(spare8_buf_8x_unused)); | |
2356 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
2357 | .in01(1'b1), | |
2358 | .in10(1'b1), | |
2359 | .in11(1'b1), | |
2360 | .out(spare8_oai22_4x_unused)); | |
2361 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
2362 | .out(spare8_inv_16x_unused)); | |
2363 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
2364 | .in1(1'b1), | |
2365 | .out(spare8_nand2_16x_unused)); | |
2366 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
2367 | .in1(1'b0), | |
2368 | .in2(1'b0), | |
2369 | .out(spare8_nor3_4x_unused)); | |
2370 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
2371 | .in1(1'b1), | |
2372 | .out(spare8_nand2_8x_unused)); | |
2373 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
2374 | .out(spare8_buf_16x_unused)); | |
2375 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
2376 | .in1(1'b0), | |
2377 | .out(spare8_nor2_16x_unused)); | |
2378 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
2379 | .out(spare8_inv_32x_unused)); | |
2380 | ||
2381 | cl_sc1_msff_8x spare9_flop (.l1clk(l1clk), | |
2382 | .siclk(siclk), | |
2383 | .soclk(soclk), | |
2384 | .si(si_9), | |
2385 | .so(so_9), | |
2386 | .d(1'b0), | |
2387 | .q(spare9_flop_unused)); | |
2388 | assign si_9 = so_8; | |
2389 | ||
2390 | cl_u1_buf_32x spare9_buf_32x (.in(1'b1), | |
2391 | .out(spare9_buf_32x_unused)); | |
2392 | cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1), | |
2393 | .in1(1'b1), | |
2394 | .in2(1'b1), | |
2395 | .out(spare9_nand3_8x_unused)); | |
2396 | cl_u1_inv_8x spare9_inv_8x (.in(1'b1), | |
2397 | .out(spare9_inv_8x_unused)); | |
2398 | cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1), | |
2399 | .in01(1'b1), | |
2400 | .in10(1'b1), | |
2401 | .in11(1'b1), | |
2402 | .out(spare9_aoi22_4x_unused)); | |
2403 | cl_u1_buf_8x spare9_buf_8x (.in(1'b1), | |
2404 | .out(spare9_buf_8x_unused)); | |
2405 | cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1), | |
2406 | .in01(1'b1), | |
2407 | .in10(1'b1), | |
2408 | .in11(1'b1), | |
2409 | .out(spare9_oai22_4x_unused)); | |
2410 | cl_u1_inv_16x spare9_inv_16x (.in(1'b1), | |
2411 | .out(spare9_inv_16x_unused)); | |
2412 | cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1), | |
2413 | .in1(1'b1), | |
2414 | .out(spare9_nand2_16x_unused)); | |
2415 | cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0), | |
2416 | .in1(1'b0), | |
2417 | .in2(1'b0), | |
2418 | .out(spare9_nor3_4x_unused)); | |
2419 | cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1), | |
2420 | .in1(1'b1), | |
2421 | .out(spare9_nand2_8x_unused)); | |
2422 | cl_u1_buf_16x spare9_buf_16x (.in(1'b1), | |
2423 | .out(spare9_buf_16x_unused)); | |
2424 | cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0), | |
2425 | .in1(1'b0), | |
2426 | .out(spare9_nor2_16x_unused)); | |
2427 | cl_u1_inv_32x spare9_inv_32x (.in(1'b1), | |
2428 | .out(spare9_inv_32x_unused)); | |
2429 | ||
2430 | cl_sc1_msff_8x spare10_flop (.l1clk(l1clk), | |
2431 | .siclk(siclk), | |
2432 | .soclk(soclk), | |
2433 | .si(si_10), | |
2434 | .so(so_10), | |
2435 | .d(1'b0), | |
2436 | .q(spare10_flop_unused)); | |
2437 | assign si_10 = so_9; | |
2438 | ||
2439 | cl_u1_buf_32x spare10_buf_32x (.in(1'b1), | |
2440 | .out(spare10_buf_32x_unused)); | |
2441 | cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1), | |
2442 | .in1(1'b1), | |
2443 | .in2(1'b1), | |
2444 | .out(spare10_nand3_8x_unused)); | |
2445 | cl_u1_inv_8x spare10_inv_8x (.in(1'b1), | |
2446 | .out(spare10_inv_8x_unused)); | |
2447 | cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1), | |
2448 | .in01(1'b1), | |
2449 | .in10(1'b1), | |
2450 | .in11(1'b1), | |
2451 | .out(spare10_aoi22_4x_unused)); | |
2452 | cl_u1_buf_8x spare10_buf_8x (.in(1'b1), | |
2453 | .out(spare10_buf_8x_unused)); | |
2454 | cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1), | |
2455 | .in01(1'b1), | |
2456 | .in10(1'b1), | |
2457 | .in11(1'b1), | |
2458 | .out(spare10_oai22_4x_unused)); | |
2459 | cl_u1_inv_16x spare10_inv_16x (.in(1'b1), | |
2460 | .out(spare10_inv_16x_unused)); | |
2461 | cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1), | |
2462 | .in1(1'b1), | |
2463 | .out(spare10_nand2_16x_unused)); | |
2464 | cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0), | |
2465 | .in1(1'b0), | |
2466 | .in2(1'b0), | |
2467 | .out(spare10_nor3_4x_unused)); | |
2468 | cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1), | |
2469 | .in1(1'b1), | |
2470 | .out(spare10_nand2_8x_unused)); | |
2471 | cl_u1_buf_16x spare10_buf_16x (.in(1'b1), | |
2472 | .out(spare10_buf_16x_unused)); | |
2473 | cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0), | |
2474 | .in1(1'b0), | |
2475 | .out(spare10_nor2_16x_unused)); | |
2476 | cl_u1_inv_32x spare10_inv_32x (.in(1'b1), | |
2477 | .out(spare10_inv_32x_unused)); | |
2478 | assign scan_out = so_10; | |
2479 | ||
2480 | ||
2481 | ||
2482 | endmodule | |
2483 |