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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_ucbbusin8_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ncu_ucbbusin8_ctl ( | |
36 | iol2clk, | |
37 | scan_in, | |
38 | scan_out, | |
39 | tcu_pce_ov, | |
40 | tcu_clk_stop, | |
41 | tcu_scan_en, | |
42 | tcu_aclk, | |
43 | tcu_bclk, | |
44 | vld, | |
45 | data, | |
46 | stall, | |
47 | indata_buf_vld, | |
48 | indata_buf, | |
49 | stall_a1) ; | |
50 | wire stall_d1_n; | |
51 | wire stall_d1; | |
52 | wire vld_d1_ff_scanin; | |
53 | wire vld_d1_ff_scanout; | |
54 | wire vld_d1; | |
55 | wire l1clk; | |
56 | wire rdy1; | |
57 | wire data_d1_ff_scanin; | |
58 | wire data_d1_ff_scanout; | |
59 | wire [7:0] data_d1; | |
60 | wire stall_ff_scanin; | |
61 | wire stall_ff_scanout; | |
62 | wire stall_d1_ff_scanin; | |
63 | wire stall_d1_ff_scanout; | |
64 | wire rdy0_ff_scanin; | |
65 | wire rdy0_ff_scanout; | |
66 | wire rdy0; | |
67 | wire rdy1_ff_scanin; | |
68 | wire rdy1_ff_scanout; | |
69 | wire skid_buf0_en; | |
70 | wire vld_buf0_ff_scanin; | |
71 | wire vld_buf0_ff_scanout; | |
72 | wire vld_buf0; | |
73 | wire data_buf0_ff_scanin; | |
74 | wire data_buf0_ff_scanout; | |
75 | wire [7:0] data_buf0; | |
76 | wire skid_buf1_en_ff_scanin; | |
77 | wire skid_buf1_en_ff_scanout; | |
78 | wire skid_buf1_en; | |
79 | wire vld_buf1_ff_scanin; | |
80 | wire vld_buf1_ff_scanout; | |
81 | wire vld_buf1; | |
82 | wire data_buf1_ff_scanin; | |
83 | wire data_buf1_ff_scanout; | |
84 | wire [7:0] data_buf1; | |
85 | wire skid_buf0_sel; | |
86 | wire skid_buf1_sel_ff_scanin; | |
87 | wire skid_buf1_sel_ff_scanout; | |
88 | wire skid_buf1_sel; | |
89 | wire vld_mux; | |
90 | wire [7:0] data_mux; | |
91 | wire [15:0] indata_vec_next; | |
92 | wire [15:0] indata_vec; | |
93 | wire stall_a1_n; | |
94 | wire indata_vec_ff_scanin; | |
95 | wire indata_vec_ff_scanout; | |
96 | wire [127:0] indata_buf_next; | |
97 | wire indata_buf_ff_scanin; | |
98 | wire indata_buf_ff_scanout; | |
99 | wire indata_vec0_d1_ff_scanin; | |
100 | wire indata_vec0_d1_ff_scanout; | |
101 | wire indata_vec0_d1; | |
102 | wire siclk; | |
103 | wire soclk; | |
104 | wire se; | |
105 | wire pce_ov; | |
106 | wire stop; | |
107 | ||
108 | ||
109 | //////////////////////////////////////////////////////////////////////// | |
110 | // Signal declarations | |
111 | //////////////////////////////////////////////////////////////////////// | |
112 | // Global interface | |
113 | input iol2clk; | |
114 | input scan_in; | |
115 | output scan_out; | |
116 | input tcu_pce_ov; | |
117 | input tcu_clk_stop; | |
118 | input tcu_scan_en; | |
119 | input tcu_aclk; | |
120 | input tcu_bclk; | |
121 | ||
122 | // UCB bus interface | |
123 | input vld; | |
124 | input [7 :0] data; | |
125 | output stall; | |
126 | ||
127 | ||
128 | // Local interface | |
129 | output indata_buf_vld; | |
130 | output [127:0] indata_buf; | |
131 | input stall_a1; | |
132 | ||
133 | ||
134 | // Internal signals | |
135 | ||
136 | ||
137 | ||
138 | //////////////////////////////////////////////////////////////////////// | |
139 | // Code starts here | |
140 | //////////////////////////////////////////////////////////////////////// | |
141 | /************************************************************ | |
142 | * UCB bus interface flops | |
143 | * This is to make signals going between IOB and UCB flop-to-flop | |
144 | * to improve timing. | |
145 | ************************************************************/ | |
146 | assign stall_d1_n = ~stall_d1; | |
147 | ||
148 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_d1_ff | |
149 | ( | |
150 | .scan_in(vld_d1_ff_scanin), | |
151 | .scan_out(vld_d1_ff_scanout), | |
152 | .dout (vld_d1), | |
153 | .l1clk (l1clk), | |
154 | .en (stall_d1_n&rdy1), | |
155 | .din (vld), | |
156 | .siclk(siclk), | |
157 | .soclk(soclk) | |
158 | ); | |
159 | ||
160 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_d1_ff | |
161 | ( | |
162 | .scan_in(data_d1_ff_scanin), | |
163 | .scan_out(data_d1_ff_scanout), | |
164 | .dout (data_d1[7 :0]), | |
165 | .l1clk (l1clk), | |
166 | .en (stall_d1_n), | |
167 | .din (data[7 :0]), | |
168 | .siclk(siclk), | |
169 | .soclk(soclk) | |
170 | ); | |
171 | ||
172 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 stall_ff | |
173 | ( | |
174 | .scan_in(stall_ff_scanin), | |
175 | .scan_out(stall_ff_scanout), | |
176 | .dout (stall), | |
177 | .l1clk (l1clk), | |
178 | .din (stall_a1), | |
179 | .siclk(siclk), | |
180 | .soclk(soclk) | |
181 | ); | |
182 | ||
183 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 stall_d1_ff | |
184 | ( | |
185 | .scan_in(stall_d1_ff_scanin), | |
186 | .scan_out(stall_d1_ff_scanout), | |
187 | .dout (stall_d1), | |
188 | .l1clk (l1clk), | |
189 | .din (stall), | |
190 | .siclk(siclk), | |
191 | .soclk(soclk) | |
192 | ); | |
193 | ||
194 | ||
195 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 rdy0_ff | |
196 | ( | |
197 | .scan_in(rdy0_ff_scanin), | |
198 | .scan_out(rdy0_ff_scanout), | |
199 | .dout (rdy0), | |
200 | .l1clk (l1clk), | |
201 | .din (1'b1), | |
202 | .siclk(siclk), | |
203 | .soclk(soclk) | |
204 | ); | |
205 | ||
206 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 rdy1_ff | |
207 | ( | |
208 | .scan_in(rdy1_ff_scanin), | |
209 | .scan_out(rdy1_ff_scanout), | |
210 | .dout (rdy1), | |
211 | .l1clk (l1clk), | |
212 | .din (rdy0), | |
213 | .siclk(siclk), | |
214 | .soclk(soclk) | |
215 | ); | |
216 | ||
217 | /************************************************************ | |
218 | * Skid buffer | |
219 | * We need a two deep skid buffer to handle stalling. | |
220 | ************************************************************/ | |
221 | // Assertion: stall has to be deasserted for more than 1 cycle | |
222 | // ie time between two separate stalls has to be | |
223 | // at least two cycles. Otherwise, contents from | |
224 | // skid buffer will be lost. | |
225 | ||
226 | // Buffer 0 | |
227 | assign skid_buf0_en = stall_a1 & ~stall; | |
228 | ||
229 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_buf0_ff | |
230 | ( | |
231 | .scan_in(vld_buf0_ff_scanin), | |
232 | .scan_out(vld_buf0_ff_scanout), | |
233 | .dout (vld_buf0), | |
234 | .l1clk (l1clk), | |
235 | .en (skid_buf0_en), | |
236 | .din (vld_d1), | |
237 | .siclk(siclk), | |
238 | .soclk(soclk) | |
239 | ); | |
240 | ||
241 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_buf0_ff | |
242 | ( | |
243 | .scan_in(data_buf0_ff_scanin), | |
244 | .scan_out(data_buf0_ff_scanout), | |
245 | .dout (data_buf0[7 :0]), | |
246 | .l1clk (l1clk), | |
247 | .en (skid_buf0_en), | |
248 | .din (data_d1[7 :0]), | |
249 | .siclk(siclk), | |
250 | .soclk(soclk) | |
251 | ); | |
252 | ||
253 | // Buffer 1 | |
254 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 skid_buf1_en_ff | |
255 | ( | |
256 | .scan_in(skid_buf1_en_ff_scanin), | |
257 | .scan_out(skid_buf1_en_ff_scanout), | |
258 | .dout (skid_buf1_en), | |
259 | .l1clk (l1clk), | |
260 | .din (skid_buf0_en), | |
261 | .siclk(siclk), | |
262 | .soclk(soclk) | |
263 | ); | |
264 | ||
265 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_buf1_ff | |
266 | ( | |
267 | .scan_in(vld_buf1_ff_scanin), | |
268 | .scan_out(vld_buf1_ff_scanout), | |
269 | .dout (vld_buf1), | |
270 | .l1clk (l1clk), | |
271 | .en (skid_buf1_en), | |
272 | .din (vld_d1), | |
273 | .siclk(siclk), | |
274 | .soclk(soclk) | |
275 | ); | |
276 | ||
277 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_buf1_ff | |
278 | ( | |
279 | .scan_in(data_buf1_ff_scanin), | |
280 | .scan_out(data_buf1_ff_scanout), | |
281 | .dout (data_buf1[7 :0]), | |
282 | .l1clk (l1clk), | |
283 | .en (skid_buf1_en), | |
284 | .din (data_d1[7 :0]), | |
285 | .siclk(siclk), | |
286 | .soclk(soclk) | |
287 | ); | |
288 | ||
289 | ||
290 | /************************************************************ | |
291 | * Mux between skid buffer and interface flop | |
292 | ************************************************************/ | |
293 | // Assertion: stall has to be deasserted for more than 1 cycle | |
294 | // ie time between two separate stalls has to be | |
295 | // at least two cycles. Otherwise, contents from | |
296 | // skid buffer will be lost. | |
297 | ||
298 | assign skid_buf0_sel = ~stall_a1 & stall; | |
299 | ||
300 | ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 skid_buf1_sel_ff | |
301 | ( | |
302 | .scan_in(skid_buf1_sel_ff_scanin), | |
303 | .scan_out(skid_buf1_sel_ff_scanout), | |
304 | .dout (skid_buf1_sel), | |
305 | .l1clk (l1clk), | |
306 | .din (skid_buf0_sel), | |
307 | .siclk(siclk), | |
308 | .soclk(soclk) | |
309 | ); | |
310 | ||
311 | assign vld_mux = skid_buf0_sel ? vld_buf0 : | |
312 | skid_buf1_sel ? vld_buf1 : | |
313 | vld_d1; | |
314 | ||
315 | assign data_mux[7 :0] = skid_buf0_sel ? data_buf0[7 :0] : | |
316 | skid_buf1_sel ? data_buf1[7 :0] : | |
317 | data_d1[7 :0]; | |
318 | ||
319 | ||
320 | /************************************************************ | |
321 | * Assemble inbound data | |
322 | ************************************************************/ | |
323 | // valid vector | |
324 | assign indata_vec_next[15:0] = {vld_mux, indata_vec[15 :1]}; | |
325 | ||
326 | assign stall_a1_n = ~stall_a1; | |
327 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_16 indata_vec_ff | |
328 | ( | |
329 | .scan_in(indata_vec_ff_scanin), | |
330 | .scan_out(indata_vec_ff_scanout), | |
331 | .dout (indata_vec[15 :0]), | |
332 | .l1clk (l1clk), | |
333 | .en (stall_a1_n), | |
334 | .din (indata_vec_next[15 :0]), | |
335 | .siclk(siclk), | |
336 | .soclk(soclk) | |
337 | ); | |
338 | ||
339 | // data buffer | |
340 | assign indata_buf_next[127:0] = {data_mux[7 :0], indata_buf[127:8 ]}; | |
341 | ||
342 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_128 indata_buf_ff | |
343 | ( | |
344 | .scan_in(indata_buf_ff_scanin), | |
345 | .scan_out(indata_buf_ff_scanout), | |
346 | .dout (indata_buf[127:0]), | |
347 | .l1clk (l1clk), | |
348 | .en (stall_a1_n), | |
349 | .din (indata_buf_next[127:0]), | |
350 | .siclk(siclk), | |
351 | .soclk(soclk) | |
352 | ); | |
353 | ||
354 | // detect a new packet | |
355 | ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 indata_vec0_d1_ff | |
356 | ( | |
357 | .scan_in(indata_vec0_d1_ff_scanin), | |
358 | .scan_out(indata_vec0_d1_ff_scanout), | |
359 | .dout (indata_vec0_d1), | |
360 | .l1clk (l1clk), | |
361 | .en (stall_a1_n), | |
362 | .din (indata_vec[0]), | |
363 | .siclk(siclk), | |
364 | .soclk(soclk) | |
365 | ); | |
366 | ||
367 | assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1; | |
368 | ||
369 | ||
370 | ||
371 | /**** adding clock header ****/ | |
372 | ncu_ucbbusin8_ctl_l1clkhdr_ctl_macro clkgen ( | |
373 | .l2clk (iol2clk), | |
374 | .l1en (1'b1), | |
375 | .l1clk (l1clk), | |
376 | .pce_ov(pce_ov), | |
377 | .stop(stop), | |
378 | .se(se) | |
379 | ); | |
380 | ||
381 | /*** building tcu port ***/ | |
382 | assign siclk = tcu_aclk; | |
383 | assign soclk = tcu_bclk; | |
384 | assign se = tcu_scan_en; | |
385 | assign pce_ov = tcu_pce_ov; | |
386 | assign stop = tcu_clk_stop; | |
387 | ||
388 | // fixscan start: | |
389 | assign vld_d1_ff_scanin = scan_in ; | |
390 | assign data_d1_ff_scanin = vld_d1_ff_scanout ; | |
391 | assign stall_ff_scanin = data_d1_ff_scanout ; | |
392 | assign stall_d1_ff_scanin = stall_ff_scanout ; | |
393 | assign rdy0_ff_scanin = stall_d1_ff_scanout ; | |
394 | assign rdy1_ff_scanin = rdy0_ff_scanout ; | |
395 | assign vld_buf0_ff_scanin = rdy1_ff_scanout ; | |
396 | assign data_buf0_ff_scanin = vld_buf0_ff_scanout ; | |
397 | assign skid_buf1_en_ff_scanin = data_buf0_ff_scanout ; | |
398 | assign vld_buf1_ff_scanin = skid_buf1_en_ff_scanout ; | |
399 | assign data_buf1_ff_scanin = vld_buf1_ff_scanout ; | |
400 | assign skid_buf1_sel_ff_scanin = data_buf1_ff_scanout ; | |
401 | assign indata_vec_ff_scanin = skid_buf1_sel_ff_scanout ; | |
402 | assign indata_buf_ff_scanin = indata_vec_ff_scanout ; | |
403 | assign indata_vec0_d1_ff_scanin = indata_buf_ff_scanout ; | |
404 | assign scan_out = indata_vec0_d1_ff_scanout; | |
405 | // fixscan end: | |
406 | endmodule // ucb_bus_in | |
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | // any PARAMS parms go into naming of macro | |
414 | ||
415 | module ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 ( | |
416 | din, | |
417 | en, | |
418 | l1clk, | |
419 | scan_in, | |
420 | siclk, | |
421 | soclk, | |
422 | dout, | |
423 | scan_out); | |
424 | wire [0:0] fdin; | |
425 | ||
426 | input [0:0] din; | |
427 | input en; | |
428 | input l1clk; | |
429 | input scan_in; | |
430 | ||
431 | ||
432 | input siclk; | |
433 | input soclk; | |
434 | ||
435 | output [0:0] dout; | |
436 | output scan_out; | |
437 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
438 | ||
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | dff #(1) d0_0 ( | |
445 | .l1clk(l1clk), | |
446 | .siclk(siclk), | |
447 | .soclk(soclk), | |
448 | .d(fdin[0:0]), | |
449 | .si(scan_in), | |
450 | .so(scan_out), | |
451 | .q(dout[0:0]) | |
452 | ); | |
453 | ||
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | endmodule | |
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | // any PARAMS parms go into naming of macro | |
480 | ||
481 | module ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 ( | |
482 | din, | |
483 | en, | |
484 | l1clk, | |
485 | scan_in, | |
486 | siclk, | |
487 | soclk, | |
488 | dout, | |
489 | scan_out); | |
490 | wire [7:0] fdin; | |
491 | wire [6:0] so; | |
492 | ||
493 | input [7:0] din; | |
494 | input en; | |
495 | input l1clk; | |
496 | input scan_in; | |
497 | ||
498 | ||
499 | input siclk; | |
500 | input soclk; | |
501 | ||
502 | output [7:0] dout; | |
503 | output scan_out; | |
504 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | dff #(8) d0_0 ( | |
512 | .l1clk(l1clk), | |
513 | .siclk(siclk), | |
514 | .soclk(soclk), | |
515 | .d(fdin[7:0]), | |
516 | .si({scan_in,so[6:0]}), | |
517 | .so({so[6:0],scan_out}), | |
518 | .q(dout[7:0]) | |
519 | ); | |
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | endmodule | |
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | // any PARAMS parms go into naming of macro | |
547 | ||
548 | module ncu_ucbbusin8_ctl_msff_ctl_macro__width_1 ( | |
549 | din, | |
550 | l1clk, | |
551 | scan_in, | |
552 | siclk, | |
553 | soclk, | |
554 | dout, | |
555 | scan_out); | |
556 | wire [0:0] fdin; | |
557 | ||
558 | input [0:0] din; | |
559 | input l1clk; | |
560 | input scan_in; | |
561 | ||
562 | ||
563 | input siclk; | |
564 | input soclk; | |
565 | ||
566 | output [0:0] dout; | |
567 | output scan_out; | |
568 | assign fdin[0:0] = din[0:0]; | |
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | dff #(1) d0_0 ( | |
576 | .l1clk(l1clk), | |
577 | .siclk(siclk), | |
578 | .soclk(soclk), | |
579 | .d(fdin[0:0]), | |
580 | .si(scan_in), | |
581 | .so(scan_out), | |
582 | .q(dout[0:0]) | |
583 | ); | |
584 | ||
585 | ||
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | endmodule | |
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | // any PARAMS parms go into naming of macro | |
611 | ||
612 | module ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_16 ( | |
613 | din, | |
614 | en, | |
615 | l1clk, | |
616 | scan_in, | |
617 | siclk, | |
618 | soclk, | |
619 | dout, | |
620 | scan_out); | |
621 | wire [15:0] fdin; | |
622 | wire [14:0] so; | |
623 | ||
624 | input [15:0] din; | |
625 | input en; | |
626 | input l1clk; | |
627 | input scan_in; | |
628 | ||
629 | ||
630 | input siclk; | |
631 | input soclk; | |
632 | ||
633 | output [15:0] dout; | |
634 | output scan_out; | |
635 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | dff #(16) d0_0 ( | |
643 | .l1clk(l1clk), | |
644 | .siclk(siclk), | |
645 | .soclk(soclk), | |
646 | .d(fdin[15:0]), | |
647 | .si({scan_in,so[14:0]}), | |
648 | .so({so[14:0],scan_out}), | |
649 | .q(dout[15:0]) | |
650 | ); | |
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | endmodule | |
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | // any PARAMS parms go into naming of macro | |
678 | ||
679 | module ncu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_128 ( | |
680 | din, | |
681 | en, | |
682 | l1clk, | |
683 | scan_in, | |
684 | siclk, | |
685 | soclk, | |
686 | dout, | |
687 | scan_out); | |
688 | wire [127:0] fdin; | |
689 | wire [126:0] so; | |
690 | ||
691 | input [127:0] din; | |
692 | input en; | |
693 | input l1clk; | |
694 | input scan_in; | |
695 | ||
696 | ||
697 | input siclk; | |
698 | input soclk; | |
699 | ||
700 | output [127:0] dout; | |
701 | output scan_out; | |
702 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | dff #(128) d0_0 ( | |
710 | .l1clk(l1clk), | |
711 | .siclk(siclk), | |
712 | .soclk(soclk), | |
713 | .d(fdin[127:0]), | |
714 | .si({scan_in,so[126:0]}), | |
715 | .so({so[126:0],scan_out}), | |
716 | .q(dout[127:0]) | |
717 | ); | |
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | endmodule | |
731 | ||
732 | ||
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | // any PARAMS parms go into naming of macro | |
745 | ||
746 | module ncu_ucbbusin8_ctl_l1clkhdr_ctl_macro ( | |
747 | l2clk, | |
748 | l1en, | |
749 | pce_ov, | |
750 | stop, | |
751 | se, | |
752 | l1clk); | |
753 | ||
754 | ||
755 | input l2clk; | |
756 | input l1en; | |
757 | input pce_ov; | |
758 | input stop; | |
759 | input se; | |
760 | output l1clk; | |
761 | ||
762 | ||
763 | ||
764 | ||
765 | ||
766 | cl_sc1_l1hdr_8x c_0 ( | |
767 | ||
768 | ||
769 | .l2clk(l2clk), | |
770 | .pce(l1en), | |
771 | .l1clk(l1clk), | |
772 | .se(se), | |
773 | .pce_ov(pce_ov), | |
774 | .stop(stop) | |
775 | ); | |
776 | ||
777 | ||
778 | ||
779 | endmodule | |
780 | ||
781 | ||
782 | ||
783 | ||
784 | ||
785 | ||
786 | ||
787 |