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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: MDIO2P_IO.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | //////////////////////////////////////////////////////////////////////////////// | |
36 | // | |
37 | // Copyright (c) 2003 Texas Instruments, Inc. | |
38 | // All rights reserved | |
39 | // | |
40 | // This is an unpublished work created in the year stated above. | |
41 | // Texas Instruments owns all rights in and to the work and intends to | |
42 | // maintain it and protect it as unpublished copyright. In the event | |
43 | // of either inadvertant or deliberate publication, the above stated | |
44 | // date shall be treated as the year of first publication. In the event | |
45 | // of such publication, Texas Instruments intends to enforce its rights | |
46 | // in the work under the copyright laws as a published work. | |
47 | // | |
48 | // These commodities are under U.S. Government distribution license | |
49 | // control. As such, they are not be re-exported without prior approval | |
50 | // from the U.S. Department of Commerce. | |
51 | // | |
52 | //////////////////////////////////////////////////////////////////////////////// | |
53 | ||
54 | //////////////////////////////////////////////////////////////////////////////// | |
55 | // | |
56 | // FUNCTION: MDIO Clock muxing and CFG decode | |
57 | // COMMENTS: | |
58 | // VERSION: #VERSION# | |
59 | // DATE: #DATE# | |
60 | // | |
61 | //////////////////////////////////////////////////////////////////////////////// | |
62 | ||
63 | `timescale 1ns / 1ps | |
64 | ||
65 | module MDIO2P_IO | |
66 | ( | |
67 | tcu_clk_stop, | |
68 | tcu_scan_mode, | |
69 | ||
70 | RESET, | |
71 | MDCLK, | |
72 | SCANEN, | |
73 | SCANCLK, | |
74 | CFG, | |
75 | IO_MDCLK, | |
76 | IO_RESET, | |
77 | IO_CLAUSE45, | |
78 | IO_PRTID, | |
79 | IO_DEVID, | |
80 | IO_BASEAD, | |
81 | IO_ACRAD, | |
82 | IO_IPRAD | |
83 | ); | |
84 | ||
85 | ||
86 | //////////////////////////////////////////////////////////////////////////////// | |
87 | // | |
88 | // Port Declarations | |
89 | // | |
90 | //////////////////////////////////////////////////////////////////////////////// | |
91 | ||
92 | input RESET; // Global reset | |
93 | ||
94 | // Scan clock control | |
95 | input tcu_clk_stop; // For N2 DFT clock control | |
96 | input tcu_scan_mode; // For N2 DFT clock control | |
97 | ||
98 | // MDIO Interface | |
99 | input MDCLK; // Clock | |
100 | ||
101 | // Scan Interface | |
102 | input SCANEN; // Bypass MDIO2P clocks for scan | |
103 | input SCANCLK; // Scan clock source | |
104 | ||
105 | // Configuration Interface | |
106 | input[15:0] CFG; // Configuration | |
107 | output IO_CLAUSE45; // Clause45 | |
108 | output[4:0] IO_PRTID; // Port address ID | |
109 | output[4:0] IO_DEVID; // Device address ID | |
110 | output[4:0] IO_BASEAD; // Base address | |
111 | output[3:0] IO_ACRAD; // AddrCtl register address | |
112 | output[3:0] IO_IPRAD; // Indirect port register address | |
113 | ||
114 | // Internal Connections | |
115 | output IO_MDCLK; // Internal clock, after DFT muxing | |
116 | output IO_RESET; // Internal reset, after DFT override | |
117 | ||
118 | ||
119 | //////////////////////////////////////////////////////////////////////////////// | |
120 | // | |
121 | // Clock muxing and reset control for test | |
122 | // | |
123 | //////////////////////////////////////////////////////////////////////////////// | |
124 | wire IO_MDCLK_mux; | |
125 | wire tcu_clk_stop_sync; | |
126 | wire tcu_clk_stop_sync_mux; | |
127 | ||
128 | cl_a1_clk_mux2_8x hedwig_mdio2p_io_mux ( | |
129 | .in0(SCANCLK), | |
130 | .in1(MDCLK), | |
131 | .sel0(tcu_scan_mode), | |
132 | .out(IO_MDCLK_mux)); | |
133 | ||
134 | // assign IO_MDCLK_mux = tcu_scan_mode ? SCANCLK : MDCLK; | |
135 | ||
136 | assign IO_RESET = ~SCANEN & RESET; | |
137 | ||
138 | SYNC_CELL SYNC_CELL_mdio (.D(tcu_clk_stop),.CP(IO_MDCLK_mux),.Q(tcu_clk_stop_sync)); | |
139 | ||
140 | assign tcu_clk_stop_sync_mux = tcu_scan_mode ? tcu_clk_stop : tcu_clk_stop_sync; | |
141 | ||
142 | cl_a1_l1hdr_12x hedwig_mdio2p_io_l1 ( | |
143 | .l2clk(IO_MDCLK_mux), | |
144 | .se(SCANEN), | |
145 | .pce(1'b1), | |
146 | .pce_ov(1'b0), | |
147 | .stop(tcu_clk_stop_sync_mux), | |
148 | .l1clk(IO_MDCLK)); | |
149 | ||
150 | ||
151 | //////////////////////////////////////////////////////////////////////////////// | |
152 | // | |
153 | // General decode | |
154 | // - CFG bus fields are extracted and named for clarity | |
155 | // - vsmmdbase identifies LS 16 register locations, which must be readable if | |
156 | // mapped to DEVID 30 or 31 (Clause 45 only). | |
157 | // | |
158 | //////////////////////////////////////////////////////////////////////////////// | |
159 | ||
160 | assign IO_CLAUSE45 = CFG[15]; | |
161 | assign IO_PRTID = CFG[14:10]; | |
162 | assign IO_DEVID = CFG[9:5]; | |
163 | assign IO_BASEAD = CFG[4:0]; | |
164 | assign IO_ACRAD = CFG[8:5]; | |
165 | assign IO_IPRAD = CFG[3:0]; | |
166 | ||
167 | endmodule |