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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / P2REGS.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: P2REGS.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35////////////////////////////////////////////////////////////////////////////////
36//
37// Copyright (c) 2004 Texas Instruments, Inc.
38// All rights reserved
39//
40// This is an unpublished work created in the year stated above.
41// Texas Instruments owns all rights in and to the work and intends to
42// maintain it and protect it as unpublished copyright. In the event
43// of either inadvertant or deliberate publication, the above stated
44// date shall be treated as the year of first publication. In the event
45// of such publication, Texas Instruments intends to enforce its rights
46// in the work under the copyright laws as a published work.
47//
48// These commodities are under U.S. Government distribution license
49// control. As such, they are not be re-exported without prior approval
50// from the U.S. Department of Commerce.
51//
52////////////////////////////////////////////////////////////////////////////////
53////////////////////////////////////////////////////////////////////////////////
54// ***********************************************************************
55//
56// File: P2REGS.v
57//
58// Author: Andre Szczepanek
59//
60// Purpose: Top level of Register block
61//
62// Contains MDIO Register instantiations and associated R/W decode
63//
64//
65// Date Author Changes
66// ------- ------ -----------------------------------------------------
67// 21May04 Andre Created
68// 02Feb05 Andre Add Clock inputs to allow asynchronous sticky bits
69//
70// ***********************************************************************
71////////////////////////////////////////////////////////////////////////////////
72//
73// ____ ____ ___
74// MDCLK ___/ \____/ \____/
75// _________
76// PW XXXXX_________/ XXX
77// _________ _________
78// PA XXXXX____A1___X____A2___XXX
79// _________
80// PR XXXXX_________/ XXX
81// _________
82// WRITE_DATA XXXXXXXXXXXXXXX____Q1___XXX
83// ___
84// READ_DATA XXXXXXXXXXXXXXXXXXXXX<D2_>X
85//
86////////////////////////////////////////////////////////////////////////////////
87
88
89////////////////////////////////////////////////////////////////////////////////
90//
91// Select Macro configuration through include files
92//
93////////////////////////////////////////////////////////////////////////////////
94
95`include "make_b8_macro.v"
96
97
98`timescale 1ns / 1ps
99
100module P2REGS
101 (
102
103 RESET,
104 IO_MDCLK, // cc 093005 consolidated clock domains to single l1 header
105 SCANEN,
106// SCANCLK, // cc 093005 scan clock not needed
107 WRITE_DATA,
108 PW,
109 PR,
110 PA,
111 READ_DATA,
112
113`ifdef MAKE_REGS_TX_0
114 CFGTX0,
115 STSTX0,
116 TXBCLKIN0,
117`endif
118`ifdef MAKE_REGS_TX_1
119 CFGTX1,
120 STSTX1,
121 TXBCLKIN1,
122`endif
123`ifdef MAKE_REGS_TX_2
124 CFGTX2,
125 STSTX2,
126 TXBCLKIN2,
127`endif
128`ifdef MAKE_REGS_TX_3
129 CFGTX3,
130 STSTX3,
131 TXBCLKIN3,
132`endif
133`ifdef MAKE_REGS_TX_4
134 CFGTX4,
135 STSTX4,
136 TXBCLKIN4,
137`endif
138`ifdef MAKE_REGS_TX_5
139 CFGTX5,
140 STSTX5,
141 TXBCLKIN5,
142`endif
143`ifdef MAKE_REGS_TX_6
144 CFGTX6,
145 STSTX6,
146 TXBCLKIN6,
147`endif
148`ifdef MAKE_REGS_TX_7
149 CFGTX7,
150 STSTX7,
151 TXBCLKIN7,
152`endif
153`ifdef MAKE_REGS_RX_0
154 CFGRX0,
155 STSRX0,
156 RXBCLKIN0,
157`endif
158`ifdef MAKE_REGS_RX_1
159 CFGRX1,
160 STSRX1,
161 RXBCLKIN1,
162`endif
163`ifdef MAKE_REGS_RX_2
164 CFGRX2,
165 STSRX2,
166 RXBCLKIN2,
167`endif
168`ifdef MAKE_REGS_RX_3
169 CFGRX3,
170 STSRX3,
171 RXBCLKIN3,
172`endif
173`ifdef MAKE_REGS_RX_4
174 CFGRX4,
175 STSRX4,
176 RXBCLKIN4,
177`endif
178`ifdef MAKE_REGS_RX_5
179 CFGRX5,
180 STSRX5,
181 RXBCLKIN5,
182`endif
183`ifdef MAKE_REGS_RX_6
184 CFGRX6,
185 STSRX6,
186 RXBCLKIN6,
187`endif
188`ifdef MAKE_REGS_RX_7
189 CFGRX7,
190 STSRX7,
191 RXBCLKIN7,
192`endif
193 TESTCFG,
194 CFGPLL,
195 STSPLL
196 );
197
198////////////////////////////////////////////////////////////////////////////////
199//
200// Parameters
201//
202////////////////////////////////////////////////////////////////////////////////
203
204parameter pl_cw=12; // (default) PLL config bus width
205parameter pl_cr=32'h0000_0000; // (default) PLL config reg reset value
206parameter pl_ci=32'h0000_0f3f; // (default) PLL config reg bit instantiations
207
208parameter pl_sw=4; // (default) PLL status bus width
209parameter pl_sr=32'h0000_0000; // (default) PLL status reg reset value
210parameter pl_si=32'h0000_0001; // (default) PLL status reg bit instantiations
211parameter pl_ss=32'h0000_0000; // (default) PLL status sticky reg bit locations
212
213parameter te_cw=16; // (default) TEST config bus width
214parameter te_cr=32'h0000_0000; // (default) TEST config reg reset value
215parameter te_ci=32'h0000_7fff; // (default) TEST config reg bit instantiations
216
217parameter tx_cw=24; // (default) TX config bus width
218parameter tx_cr=32'h0000_0000; // (default) TX config reg reset value
219parameter tx_ci=32'h0073_ffff; // (default) TX config reg bit instantiations
220
221parameter tx_sw=4; // (default) TX status bus width
222parameter tx_sr=32'h0000_0000; // (default) TX status reg reset value
223parameter tx_si=32'h0000_0003; // (default) TX status reg bit instantiations
224parameter tx_ss=32'h0000_0001; // (default) TX status sticky reg bit locations
225
226parameter rx_cw=28; // (default) RX config bus width
227parameter rx_cr=32'h0000_0000; // (default) RX config reg reset value
228parameter rx_ci=32'h033f_f7ff; // (default) RX config reg bit instantiations
229
230parameter rx_sw=12; // (default) RX status bus width
231parameter rx_sr=32'h0000_0000; // (default) RX status reg reset value
232parameter rx_si=32'h0000_0339; // (default) RX status reg bit instantiations
233parameter rx_ss=32'h0000_0001; // (default) RX status sticky reg bit locations
234
235//
236// Note : The top ten bits of indirect address are {1'b1,BASEAD}
237//
238parameter pl_ra=10'h000; // (default) PLL register block base address
239parameter te_ra=10'h004; // (default) TEST register block base address
240parameter t0_ra=10'h100; // (default) TX_0 register block base address
241parameter t1_ra=10'h104; // (default) TX_1 register block base address
242parameter t2_ra=10'h108; // (default) TX_2 register block base address
243parameter t3_ra=10'h10C; // (default) TX_3 register block base address
244parameter t4_ra=10'h110; // (default) TX_4 register block base address
245parameter t5_ra=10'h114; // (default) TX_5 register block base address
246parameter t6_ra=10'h118; // (default) TX_6 register block base address
247parameter t7_ra=10'h11C; // (default) TX_7 register block base address
248parameter r0_ra=10'h120; // (default) RX_0 register block base address
249parameter r1_ra=10'h124; // (default) RX_1 register block base address
250parameter r2_ra=10'h128; // (default) RX_2 register block base address
251parameter r3_ra=10'h12C; // (default) RX_3 register block base address
252parameter r4_ra=10'h130; // (default) RX_4 register block base address
253parameter r5_ra=10'h134; // (default) RX_5 register block base address
254parameter r6_ra=10'h138; // (default) RX_6 register block base address
255parameter r7_ra=10'h13C; // (default) RX_7 register block base address
256
257
258////////////////////////////////////////////////////////////////////////////////
259//
260// Port Declarations
261//
262////////////////////////////////////////////////////////////////////////////////
263
264 // MDIO Interface
265 input RESET; // Global reset
266 input IO_MDCLK; // Clock
267
268 // Scan Interface
269 input SCANEN; // Bypass P2REGS clocks for scan
270// input SCANCLK; // Scan clock source
271
272 // Parallel Interface
273 input PW; // Write enable
274 input PR; // Read indicator
275 input [9:0] PA; // Address
276 input [15:0] WRITE_DATA; // Data in
277 output [15:0] READ_DATA; // Data out
278
279
280 // Interface to Macro
281
282`ifdef MAKE_REGS_TX_0
283output [tx_cw-1:0] CFGTX0;
284input [tx_sw-1:0] STSTX0;
285input TXBCLKIN0;
286`endif
287`ifdef MAKE_REGS_TX_1
288output [tx_cw-1:0] CFGTX1;
289input [tx_sw-1:0] STSTX1;
290input TXBCLKIN1;
291`endif
292`ifdef MAKE_REGS_TX_2
293output [tx_cw-1:0] CFGTX2;
294input [tx_sw-1:0] STSTX2;
295input TXBCLKIN2;
296`endif
297`ifdef MAKE_REGS_TX_3
298output [tx_cw-1:0] CFGTX3;
299input [tx_sw-1:0] STSTX3;
300input TXBCLKIN3;
301`endif
302`ifdef MAKE_REGS_TX_4
303output [tx_cw-1:0] CFGTX4;
304input [tx_sw-1:0] STSTX4;
305input TXBCLKIN4;
306`endif
307`ifdef MAKE_REGS_TX_5
308output [tx_cw-1:0] CFGTX5;
309input [tx_sw-1:0] STSTX5;
310input TXBCLKIN5;
311`endif
312`ifdef MAKE_REGS_TX_6
313output [tx_cw-1:0] CFGTX6;
314input [tx_sw-1:0] STSTX6;
315input TXBCLKIN6;
316`endif
317`ifdef MAKE_REGS_TX_7
318output [tx_cw-1:0] CFGTX7;
319input [tx_sw-1:0] STSTX7;
320input TXBCLKIN7;
321`endif
322`ifdef MAKE_REGS_RX_0
323output [rx_cw-1:0] CFGRX0;
324input [rx_sw-1:0] STSRX0;
325input RXBCLKIN0;
326`endif
327`ifdef MAKE_REGS_RX_1
328output [rx_cw-1:0] CFGRX1;
329input [rx_sw-1:0] STSRX1;
330input RXBCLKIN1;
331`endif
332`ifdef MAKE_REGS_RX_2
333output [rx_cw-1:0] CFGRX2;
334input [rx_sw-1:0] STSRX2;
335input RXBCLKIN2;
336`endif
337`ifdef MAKE_REGS_RX_3
338output [rx_cw-1:0] CFGRX3;
339input [rx_sw-1:0] STSRX3;
340input RXBCLKIN3;
341`endif
342`ifdef MAKE_REGS_RX_4
343output [rx_cw-1:0] CFGRX4;
344input [rx_sw-1:0] STSRX4;
345input RXBCLKIN4;
346`endif
347`ifdef MAKE_REGS_RX_5
348output [rx_cw-1:0] CFGRX5;
349input [rx_sw-1:0] STSRX5;
350input RXBCLKIN5;
351`endif
352`ifdef MAKE_REGS_RX_6
353output [rx_cw-1:0] CFGRX6;
354input [rx_sw-1:0] STSRX6;
355input RXBCLKIN6;
356`endif
357`ifdef MAKE_REGS_RX_7
358output [rx_cw-1:0] CFGRX7;
359input [rx_sw-1:0] STSRX7;
360input RXBCLKIN7;
361`endif
362output [te_cw-1:0] TESTCFG;
363output [pl_cw-1:0] CFGPLL;
364input [pl_sw-1:0] STSPLL;
365
366////////////////////////////////////////////////////////////////////////////////
367//
368// Output Register Declarations
369//
370////////////////////////////////////////////////////////////////////////////////
371
372reg [15:0] READ_DATA; // Data out
373
374
375////////////////////////////////////////////////////////////////////////////////
376//
377// Internal Declarations
378//
379////////////////////////////////////////////////////////////////////////////////
380
381 // Flops
382
383 // Combinatorials
384
385 reg PW_PLL ; // Write to PLL register block address space
386 reg PW_TEST; // Write to TEST register block address space
387 reg PW_TX_0; // Write to TX_0 register block address space
388 reg PW_TX_1; // Write to TX_1 register block address space
389 reg PW_TX_2; // Write to TX_2 register block address space
390 reg PW_TX_3; // Write to TX_3 register block address space
391 reg PW_TX_4; // Write to TX_4 register block address space
392 reg PW_TX_5; // Write to TX_5 register block address space
393 reg PW_TX_6; // Write to TX_6 register block address space
394 reg PW_TX_7; // Write to TX_7 register block address space
395 reg PW_RX_0; // Write to RX_0 register block address space
396 reg PW_RX_1; // Write to RX_1 register block address space
397 reg PW_RX_2; // Write to RX_2 register block address space
398 reg PW_RX_3; // Write to RX_3 register block address space
399 reg PW_RX_4; // Write to RX_4 register block address space
400 reg PW_RX_5; // Write to RX_5 register block address space
401 reg PW_RX_6; // Write to RX_6 register block address space
402 reg PW_RX_7; // Write to RX_7 register block address space
403
404 reg PR_PLL ; // Read to PLL register block address space
405 reg PR_TEST; // Read to TEST register block address space
406 reg PR_TX_0; // Read to TX_0 register block address space
407 reg PR_TX_1; // Read to TX_1 register block address space
408 reg PR_TX_2; // Read to TX_2 register block address space
409 reg PR_TX_3; // Read to TX_3 register block address space
410 reg PR_TX_4; // Read to TX_4 register block address space
411 reg PR_TX_5; // Read to TX_5 register block address space
412 reg PR_TX_6; // Read to TX_6 register block address space
413 reg PR_TX_7; // Read to TX_7 register block address space
414 reg PR_RX_0; // Read to RX_0 register block address space
415 reg PR_RX_1; // Read to RX_1 register block address space
416 reg PR_RX_2; // Read to RX_2 register block address space
417 reg PR_RX_3; // Read to RX_3 register block address space
418 reg PR_RX_4; // Read to RX_4 register block address space
419 reg PR_RX_5; // Read to RX_5 register block address space
420 reg PR_RX_6; // Read to RX_6 register block address space
421 reg PR_RX_7; // Read to RX_7 register block address space
422
423 wire[15:0] READ_DATA_PLL ; // PLL register block read data
424 wire[15:0] READ_DATA_TEST; // TEST register block read data
425 wire[15:0] READ_DATA_TX_0; // TX_0 register block read data
426 wire[15:0] READ_DATA_TX_1; // TX_1 register block read data
427 wire[15:0] READ_DATA_TX_2; // TX_2 register block read data
428 wire[15:0] READ_DATA_TX_3; // TX_3 register block read data
429 wire[15:0] READ_DATA_TX_4; // TX_4 register block read data
430 wire[15:0] READ_DATA_TX_5; // TX_5 register block read data
431 wire[15:0] READ_DATA_TX_6; // TX_6 register block read data
432 wire[15:0] READ_DATA_TX_7; // TX_7 register block read data
433 wire[15:0] READ_DATA_RX_0; // RX_0 register block read data
434 wire[15:0] READ_DATA_RX_1; // RX_1 register block read data
435 wire[15:0] READ_DATA_RX_2; // RX_2 register block read data
436 wire[15:0] READ_DATA_RX_3; // RX_3 register block read data
437 wire[15:0] READ_DATA_RX_4; // RX_4 register block read data
438 wire[15:0] READ_DATA_RX_5; // RX_5 register block read data
439 wire[15:0] READ_DATA_RX_6; // RX_6 register block read data
440 wire[15:0] READ_DATA_RX_7; // RX_7 register block read data
441
442
443////////////////////////////////////////////////////////////////////////////////
444//
445// Clock muxing and reset control for test
446//
447////////////////////////////////////////////////////////////////////////////////
448
449 SYNC_CELL IO_RESET_SYNC_CELL (.D(~SCANEN & RESET),.CP(IO_MDCLK),.Q(IO_RESET)); // loj@8-30-05
450
451
452////////////////////////////////////////////////////////////////////////////////
453//
454// Write decoder
455//
456////////////////////////////////////////////////////////////////////////////////
457
458always @(PA or PW)
459 begin
460
461 PW_PLL = 1'b0;
462 PW_TEST = 1'b0;
463 PW_TX_0 = 1'b0;
464 PW_TX_1 = 1'b0;
465 PW_TX_2 = 1'b0;
466 PW_TX_3 = 1'b0;
467 PW_TX_4 = 1'b0;
468 PW_TX_5 = 1'b0;
469 PW_TX_6 = 1'b0;
470 PW_TX_7 = 1'b0;
471 PW_RX_0 = 1'b0;
472 PW_RX_1 = 1'b0;
473 PW_RX_2 = 1'b0;
474 PW_RX_3 = 1'b0;
475 PW_RX_4 = 1'b0;
476 PW_RX_5 = 1'b0;
477 PW_RX_6 = 1'b0;
478 PW_RX_7 = 1'b0;
479
480 if (PW)
481 case (PA[9:2])
482 (pl_ra >> 2) : PW_PLL = 1'b1;
483 (te_ra >> 2) : PW_TEST = 1'b1;
484 (t0_ra >> 2) : PW_TX_0 = 1'b1;
485 (t1_ra >> 2) : PW_TX_1 = 1'b1;
486 (t2_ra >> 2) : PW_TX_2 = 1'b1;
487 (t3_ra >> 2) : PW_TX_3 = 1'b1;
488 (t4_ra >> 2) : PW_TX_4 = 1'b1;
489 (t5_ra >> 2) : PW_TX_5 = 1'b1;
490 (t6_ra >> 2) : PW_TX_6 = 1'b1;
491 (t7_ra >> 2) : PW_TX_7 = 1'b1;
492 (r0_ra >> 2) : PW_RX_0 = 1'b1;
493 (r1_ra >> 2) : PW_RX_1 = 1'b1;
494 (r2_ra >> 2) : PW_RX_2 = 1'b1;
495 (r3_ra >> 2) : PW_RX_3 = 1'b1;
496 (r4_ra >> 2) : PW_RX_4 = 1'b1;
497 (r5_ra >> 2) : PW_RX_5 = 1'b1;
498 (r6_ra >> 2) : PW_RX_6 = 1'b1;
499 (r7_ra >> 2) : PW_RX_7 = 1'b1;
500 default : PW_PLL = 1'b0;
501 endcase
502 end
503
504////////////////////////////////////////////////////////////////////////////////
505//
506// Read decoder
507//
508////////////////////////////////////////////////////////////////////////////////
509
510always @(PA or PR)
511 begin
512
513 PR_PLL = 1'b0;
514 PR_TEST = 1'b0;
515 PR_TX_0 = 1'b0;
516 PR_TX_1 = 1'b0;
517 PR_TX_2 = 1'b0;
518 PR_TX_3 = 1'b0;
519 PR_TX_4 = 1'b0;
520 PR_TX_5 = 1'b0;
521 PR_TX_6 = 1'b0;
522 PR_TX_7 = 1'b0;
523 PR_RX_0 = 1'b0;
524 PR_RX_1 = 1'b0;
525 PR_RX_2 = 1'b0;
526 PR_RX_3 = 1'b0;
527 PR_RX_4 = 1'b0;
528 PR_RX_5 = 1'b0;
529 PR_RX_6 = 1'b0;
530 PR_RX_7 = 1'b0;
531
532 if (PR)
533 case (PA[9:2])
534 (pl_ra >> 2) : PR_PLL = 1'b1;
535 (te_ra >> 2) : PR_TEST = 1'b1;
536 (t0_ra >> 2) : PR_TX_0 = 1'b1;
537 (t1_ra >> 2) : PR_TX_1 = 1'b1;
538 (t2_ra >> 2) : PR_TX_2 = 1'b1;
539 (t3_ra >> 2) : PR_TX_3 = 1'b1;
540 (t4_ra >> 2) : PR_TX_4 = 1'b1;
541 (t5_ra >> 2) : PR_TX_5 = 1'b1;
542 (t6_ra >> 2) : PR_TX_6 = 1'b1;
543 (t7_ra >> 2) : PR_TX_7 = 1'b1;
544 (r0_ra >> 2) : PR_RX_0 = 1'b1;
545 (r1_ra >> 2) : PR_RX_1 = 1'b1;
546 (r2_ra >> 2) : PR_RX_2 = 1'b1;
547 (r3_ra >> 2) : PR_RX_3 = 1'b1;
548 (r4_ra >> 2) : PR_RX_4 = 1'b1;
549 (r5_ra >> 2) : PR_RX_5 = 1'b1;
550 (r6_ra >> 2) : PR_RX_6 = 1'b1;
551 (r7_ra >> 2) : PR_RX_7 = 1'b1;
552 default : PR_PLL = 1'b0;
553 endcase
554 end
555
556
557////////////////////////////////////////////////////////////////////////////////
558//
559// Read decoder
560//
561////////////////////////////////////////////////////////////////////////////////
562
563always @(PA or READ_DATA_PLL or READ_DATA_TEST or
564 READ_DATA_TX_0 or READ_DATA_TX_1 or READ_DATA_TX_2 or READ_DATA_TX_3 or
565 READ_DATA_TX_4 or READ_DATA_TX_5 or READ_DATA_TX_6 or READ_DATA_TX_7 or
566 READ_DATA_RX_0 or READ_DATA_RX_1 or READ_DATA_RX_2 or READ_DATA_RX_3 or
567 READ_DATA_RX_4 or READ_DATA_RX_5 or READ_DATA_RX_6 or READ_DATA_RX_7)
568 begin
569 case (PA[9:2])
570 (pl_ra >> 2) : READ_DATA = READ_DATA_PLL ;
571 (te_ra >> 2) : READ_DATA = READ_DATA_TEST;
572 (t0_ra >> 2) : READ_DATA = READ_DATA_TX_0;
573 (t1_ra >> 2) : READ_DATA = READ_DATA_TX_1;
574 (t2_ra >> 2) : READ_DATA = READ_DATA_TX_2;
575 (t3_ra >> 2) : READ_DATA = READ_DATA_TX_3;
576 (t4_ra >> 2) : READ_DATA = READ_DATA_TX_4;
577 (t5_ra >> 2) : READ_DATA = READ_DATA_TX_5;
578 (t6_ra >> 2) : READ_DATA = READ_DATA_TX_6;
579 (t7_ra >> 2) : READ_DATA = READ_DATA_TX_7;
580 (r0_ra >> 2) : READ_DATA = READ_DATA_RX_0;
581 (r1_ra >> 2) : READ_DATA = READ_DATA_RX_1;
582 (r2_ra >> 2) : READ_DATA = READ_DATA_RX_2;
583 (r3_ra >> 2) : READ_DATA = READ_DATA_RX_3;
584 (r4_ra >> 2) : READ_DATA = READ_DATA_RX_4;
585 (r5_ra >> 2) : READ_DATA = READ_DATA_RX_5;
586 (r6_ra >> 2) : READ_DATA = READ_DATA_RX_6;
587 (r7_ra >> 2) : READ_DATA = READ_DATA_RX_7;
588 default : READ_DATA = 16'h0000 ;
589 endcase
590 end
591
592
593////////////////////////////////////////////////////////////////////////////////
594//
595// Register Block Instantiations
596//
597////////////////////////////////////////////////////////////////////////////////
598
599 P2REGS_CFG_STS #(pl_cw,pl_cr,pl_ci,pl_sw,pl_sr,pl_si,pl_ss) I_P2REGS_CFG_STS_PLL
600 (
601 .RESET (IO_RESET ),
602 .MDCLK (IO_MDCLK ),
603 .WDCLK (1'b0 ),
604 .PW (PW_PLL ),
605 .PR (PR_PLL ),
606 .PA (PA[1:0] ),
607 .READ_DATA (READ_DATA_PLL ),
608 .WRITE_DATA (WRITE_DATA ),
609 .CONFIG_BUS (CFGPLL ),
610 .STATUS_BUS (STSPLL )
611 );
612
613 // Note TEST interface only has a config bus - doesn't have a status bus (So tie off)
614 //
615 P2REGS_CFG_STS #(te_cw,te_cr,te_ci,2,32'h0,32'h0,16'h0) I_P2REGS_CFG_STS_TEST
616 (
617 .RESET (IO_RESET ),
618 .MDCLK (IO_MDCLK ),
619 .WDCLK (1'b0 ),
620 .PW (PW_TEST ),
621 .PR (PR_TEST ),
622 .PA (PA[1:0] ),
623 .READ_DATA (READ_DATA_TEST ),
624 .WRITE_DATA (WRITE_DATA ),
625 .CONFIG_BUS (TESTCFG ),
626 .STATUS_BUS (2'b00 )
627 );
628
629
630`ifdef MAKE_REGS_TX_0
631
632 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_0
633 (
634 .RESET (IO_RESET ),
635 .MDCLK (IO_MDCLK ),
636 .WDCLK (TXBCLKIN0 ),
637 .PW (PW_TX_0 ),
638 .PR (PR_TX_0 ),
639 .PA (PA[1:0] ),
640 .READ_DATA (READ_DATA_TX_0 ),
641 .WRITE_DATA (WRITE_DATA ),
642 .CONFIG_BUS (CFGTX0 ),
643 .STATUS_BUS (STSTX0 )
644 );
645`else
646assign READ_DATA_TX_0 = 16'h0000;
647`endif
648
649`ifdef MAKE_REGS_TX_1
650
651 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_1
652 (
653 .RESET (IO_RESET ),
654 .MDCLK (IO_MDCLK ),
655 .WDCLK (TXBCLKIN1 ),
656 .PW (PW_TX_1 ),
657 .PR (PR_TX_1 ),
658 .PA (PA[1:0] ),
659 .READ_DATA (READ_DATA_TX_1 ),
660 .WRITE_DATA (WRITE_DATA ),
661 .CONFIG_BUS (CFGTX1 ),
662 .STATUS_BUS (STSTX1 )
663 );
664`else
665assign READ_DATA_TX_1 = 16'h0000;
666`endif
667
668
669`ifdef MAKE_REGS_TX_2
670
671 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_2
672 (
673 .RESET (IO_RESET ),
674 .MDCLK (IO_MDCLK ),
675 .WDCLK (TXBCLKIN2 ),
676 .PW (PW_TX_2 ),
677 .PR (PR_TX_2 ),
678 .PA (PA[1:0] ),
679 .READ_DATA (READ_DATA_TX_2 ),
680 .WRITE_DATA (WRITE_DATA ),
681 .CONFIG_BUS (CFGTX2 ),
682 .STATUS_BUS (STSTX2 )
683 );
684`else
685assign READ_DATA_TX_2 = 16'h0000;
686`endif
687
688
689`ifdef MAKE_REGS_TX_3
690
691 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_3
692 (
693 .RESET (IO_RESET ),
694 .MDCLK (IO_MDCLK ),
695 .WDCLK (TXBCLKIN3 ),
696 .PW (PW_TX_3 ),
697 .PR (PR_TX_3 ),
698 .PA (PA[1:0] ),
699 .READ_DATA (READ_DATA_TX_3 ),
700 .WRITE_DATA (WRITE_DATA ),
701 .CONFIG_BUS (CFGTX3 ),
702 .STATUS_BUS (STSTX3 )
703 );
704`else
705assign READ_DATA_TX_3 = 16'h0000;
706`endif
707
708
709`ifdef MAKE_REGS_TX_4
710
711 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_4
712 (
713 .RESET (IO_RESET ),
714 .MDCLK (IO_MDCLK ),
715 .WDCLK (TXBCLKIN4 ),
716 .PW (PW_TX_4 ),
717 .PR (PR_TX_4 ),
718 .PA (PA[1:0] ),
719 .READ_DATA (READ_DATA_TX_4 ),
720 .WRITE_DATA (WRITE_DATA ),
721 .CONFIG_BUS (CFGTX4 ),
722 .STATUS_BUS (STSTX4 )
723 );
724`else
725assign READ_DATA_TX_4 = 16'h0000;
726`endif
727
728
729`ifdef MAKE_REGS_TX_5
730
731 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_5
732 (
733 .RESET (IO_RESET ),
734 .MDCLK (IO_MDCLK ),
735 .WDCLK (TXBCLKIN5 ),
736 .PW (PW_TX_5 ),
737 .PR (PR_TX_5 ),
738 .PA (PA[1:0] ),
739 .READ_DATA (READ_DATA_TX_5 ),
740 .WRITE_DATA (WRITE_DATA ),
741 .CONFIG_BUS (CFGTX5 ),
742 .STATUS_BUS (STSTX5 )
743 );
744`else
745assign READ_DATA_TX_5 = 16'h0000;
746`endif
747
748
749`ifdef MAKE_REGS_TX_6
750
751 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_6
752 (
753 .RESET (IO_RESET ),
754 .MDCLK (IO_MDCLK ),
755 .WDCLK (TXBCLKIN6 ),
756 .PW (PW_TX_6 ),
757 .PR (PR_TX_6 ),
758 .PA (PA[1:0] ),
759 .READ_DATA (READ_DATA_TX_6 ),
760 .WRITE_DATA (WRITE_DATA ),
761 .CONFIG_BUS (CFGTX6 ),
762 .STATUS_BUS (STSTX6 )
763 );
764`else
765assign READ_DATA_TX_6 = 16'h0000;
766`endif
767
768
769`ifdef MAKE_REGS_TX_7
770
771 P2REGS_CFG_STS #(tx_cw,tx_cr,tx_ci,tx_sw,tx_sr,tx_si,tx_ss) I_P2REGS_CFG_STS_TX_7
772 (
773 .RESET (IO_RESET ),
774 .MDCLK (IO_MDCLK ),
775 .WDCLK (TXBCLKIN7 ),
776 .PW (PW_TX_7 ),
777 .PR (PR_TX_7 ),
778 .PA (PA[1:0] ),
779 .READ_DATA (READ_DATA_TX_7 ),
780 .WRITE_DATA (WRITE_DATA ),
781 .CONFIG_BUS (CFGTX7 ),
782 .STATUS_BUS (STSTX7 )
783 );
784`else
785assign READ_DATA_TX_7 = 16'h0000;
786`endif
787
788
789
790
791`ifdef MAKE_REGS_RX_0
792
793 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_0
794 (
795 .RESET (IO_RESET ),
796 .MDCLK (IO_MDCLK ),
797 .WDCLK (RXBCLKIN0 ),
798 .PW (PW_RX_0 ),
799 .PR (PR_RX_0 ),
800 .PA (PA[1:0] ),
801 .READ_DATA (READ_DATA_RX_0 ),
802 .WRITE_DATA (WRITE_DATA ),
803 .CONFIG_BUS (CFGRX0 ),
804 .STATUS_BUS (STSRX0 )
805 );
806`else
807assign READ_DATA_RX_0 = 16'h0000;
808`endif
809
810`ifdef MAKE_REGS_RX_1
811
812 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_1
813 (
814 .RESET (IO_RESET ),
815 .MDCLK (IO_MDCLK ),
816 .WDCLK (RXBCLKIN1 ),
817 .PW (PW_RX_1 ),
818 .PR (PR_RX_1 ),
819 .PA (PA[1:0] ),
820 .READ_DATA (READ_DATA_RX_1 ),
821 .WRITE_DATA (WRITE_DATA ),
822 .CONFIG_BUS (CFGRX1 ),
823 .STATUS_BUS (STSRX1 )
824 );
825`else
826assign READ_DATA_RX_1 = 16'h0000;
827`endif
828
829
830`ifdef MAKE_REGS_RX_2
831
832 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_2
833 (
834 .RESET (IO_RESET ),
835 .MDCLK (IO_MDCLK ),
836 .WDCLK (RXBCLKIN2 ),
837 .PW (PW_RX_2 ),
838 .PR (PR_RX_2 ),
839 .PA (PA[1:0] ),
840 .READ_DATA (READ_DATA_RX_2 ),
841 .WRITE_DATA (WRITE_DATA ),
842 .CONFIG_BUS (CFGRX2 ),
843 .STATUS_BUS (STSRX2 )
844 );
845`else
846assign READ_DATA_RX_2 = 16'h0000;
847`endif
848
849
850`ifdef MAKE_REGS_RX_3
851
852 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_3
853 (
854 .RESET (IO_RESET ),
855 .MDCLK (IO_MDCLK ),
856 .WDCLK (RXBCLKIN3 ),
857 .PW (PW_RX_3 ),
858 .PR (PR_RX_3 ),
859 .PA (PA[1:0] ),
860 .READ_DATA (READ_DATA_RX_3 ),
861 .WRITE_DATA (WRITE_DATA ),
862 .CONFIG_BUS (CFGRX3 ),
863 .STATUS_BUS (STSRX3 )
864 );
865`else
866assign READ_DATA_RX_3 = 16'h0000;
867`endif
868
869
870`ifdef MAKE_REGS_RX_4
871
872 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_4
873 (
874 .RESET (IO_RESET ),
875 .MDCLK (IO_MDCLK ),
876 .WDCLK (RXBCLKIN4 ),
877 .PW (PW_RX_4 ),
878 .PR (PR_RX_4 ),
879 .PA (PA[1:0] ),
880 .READ_DATA (READ_DATA_RX_4 ),
881 .WRITE_DATA (WRITE_DATA ),
882 .CONFIG_BUS (CFGRX4 ),
883 .STATUS_BUS (STSRX4 )
884 );
885`else
886assign READ_DATA_RX_4 = 16'h0000;
887`endif
888
889
890`ifdef MAKE_REGS_RX_5
891
892 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_5
893 (
894 .RESET (IO_RESET ),
895 .MDCLK (IO_MDCLK ),
896 .WDCLK (RXBCLKIN5 ),
897 .PW (PW_RX_5 ),
898 .PR (PR_RX_5 ),
899 .PA (PA[1:0] ),
900 .READ_DATA (READ_DATA_RX_5 ),
901 .WRITE_DATA (WRITE_DATA ),
902 .CONFIG_BUS (CFGRX5 ),
903 .STATUS_BUS (STSRX5 )
904 );
905`else
906assign READ_DATA_RX_5 = 16'h0000;
907`endif
908
909
910`ifdef MAKE_REGS_RX_6
911
912 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_6
913 (
914 .RESET (IO_RESET ),
915 .MDCLK (IO_MDCLK ),
916 .WDCLK (RXBCLKIN6 ),
917 .PW (PW_RX_6 ),
918 .PR (PR_RX_6 ),
919 .PA (PA[1:0] ),
920 .READ_DATA (READ_DATA_RX_6 ),
921 .WRITE_DATA (WRITE_DATA ),
922 .CONFIG_BUS (CFGRX6 ),
923 .STATUS_BUS (STSRX6 )
924 );
925`else
926assign READ_DATA_RX_6 = 16'h0000;
927`endif
928
929
930`ifdef MAKE_REGS_RX_7
931
932 P2REGS_CFG_STS #(rx_cw,rx_cr,rx_ci,rx_sw,rx_sr,rx_si,rx_ss) I_P2REGS_CFG_STS_RX_7
933 (
934 .RESET (IO_RESET ),
935 .MDCLK (IO_MDCLK ),
936 .WDCLK (RXBCLKIN7 ),
937 .PW (PW_RX_7 ),
938 .PR (PR_RX_7 ),
939 .PA (PA[1:0] ),
940 .READ_DATA (READ_DATA_RX_7 ),
941 .WRITE_DATA (WRITE_DATA ),
942 .CONFIG_BUS (CFGRX7 ),
943 .STATUS_BUS (STSRX7 )
944 );
945`else
946assign READ_DATA_RX_7 = 16'h0000;
947`endif
948
949
950
951endmodule
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