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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / address_decoder.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: address_decoder.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
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13// This program is distributed in the hope that it will be useful,
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17//
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35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : address_decoder.v
40 * Author Name : John Lo
41 * Description : decode incoming DA, flow control frame, bcast,mcast.
42 * Parent Module: rx_xmac
43 * Child Module:
44 * Interface Mod: many.
45 * Date Created : 5/9/00
46 *
47 * Copyright (c) 2002, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 *************************************************************************/
55
56`include "xmac.h"
57
58module address_decoder(
59 rx_clk,
60 rx_reset,
61 eop,
62 bad_pkt_bit,
63 promisc_all, // control enable
64 promisc_group, // control enable
65 reserve_multicast, // control enable
66 rx_pause_en, // control enable
67 rx_data_64bit_reg0_gmux,
68 rx_data_valid_gmux_lead,
69 mac_unique_addr,
70 // start of ALT_ADDR_AND_HASH_FUNC specific signals
71 new_crc5_result,
72 addr_filter_en,
73 hash_filter_en,
74 alt_addr_comp_en,
75 mac_alt_addr0,
76 mac_alt_addr1,
77 mac_alt_addr2,
78 mac_alt_addr3,
79 mac_alt_addr4,
80 mac_alt_addr5,
81 mac_alt_addr6,
82 mac_alt_addr7,
83 mac_alt_addr8,
84 mac_alt_addr9,
85 mac_alt_addr10,
86 mac_alt_addr11,
87 mac_alt_addr12,
88 mac_alt_addr13,
89 mac_alt_addr14,
90 mac_alt_addr15,
91 addr_filter,
92 addr_filter_mask_msb,
93 addr_filter_mask_lsb,
94 hash_table,
95 mac_host_info0 ,
96 mac_host_info1 ,
97 mac_host_info2 ,
98 mac_host_info3 ,
99 mac_host_info4 ,
100 mac_host_info5 ,
101 mac_host_info6 ,
102 mac_host_info7 ,
103 mac_host_info8 ,
104 mac_host_info9 ,
105 mac_host_info10,
106 mac_host_info11,
107 mac_host_info12,
108 mac_host_info13,
109 mac_host_info14,
110 mac_host_info15,
111 mac_host_info16,
112 mac_host_info17,
113 mac_host_info18,
114 mac_host_info19,
115 rx_ok,
116// output signals
117 alt_addr_filter_value,
118 hash_hit_match,
119 hash_value,
120 mac_ctrl_word,
121 mac_ctrl_word_wr_en,
122 // end of ALT_ADDR_AND_HASH_FUNC specific signals
123 rx_fc_pkt,
124 rx_fc_pkt_ok,
125 pause_time,
126 da_match,
127 da_match_err,
128 mac_own_da_match,
129 inc_bcast_count, // ***** signal crossing different clk
130 inc_mcast_count // ***** signal crossing different clk
131);
132
133 input rx_clk;
134 input rx_reset;
135 input eop;
136 input bad_pkt_bit;
137 input promisc_all; // control enable
138 input promisc_group; // control enable
139 input reserve_multicast; // control enable
140 input rx_pause_en; // control enable
141 input [63:0] rx_data_64bit_reg0_gmux;
142 input rx_data_valid_gmux_lead;
143 input [47:0] mac_unique_addr;
144 // start of ALT_ADDR_AND_HASH_FUNC specific signals
145 input [15:0] new_crc5_result;
146 input addr_filter_en;
147 input hash_filter_en;
148 input [15:0] alt_addr_comp_en;
149 input [47:0] mac_alt_addr0;
150 input [47:0] mac_alt_addr1;
151 input [47:0] mac_alt_addr2;
152 input [47:0] mac_alt_addr3;
153 input [47:0] mac_alt_addr4;
154 input [47:0] mac_alt_addr5;
155 input [47:0] mac_alt_addr6;
156 input [47:0] mac_alt_addr7;
157 input [47:0] mac_alt_addr8;
158 input [47:0] mac_alt_addr9;
159 input [47:0] mac_alt_addr10;
160 input [47:0] mac_alt_addr11;
161 input [47:0] mac_alt_addr12;
162 input [47:0] mac_alt_addr13;
163 input [47:0] mac_alt_addr14;
164 input [47:0] mac_alt_addr15;
165 input [47:0] addr_filter;
166 input [7:0] addr_filter_mask_msb;
167 input [15:0] addr_filter_mask_lsb;
168 input [255:0] hash_table;
169 input [`H_INFO] mac_host_info0 ;
170 input [`H_INFO] mac_host_info1 ;
171 input [`H_INFO] mac_host_info2 ;
172 input [`H_INFO] mac_host_info3 ;
173 input [`H_INFO] mac_host_info4 ;
174 input [`H_INFO] mac_host_info5 ;
175 input [`H_INFO] mac_host_info6 ;
176 input [`H_INFO] mac_host_info7 ;
177 input [`H_INFO] mac_host_info8 ;
178 input [`H_INFO] mac_host_info9 ;
179 input [`H_INFO] mac_host_info10;
180 input [`H_INFO] mac_host_info11;
181 input [`H_INFO] mac_host_info12;
182 input [`H_INFO] mac_host_info13;
183 input [`H_INFO] mac_host_info14;
184 input [`H_INFO] mac_host_info15;
185 input [`H_INFO] mac_host_info16;
186 input [`H_INFO] mac_host_info17;
187 input [`H_INFO] mac_host_info18;
188 input [`H_INFO] mac_host_info19;
189 input rx_ok;
190// output signals
191 output [6:0] alt_addr_filter_value;
192 output hash_hit_match;
193 output [15:0] hash_value;
194 output [`MAC_CTRL] mac_ctrl_word;
195 output mac_ctrl_word_wr_en;
196 // end of ALT_ADDR_AND_HASH_FUNC specific signals
197 output rx_fc_pkt;
198 output rx_fc_pkt_ok;
199 output [15:0] pause_time;
200 output da_match;
201 output da_match_err;
202 output mac_own_da_match;
203 output inc_bcast_count; // * signal crossing different clk
204 output inc_mcast_count; // * signal crossing different clk
205
206 wire [7:0] rx_byte0 = rx_data_64bit_reg0_gmux[`BYTE0];
207 wire [7:0] rx_byte1 = rx_data_64bit_reg0_gmux[`BYTE1];
208 wire [7:0] rx_byte2 = rx_data_64bit_reg0_gmux[`BYTE2];
209 wire [7:0] rx_byte3 = rx_data_64bit_reg0_gmux[`BYTE3];
210 wire [7:0] rx_byte4 = rx_data_64bit_reg0_gmux[`BYTE4];
211 wire [7:0] rx_byte5 = rx_data_64bit_reg0_gmux[`BYTE5];
212 wire [7:0] rx_byte6 = rx_data_64bit_reg0_gmux[`BYTE6];
213 wire [7:0] rx_byte7 = rx_data_64bit_reg0_gmux[`BYTE7];
214
215 wire set_mac_reserve_multicast_match,
216 mac_reserve_multicast_match,
217 set_mac_own_da_match,
218 mac_own_da_match,
219 set_addr_filter_match,
220 addr_filter_match,
221 set_all_mac_alt_addr_match,
222 all_mac_alt_addr_match,
223 set_hash_hit_match,
224 hash_hit_match,
225 set_mac_fc_match,
226 mac_fc_match,
227 set_rx_fc_pkt,
228 promisc_all_match,
229 set_grp_match,
230 grp_match,
231 promisc_grp_match,
232 set_bcast_match,
233 bcast_match;
234 wire d_rx_data_valid_gmux_lead,type_mac_control,opcode_pause;
235 wire rx_reset_counters = rx_reset | eop;
236 wire rx_1st_word_time = rx_data_valid_gmux_lead;
237 wire rx_2nd_word_time = d_rx_data_valid_gmux_lead;
238 wire load_pause_time;
239// vlint flag_net_has_no_load off
240// vlint flag_dangling_net_within_module off
241 wire load_pause_time_trail;
242// vlint flag_dangling_net_within_module on
243// vlint flag_net_has_no_load on
244
245/**************************************************************************
246 * Start of NIC selectable logic signals
247 * ************************************************************************/
248/**************************************************************************
249 * end of NIC selectable logic signals
250 * ************************************************************************/
251
252 FD1 d_rx_data_valid_gmux_lead_FD1 (.D(rx_data_valid_gmux_lead),
253 .CP(rx_clk),
254 .Q(d_rx_data_valid_gmux_lead));
255
256/* -------------------- promiscuous all match ------------------------- */
257
258 FD1 promisc_all_match_FF1(.D(promisc_all),.CP(rx_clk),
259 .Q(promisc_all_match)); // a level
260
261/* -------------------- promiscuous group match ----------------------- */
262 // I/G bit: 1st byte, bit 0. if (I/G = 1) then GROUP else INIDIVIDUAL
263
264 // a pulse
265 assign set_grp_match = rx_1st_word_time & rx_byte0[0];
266 RS_FF grp_match_RS_FF (.set(set_grp_match),.rst(1'b0),
267 .clk(rx_clk),.reset(rx_reset_counters),.qout(grp_match));
268
269 assign promisc_grp_match = promisc_group & grp_match; // a level
270
271/* -------------------- broadcast match ------------------------------- */
272 // a pulse
273 assign set_bcast_match = rx_1st_word_time &
274 (rx_byte0 == 8'hFF) &
275 (rx_byte1 == 8'hFF) &
276 (rx_byte2 == 8'hFF) &
277 (rx_byte3 == 8'hFF) &
278 (rx_byte4 == 8'hFF) &
279 (rx_byte5 == 8'hFF) ;
280 RS_FF bcast_match_RS_FF (.set(set_bcast_match),.rst(1'b0),
281 .clk(rx_clk),.reset(rx_reset_counters),.qout(bcast_match));
282
283/* -------------------- own da match ---------------------------------- */
284 // a pulse
285 assign set_mac_own_da_match = rx_1st_word_time &
286 (rx_byte0 == mac_unique_addr[`BYTE1]) & // a
287 (rx_byte1 == mac_unique_addr[`BYTE0]) & // b
288 (rx_byte2 == mac_unique_addr[`BYTE3]) & // c
289 (rx_byte3 == mac_unique_addr[`BYTE2]) & // d
290 (rx_byte4 == mac_unique_addr[`BYTE5]) & // e
291 (rx_byte5 == mac_unique_addr[`BYTE4]) ; // f
292
293 RS_FF mac_own_da_match_RS_FF (.set(set_mac_own_da_match),.rst(1'b0),
294 .clk(rx_clk),.reset(rx_reset_counters),.qout(mac_own_da_match));
295
296/* -------------------- flow control frame match ---------------------- */
297 // 01-80-C2-00-00-01 is the globally-assigned 48 bit multicast
298 // address for used in Mac Control Pause frames for inhibiting
299 // transmission of data from a DTE in a full-duplex mode LAN.
300 // Refer to IEEE Std 802.3x & 802.3y Annex31B, pp-300.
301 // This signal is a pulse.
302 assign set_mac_fc_match = rx_1st_word_time & // a pulse
303 (rx_byte0 == 8'h01) &
304 (rx_byte1 == 8'h80) &
305 (rx_byte2 == 8'hC2) &
306 (rx_byte3 == 8'h00) &
307 (rx_byte4 == 8'h00) &
308 (rx_byte5 == 8'h01) ;
309
310 // fc_match is available at rx_2nd_word_time
311 RS_FF mac_fc_match_RS_FF (.set(set_mac_fc_match),.rst(1'b0),
312 .clk(rx_clk),.reset(rx_reset_counters),.qout(mac_fc_match));
313 //
314 assign type_mac_control = ({rx_byte4,rx_byte5} == 16'h8808);
315 assign opcode_pause = ({rx_byte6,rx_byte7} == 16'h0001);
316
317 // set_rx_fc_pk is valid at rx_2nd_word_time. It is a pulse.
318 assign set_rx_fc_pkt = rx_2nd_word_time & rx_pause_en &
319 mac_fc_match & type_mac_control & opcode_pause;
320
321 // rx_fc_pkt is valid at rx_3rd_word_time. It is a level.
322 RS_FF rx_fc_pkt_RS_FF (.set(set_rx_fc_pkt),.rst(1'b0),
323 .clk(rx_clk),.reset(rx_reset_counters),.qout(rx_fc_pkt));
324
325 // load pause_time at rx_3rd_word_time
326 // Request TxMac to load pause_time, only after eop.
327PlsGen2 load_pause_time_PlsGen2(.sig_in(rx_fc_pkt),.clk(rx_clk),
328 .lead(load_pause_time),.trail(load_pause_time_trail));
329
330 assign rx_fc_pkt_ok = eop & rx_fc_pkt & ~bad_pkt_bit;
331
332 // pause_time is valid at rx_4th_word_time. It is a level.
333register_load_X16 pause_time_register_load_X16(.clk(rx_clk),
334 .load(load_pause_time), // load data @ rx_3rd_word_time
335 .din({rx_byte0,rx_byte1}),// rx_3rd_word_time data.
336 .dout(pause_time)); // available at rx_4th_word_time
337
338/* -------------------- reserve multicast frames ---------------------- */
339 // a pulse
340 assign set_mac_reserve_multicast_match = rx_1st_word_time &
341 reserve_multicast &
342 (rx_byte0 == mac_unique_addr[15:08]) &
343 (rx_byte1 == mac_unique_addr[07:00]) &
344 (rx_byte2 == mac_unique_addr[31:24]) &
345 (rx_byte3 == mac_unique_addr[23:16]) &
346 (rx_byte4 == mac_unique_addr[47:40]) &
347 (rx_byte5[7:4] == mac_unique_addr[39:36]); // skip big [35:32]
348
349 RS_FF mac_reserve_match_RS_FF (.set(set_mac_reserve_multicast_match),
350 .rst(1'b0),.clk(rx_clk),
351 .reset(rx_reset_counters),
352 .qout(mac_reserve_multicast_match));
353
354/* -------------------- da_match, match conclusion -------------------- */
355 // a level
356 assign da_match = promisc_all_match |
357 promisc_grp_match |
358 bcast_match |
359 mac_own_da_match |
360 //
361 hash_hit_match |
362 addr_filter_match |
363 all_mac_alt_addr_match | // new 64 hosts
364 //
365 mac_fc_match |
366 mac_reserve_multicast_match;
367
368 // a pulse for xrlm_sm only
369 wire da_match_pls = (promisc_all_match |
370 (promisc_group & set_grp_match) |
371 set_bcast_match |
372 set_mac_own_da_match |
373 //
374 set_hash_hit_match |
375 set_addr_filter_match |
376 set_all_mac_alt_addr_match | // new 64 hosts
377 //
378 set_mac_fc_match |
379 set_mac_reserve_multicast_match);
380
381
382 assign da_match_err = ~da_match_pls;
383
384/* -------------------- RMON Support ---------------------------------- */
385 assign inc_bcast_count = set_bcast_match;
386 assign inc_mcast_count = set_grp_match & !set_bcast_match;
387
388/**************************************************************************
389 * start of ALT_ADDR_AND_HASH_FUNC selectable logic
390 * ************************************************************************/
391`ifdef ALT_ADDR_AND_HASH_FUNC
392 wire set_mac_alt_addr0_match,
393 set_mac_alt_addr1_match,
394 set_mac_alt_addr2_match,
395 set_mac_alt_addr3_match,
396 set_mac_alt_addr4_match,
397 set_mac_alt_addr5_match,
398 set_mac_alt_addr6_match,
399 set_mac_alt_addr7_match,
400 set_mac_alt_addr8_match,
401 set_mac_alt_addr9_match,
402 set_mac_alt_addr10_match,
403 set_mac_alt_addr11_match,
404 set_mac_alt_addr12_match,
405 set_mac_alt_addr13_match,
406 set_mac_alt_addr14_match,
407 set_mac_alt_addr15_match;
408
409/* -------------------- hash multicast match -------------------------- */
410 wire [7:0] hash_key = {new_crc5_result[0],
411 new_crc5_result[1],
412 new_crc5_result[2],
413 new_crc5_result[3],
414 new_crc5_result[4],
415 new_crc5_result[5],
416 new_crc5_result[6],
417 new_crc5_result[7]};
418
419 wire hash_bit = hash_table[hash_key];
420
421 assign set_hash_hit_match = hash_filter_en &
422 (rx_1st_word_time & rx_byte0[0] & hash_bit);
423
424 RS_FF hash_hit_match_RS_FF (.set(set_hash_hit_match),.rst(1'b0),
425 .clk(rx_clk),.reset(rx_reset_counters),.qout(hash_hit_match));
426
427 xREG #(16) hash_value_xREG(.din({new_crc5_result[0],
428 new_crc5_result[1],
429 new_crc5_result[2],
430 new_crc5_result[3],
431 new_crc5_result[4],
432 new_crc5_result[5],
433 new_crc5_result[6],
434 new_crc5_result[7],
435 new_crc5_result[8],
436 new_crc5_result[9],
437 new_crc5_result[10],
438 new_crc5_result[11],
439 new_crc5_result[12],
440 new_crc5_result[13],
441 new_crc5_result[14],
442 new_crc5_result[15]}),
443 .clk(rx_clk),
444 .en(rx_1st_word_time),
445 .reset(rx_reset_counters),
446 .qout(hash_value[15:0]));
447
448/* -------------------- addr filter match ---------------------------- */
449 // a pulse
450 assign set_addr_filter_match = rx_1st_word_time & addr_filter_en & (
451 ((rx_byte0[`NIB1] == addr_filter[15:12]) | !addr_filter_mask_msb[7]) &
452 ((rx_byte0[`NIB0] == addr_filter[11:8]) | !addr_filter_mask_msb[6]) |
453
454 ((rx_byte1[`NIB1] == addr_filter[7:4]) | !addr_filter_mask_msb[5]) &
455 ((rx_byte1[`NIB0] == addr_filter[3:0]) | !addr_filter_mask_msb[4]) |
456
457 ((rx_byte2[`NIB1] == addr_filter[31:28]) | !addr_filter_mask_msb[3]) &
458 ((rx_byte2[`NIB0] == addr_filter[27:24]) | !addr_filter_mask_msb[2]) |
459
460 ((rx_byte3[`NIB1] == addr_filter[23:20]) | !addr_filter_mask_msb[1]) &
461 ((rx_byte3[`NIB0] == addr_filter[19:16]) | !addr_filter_mask_msb[0]) |
462
463 ((rx_byte4[7] == addr_filter[47]) | !addr_filter_mask_lsb[15]) &
464 ((rx_byte4[6] == addr_filter[46]) | !addr_filter_mask_lsb[14]) &
465 ((rx_byte4[5] == addr_filter[45]) | !addr_filter_mask_lsb[13]) &
466 ((rx_byte4[4] == addr_filter[44]) | !addr_filter_mask_lsb[12]) &
467 ((rx_byte4[3] == addr_filter[43]) | !addr_filter_mask_lsb[11]) &
468 ((rx_byte4[2] == addr_filter[42]) | !addr_filter_mask_lsb[10]) &
469 ((rx_byte4[1] == addr_filter[41]) | !addr_filter_mask_lsb[9]) &
470 ((rx_byte4[0] == addr_filter[40]) | !addr_filter_mask_lsb[8]) |
471
472 ((rx_byte5[7] == addr_filter[39]) | !addr_filter_mask_lsb[7]) &
473 ((rx_byte5[6] == addr_filter[38]) | !addr_filter_mask_lsb[6]) &
474 ((rx_byte5[5] == addr_filter[37]) | !addr_filter_mask_lsb[5]) &
475 ((rx_byte5[4] == addr_filter[36]) | !addr_filter_mask_lsb[4]) &
476 ((rx_byte5[3] == addr_filter[35]) | !addr_filter_mask_lsb[3]) &
477 ((rx_byte5[2] == addr_filter[34]) | !addr_filter_mask_lsb[2]) &
478 ((rx_byte5[1] == addr_filter[33]) | !addr_filter_mask_lsb[1]) &
479 ((rx_byte5[0] == addr_filter[32]) | !addr_filter_mask_lsb[0]) );
480
481 RS_FF addr_filter_match_RS_FF (.set(set_addr_filter_match),.rst(1'b0),
482 .clk(rx_clk),.reset(rx_reset_counters),.qout(addr_filter_match));
483
484/* -------------------- mac alternative addr0 match ------------------- */
485 // a pulse
486 assign set_mac_alt_addr0_match = rx_1st_word_time &
487 alt_addr_comp_en[0] &
488 (rx_byte0 == mac_alt_addr0[`BYTE1]) & // a
489 (rx_byte1 == mac_alt_addr0[`BYTE0]) & // b
490 (rx_byte2 == mac_alt_addr0[`BYTE3]) & // c
491 (rx_byte3 == mac_alt_addr0[`BYTE2]) & // d
492 (rx_byte4 == mac_alt_addr0[`BYTE5]) & // e
493 (rx_byte5 == mac_alt_addr0[`BYTE4]) ; // f
494
495/* -------------------- mac alternative addr1 match ------------------- */
496 // a pulse
497 assign set_mac_alt_addr1_match = rx_1st_word_time &
498 alt_addr_comp_en[1] &
499 (rx_byte0 == mac_alt_addr1[`BYTE1]) & // a
500 (rx_byte1 == mac_alt_addr1[`BYTE0]) & // b
501 (rx_byte2 == mac_alt_addr1[`BYTE3]) & // c
502 (rx_byte3 == mac_alt_addr1[`BYTE2]) & // d
503 (rx_byte4 == mac_alt_addr1[`BYTE5]) & // e
504 (rx_byte5 == mac_alt_addr1[`BYTE4]) ; // f
505
506/* -------------------- mac alternative addr2 match ------------------- */
507 // a pulse
508 assign set_mac_alt_addr2_match = rx_1st_word_time &
509 alt_addr_comp_en[2] &
510 (rx_byte0 == mac_alt_addr2[`BYTE1]) & // a
511 (rx_byte1 == mac_alt_addr2[`BYTE0]) & // b
512 (rx_byte2 == mac_alt_addr2[`BYTE3]) & // c
513 (rx_byte3 == mac_alt_addr2[`BYTE2]) & // d
514 (rx_byte4 == mac_alt_addr2[`BYTE5]) & // e
515 (rx_byte5 == mac_alt_addr2[`BYTE4]) ; // f
516
517/* -------------------- mac alternative addr3 match ------------------- */
518 // a pulse
519 assign set_mac_alt_addr3_match = rx_1st_word_time &
520 alt_addr_comp_en[3] &
521 (rx_byte0 == mac_alt_addr3[`BYTE1]) & // a
522 (rx_byte1 == mac_alt_addr3[`BYTE0]) & // b
523 (rx_byte2 == mac_alt_addr3[`BYTE3]) & // c
524 (rx_byte3 == mac_alt_addr3[`BYTE2]) & // d
525 (rx_byte4 == mac_alt_addr3[`BYTE5]) & // e
526 (rx_byte5 == mac_alt_addr3[`BYTE4]) ; // f
527
528/* -------------------- mac alternative addr4 match ------------------- */
529 // a pulse
530 assign set_mac_alt_addr4_match = rx_1st_word_time &
531 alt_addr_comp_en[4] &
532 (rx_byte0 == mac_alt_addr4[`BYTE1]) & // a
533 (rx_byte1 == mac_alt_addr4[`BYTE0]) & // b
534 (rx_byte2 == mac_alt_addr4[`BYTE3]) & // c
535 (rx_byte3 == mac_alt_addr4[`BYTE2]) & // d
536 (rx_byte4 == mac_alt_addr4[`BYTE5]) & // e
537 (rx_byte5 == mac_alt_addr4[`BYTE4]) ; // f
538
539/* -------------------- mac alternative addr5 match ------------------- */
540 // a pulse
541 assign set_mac_alt_addr5_match = rx_1st_word_time &
542 alt_addr_comp_en[5] &
543 (rx_byte0 == mac_alt_addr5[`BYTE1]) & // a
544 (rx_byte1 == mac_alt_addr5[`BYTE0]) & // b
545 (rx_byte2 == mac_alt_addr5[`BYTE3]) & // c
546 (rx_byte3 == mac_alt_addr5[`BYTE2]) & // d
547 (rx_byte4 == mac_alt_addr5[`BYTE5]) & // e
548 (rx_byte5 == mac_alt_addr5[`BYTE4]) ; // f
549
550/* -------------------- mac alternative addr6 match ------------------- */
551 // a pulse
552 assign set_mac_alt_addr6_match = rx_1st_word_time &
553 alt_addr_comp_en[6] &
554 (rx_byte0 == mac_alt_addr6[`BYTE1]) & // a
555 (rx_byte1 == mac_alt_addr6[`BYTE0]) & // b
556 (rx_byte2 == mac_alt_addr6[`BYTE3]) & // c
557 (rx_byte3 == mac_alt_addr6[`BYTE2]) & // d
558 (rx_byte4 == mac_alt_addr6[`BYTE5]) & // e
559 (rx_byte5 == mac_alt_addr6[`BYTE4]) ; // f
560
561/* -------------------- mac alternative addr7 match ------------------- */
562 // a pulse
563 assign set_mac_alt_addr7_match = rx_1st_word_time &
564 alt_addr_comp_en[7] &
565 (rx_byte0 == mac_alt_addr7[`BYTE1]) & // a
566 (rx_byte1 == mac_alt_addr7[`BYTE0]) & // b
567 (rx_byte2 == mac_alt_addr7[`BYTE3]) & // c
568 (rx_byte3 == mac_alt_addr7[`BYTE2]) & // d
569 (rx_byte4 == mac_alt_addr7[`BYTE5]) & // e
570 (rx_byte5 == mac_alt_addr7[`BYTE4]) ; // f
571
572/* -------------------- mac alternative addr8 match ------------------- */
573 // a pulse
574 assign set_mac_alt_addr8_match = rx_1st_word_time &
575 alt_addr_comp_en[8] &
576 (rx_byte0 == mac_alt_addr8[`BYTE1]) & // a
577 (rx_byte1 == mac_alt_addr8[`BYTE0]) & // b
578 (rx_byte2 == mac_alt_addr8[`BYTE3]) & // c
579 (rx_byte3 == mac_alt_addr8[`BYTE2]) & // d
580 (rx_byte4 == mac_alt_addr8[`BYTE5]) & // e
581 (rx_byte5 == mac_alt_addr8[`BYTE4]) ; // f
582
583/* -------------------- mac alternative addr9 match ------------------- */
584 // a pulse
585 assign set_mac_alt_addr9_match = rx_1st_word_time &
586 alt_addr_comp_en[9] &
587 (rx_byte0 == mac_alt_addr9[`BYTE1]) & // a
588 (rx_byte1 == mac_alt_addr9[`BYTE0]) & // b
589 (rx_byte2 == mac_alt_addr9[`BYTE3]) & // c
590 (rx_byte3 == mac_alt_addr9[`BYTE2]) & // d
591 (rx_byte4 == mac_alt_addr9[`BYTE5]) & // e
592 (rx_byte5 == mac_alt_addr9[`BYTE4]) ; // f
593
594/* -------------------- mac alternative addr10 match ------------------ */
595 // a pulse
596 assign set_mac_alt_addr10_match = rx_1st_word_time &
597 alt_addr_comp_en[10] &
598 (rx_byte0 == mac_alt_addr10[`BYTE1]) & // a
599 (rx_byte1 == mac_alt_addr10[`BYTE0]) & // b
600 (rx_byte2 == mac_alt_addr10[`BYTE3]) & // c
601 (rx_byte3 == mac_alt_addr10[`BYTE2]) & // d
602 (rx_byte4 == mac_alt_addr10[`BYTE5]) & // e
603 (rx_byte5 == mac_alt_addr10[`BYTE4]) ; // f
604
605/* -------------------- mac alternative addr11 match ------------------ */
606 // a pulse
607 assign set_mac_alt_addr11_match = rx_1st_word_time &
608 alt_addr_comp_en[11] &
609 (rx_byte0 == mac_alt_addr11[`BYTE1]) & // a
610 (rx_byte1 == mac_alt_addr11[`BYTE0]) & // b
611 (rx_byte2 == mac_alt_addr11[`BYTE3]) & // c
612 (rx_byte3 == mac_alt_addr11[`BYTE2]) & // d
613 (rx_byte4 == mac_alt_addr11[`BYTE5]) & // e
614 (rx_byte5 == mac_alt_addr11[`BYTE4]) ; // f
615
616/* -------------------- mac alternative addr12 match ------------------ */
617 // a pulse
618 assign set_mac_alt_addr12_match = rx_1st_word_time &
619 alt_addr_comp_en[12] &
620 (rx_byte0 == mac_alt_addr12[`BYTE1]) & // a
621 (rx_byte1 == mac_alt_addr12[`BYTE0]) & // b
622 (rx_byte2 == mac_alt_addr12[`BYTE3]) & // c
623 (rx_byte3 == mac_alt_addr12[`BYTE2]) & // d
624 (rx_byte4 == mac_alt_addr12[`BYTE5]) & // e
625 (rx_byte5 == mac_alt_addr12[`BYTE4]) ; // f
626
627/* -------------------- mac alternative addr13 match ------------------ */
628 // a pulse
629 assign set_mac_alt_addr13_match = rx_1st_word_time &
630 alt_addr_comp_en[13] &
631 (rx_byte0 == mac_alt_addr13[`BYTE1]) & // a
632 (rx_byte1 == mac_alt_addr13[`BYTE0]) & // b
633 (rx_byte2 == mac_alt_addr13[`BYTE3]) & // c
634 (rx_byte3 == mac_alt_addr13[`BYTE2]) & // d
635 (rx_byte4 == mac_alt_addr13[`BYTE5]) & // e
636 (rx_byte5 == mac_alt_addr13[`BYTE4]) ; // f
637
638/* -------------------- mac alternative addr14 match ------------------ */
639 // a pulse
640 assign set_mac_alt_addr14_match = rx_1st_word_time &
641 alt_addr_comp_en[14] &
642 (rx_byte0 == mac_alt_addr14[`BYTE1]) & // a
643 (rx_byte1 == mac_alt_addr14[`BYTE0]) & // b
644 (rx_byte2 == mac_alt_addr14[`BYTE3]) & // c
645 (rx_byte3 == mac_alt_addr14[`BYTE2]) & // d
646 (rx_byte4 == mac_alt_addr14[`BYTE5]) & // e
647 (rx_byte5 == mac_alt_addr14[`BYTE4]) ; // f
648
649/* -------------------- mac alternative addr15 match ------------------ */
650 // a pulse
651 assign set_mac_alt_addr15_match = rx_1st_word_time &
652 alt_addr_comp_en[15] &
653 (rx_byte0 == mac_alt_addr15[`BYTE1]) & // a
654 (rx_byte1 == mac_alt_addr15[`BYTE0]) & // b
655 (rx_byte2 == mac_alt_addr15[`BYTE3]) & // c
656 (rx_byte3 == mac_alt_addr15[`BYTE2]) & // d
657 (rx_byte4 == mac_alt_addr15[`BYTE5]) & // e
658 (rx_byte5 == mac_alt_addr15[`BYTE4]) ; // f
659
660
661/* --------- conclusion of all 64 mac's alt address matches------------ */
662 assign set_all_mac_alt_addr_match = set_mac_alt_addr0_match |
663 set_mac_alt_addr1_match |
664 set_mac_alt_addr2_match |
665 set_mac_alt_addr3_match |
666 set_mac_alt_addr4_match |
667 set_mac_alt_addr5_match |
668 set_mac_alt_addr6_match |
669 set_mac_alt_addr7_match |
670 set_mac_alt_addr8_match |
671 set_mac_alt_addr9_match |
672 set_mac_alt_addr10_match |
673 set_mac_alt_addr11_match |
674 set_mac_alt_addr12_match |
675 set_mac_alt_addr13_match |
676 set_mac_alt_addr14_match |
677 set_mac_alt_addr15_match ;
678
679 RS_FF all_mac_alt_addr_match_RS_FF (.set(set_all_mac_alt_addr_match),
680 .rst(1'b0),
681 .clk(rx_clk),
682 .reset(rx_reset_counters),
683 .qout(all_mac_alt_addr_match));
684
685/* -------------------- mac address value generation ------------------ */
686 wire [6:0] alt_addr_filter_value = 0;
687
688
689/* -------------------- mac control word generation --------------- */
690 reg [`MAC_CTRL] mac_info;
691 wire [`MAC_CTRL] mac_ctrl_word;
692 wire p_hit = 1'b1;// p_hit == 1: perfect match | hash hit
693 // p_hit == 0: non of above
694
695always @ (/*AUTOSENSE*/mac_host_info0 or mac_host_info1
696 or mac_host_info10 or mac_host_info11 or mac_host_info12
697 or mac_host_info13 or mac_host_info14 or mac_host_info15
698 or mac_host_info16 or mac_host_info17 or mac_host_info18
699 or mac_host_info19 or mac_host_info2 or mac_host_info3
700 or mac_host_info4 or mac_host_info5 or mac_host_info6
701 or mac_host_info7 or mac_host_info8 or mac_host_info9
702 or p_hit or promisc_all or set_addr_filter_match
703 or set_hash_hit_match or set_mac_alt_addr0_match
704 or set_mac_alt_addr10_match or set_mac_alt_addr11_match
705 or set_mac_alt_addr12_match or set_mac_alt_addr13_match
706 or set_mac_alt_addr14_match or set_mac_alt_addr15_match
707 or set_mac_alt_addr1_match or set_mac_alt_addr2_match
708 or set_mac_alt_addr3_match or set_mac_alt_addr4_match
709 or set_mac_alt_addr5_match or set_mac_alt_addr6_match
710 or set_mac_alt_addr7_match or set_mac_alt_addr8_match
711 or set_mac_alt_addr9_match or set_mac_fc_match
712 or set_mac_own_da_match)
713 begin
714 if (set_mac_alt_addr0_match)
715 mac_info = {mac_host_info0,p_hit,promisc_all} ;
716 else if (set_mac_alt_addr1_match)
717 mac_info = {mac_host_info1,p_hit,promisc_all} ;
718 else if (set_mac_alt_addr2_match)
719 mac_info = {mac_host_info2,p_hit,promisc_all} ;
720 else if (set_mac_alt_addr3_match)
721 mac_info = {mac_host_info3,p_hit,promisc_all} ;
722 else if (set_mac_alt_addr4_match)
723 mac_info = {mac_host_info4,p_hit,promisc_all} ;
724 else if (set_mac_alt_addr5_match)
725 mac_info = {mac_host_info5,p_hit,promisc_all} ;
726 else if (set_mac_alt_addr6_match)
727 mac_info = {mac_host_info6,p_hit,promisc_all} ;
728 else if (set_mac_alt_addr7_match)
729 mac_info = {mac_host_info7,p_hit,promisc_all} ;
730 else if (set_mac_alt_addr8_match)
731 mac_info = {mac_host_info8,p_hit,promisc_all} ;
732 else if (set_mac_alt_addr9_match)
733 mac_info = {mac_host_info9,p_hit,promisc_all} ;
734 else if (set_mac_alt_addr10_match)
735 mac_info = {mac_host_info10,p_hit,promisc_all} ;
736 else if (set_mac_alt_addr11_match)
737 mac_info = {mac_host_info11,p_hit,promisc_all} ;
738 else if (set_mac_alt_addr12_match)
739 mac_info = {mac_host_info12,p_hit,promisc_all} ;
740 else if (set_mac_alt_addr13_match)
741 mac_info = {mac_host_info13,p_hit,promisc_all} ;
742 else if (set_mac_alt_addr14_match)
743 mac_info = {mac_host_info14,p_hit,promisc_all} ;
744 else if (set_mac_alt_addr15_match)
745 mac_info = {mac_host_info15,p_hit,promisc_all} ;
746 else if (set_hash_hit_match)// perfect match has higher pri over hash hit.
747 mac_info = {mac_host_info16,p_hit,promisc_all} ;
748 else if (set_mac_own_da_match) // station unique address
749 mac_info = {mac_host_info17,p_hit,promisc_all} ;
750 else if (set_addr_filter_match)
751 mac_info = {mac_host_info18,p_hit,promisc_all} ;
752 else if (set_mac_fc_match)
753 mac_info = {mac_host_info19,p_hit,promisc_all} ;
754 else
755 // no perfet hit or hash hit.
756 // This condition will happen only when
757 // promiscuous all, promiscuous group, broadcast packets.
758 mac_info = {mac_host_info16,1'b0,promisc_all} ;
759 end
760
761 // The following reason for registering mac_info:
762 // 1. mac_info should be written ONLY when mac_alt_addr is a match or
763 // the packet will be filterred out in the first place. The packet
764 // won't even be written to packet fifo (rxfifo).
765 // 2. mac_info aligned with set_all_mac_alt_addr_match. This is a pre
766 // registration of mac_info right before written to srfifo.
767 //
768 // mac_info[`MAC_CTRL] <- set_all_mac_alt_addr_match
769 //
770 // | | <- register
771 // v v
772 //
773 // mac_ctrl_word[`MAC_CTRL] <- mac_ctrl_word_wr_en
774 //
775 // 3. mac_ctrl_word has to line up with the first word (64bit) to be
776 // written to rxfifo.
777 // 4. to compensate the mac_ctrl_word delay and to align with
778 // eop time (reg1 time).
779
780 xREG #(`MAC_CTRL_WIDTH) mac_ctrl_word_xREG(.din(mac_info),
781 .clk(rx_clk),
782 .en(rx_ok),
783 .reset(rx_reset),
784 .qout(mac_ctrl_word));
785 // rx_ok is from xrlm_sm. It is a pulse. It is valid at rx_1st_word_time.
786 FD1 mac_ctrl_word_wr_en_FD1 (.D(rx_ok),
787 .CP(rx_clk),
788 .Q(mac_ctrl_word_wr_en)); // rx_2nd_word_time
789
790
791`else // !ifdef ALT_ADDR_AND_HASH_FUNC
792 wire hash_hit_match = 0;
793 wire [15:0] hash_value = 0;
794 wire [6:0] alt_addr_filter_value = 0;
795`endif // !ifdef ALT_ADDR_AND_HASH_FUNC
796
797/**************************************************************************
798 * end of ALT_ADDR_AND_HASH_FUNC selectable logic
799 * ************************************************************************/
800
801endmodule // address_decoder
802
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