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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: debug.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * debug.v | |
38 | * | |
39 | * Global Debug Module | |
40 | * | |
41 | * Orignal Author(s): Rahoul Puri | |
42 | * Modifier(s): Maya Suresh, Elisa Rodrigues | |
43 | * Project(s): Neptune/Niagara 2 | |
44 | * | |
45 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
46 | * | |
47 | * All Rights Reserved. | |
48 | * | |
49 | * This verilog model is the confidential and proprietary property of | |
50 | * Sun Microsystems, Inc., and the possession or use of this model | |
51 | * requires a written license from Sun Microsystems, Inc. | |
52 | * | |
53 | **********************************************************************/ | |
54 | ||
55 | module debug (/*AUTOARG*/ | |
56 | // Outputs | |
57 | debug_port_data_out, debug_clock0_out, debug_clock1_out, | |
58 | // Inputs | |
59 | debug_port_sel_in, txc_debug_port, tdmc_debug_port, | |
60 | rdmc_debug_port, zcp_debug_port, ipp_debug_port, fflp_debug_port, | |
61 | pio_debug_port, mac_debug_port, | |
62 | meta_arb_debug_port, | |
63 | niu_clk, | |
64 | ||
65 | `ifdef NEPTUNE | |
66 | mac_debug_clock0, | |
67 | mac_debug_clock1, | |
68 | peu_debug_port, | |
69 | peu_debug_clock0, | |
70 | peu_debug_clock1, | |
71 | peu_phy_debug_out, | |
72 | peu_phy_debug_sel, | |
73 | ext_spc_stuck | |
74 | `else | |
75 | smx_debug_port | |
76 | `endif | |
77 | ||
78 | ); | |
79 | ||
80 | ||
81 | // Debug IO Ports (to/from pads) | |
82 | input [4:0] debug_port_sel_in; // connect to test_sel_x_in on top (from pads) | |
83 | ||
84 | output [31:0] debug_port_data_out; // output to pads | |
85 | ||
86 | // NIU Debug Ports | |
87 | input [31:0] txc_debug_port; | |
88 | input [31:0] tdmc_debug_port; | |
89 | input [31:0] rdmc_debug_port; | |
90 | input [31:0] zcp_debug_port; | |
91 | input [31:0] ipp_debug_port; | |
92 | input [31:0] fflp_debug_port; | |
93 | input [31:0] pio_debug_port; | |
94 | input [31:0] mac_debug_port; | |
95 | input [31:0] meta_arb_debug_port; | |
96 | ||
97 | input niu_clk; | |
98 | ||
99 | `ifdef NEPTUNE | |
100 | input [31:0] peu_debug_port; | |
101 | input peu_debug_clock0; | |
102 | input peu_debug_clock1; | |
103 | input mac_debug_clock0; | |
104 | input mac_debug_clock1; | |
105 | input [31:0] peu_phy_debug_out; | |
106 | output [1:0] peu_phy_debug_sel; | |
107 | output ext_spc_stuck; | |
108 | `else | |
109 | input [31:0] smx_debug_port; | |
110 | `endif | |
111 | ||
112 | ||
113 | ||
114 | // add input of clock from diff domain | |
115 | ||
116 | output debug_clock0_out; // output to pads | |
117 | output debug_clock1_out; | |
118 | ||
119 | reg [31:0] debug_port_data_out; | |
120 | reg debug_clock0_out; | |
121 | reg debug_clock1_out; | |
122 | reg niu_clk_divby2; | |
123 | reg niu_clk_divby4; | |
124 | reg niu_clk_divby8; | |
125 | //reg [1:0] peu_phy_debug_sel; | |
126 | ||
127 | `ifdef NEPTUNE | |
128 | reg mac_debug_clock0_divby2; | |
129 | reg mac_debug_clock0_divby4; | |
130 | reg mac_debug_clock0_divby8; | |
131 | reg mac_debug_clock1_divby2; | |
132 | reg mac_debug_clock1_divby4; | |
133 | reg mac_debug_clock1_divby8; | |
134 | reg peu_debug_clock0_divby2; | |
135 | reg peu_debug_clock0_divby4; | |
136 | reg peu_debug_clock0_divby8; | |
137 | reg peu_debug_clock1_divby2; | |
138 | reg peu_debug_clock1_divby4; | |
139 | reg peu_debug_clock1_divby8; | |
140 | reg [1:0] peu_phy_debug_sel; | |
141 | wire ext_spc_stuck; | |
142 | wire [31:0] smx_debug_port= 32'h0; | |
143 | `else | |
144 | wire [31:0] peu_debug_port= 32'h0; | |
145 | // wire peu_debug_clock0= 1'b0; | |
146 | // wire peu_debug_clock1= 1'b0; | |
147 | // wire mac_debug_clock0= 1'b0; | |
148 | // wire mac_debug_clock1= 1'b0; | |
149 | //wire mac_debug_clock0_divby2 = 1'b0; VJH | |
150 | //wire mac_debug_clock0_divby4 = 1'b0; VJH | |
151 | wire mac_debug_clock0_divby8 = 1'b0; | |
152 | //wire mac_debug_clock1_divby2 = 1'b0; VJH | |
153 | //wire mac_debug_clock1_divby4 = 1'b0; VJH | |
154 | wire mac_debug_clock1_divby8 = 1'b0; | |
155 | //wire peu_debug_clock0_divby2 = 1'b0; VJH | |
156 | //wire peu_debug_clock0_divby4 = 1'b0; VJH | |
157 | wire peu_debug_clock0_divby8 = 1'b0; | |
158 | //wire peu_debug_clock1_divby2 = 1'b0; VJH | |
159 | //wire peu_debug_clock1_divby4 = 1'b0; VJH | |
160 | wire peu_debug_clock1_divby8 = 1'b0; | |
161 | //wire [31:0] peu_phy_debug_out = 32'h0; VJH | |
162 | `endif | |
163 | ||
164 | `ifdef NEPTUNE | |
165 | always @(/*AUTOSENSE*/debug_port_sel_in or fflp_debug_port | |
166 | or ipp_debug_port or mac_debug_port or meta_arb_debug_port | |
167 | or peu_debug_port or pio_debug_port or rdmc_debug_port | |
168 | or smx_debug_port or tdmc_debug_port or txc_debug_port | |
169 | or zcp_debug_port or peu_phy_debug_out) | |
170 | `else | |
171 | always @(/*AUTOSENSE*/debug_port_sel_in or fflp_debug_port | |
172 | or ipp_debug_port or mac_debug_port or meta_arb_debug_port | |
173 | or peu_debug_port or pio_debug_port or rdmc_debug_port | |
174 | or smx_debug_port or tdmc_debug_port or txc_debug_port | |
175 | or zcp_debug_port ) | |
176 | `endif | |
177 | begin | |
178 | case(debug_port_sel_in) // Synopsys full_case parallel_case | |
179 | 5'h11 : debug_port_data_out = txc_debug_port; | |
180 | 5'h12 : debug_port_data_out = tdmc_debug_port; | |
181 | 5'h13 : debug_port_data_out = rdmc_debug_port; | |
182 | 5'h14 : debug_port_data_out = zcp_debug_port; | |
183 | 5'h15 : debug_port_data_out = ipp_debug_port; | |
184 | 5'h16 : debug_port_data_out = fflp_debug_port; | |
185 | 5'h17 : debug_port_data_out = pio_debug_port; | |
186 | 5'h18 : debug_port_data_out = mac_debug_port; | |
187 | 5'h19 : debug_port_data_out = peu_debug_port; | |
188 | 5'h1a : debug_port_data_out = meta_arb_debug_port; | |
189 | 5'h1b : debug_port_data_out = smx_debug_port; | |
190 | `ifdef NEPTUNE | |
191 | 5'h1c : debug_port_data_out = peu_phy_debug_out; | |
192 | 5'h1d : debug_port_data_out = peu_phy_debug_out; | |
193 | 5'h1e : debug_port_data_out = peu_phy_debug_out; | |
194 | 5'h1f : debug_port_data_out = peu_phy_debug_out; | |
195 | `endif | |
196 | default : debug_port_data_out = 32'h0; | |
197 | endcase | |
198 | end | |
199 | ||
200 | // generate niu_clk_divby2,niu_clk_divby4,niu_clk_divby8 | |
201 | ||
202 | always @(posedge niu_clk) | |
203 | begin | |
204 | niu_clk_divby2 <= ~niu_clk_divby2; | |
205 | end | |
206 | ||
207 | always @(posedge niu_clk_divby2) | |
208 | begin | |
209 | niu_clk_divby4 <= ~niu_clk_divby4; | |
210 | end | |
211 | ||
212 | always @(posedge niu_clk_divby4) | |
213 | begin | |
214 | niu_clk_divby8 <= ~niu_clk_divby8; | |
215 | end | |
216 | ||
217 | // generate mac_debug_clock0_divby2 & | |
218 | // generate mac_debug_clock1_divby2 in neptune mode only | |
219 | // this is driven to zero in n2 mode | |
220 | ||
221 | `ifdef NEPTUNE | |
222 | ||
223 | always @(posedge mac_debug_clock0) | |
224 | begin | |
225 | mac_debug_clock0_divby2 = ~mac_debug_clock0_divby2; | |
226 | end | |
227 | ||
228 | always @(posedge mac_debug_clock0_divby2) | |
229 | begin | |
230 | mac_debug_clock0_divby4 = ~mac_debug_clock0_divby4; | |
231 | end | |
232 | ||
233 | always @(posedge mac_debug_clock0_divby4) | |
234 | begin | |
235 | mac_debug_clock0_divby8 = ~mac_debug_clock0_divby8; | |
236 | end | |
237 | ||
238 | ||
239 | ||
240 | always @(posedge mac_debug_clock1) | |
241 | begin | |
242 | mac_debug_clock1_divby2 = ~mac_debug_clock1_divby2; | |
243 | end | |
244 | ||
245 | always @(posedge mac_debug_clock1_divby2) | |
246 | begin | |
247 | mac_debug_clock1_divby4 = ~mac_debug_clock1_divby4; | |
248 | end | |
249 | ||
250 | always @(posedge mac_debug_clock1_divby4) | |
251 | begin | |
252 | mac_debug_clock1_divby8 = ~mac_debug_clock1_divby8; | |
253 | end | |
254 | ||
255 | `endif | |
256 | ||
257 | // generate peu_debug_clock0_divby2 & | |
258 | // generate peu_debug_clock1_divby2 in neptune mode only | |
259 | // this is driven to zero in n2 mode | |
260 | ||
261 | `ifdef NEPTUNE | |
262 | ||
263 | always @(posedge peu_debug_clock0) | |
264 | begin | |
265 | peu_debug_clock0_divby2 = ~peu_debug_clock0_divby2; | |
266 | end | |
267 | ||
268 | always @(posedge peu_debug_clock0_divby2) | |
269 | begin | |
270 | peu_debug_clock0_divby4 = ~peu_debug_clock0_divby4; | |
271 | end | |
272 | ||
273 | always @(posedge peu_debug_clock0_divby4) | |
274 | begin | |
275 | peu_debug_clock0_divby8 = ~peu_debug_clock0_divby8; | |
276 | end | |
277 | ||
278 | always @(posedge peu_debug_clock1) | |
279 | begin | |
280 | peu_debug_clock1_divby2 = ~peu_debug_clock1_divby2; | |
281 | end | |
282 | ||
283 | always @(posedge peu_debug_clock1_divby2) | |
284 | begin | |
285 | peu_debug_clock1_divby4 = ~peu_debug_clock1_divby4; | |
286 | end | |
287 | ||
288 | always @(posedge peu_debug_clock1_divby4) | |
289 | begin | |
290 | peu_debug_clock1_divby8 = ~peu_debug_clock1_divby8; | |
291 | end | |
292 | ||
293 | `endif | |
294 | ||
295 | ||
296 | ||
297 | ||
298 | always @(/*AUTOSENSE*/debug_port_sel_in or mac_debug_clock0_divby8 or niu_clk_divby8 | |
299 | or peu_debug_clock0_divby8) | |
300 | begin | |
301 | case(debug_port_sel_in) // Synopsys full_case parallel_case | |
302 | 5'h0 : debug_clock0_out=1'b0; | |
303 | 5'h8 : debug_clock0_out= mac_debug_clock0_divby8; | |
304 | 5'h9 : debug_clock0_out= peu_debug_clock0_divby8; | |
305 | default : debug_clock0_out= niu_clk_divby8; | |
306 | endcase | |
307 | end | |
308 | ||
309 | ||
310 | // added code for driving peu_phy_sel signal | |
311 | `ifdef NEPTUNE | |
312 | always @(/*AUTOSENSE*/debug_port_sel_in) | |
313 | begin | |
314 | case(debug_port_sel_in) // Synopsys full_case parallel_case | |
315 | 5'h1c : peu_phy_debug_sel = 2'b00; | |
316 | 5'h1d : peu_phy_debug_sel = 2'b01; | |
317 | 5'h1e : peu_phy_debug_sel = 2'b10; | |
318 | 5'h1f : peu_phy_debug_sel = 2'b11; | |
319 | default : peu_phy_debug_sel = 2'b00; | |
320 | endcase | |
321 | end | |
322 | `endif | |
323 | ||
324 | always @(/*AUTOSENSE*/debug_port_sel_in or mac_debug_clock1_divby8 or niu_clk_divby8 | |
325 | or peu_debug_clock1_divby8) | |
326 | begin | |
327 | case(debug_port_sel_in) // Synopsys full_case parallel_case | |
328 | 5'h0 : debug_clock1_out= 1'b0; | |
329 | 5'h8 : debug_clock1_out= mac_debug_clock1_divby8; | |
330 | 5'h9 : debug_clock1_out= peu_debug_clock1_divby8; | |
331 | default : debug_clock1_out= niu_clk_divby8; | |
332 | endcase | |
333 | end | |
334 | ||
335 | // add code to drive the ext_spc_stuck signal, | |
336 | // when sel is 5'h1b | |
337 | ||
338 | `ifdef NEPTUNE | |
339 | assign ext_spc_stuck = (debug_port_sel_in == 5'h1b); | |
340 | `endif | |
341 | ||
342 | ||
343 | endmodule |