projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: fflp.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | /**********************************************************************/ | |
| 36 | /*project name: NIU */ | |
| 37 | /*module name: fflp */ | |
| 38 | /*description: Receive classification */ | |
| 39 | /* */ | |
| 40 | /*parent module in: top */ | |
| 41 | /*child modules in: none */ | |
| 42 | /*interface modules: */ | |
| 43 | /*author name: Jeanne Cai */ | |
| 44 | /*date created: 03-22-2004 */ | |
| 45 | /* */ | |
| 46 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
| 47 | /* Sun Proprietary and Confidential */ | |
| 48 | /* */ | |
| 49 | /*modifications: */ | |
| 50 | /**********************************************************************/ | |
| 51 | ||
| 52 | //`include "fflp.h" | |
| 53 | ||
| 54 | module fflp | |
| 55 | ( | |
| 56 | cclk, | |
| 57 | reset_l, | |
| 58 | //ipp if | |
| 59 | ipp_fflp_dvalid, | |
| 60 | ipp_fflp_data, | |
| 61 | ipp_fflp_mac_default, | |
| 62 | ipp_fflp_mac_port, | |
| 63 | ||
| 64 | fflp_ipp_ready, | |
| 65 | fflp_ipp_dvalid, | |
| 66 | fflp_ipp_data, | |
| 67 | //cam if | |
| 68 | cam_hit, | |
| 69 | cam_valid, | |
| 70 | cam_haddr, | |
| 71 | pio_rd_vld, | |
| 72 | cam_msk_dat_out, | |
| 73 | ||
| 74 | cam_data_inp, | |
| 75 | cam_compare, | |
| 76 | cam_pio_wr, | |
| 77 | cam_pio_rd, | |
| 78 | cam_pio_sel, | |
| 79 | cam_index, | |
| 80 | //ram if | |
| 81 | am_din, | |
| 82 | ||
| 83 | am_rd, | |
| 84 | am_wr, | |
| 85 | am_addr, | |
| 86 | am_dout, | |
| 87 | //zcp if | |
| 88 | fflp_zcp_wr, | |
| 89 | fflp_zcp_data, | |
| 90 | //pio if | |
| 91 | pio_fflp_wdata, | |
| 92 | pio_fflp_rd, | |
| 93 | pio_fflp_sel, | |
| 94 | pio_fflp_addr, | |
| 95 | ||
| 96 | `ifdef NEPTUNE | |
| 97 | pio_client_32b, | |
| 98 | `endif | |
| 99 | ||
| 100 | fflp_pio_rdata, | |
| 101 | fflp_pio_ack, | |
| 102 | fflp_pio_err, | |
| 103 | fflp_pio_intr, | |
| 104 | //vlan table | |
| 105 | vlan_tbl_rd_din, | |
| 106 | vlan_tbl_cs, | |
| 107 | vlan_tbl_wr, | |
| 108 | vlan_tbl_addr, | |
| 109 | vlan_tbl_wr_dout, | |
| 110 | ||
| 111 | //fcram if | |
| 112 | `ifdef NEPTUNE | |
| 113 | fcram_clk, | |
| 114 | fcram_fflp_mstrready, | |
| 115 | fcram_fflp_fatal_err, | |
| 116 | fcram_fflp_data_ready, | |
| 117 | fcram_fflp_even_din, | |
| 118 | fcram_fflp_odd_din, | |
| 119 | fcram_fflp_cfg_datrd, | |
| 120 | fcram_fflp_cfg_done, | |
| 121 | fcram_fflp_cfg_err, | |
| 122 | ||
| 123 | fflp_fcram_cfg_rst, | |
| 124 | fflp_fcram_cfg_sel, | |
| 125 | fflp_fcram_cfg_rd, | |
| 126 | fflp_fcram_cfg_addr, | |
| 127 | fflp_fcram_cfg_datwr, | |
| 128 | fflp_fcram_slv_update, | |
| 129 | fflp_fcram_rd_en, | |
| 130 | fflp_fcram_cs_l, | |
| 131 | fflp_fcram_fn, | |
| 132 | fflp_fcram_pd_l, | |
| 133 | fflp_fcram_ba0, | |
| 134 | fflp_fcram_ba1, | |
| 135 | fflp_fcram_addr, | |
| 136 | fflp_fcram_ds, | |
| 137 | fflp_fcram_triz_en_l, | |
| 138 | fflp_fcram_even_dout, | |
| 139 | fflp_fcram_odd_dout, | |
| 140 | `endif | |
| 141 | ||
| 142 | fflp_debug_port | |
| 143 | ||
| 144 | ); | |
| 145 | ||
| 146 | input cclk; | |
| 147 | input reset_l; | |
| 148 | ||
| 149 | input ipp_fflp_dvalid; | |
| 150 | input[127:0] ipp_fflp_data; | |
| 151 | input[11:0] ipp_fflp_mac_default; | |
| 152 | input[1:0] ipp_fflp_mac_port; | |
| 153 | output fflp_ipp_ready; | |
| 154 | output[3:0] fflp_ipp_dvalid; | |
| 155 | output[15:0] fflp_ipp_data; | |
| 156 | ||
| 157 | input cam_hit; | |
| 158 | input cam_valid; | |
| 159 | input[9:0] cam_haddr; | |
| 160 | input pio_rd_vld; | |
| 161 | input[199:0] cam_msk_dat_out; | |
| 162 | output[199:0] cam_data_inp; | |
| 163 | output cam_compare; | |
| 164 | output cam_pio_wr; | |
| 165 | output cam_pio_rd; | |
| 166 | output cam_pio_sel; | |
| 167 | output[9:0] cam_index; | |
| 168 | ||
| 169 | input[41:0] am_din; | |
| 170 | output am_rd; | |
| 171 | output am_wr; | |
| 172 | output[9:0] am_addr; | |
| 173 | output[41:0] am_dout; | |
| 174 | ||
| 175 | output[4:0] fflp_zcp_wr; | |
| 176 | output[215:0] fflp_zcp_data; | |
| 177 | ||
| 178 | input[63:0] pio_fflp_wdata; | |
| 179 | input pio_fflp_rd; | |
| 180 | input pio_fflp_sel; | |
| 181 | input[19:0] pio_fflp_addr; | |
| 182 | ||
| 183 | `ifdef NEPTUNE | |
| 184 | input pio_client_32b; | |
| 185 | `endif | |
| 186 | ||
| 187 | output[63:0] fflp_pio_rdata; | |
| 188 | output fflp_pio_ack; | |
| 189 | output fflp_pio_err; | |
| 190 | output fflp_pio_intr; | |
| 191 | ||
| 192 | input[17:0] vlan_tbl_rd_din; | |
| 193 | output vlan_tbl_cs; | |
| 194 | output vlan_tbl_wr; | |
| 195 | output[11:0] vlan_tbl_addr; | |
| 196 | output[17:0] vlan_tbl_wr_dout; | |
| 197 | ||
| 198 | `ifdef NEPTUNE | |
| 199 | input fcram_clk; | |
| 200 | input fcram_fflp_mstrready; | |
| 201 | input fcram_fflp_fatal_err; | |
| 202 | input[3:0] fcram_fflp_data_ready; | |
| 203 | input[35:0] fcram_fflp_even_din; | |
| 204 | input[35:0] fcram_fflp_odd_din; | |
| 205 | input[15:0] fcram_fflp_cfg_datrd; | |
| 206 | input fcram_fflp_cfg_done; | |
| 207 | input fcram_fflp_cfg_err; | |
| 208 | ||
| 209 | output fflp_fcram_cfg_rst; | |
| 210 | output fflp_fcram_cfg_sel; | |
| 211 | output fflp_fcram_cfg_rd; | |
| 212 | output[7:0] fflp_fcram_cfg_addr; | |
| 213 | output[15:0] fflp_fcram_cfg_datwr; | |
| 214 | output fflp_fcram_slv_update; | |
| 215 | output[1:0] fflp_fcram_rd_en; | |
| 216 | output fflp_fcram_cs_l; | |
| 217 | output fflp_fcram_fn; | |
| 218 | output fflp_fcram_pd_l; | |
| 219 | output fflp_fcram_ba0; | |
| 220 | output fflp_fcram_ba1; | |
| 221 | output[14:0] fflp_fcram_addr; | |
| 222 | output[1:0] fflp_fcram_ds; | |
| 223 | output[1:0] fflp_fcram_triz_en_l; | |
| 224 | output[35:0] fflp_fcram_even_dout; | |
| 225 | output[35:0] fflp_fcram_odd_dout; | |
| 226 | `endif | |
| 227 | ||
| 228 | output[31:0] fflp_debug_port; | |
| 229 | ||
| 230 | `ifdef NEPTUNE | |
| 231 | `else | |
| 232 | ||
| 233 | wire pio_client_32b = 1'b0; | |
| 234 | wire fcram_clk = cclk; | |
| 235 | wire fcram_fflp_mstrready = 1'b0; | |
| 236 | wire fcram_fflp_fatal_err = 1'b0; | |
| 237 | wire[3:0] fcram_fflp_data_ready = 4'b0; | |
| 238 | wire[35:0] fcram_fflp_even_din = 36'b0; | |
| 239 | wire[35:0] fcram_fflp_odd_din = 36'b0; | |
| 240 | wire[15:0] fcram_fflp_cfg_datrd = 16'b0; | |
| 241 | wire fcram_fflp_cfg_done = 1'b0; | |
| 242 | wire fcram_fflp_cfg_err = 1'b0; | |
| 243 | ||
| 244 | `endif | |
| 245 | ||
| 246 | ||
| 247 | wire ipp_fflp_dvalid; | |
| 248 | wire[127:0] ipp_fflp_data; | |
| 249 | wire[11:0] ipp_fflp_mac_default; | |
| 250 | wire[1:0] ipp_fflp_mac_port; | |
| 251 | wire fflp_ipp_ready; | |
| 252 | wire[3:0] fflp_ipp_dvalid; | |
| 253 | wire[15:0] fflp_ipp_data; | |
| 254 | ||
| 255 | wire cam_hit; | |
| 256 | wire cam_valid; | |
| 257 | wire[9:0] cam_haddr; | |
| 258 | wire pio_rd_vld; | |
| 259 | wire[199:0] cam_msk_dat_out; | |
| 260 | wire[199:0] cam_data_inp; | |
| 261 | wire cam_compare; | |
| 262 | wire cam_pio_wr; | |
| 263 | wire cam_pio_rd; | |
| 264 | wire cam_pio_sel; | |
| 265 | wire[9:0] cam_index; | |
| 266 | ||
| 267 | wire[41:0] am_din; | |
| 268 | wire am_rd; | |
| 269 | wire am_wr; | |
| 270 | wire[9:0] am_addr; | |
| 271 | wire[41:0] am_dout; | |
| 272 | ||
| 273 | wire[4:0] fflp_zcp_wr; | |
| 274 | wire[215:0] fflp_zcp_data; | |
| 275 | ||
| 276 | wire[63:0] pio_fflp_wdata; | |
| 277 | wire pio_fflp_rd; | |
| 278 | wire pio_fflp_sel; | |
| 279 | wire[19:0] pio_fflp_addr; | |
| 280 | wire[63:0] fflp_pio_rdata; | |
| 281 | wire fflp_pio_ack; | |
| 282 | wire fflp_pio_err; | |
| 283 | wire fflp_pio_intr; | |
| 284 | ||
| 285 | wire snap_en; | |
| 286 | wire disable_chksum; | |
| 287 | wire pio_disable_cam; | |
| 288 | wire[16:0] class2_hdr_byte_value; | |
| 289 | wire[16:0] class3_hdr_byte_value; | |
| 290 | wire[25:0] class4_hdr_byte_value; | |
| 291 | wire[25:0] class5_hdr_byte_value; | |
| 292 | wire[25:0] class6_hdr_byte_value; | |
| 293 | wire[25:0] class7_hdr_byte_value; | |
| 294 | wire[2:0] class_action_reg4_dout; | |
| 295 | wire[2:0] class_action_reg5_dout; | |
| 296 | wire[2:0] class_action_reg6_dout; | |
| 297 | wire[2:0] class_action_reg7_dout; | |
| 298 | wire[2:0] class_action_reg8_dout; | |
| 299 | wire[2:0] class_action_reg9_dout; | |
| 300 | wire[2:0] class_action_reg10_dout; | |
| 301 | wire[2:0] class_action_reg11_dout; | |
| 302 | wire[2:0] class_action_reg12_dout; | |
| 303 | wire[2:0] class_action_reg13_dout; | |
| 304 | wire[2:0] class_action_reg14_dout; | |
| 305 | wire[2:0] class_action_reg15_dout; | |
| 306 | wire[9:0] f_key_class_action_reg4_dout; | |
| 307 | wire[9:0] f_key_class_action_reg5_dout; | |
| 308 | wire[9:0] f_key_class_action_reg6_dout; | |
| 309 | wire[9:0] f_key_class_action_reg7_dout; | |
| 310 | wire[9:0] f_key_class_action_reg8_dout; | |
| 311 | wire[9:0] f_key_class_action_reg9_dout; | |
| 312 | wire[9:0] f_key_class_action_reg10_dout; | |
| 313 | wire[9:0] f_key_class_action_reg11_dout; | |
| 314 | wire[9:0] f_key_class_action_reg12_dout; | |
| 315 | wire[9:0] f_key_class_action_reg13_dout; | |
| 316 | wire[9:0] f_key_class_action_reg14_dout; | |
| 317 | wire[9:0] f_key_class_action_reg15_dout; | |
| 318 | wire[11:0] hdr_ctrl_bit_mask_reg_dout; | |
| 319 | wire fflp_config_reg_wen_pulse; | |
| 320 | wire[31:0] debug_training_vector; | |
| 321 | wire[2:0] pio_debug_data_sel; | |
| 322 | ||
| 323 | wire fwd_sched; | |
| 324 | wire fwd_req; | |
| 325 | wire[199:0] key_bus; | |
| 326 | wire[445:0] fwd_info_bus; | |
| 327 | ||
| 328 | wire fc_fifo_empty; | |
| 329 | wire[512:0] fc_fifo_dout; | |
| 330 | wire fc_fifo_ren_sync; | |
| 331 | ||
| 332 | wire fflp_init_done; | |
| 333 | wire[3:0] fcram_driver_imp_ctrl; | |
| 334 | wire fcram_qs_mode; | |
| 335 | wire[3:0] fcram_lookup_ratio; | |
| 336 | wire[1:0] pio_fio_latency; | |
| 337 | wire[3:0] cam_srch_latency; | |
| 338 | wire[3:0] cam_srch_ratio; | |
| 339 | wire pio_wen; | |
| 340 | wire[19:0] pio_addr; | |
| 341 | wire pio_32b_mode; | |
| 342 | wire[63:0] pio_wr_data; | |
| 343 | wire[7:0] cam_key_reg0_dout; | |
| 344 | wire[63:0] cam_key_reg1_dout; | |
| 345 | wire[63:0] cam_key_reg2_dout; | |
| 346 | wire[63:0] cam_key_reg3_dout; | |
| 347 | wire[7:0] cam_key_mask_reg0_dout; | |
| 348 | wire[63:0] cam_key_mask_reg1_dout; | |
| 349 | wire[63:0] cam_key_mask_reg2_dout; | |
| 350 | wire[63:0] cam_key_mask_reg3_dout; | |
| 351 | wire[20:0] cam_cmd_stat_reg_dout; | |
| 352 | wire[25:0] ecc_parity_status; | |
| 353 | ||
| 354 | wire[31:0] h1_init_value_reg_dout; | |
| 355 | wire[15:0] h2_init_value_reg_dout; | |
| 356 | wire[31:0] fcram_refresh_timer_reg_dout; | |
| 357 | ||
| 358 | wire cpu_vlan_req; | |
| 359 | wire cpu_vlan_rd; | |
| 360 | wire cpu_vlan_wr; | |
| 361 | wire[11:0] cpu_vlan_addr; | |
| 362 | wire[17:0] vlan_tbl_wr_dout; | |
| 363 | ||
| 364 | wire[17:0] vlan_tbl_rd_din; | |
| 365 | wire vlan_tbl_cs; | |
| 366 | wire vlan_tbl_wr; | |
| 367 | wire[11:0] vlan_tbl_addr; | |
| 368 | wire[17:0] vlan_tbl_din_reg_dout; | |
| 369 | wire vlan_parity_err_log_en; | |
| 370 | wire[11:0] vlan_tag_id; | |
| 371 | wire cpu_vlan_gnt_3; | |
| 372 | ||
| 373 | wire[10:0] flow_part_sel_reg0_dout; | |
| 374 | wire[10:0] flow_part_sel_reg1_dout; | |
| 375 | wire[10:0] flow_part_sel_reg2_dout; | |
| 376 | wire[10:0] flow_part_sel_reg3_dout; | |
| 377 | wire[10:0] flow_part_sel_reg4_dout; | |
| 378 | wire[10:0] flow_part_sel_reg5_dout; | |
| 379 | wire[10:0] flow_part_sel_reg6_dout; | |
| 380 | wire[10:0] flow_part_sel_reg7_dout; | |
| 381 | wire[23:0] hash_tbl_addr_reg0_dout; | |
| 382 | wire[23:0] hash_tbl_addr_reg1_dout; | |
| 383 | wire[23:0] hash_tbl_addr_reg2_dout; | |
| 384 | wire[23:0] hash_tbl_addr_reg3_dout; | |
| 385 | wire[23:0] hash_tbl_addr_reg4_dout; | |
| 386 | wire[23:0] hash_tbl_addr_reg5_dout; | |
| 387 | wire[23:0] hash_tbl_addr_reg6_dout; | |
| 388 | wire[23:0] hash_tbl_addr_reg7_dout; | |
| 389 | wire[63:0] hash_tbl_data_reg0_dout; | |
| 390 | wire[63:0] hash_tbl_data_reg1_dout; | |
| 391 | wire[63:0] hash_tbl_data_reg2_dout; | |
| 392 | wire[63:0] hash_tbl_data_reg3_dout; | |
| 393 | wire[63:0] hash_tbl_data_reg4_dout; | |
| 394 | wire[63:0] hash_tbl_data_reg5_dout; | |
| 395 | wire[63:0] hash_tbl_data_reg6_dout; | |
| 396 | wire[63:0] hash_tbl_data_reg7_dout; | |
| 397 | wire[71:0] fcram_err_test_reg_dout; | |
| 398 | wire cpu_req_part0_sel; | |
| 399 | wire cpu_req_part1_sel; | |
| 400 | wire cpu_req_part2_sel; | |
| 401 | wire cpu_req_part3_sel; | |
| 402 | wire cpu_req_part4_sel; | |
| 403 | wire cpu_req_part5_sel; | |
| 404 | wire cpu_req_part6_sel; | |
| 405 | wire cpu_req_part7_sel; | |
| 406 | wire pio_rd; | |
| 407 | wire cpu_fcram_req; | |
| 408 | wire cpu_fio_req; | |
| 409 | wire pio_fio_cfg_reset; | |
| 410 | wire[7:0] fio_cfg_addr_reg_dout; | |
| 411 | ||
| 412 | wire[7:0] ext_fc_valid = {flow_part_sel_reg7_dout[10], | |
| 413 | flow_part_sel_reg6_dout[10], | |
| 414 | flow_part_sel_reg5_dout[10], | |
| 415 | flow_part_sel_reg4_dout[10], | |
| 416 | flow_part_sel_reg3_dout[10], | |
| 417 | flow_part_sel_reg2_dout[10], | |
| 418 | flow_part_sel_reg1_dout[10], | |
| 419 | flow_part_sel_reg0_dout[10]}; | |
| 420 | ||
| 421 | ||
| 422 | wire fflp_fcram_cfg_rst; | |
| 423 | wire fflp_fcram_cfg_sel; | |
| 424 | wire fflp_fcram_cfg_rd; | |
| 425 | wire[7:0] fflp_fcram_cfg_addr; | |
| 426 | wire[15:0] fflp_fcram_cfg_datwr; | |
| 427 | wire fflp_fcram_slv_update; | |
| 428 | wire[1:0] fflp_fcram_rd_en; | |
| 429 | wire fflp_fcram_cs_l; | |
| 430 | wire fflp_fcram_fn; | |
| 431 | wire fflp_fcram_pd_l; | |
| 432 | wire fflp_fcram_ba0; | |
| 433 | wire fflp_fcram_ba1; | |
| 434 | wire[14:0] fflp_fcram_addr; | |
| 435 | wire[1:0] fflp_fcram_ds; | |
| 436 | wire[1:0] fflp_fcram_triz_en_l; | |
| 437 | wire[35:0] fflp_fcram_even_dout; | |
| 438 | wire[35:0] fflp_fcram_odd_dout; | |
| 439 | wire cpu_fc_req_done; | |
| 440 | wire[71:0] fc_rd_data_reg_dout; | |
| 441 | wire fc_rd_ecc_err; | |
| 442 | wire cpu_fio_req_done; | |
| 443 | wire[31:0] cpu_fio_rd_data; | |
| 444 | wire[7:0] fio_cal_rd_latency; | |
| 445 | wire[33:0] fc_err_status; | |
| 446 | wire fc_fifo_ren; | |
| 447 | wire zcp_wr; | |
| 448 | ||
| 449 | wire fflp_zcp_wr_p; | |
| 450 | wire cpu_fc_req_done_sync; | |
| 451 | wire cpu_fio_req_done_sync; | |
| 452 | ||
| 453 | wire cpu_fcram_req_sync; | |
| 454 | wire cpu_fio_req_sync; | |
| 455 | wire fc_fifo_empty_sync; | |
| 456 | wire fflp_config_reg_wen_pulse_sync; | |
| 457 | ||
| 458 | wire reset_s; | |
| 459 | wire reset_sync; | |
| 460 | ||
| 461 | wire[31:0] fflp_debug_port; | |
| 462 | ||
| 463 | ||
| 464 | `ifdef NEPTUNE | |
| 465 | wire [3:0] do_nad; | |
| 466 | wire [3:0] do_nor; | |
| 467 | wire [3:0] do_inv; | |
| 468 | wire [3:0] do_mux; | |
| 469 | wire [3:0] do_q; | |
| 470 | wire so; | |
| 471 | ||
| 472 | nep_spare_fflp spare_fflp_0 ( | |
| 473 | .di_nd3 ({1'h1, 1'h1, do_q[3]}), | |
| 474 | .di_nd2 ({1'h1, 1'h1, do_q[2]}), | |
| 475 | .di_nd1 ({1'h1, 1'h1, do_q[1]}), | |
| 476 | .di_nd0 ({1'h1, 1'h1, do_q[0]}), | |
| 477 | .di_nr3 ({1'h0, 1'h0}), | |
| 478 | .di_nr2 ({1'h0, 1'h0}), | |
| 479 | .di_nr1 ({1'h0, 1'h0}), | |
| 480 | .di_nr0 ({1'h0, 1'h0}), | |
| 481 | .di_inv (do_nad[3:0]), | |
| 482 | .di_mx3 ({1'h0, 1'h0}), | |
| 483 | .di_mx2 ({1'h0, 1'h0}), | |
| 484 | .di_mx1 ({1'h0, 1'h0}), | |
| 485 | .di_mx0 ({1'h0, 1'h0}), | |
| 486 | .mx_sel (do_nor[3:0]), | |
| 487 | .di_reg (do_inv[3:0]), | |
| 488 | .wt_ena (do_mux[3:0]), | |
| 489 | .rst ({reset_s,reset_s,reset_s,reset_s}), | |
| 490 | .si (1'h0), | |
| 491 | .se (1'h0), | |
| 492 | .clk (cclk), | |
| 493 | .do_nad (do_nad[3:0]), | |
| 494 | .do_nor (do_nor[3:0]), | |
| 495 | .do_inv (do_inv[3:0]), | |
| 496 | .do_mux (do_mux[3:0]), | |
| 497 | .do_q (do_q[3:0]), | |
| 498 | .so (so) | |
| 499 | ); | |
| 500 | ||
| 501 | `endif | |
| 502 | ||
| 503 | ||
| 504 | fflp_hdr fflp_hdr_inst ( | |
| 505 | .cclk (cclk), | |
| 506 | .reset (reset_s), | |
| 507 | .ipp_fflp_dvalid (ipp_fflp_dvalid), | |
| 508 | .ipp_fflp_data (ipp_fflp_data), | |
| 509 | .ipp_fflp_mac_default (ipp_fflp_mac_default), | |
| 510 | .ipp_fflp_mac_port (ipp_fflp_mac_port), | |
| 511 | .snap_en (snap_en), | |
| 512 | .disable_chksum (disable_chksum), | |
| 513 | .class2_hdr_byte_value (class2_hdr_byte_value), | |
| 514 | .class3_hdr_byte_value (class3_hdr_byte_value), | |
| 515 | .class4_hdr_byte_value (class4_hdr_byte_value), | |
| 516 | .class5_hdr_byte_value (class5_hdr_byte_value), | |
| 517 | .class6_hdr_byte_value (class6_hdr_byte_value), | |
| 518 | .class7_hdr_byte_value (class7_hdr_byte_value), | |
| 519 | .class_action_reg4_dout (class_action_reg4_dout), | |
| 520 | .class_action_reg5_dout (class_action_reg5_dout), | |
| 521 | .class_action_reg6_dout (class_action_reg6_dout), | |
| 522 | .class_action_reg7_dout (class_action_reg7_dout), | |
| 523 | .class_action_reg8_dout (class_action_reg8_dout), | |
| 524 | .class_action_reg9_dout (class_action_reg9_dout), | |
| 525 | .class_action_reg10_dout (class_action_reg10_dout), | |
| 526 | .class_action_reg11_dout (class_action_reg11_dout), | |
| 527 | .class_action_reg12_dout (class_action_reg12_dout), | |
| 528 | .class_action_reg13_dout (class_action_reg13_dout), | |
| 529 | .class_action_reg14_dout (class_action_reg14_dout), | |
| 530 | .class_action_reg15_dout (class_action_reg15_dout), | |
| 531 | .f_key_class_action_reg4_dout (f_key_class_action_reg4_dout), | |
| 532 | .f_key_class_action_reg5_dout (f_key_class_action_reg5_dout), | |
| 533 | .f_key_class_action_reg6_dout (f_key_class_action_reg6_dout), | |
| 534 | .f_key_class_action_reg7_dout (f_key_class_action_reg7_dout), | |
| 535 | .f_key_class_action_reg8_dout (f_key_class_action_reg8_dout), | |
| 536 | .f_key_class_action_reg9_dout (f_key_class_action_reg9_dout), | |
| 537 | .f_key_class_action_reg10_dout (f_key_class_action_reg10_dout), | |
| 538 | .f_key_class_action_reg11_dout (f_key_class_action_reg11_dout), | |
| 539 | .f_key_class_action_reg12_dout (f_key_class_action_reg12_dout), | |
| 540 | .f_key_class_action_reg13_dout (f_key_class_action_reg13_dout), | |
| 541 | .f_key_class_action_reg14_dout (f_key_class_action_reg14_dout), | |
| 542 | .f_key_class_action_reg15_dout (f_key_class_action_reg15_dout), | |
| 543 | .hdr_ctrl_bit_mask_reg_dout (hdr_ctrl_bit_mask_reg_dout), | |
| 544 | .cpu_vlan_req (cpu_vlan_req), | |
| 545 | .cpu_vlan_rd (cpu_vlan_rd), | |
| 546 | .cpu_vlan_wr (cpu_vlan_wr), | |
| 547 | .cpu_vlan_addr (cpu_vlan_addr), | |
| 548 | .vlan_tbl_rd_din (vlan_tbl_rd_din), | |
| 549 | .fwd_sched (fwd_sched), | |
| 550 | ||
| 551 | .fflp_ipp_ready (fflp_ipp_ready), | |
| 552 | .fflp_ipp_dvalid (fflp_ipp_dvalid), | |
| 553 | .fflp_ipp_data (fflp_ipp_data), | |
| 554 | .fwd_req (fwd_req), | |
| 555 | .key_bus (key_bus), | |
| 556 | .fwd_info_bus (fwd_info_bus), | |
| 557 | .vlan_tbl_cs (vlan_tbl_cs), | |
| 558 | .vlan_tbl_wr (vlan_tbl_wr), | |
| 559 | .vlan_tbl_addr (vlan_tbl_addr), | |
| 560 | .vlan_tbl_din_reg_dout (vlan_tbl_din_reg_dout), | |
| 561 | .vlan_parity_err_log_en (vlan_parity_err_log_en), | |
| 562 | .vlan_tag_id (vlan_tag_id), | |
| 563 | .cpu_vlan_gnt_3 (cpu_vlan_gnt_3) | |
| 564 | ||
| 565 | ); | |
| 566 | ||
| 567 | ||
| 568 | fflp_cam_ram fflp_cam_ram_inst ( | |
| 569 | .cclk (cclk), | |
| 570 | .reset (reset_s), | |
| 571 | .pio_disable_cam (pio_disable_cam), | |
| 572 | .disable_chksum (disable_chksum), | |
| 573 | .cam_srch_latency (cam_srch_latency), | |
| 574 | .h1_init_value_reg_dout (h1_init_value_reg_dout), | |
| 575 | .h2_init_value_reg_dout (h2_init_value_reg_dout), | |
| 576 | .cam_srch_ratio (cam_srch_ratio), | |
| 577 | .fwd_req (fwd_req), | |
| 578 | .key_bus (key_bus), | |
| 579 | .fwd_info_bus (fwd_info_bus), | |
| 580 | .cam_hit (cam_hit), | |
| 581 | .cam_valid (cam_valid), | |
| 582 | .cam_haddr (cam_haddr), | |
| 583 | .pio_rd_vld (pio_rd_vld), | |
| 584 | .cam_msk_dat_out (cam_msk_dat_out), | |
| 585 | .pio_wen (pio_wen), | |
| 586 | .pio_addr (pio_addr), | |
| 587 | .pio_32b_mode (pio_32b_mode), | |
| 588 | .pio_wr_data (pio_wr_data), | |
| 589 | .am_din (am_din), | |
| 590 | .fc_fifo_ren_sync (fc_fifo_ren_sync), | |
| 591 | .ext_fc_valid (ext_fc_valid), | |
| 592 | ||
| 593 | .fwd_sched (fwd_sched), | |
| 594 | .cam_data_inp (cam_data_inp), | |
| 595 | .cam_compare (cam_compare), | |
| 596 | .cam_pio_wr (cam_pio_wr), | |
| 597 | .cam_pio_rd (cam_pio_rd), | |
| 598 | .cam_pio_sel (cam_pio_sel), | |
| 599 | .cam_index (cam_index), | |
| 600 | .cam_key_reg0_dout (cam_key_reg0_dout), | |
| 601 | .cam_key_reg1_dout (cam_key_reg1_dout), | |
| 602 | .cam_key_reg2_dout (cam_key_reg2_dout), | |
| 603 | .cam_key_reg3_dout (cam_key_reg3_dout), | |
| 604 | .cam_key_mask_reg0_dout (cam_key_mask_reg0_dout), | |
| 605 | .cam_key_mask_reg1_dout (cam_key_mask_reg1_dout), | |
| 606 | .cam_key_mask_reg2_dout (cam_key_mask_reg2_dout), | |
| 607 | .cam_key_mask_reg3_dout (cam_key_mask_reg3_dout), | |
| 608 | .cam_cmd_stat_reg_dout (cam_cmd_stat_reg_dout), | |
| 609 | .am_rd (am_rd), | |
| 610 | .am_wr (am_wr), | |
| 611 | .am_addr (am_addr), | |
| 612 | .am_dout (am_dout), | |
| 613 | .ecc_parity_status (ecc_parity_status), | |
| 614 | .fc_fifo_empty (fc_fifo_empty), | |
| 615 | .fc_fifo_dout (fc_fifo_dout) | |
| 616 | ||
| 617 | ); | |
| 618 | ||
| 619 | ||
| 620 | fflp_pio_if fflp_pio_if_inst ( | |
| 621 | .cclk (cclk), | |
| 622 | .reset_l (reset_l), | |
| 623 | .pio_fflp_wdata (pio_fflp_wdata), | |
| 624 | .pio_fflp_rd (pio_fflp_rd), | |
| 625 | .pio_fflp_sel (pio_fflp_sel), | |
| 626 | .pio_fflp_addr (pio_fflp_addr), | |
| 627 | .pio_client_32b (pio_client_32b), | |
| 628 | .cam_key_reg0_dout (cam_key_reg0_dout), | |
| 629 | .cam_key_reg1_dout (cam_key_reg1_dout), | |
| 630 | .cam_key_reg2_dout (cam_key_reg2_dout), | |
| 631 | .cam_key_reg3_dout (cam_key_reg3_dout), | |
| 632 | .cam_key_mask_reg0_dout (cam_key_mask_reg0_dout), | |
| 633 | .cam_key_mask_reg1_dout (cam_key_mask_reg1_dout), | |
| 634 | .cam_key_mask_reg2_dout (cam_key_mask_reg2_dout), | |
| 635 | .cam_key_mask_reg3_dout (cam_key_mask_reg3_dout), | |
| 636 | .cam_cmd_stat_reg_dout (cam_cmd_stat_reg_dout), | |
| 637 | .vlan_tbl_din_reg_dout (vlan_tbl_din_reg_dout), | |
| 638 | .vlan_parity_err_log_en (vlan_parity_err_log_en), | |
| 639 | .vlan_tag_id (vlan_tag_id), | |
| 640 | .cpu_vlan_gnt_3 (cpu_vlan_gnt_3), | |
| 641 | .cpu_fc_req_done_sync (cpu_fc_req_done_sync), | |
| 642 | .fc_rd_data_reg_dout (fc_rd_data_reg_dout), | |
| 643 | .fc_rd_ecc_err (fc_rd_ecc_err), | |
| 644 | .fflp_zcp_wr_p (fflp_zcp_wr_p), | |
| 645 | .fc_err_status (fc_err_status), | |
| 646 | .ecc_parity_status (ecc_parity_status), | |
| 647 | .cpu_fio_req_done_sync (cpu_fio_req_done_sync), | |
| 648 | .cpu_fio_rd_data (cpu_fio_rd_data), | |
| 649 | .fio_cal_rd_latency (fio_cal_rd_latency), | |
| 650 | ||
| 651 | .reset_s (reset_s), | |
| 652 | .pio_wen (pio_wen), | |
| 653 | .pio_addr (pio_addr), | |
| 654 | .pio_32b_mode (pio_32b_mode), | |
| 655 | .pio_wr_data (pio_wr_data), | |
| 656 | .fflp_pio_rdata (fflp_pio_rdata), | |
| 657 | .fflp_pio_ack (fflp_pio_ack), | |
| 658 | .fflp_pio_err (fflp_pio_err), | |
| 659 | .fflp_pio_intr (fflp_pio_intr), | |
| 660 | .snap_en (snap_en), | |
| 661 | .disable_chksum (disable_chksum), | |
| 662 | .pio_disable_cam (pio_disable_cam), | |
| 663 | .fflp_init_done (fflp_init_done), | |
| 664 | .fcram_driver_imp_ctrl (fcram_driver_imp_ctrl), | |
| 665 | .fcram_qs_mode (fcram_qs_mode), | |
| 666 | .fcram_lookup_ratio (fcram_lookup_ratio), | |
| 667 | .pio_fio_latency (pio_fio_latency), | |
| 668 | .cam_srch_latency (cam_srch_latency), | |
| 669 | .cam_srch_ratio (cam_srch_ratio), | |
| 670 | .h1_init_value_reg_dout (h1_init_value_reg_dout), | |
| 671 | .h2_init_value_reg_dout (h2_init_value_reg_dout), | |
| 672 | .fcram_refresh_timer_reg_dout (fcram_refresh_timer_reg_dout), | |
| 673 | .class2_hdr_byte_value (class2_hdr_byte_value), | |
| 674 | .class3_hdr_byte_value (class3_hdr_byte_value), | |
| 675 | .class4_hdr_byte_value (class4_hdr_byte_value), | |
| 676 | .class5_hdr_byte_value (class5_hdr_byte_value), | |
| 677 | .class6_hdr_byte_value (class6_hdr_byte_value), | |
| 678 | .class7_hdr_byte_value (class7_hdr_byte_value), | |
| 679 | .class_action_reg4_dout (class_action_reg4_dout), | |
| 680 | .class_action_reg5_dout (class_action_reg5_dout), | |
| 681 | .class_action_reg6_dout (class_action_reg6_dout), | |
| 682 | .class_action_reg7_dout (class_action_reg7_dout), | |
| 683 | .class_action_reg8_dout (class_action_reg8_dout), | |
| 684 | .class_action_reg9_dout (class_action_reg9_dout), | |
| 685 | .class_action_reg10_dout (class_action_reg10_dout), | |
| 686 | .class_action_reg11_dout (class_action_reg11_dout), | |
| 687 | .class_action_reg12_dout (class_action_reg12_dout), | |
| 688 | .class_action_reg13_dout (class_action_reg13_dout), | |
| 689 | .class_action_reg14_dout (class_action_reg14_dout), | |
| 690 | .class_action_reg15_dout (class_action_reg15_dout), | |
| 691 | .f_key_class_action_reg4_dout (f_key_class_action_reg4_dout), | |
| 692 | .f_key_class_action_reg5_dout (f_key_class_action_reg5_dout), | |
| 693 | .f_key_class_action_reg6_dout (f_key_class_action_reg6_dout), | |
| 694 | .f_key_class_action_reg7_dout (f_key_class_action_reg7_dout), | |
| 695 | .f_key_class_action_reg8_dout (f_key_class_action_reg8_dout), | |
| 696 | .f_key_class_action_reg9_dout (f_key_class_action_reg9_dout), | |
| 697 | .f_key_class_action_reg10_dout (f_key_class_action_reg10_dout), | |
| 698 | .f_key_class_action_reg11_dout (f_key_class_action_reg11_dout), | |
| 699 | .f_key_class_action_reg12_dout (f_key_class_action_reg12_dout), | |
| 700 | .f_key_class_action_reg13_dout (f_key_class_action_reg13_dout), | |
| 701 | .f_key_class_action_reg14_dout (f_key_class_action_reg14_dout), | |
| 702 | .f_key_class_action_reg15_dout (f_key_class_action_reg15_dout), | |
| 703 | .hdr_ctrl_bit_mask_reg_dout (hdr_ctrl_bit_mask_reg_dout), | |
| 704 | .cpu_vlan_req (cpu_vlan_req), | |
| 705 | .cpu_vlan_rd (cpu_vlan_rd), | |
| 706 | .cpu_vlan_wr (cpu_vlan_wr), | |
| 707 | .cpu_vlan_addr (cpu_vlan_addr), | |
| 708 | .vlan_tbl_wr_dout (vlan_tbl_wr_dout), | |
| 709 | .flow_part_sel_reg0_dout (flow_part_sel_reg0_dout), | |
| 710 | .flow_part_sel_reg1_dout (flow_part_sel_reg1_dout), | |
| 711 | .flow_part_sel_reg2_dout (flow_part_sel_reg2_dout), | |
| 712 | .flow_part_sel_reg3_dout (flow_part_sel_reg3_dout), | |
| 713 | .flow_part_sel_reg4_dout (flow_part_sel_reg4_dout), | |
| 714 | .flow_part_sel_reg5_dout (flow_part_sel_reg5_dout), | |
| 715 | .flow_part_sel_reg6_dout (flow_part_sel_reg6_dout), | |
| 716 | .flow_part_sel_reg7_dout (flow_part_sel_reg7_dout), | |
| 717 | .hash_tbl_addr_reg0_dout (hash_tbl_addr_reg0_dout), | |
| 718 | .hash_tbl_addr_reg1_dout (hash_tbl_addr_reg1_dout), | |
| 719 | .hash_tbl_addr_reg2_dout (hash_tbl_addr_reg2_dout), | |
| 720 | .hash_tbl_addr_reg3_dout (hash_tbl_addr_reg3_dout), | |
| 721 | .hash_tbl_addr_reg4_dout (hash_tbl_addr_reg4_dout), | |
| 722 | .hash_tbl_addr_reg5_dout (hash_tbl_addr_reg5_dout), | |
| 723 | .hash_tbl_addr_reg6_dout (hash_tbl_addr_reg6_dout), | |
| 724 | .hash_tbl_addr_reg7_dout (hash_tbl_addr_reg7_dout), | |
| 725 | .hash_tbl_data_reg0_dout (hash_tbl_data_reg0_dout), | |
| 726 | .hash_tbl_data_reg1_dout (hash_tbl_data_reg1_dout), | |
| 727 | .hash_tbl_data_reg2_dout (hash_tbl_data_reg2_dout), | |
| 728 | .hash_tbl_data_reg3_dout (hash_tbl_data_reg3_dout), | |
| 729 | .hash_tbl_data_reg4_dout (hash_tbl_data_reg4_dout), | |
| 730 | .hash_tbl_data_reg5_dout (hash_tbl_data_reg5_dout), | |
| 731 | .hash_tbl_data_reg6_dout (hash_tbl_data_reg6_dout), | |
| 732 | .hash_tbl_data_reg7_dout (hash_tbl_data_reg7_dout), | |
| 733 | .fcram_err_test_reg_dout (fcram_err_test_reg_dout), | |
| 734 | .cpu_req_part0_sel (cpu_req_part0_sel), | |
| 735 | .cpu_req_part1_sel (cpu_req_part1_sel), | |
| 736 | .cpu_req_part2_sel (cpu_req_part2_sel), | |
| 737 | .cpu_req_part3_sel (cpu_req_part3_sel), | |
| 738 | .cpu_req_part4_sel (cpu_req_part4_sel), | |
| 739 | .cpu_req_part5_sel (cpu_req_part5_sel), | |
| 740 | .cpu_req_part6_sel (cpu_req_part6_sel), | |
| 741 | .cpu_req_part7_sel (cpu_req_part7_sel), | |
| 742 | .pio_rd (pio_rd), | |
| 743 | .cpu_fcram_req (cpu_fcram_req), | |
| 744 | .cpu_fio_req (cpu_fio_req), | |
| 745 | .pio_fio_cfg_reset (pio_fio_cfg_reset), | |
| 746 | .fio_cfg_addr_reg_dout (fio_cfg_addr_reg_dout), | |
| 747 | .fflp_config_reg_wen_pulse (fflp_config_reg_wen_pulse), | |
| 748 | .debug_training_vector (debug_training_vector), | |
| 749 | .pio_debug_data_sel (pio_debug_data_sel) | |
| 750 | ||
| 751 | ); | |
| 752 | ||
| 753 | ||
| 754 | fflp_sync2fc_clk fflp_sync2fc_clk_inst | |
| 755 | ( | |
| 756 | .cclk (fcram_clk), | |
| 757 | .reset (reset_s), | |
| 758 | .cpu_fcram_req (cpu_fcram_req), | |
| 759 | .cpu_fio_req (cpu_fio_req), | |
| 760 | .fc_fifo_empty (fc_fifo_empty), | |
| 761 | .fflp_config_reg_wen_pulse (fflp_config_reg_wen_pulse), | |
| 762 | ||
| 763 | .reset_sync (reset_sync), | |
| 764 | .cpu_fcram_req_sync (cpu_fcram_req_sync), | |
| 765 | .cpu_fio_req_sync (cpu_fio_req_sync), | |
| 766 | .fc_fifo_empty_sync (fc_fifo_empty_sync), | |
| 767 | .fflp_config_reg_wen_pulse_sync (fflp_config_reg_wen_pulse_sync) | |
| 768 | ||
| 769 | ); | |
| 770 | ||
| 771 | ||
| 772 | ||
| 773 | fflp_sync2sys_clk fflp_sync2sys_clk_inst | |
| 774 | ( | |
| 775 | .cclk (cclk), | |
| 776 | .cpu_fc_req_done (cpu_fc_req_done), | |
| 777 | .cpu_fio_req_done (cpu_fio_req_done), | |
| 778 | .fc_fifo_ren (fc_fifo_ren), | |
| 779 | .zcp_wr (zcp_wr), | |
| 780 | ||
| 781 | .cpu_fc_req_done_sync (cpu_fc_req_done_sync), | |
| 782 | .cpu_fio_req_done_sync (cpu_fio_req_done_sync), | |
| 783 | .fc_fifo_ren_sync (fc_fifo_ren_sync), | |
| 784 | .fflp_zcp_wr_p (fflp_zcp_wr_p), | |
| 785 | .fflp_zcp_wr (fflp_zcp_wr) | |
| 786 | ||
| 787 | ); | |
| 788 | ||
| 789 | ||
| 790 | fflp_fcram_top fflp_fcram_top_inst | |
| 791 | ( | |
| 792 | .cclk (fcram_clk), | |
| 793 | .reset (reset_sync), | |
| 794 | .disable_chksum (disable_chksum), | |
| 795 | .pio_fio_latency (pio_fio_latency), | |
| 796 | .fcram_lookup_ratio (fcram_lookup_ratio), | |
| 797 | .fflp_init_done (fflp_init_done), | |
| 798 | .fcram_refresh_timer_reg_dout (fcram_refresh_timer_reg_dout), | |
| 799 | .flow_part_sel_reg0_dout (flow_part_sel_reg0_dout[9:0]), | |
| 800 | .flow_part_sel_reg1_dout (flow_part_sel_reg1_dout[9:0]), | |
| 801 | .flow_part_sel_reg2_dout (flow_part_sel_reg2_dout[9:0]), | |
| 802 | .flow_part_sel_reg3_dout (flow_part_sel_reg3_dout[9:0]), | |
| 803 | .flow_part_sel_reg4_dout (flow_part_sel_reg4_dout[9:0]), | |
| 804 | .flow_part_sel_reg5_dout (flow_part_sel_reg5_dout[9:0]), | |
| 805 | .flow_part_sel_reg6_dout (flow_part_sel_reg6_dout[9:0]), | |
| 806 | .flow_part_sel_reg7_dout (flow_part_sel_reg7_dout[9:0]), | |
| 807 | .hash_tbl_addr_reg0_dout (hash_tbl_addr_reg0_dout), | |
| 808 | .hash_tbl_addr_reg1_dout (hash_tbl_addr_reg1_dout), | |
| 809 | .hash_tbl_addr_reg2_dout (hash_tbl_addr_reg2_dout), | |
| 810 | .hash_tbl_addr_reg3_dout (hash_tbl_addr_reg3_dout), | |
| 811 | .hash_tbl_addr_reg4_dout (hash_tbl_addr_reg4_dout), | |
| 812 | .hash_tbl_addr_reg5_dout (hash_tbl_addr_reg5_dout), | |
| 813 | .hash_tbl_addr_reg6_dout (hash_tbl_addr_reg6_dout), | |
| 814 | .hash_tbl_addr_reg7_dout (hash_tbl_addr_reg7_dout), | |
| 815 | .hash_tbl_data_reg0_dout (hash_tbl_data_reg0_dout), | |
| 816 | .hash_tbl_data_reg1_dout (hash_tbl_data_reg1_dout), | |
| 817 | .hash_tbl_data_reg2_dout (hash_tbl_data_reg2_dout), | |
| 818 | .hash_tbl_data_reg3_dout (hash_tbl_data_reg3_dout), | |
| 819 | .hash_tbl_data_reg4_dout (hash_tbl_data_reg4_dout), | |
| 820 | .hash_tbl_data_reg5_dout (hash_tbl_data_reg5_dout), | |
| 821 | .hash_tbl_data_reg6_dout (hash_tbl_data_reg6_dout), | |
| 822 | .hash_tbl_data_reg7_dout (hash_tbl_data_reg7_dout), | |
| 823 | .fcram_err_test_reg_dout (fcram_err_test_reg_dout), | |
| 824 | .cpu_req_part0_sel (cpu_req_part0_sel), | |
| 825 | .cpu_req_part1_sel (cpu_req_part1_sel), | |
| 826 | .cpu_req_part2_sel (cpu_req_part2_sel), | |
| 827 | .cpu_req_part3_sel (cpu_req_part3_sel), | |
| 828 | .cpu_req_part4_sel (cpu_req_part4_sel), | |
| 829 | .cpu_req_part5_sel (cpu_req_part5_sel), | |
| 830 | .cpu_req_part6_sel (cpu_req_part6_sel), | |
| 831 | .cpu_req_part7_sel (cpu_req_part7_sel), | |
| 832 | .pio_rd (pio_rd), | |
| 833 | .pio_wr_data (pio_wr_data[15:0]), | |
| 834 | .pio_fio_cfg_reset (pio_fio_cfg_reset), | |
| 835 | .fio_cfg_addr_reg_dout (fio_cfg_addr_reg_dout), | |
| 836 | .cpu_fio_req_sync (cpu_fio_req_sync), | |
| 837 | .fcram_driver_imp_ctrl (fcram_driver_imp_ctrl), | |
| 838 | .fcram_qs_mode (fcram_qs_mode), | |
| 839 | .cpu_fcram_req_sync (cpu_fcram_req_sync), | |
| 840 | .fc_fifo_empty_sync (fc_fifo_empty_sync), | |
| 841 | .fflp_config_reg_wen_pulse_sync (fflp_config_reg_wen_pulse_sync), | |
| 842 | .debug_training_vector (debug_training_vector), | |
| 843 | .pio_debug_data_sel (pio_debug_data_sel), | |
| 844 | .fc_fifo_dout (fc_fifo_dout), | |
| 845 | .fcram_fflp_mstrready (fcram_fflp_mstrready), | |
| 846 | .fcram_fflp_fatal_err (fcram_fflp_fatal_err), | |
| 847 | .fcram_fflp_data_ready (fcram_fflp_data_ready), | |
| 848 | .fcram_fflp_even_din (fcram_fflp_even_din), | |
| 849 | .fcram_fflp_odd_din (fcram_fflp_odd_din), | |
| 850 | .fcram_fflp_cfg_datrd (fcram_fflp_cfg_datrd), | |
| 851 | .fcram_fflp_cfg_done (fcram_fflp_cfg_done), | |
| 852 | .fcram_fflp_cfg_err (fcram_fflp_cfg_err), | |
| 853 | ||
| 854 | .fflp_fcram_cfg_rst (fflp_fcram_cfg_rst), | |
| 855 | .fflp_fcram_cfg_sel (fflp_fcram_cfg_sel), | |
| 856 | .fflp_fcram_cfg_rd (fflp_fcram_cfg_rd), | |
| 857 | .fflp_fcram_cfg_addr (fflp_fcram_cfg_addr), | |
| 858 | .fflp_fcram_cfg_datwr (fflp_fcram_cfg_datwr), | |
| 859 | .fflp_fcram_slv_update (fflp_fcram_slv_update), | |
| 860 | .fflp_fcram_rd_en (fflp_fcram_rd_en), | |
| 861 | .fflp_fcram_cs_l (fflp_fcram_cs_l), | |
| 862 | .fflp_fcram_fn (fflp_fcram_fn), | |
| 863 | .fflp_fcram_pd_l (fflp_fcram_pd_l), | |
| 864 | .fflp_fcram_ba0 (fflp_fcram_ba0), | |
| 865 | .fflp_fcram_ba1 (fflp_fcram_ba1), | |
| 866 | .fflp_fcram_addr (fflp_fcram_addr), | |
| 867 | .fflp_fcram_ds (fflp_fcram_ds), | |
| 868 | .fflp_fcram_triz_en_l (fflp_fcram_triz_en_l), | |
| 869 | .fflp_fcram_even_dout (fflp_fcram_even_dout), | |
| 870 | .fflp_fcram_odd_dout (fflp_fcram_odd_dout), | |
| 871 | .cpu_fc_req_done (cpu_fc_req_done), | |
| 872 | .fc_rd_data_reg_dout (fc_rd_data_reg_dout), | |
| 873 | .fc_rd_ecc_err (fc_rd_ecc_err), | |
| 874 | .cpu_fio_req_done (cpu_fio_req_done), | |
| 875 | .cpu_fio_rd_data (cpu_fio_rd_data), | |
| 876 | .fio_cal_rd_latency (fio_cal_rd_latency), | |
| 877 | .fc_fifo_ren (fc_fifo_ren), | |
| 878 | .zcp_wr (zcp_wr), | |
| 879 | .fflp_zcp_data (fflp_zcp_data), | |
| 880 | .fc_err_status (fc_err_status), | |
| 881 | .fflp_debug_port (fflp_debug_port) | |
| 882 | ||
| 883 | ); | |
| 884 | ||
| 885 | ||
| 886 | ||
| 887 | endmodule | |
| 888 | ||
| 889 | ||
| 890 | ||
| 891 | ||
| 892 | ||
| 893 | ||
| 894 | ||
| 895 |