[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / fflp_cam_ram.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fflp_cam_ram.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/**********************************************************************/
/*project name:  NIU                                                  */
/*module name:   fflp_cam_ram                                         */
/*description:                                                        */
/*               FFLP CAM classification                              */
/*                                                                    */
/*parent module in:                                                   */
/*child modules in:  fflp_cam_srch.v, fflp_ram_cntl.v    	      */
/*                   fflp_cam_sched.v fflp_fwd_mstr.v                 */
/*interface modules:                                                  */
/*author name:       Jeanne Cai                                       */
/*date created:      03-22-04                                         */
/*                                                                    */
/*              Copyright (c) 2004, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */
/*modifications:                                                      */
/*                                                                    */

module fflp_cam_ram (
			cclk,
			reset,
			disable_chksum,
			pio_disable_cam,
			cam_srch_latency,
			cam_srch_ratio,
			h1_init_value_reg_dout,
			h2_init_value_reg_dout,
			fwd_req,
			key_bus,
			fwd_info_bus,
			cam_hit,
			cam_valid,
			cam_haddr,
			pio_rd_vld,
			cam_msk_dat_out,
			pio_wen,
			pio_addr,
			pio_32b_mode,
			pio_wr_data,
			am_din,
			fc_fifo_ren_sync,
			ext_fc_valid,

			fwd_sched,
			cam_data_inp,
			cam_compare,
			cam_pio_wr,
			cam_pio_rd,
			cam_pio_sel,
			cam_index,
			cam_key_reg0_dout,
			cam_key_reg1_dout,
			cam_key_reg2_dout,
			cam_key_reg3_dout,
			cam_key_mask_reg0_dout,
			cam_key_mask_reg1_dout,
			cam_key_mask_reg2_dout,
			cam_key_mask_reg3_dout,
			cam_cmd_stat_reg_dout,
			am_rd,
			am_wr,
			am_addr,
			am_dout,
			ecc_parity_status,
			fc_fifo_empty,
			fc_fifo_dout

			);

input		cclk;
input		reset;
input		disable_chksum;
input		pio_disable_cam;
input[3:0]	cam_srch_latency;
input[3:0]	cam_srch_ratio;
input[31:0]	h1_init_value_reg_dout;
input[15:0]	h2_init_value_reg_dout;
input		fwd_req;
input[199:0]	key_bus;
input[445:0]	fwd_info_bus;
input		cam_hit;
input		cam_valid;
input[9:0]	cam_haddr;
input		pio_rd_vld;
input[199:0]	cam_msk_dat_out;
input		pio_wen;
input[19:0]	pio_addr;
input		pio_32b_mode;
input[63:0]	pio_wr_data;
input[41:0]	am_din;
input		fc_fifo_ren_sync;
input[7:0]	ext_fc_valid;

output		fwd_sched;
output[199:0]	cam_data_inp;
output		cam_compare;
output		cam_pio_wr;
output		cam_pio_rd;
output		cam_pio_sel;
output[9:0]	cam_index;
output[7:0]	cam_key_reg0_dout;
output[63:0]	cam_key_reg1_dout;
output[63:0]	cam_key_reg2_dout;
output[63:0]	cam_key_reg3_dout;
output[7:0]	cam_key_mask_reg0_dout;
output[63:0]	cam_key_mask_reg1_dout;
output[63:0]	cam_key_mask_reg2_dout;
output[63:0]	cam_key_mask_reg3_dout;
output[20:0]	cam_cmd_stat_reg_dout;
output		am_rd;
output		am_wr;
output[9:0]	am_addr;
output[41:0]	am_dout;
output[25:0]	ecc_parity_status;
output		fc_fifo_empty;
output[512:0]	fc_fifo_dout;

wire            fwd_sched;
wire		cpu_sched;
wire[199:0]     cam_data_inp;
wire            cam_compare;
wire            cam_pio_wr;
wire            cam_pio_rd;
wire            cam_pio_sel;
wire[7:0]       cam_key_reg0_dout;
wire[63:0]      cam_key_reg1_dout;
wire[63:0]	cam_key_reg2_dout;
wire[63:0]	cam_key_reg3_dout;
wire[7:0]       cam_key_mask_reg0_dout;
wire[63:0]      cam_key_mask_reg1_dout;
wire[63:0]	cam_key_mask_reg2_dout;
wire[63:0]	cam_key_mask_reg3_dout;
wire[20:0]      cam_cmd_stat_reg_dout;
wire            am_rd;
wire            am_wr;
wire[9:0]       am_addr;
wire[41:0]      am_dout;
wire[25:0]	ecc_parity_status;
wire            fc_fifo_empty;
wire[512:0]     fc_fifo_dout;
wire		fc_fifo_space_avail;

wire[41:0]	am_din_reg_dout;
wire		cpu_req_cam_acc;
wire[1:0]	ram_acc_type;
wire		kick_off_ram_ctrl;
wire[9:0]	cam_haddr_reg1_dout;
wire[9:0]	cam_index;
wire		matchout_5;
wire		kick_off_ram_srch_5;
wire		kick_off_ram_srch_4;
wire[445:0]	fwd_info_bus_2;
wire[103:0]	key_ecc_data_2;

wire[19:0]	hash_v1;
wire[15:0]	hash_v2;

`ifdef NEPTUNE
wire      [3:0] do_nad;
wire      [3:0] do_nor;
wire      [3:0] do_inv;
wire      [3:0] do_mux;
wire      [3:0] do_q;
wire            so;

nep_spare_fflp spare_fflp_0 (
                             .di_nd3     ({1'h1, 1'h1, do_q[3]}),
                             .di_nd2     ({1'h1, 1'h1, do_q[2]}),
                             .di_nd1     ({1'h1, 1'h1, do_q[1]}),
                             .di_nd0     ({1'h1, 1'h1, do_q[0]}),
                             .di_nr3     ({1'h0, 1'h0}),
                             .di_nr2     ({1'h0, 1'h0}),
                             .di_nr1     ({1'h0, 1'h0}),
                             .di_nr0     ({1'h0, 1'h0}),
                             .di_inv     (do_nad[3:0]),
                             .di_mx3     ({1'h0, 1'h0}),
                             .di_mx2     ({1'h0, 1'h0}),
                             .di_mx1     ({1'h0, 1'h0}),
                             .di_mx0     ({1'h0, 1'h0}),
                             .mx_sel     (do_nor[3:0]),
                             .di_reg     (do_inv[3:0]),
                             .wt_ena     (do_mux[3:0]),
                             .rst        ({reset,reset,reset,reset}),
                             .si         (1'h0),
                             .se         (1'h0),
                             .clk        (cclk),
                             .do_nad     (do_nad[3:0]),
                             .do_nor     (do_nor[3:0]),
                             .do_inv     (do_inv[3:0]),
                             .do_mux     (do_mux[3:0]),
                             .do_q       (do_q[3:0]),
                             .so         (so)
                            );

`endif


fflp_cam_sched	fflp_cam_sched_inst (
				.cclk			(cclk),
				.reset			(reset),
				.cam_srch_latency	(cam_srch_latency),
				.cam_srch_ratio		(cam_srch_ratio),
				.fwd_req		(fwd_req),
				.cpu_req_cam_acc	(cpu_req_cam_acc),
				.fc_fifo_space_avail	(fc_fifo_space_avail),
		
				.fwd_sched		(fwd_sched),
				.cpu_sched		(cpu_sched)
				);

fflp_cam_srch	fflp_cam_srch_inst (
				.cclk                   (cclk),
                                .reset                  (reset),
				.pio_disable_cam	(pio_disable_cam),
				.cam_srch_latency	(cam_srch_latency),
				.fwd_sched              (fwd_sched),
                                .cpu_sched              (cpu_sched),
				.key_bus		(key_bus),
				.fwd_info_bus		(fwd_info_bus),
				.cam_hit		(cam_hit),
				.cam_valid		(cam_valid),
				.cam_haddr		(cam_haddr),
				.pio_rd_vld		(pio_rd_vld),
				.cam_msk_dat_out	(cam_msk_dat_out),
				.am_din_reg_dout	(am_din_reg_dout),
				.pio_wen		(pio_wen),
				.pio_addr		(pio_addr),
				.pio_32b_mode		(pio_32b_mode),
				.pio_wr_data		(pio_wr_data),

				.cpu_req_cam_acc	(cpu_req_cam_acc),
				.ram_acc_type		(ram_acc_type),
				.kick_off_ram_ctrl	(kick_off_ram_ctrl),
				.cam_haddr_reg1_dout	(cam_haddr_reg1_dout),
				.cam_index		(cam_index),
				.cam_data_inp		(cam_data_inp),
				.cam_compare		(cam_compare),
				.cam_pio_wr		(cam_pio_wr),
				.cam_pio_rd		(cam_pio_rd),
				.cam_pio_sel		(cam_pio_sel),
				.matchout_5		(matchout_5),
				.kick_off_ram_srch_4	(kick_off_ram_srch_4),
				.kick_off_ram_srch_5	(kick_off_ram_srch_5),
				.fwd_info_bus_2		(fwd_info_bus_2),
				.key_ecc_data_2		(key_ecc_data_2),
				.cam_key_reg0_dout	(cam_key_reg0_dout),
				.cam_key_reg1_dout	(cam_key_reg1_dout),
				.cam_key_reg2_dout      (cam_key_reg2_dout),
                                .cam_key_reg3_dout      (cam_key_reg3_dout),
				.cam_key_mask_reg0_dout	(cam_key_mask_reg0_dout),
				.cam_key_mask_reg1_dout	(cam_key_mask_reg1_dout),
				.cam_key_mask_reg2_dout (cam_key_mask_reg2_dout),
                                .cam_key_mask_reg3_dout (cam_key_mask_reg3_dout),
				.cam_cmd_stat_reg_dout	(cam_cmd_stat_reg_dout)

				);

fflp_ram_cntl	fflp_ram_cntl_inst (
				.cclk                   (cclk),
                                .reset                  (reset),
				.ram_acc_type           (ram_acc_type),
                                .kick_off_ram_ctrl      (kick_off_ram_ctrl),
				.cam_haddr_reg1_dout    (cam_haddr_reg1_dout),
                                .cam_index              (cam_index),
				.cam_key_reg1_dout      (cam_key_reg1_dout[41:0]),
				.am_din			(am_din),

				.am_rd			(am_rd),
				.am_wr			(am_wr),
				.am_addr		(am_addr),
				.am_dout		(am_dout),
				.am_din_reg_dout	(am_din_reg_dout)

				);


fflp_hash_func	fflp_hash_func_inst (
				.cclk			(cclk),
				.reset			(reset),
				.fwd_info_hash_key	(fwd_info_bus[361:0]),
				.fwd_sched		(fwd_sched),
				.kick_off_ram_srch_4	(kick_off_ram_srch_4),
				.h1_init_value_reg_dout	(h1_init_value_reg_dout),
				.h2_init_value_reg_dout	(h2_init_value_reg_dout),

				.hash_v1		(hash_v1),
				.hash_v2		(hash_v2)

				);

fflp_fwd_mstr	fflp_fwd_mstr_inst (
				.cclk                   (cclk),
                                .reset                  (reset),
				.disable_chksum		(disable_chksum),
				.fc_fifo_ren_sync	(fc_fifo_ren_sync),
				.ext_fc_valid		(ext_fc_valid),
				.fwd_info_bus_2         (fwd_info_bus_2),
				.key_ecc_data_2		(key_ecc_data_2),
				.kick_off_ram_srch_5    (kick_off_ram_srch_5),
				.matchout_5             (matchout_5),
				.cam_haddr_reg1_dout    (cam_haddr_reg1_dout),
				.am_din_reg_dout        (am_din_reg_dout),
				.hash_v1		(hash_v1),
				.hash_v2		(hash_v2),

				.ecc_parity_status	(ecc_parity_status),
				.fc_fifo_space_avail	(fc_fifo_space_avail),
				.fc_fifo_empty		(fc_fifo_empty),
				.fc_fifo_dout		(fc_fifo_dout)

				);


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: fflp_cam_ram.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/**********************************************************************/
	36	/project name: NIU /
	37	/module name: fflp_cam_ram /
	38	/description: /
	39	/* FFLP CAM classification */
	40	/* */
	41	/parent module in: /
	42	/child modules in: fflp_cam_srch.v, fflp_ram_cntl.v /
	43	/* fflp_cam_sched.v fflp_fwd_mstr.v */
	44	/interface modules: /
	45	/author name: Jeanne Cai /
	46	/date created: 03-22-04 /
	47	/* */
	48	/* Copyright (c) 2004, Sun Microsystems, Inc. */
	49	/* Sun Proprietary and Confidential */
	50	/* */
	51	/modifications: /
	52	/* */
	53
	54	module fflp_cam_ram (
	55	cclk,
	56	reset,
	57	disable_chksum,
	58	pio_disable_cam,
	59	cam_srch_latency,
	60	cam_srch_ratio,
	61	h1_init_value_reg_dout,
	62	h2_init_value_reg_dout,
	63	fwd_req,
	64	key_bus,
65	fwd_info_bus,
66	cam_hit,
67	cam_valid,
68	cam_haddr,
69	pio_rd_vld,
70	cam_msk_dat_out,
71	pio_wen,
72	pio_addr,
73	pio_32b_mode,
74	pio_wr_data,
75	am_din,
76	fc_fifo_ren_sync,
77	ext_fc_valid,
78
79	fwd_sched,
80	cam_data_inp,
81	cam_compare,
82	cam_pio_wr,
83	cam_pio_rd,
84	cam_pio_sel,
85	cam_index,
86	cam_key_reg0_dout,
87	cam_key_reg1_dout,
88	cam_key_reg2_dout,
89	cam_key_reg3_dout,
90	cam_key_mask_reg0_dout,
91	cam_key_mask_reg1_dout,
92	cam_key_mask_reg2_dout,
93	cam_key_mask_reg3_dout,
94	cam_cmd_stat_reg_dout,
95	am_rd,
96	am_wr,
97	am_addr,
98	am_dout,
99	ecc_parity_status,
100	fc_fifo_empty,
101	fc_fifo_dout
102
103	);
104
105	input cclk;
106	input reset;
107	input disable_chksum;
108	input pio_disable_cam;
109	input[3:0] cam_srch_latency;
110	input[3:0] cam_srch_ratio;
111	input[31:0] h1_init_value_reg_dout;
112	input[15:0] h2_init_value_reg_dout;
113	input fwd_req;
114	input[199:0] key_bus;
115	input[445:0] fwd_info_bus;
116	input cam_hit;
117	input cam_valid;
118	input[9:0] cam_haddr;
119	input pio_rd_vld;
120	input[199:0] cam_msk_dat_out;
121	input pio_wen;
122	input[19:0] pio_addr;
123	input pio_32b_mode;
124	input[63:0] pio_wr_data;
125	input[41:0] am_din;
126	input fc_fifo_ren_sync;
127	input[7:0] ext_fc_valid;
128
129	output fwd_sched;
130	output[199:0] cam_data_inp;
131	output cam_compare;
132	output cam_pio_wr;
133	output cam_pio_rd;
134	output cam_pio_sel;
135	output[9:0] cam_index;
136	output[7:0] cam_key_reg0_dout;
137	output[63:0] cam_key_reg1_dout;
138	output[63:0] cam_key_reg2_dout;
139	output[63:0] cam_key_reg3_dout;
140	output[7:0] cam_key_mask_reg0_dout;
141	output[63:0] cam_key_mask_reg1_dout;
142	output[63:0] cam_key_mask_reg2_dout;
143	output[63:0] cam_key_mask_reg3_dout;
144	output[20:0] cam_cmd_stat_reg_dout;
145	output am_rd;
146	output am_wr;
147	output[9:0] am_addr;
148	output[41:0] am_dout;
149	output[25:0] ecc_parity_status;
150	output fc_fifo_empty;
151	output[512:0] fc_fifo_dout;
152
153	wire fwd_sched;
154	wire cpu_sched;
155	wire[199:0] cam_data_inp;
156	wire cam_compare;
157	wire cam_pio_wr;
158	wire cam_pio_rd;
159	wire cam_pio_sel;
160	wire[7:0] cam_key_reg0_dout;
161	wire[63:0] cam_key_reg1_dout;
162	wire[63:0] cam_key_reg2_dout;
163	wire[63:0] cam_key_reg3_dout;
164	wire[7:0] cam_key_mask_reg0_dout;
165	wire[63:0] cam_key_mask_reg1_dout;
166	wire[63:0] cam_key_mask_reg2_dout;
167	wire[63:0] cam_key_mask_reg3_dout;
168	wire[20:0] cam_cmd_stat_reg_dout;
169	wire am_rd;
170	wire am_wr;
171	wire[9:0] am_addr;
172	wire[41:0] am_dout;
173	wire[25:0] ecc_parity_status;
174	wire fc_fifo_empty;
175	wire[512:0] fc_fifo_dout;
176	wire fc_fifo_space_avail;
177
178	wire[41:0] am_din_reg_dout;
179	wire cpu_req_cam_acc;
180	wire[1:0] ram_acc_type;
181	wire kick_off_ram_ctrl;
182	wire[9:0] cam_haddr_reg1_dout;
183	wire[9:0] cam_index;
184	wire matchout_5;
185	wire kick_off_ram_srch_5;
186	wire kick_off_ram_srch_4;
187	wire[445:0] fwd_info_bus_2;
188	wire[103:0] key_ecc_data_2;
189
190	wire[19:0] hash_v1;
191	wire[15:0] hash_v2;
192
193	`ifdef NEPTUNE
194	wire [3:0] do_nad;
195	wire [3:0] do_nor;
196	wire [3:0] do_inv;
197	wire [3:0] do_mux;
198	wire [3:0] do_q;
199	wire so;
200
201	nep_spare_fflp spare_fflp_0 (
202	.di_nd3 ({1'h1, 1'h1, do_q[3]}),
203	.di_nd2 ({1'h1, 1'h1, do_q[2]}),
204	.di_nd1 ({1'h1, 1'h1, do_q[1]}),
205	.di_nd0 ({1'h1, 1'h1, do_q[0]}),
206	.di_nr3 ({1'h0, 1'h0}),
207	.di_nr2 ({1'h0, 1'h0}),
208	.di_nr1 ({1'h0, 1'h0}),
209	.di_nr0 ({1'h0, 1'h0}),
210	.di_inv (do_nad[3:0]),
211	.di_mx3 ({1'h0, 1'h0}),
212	.di_mx2 ({1'h0, 1'h0}),
213	.di_mx1 ({1'h0, 1'h0}),
214	.di_mx0 ({1'h0, 1'h0}),
215	.mx_sel (do_nor[3:0]),
216	.di_reg (do_inv[3:0]),
217	.wt_ena (do_mux[3:0]),
218	.rst ({reset,reset,reset,reset}),
219	.si (1'h0),
220	.se (1'h0),
221	.clk (cclk),
222	.do_nad (do_nad[3:0]),
223	.do_nor (do_nor[3:0]),
224	.do_inv (do_inv[3:0]),
225	.do_mux (do_mux[3:0]),
226	.do_q (do_q[3:0]),
227	.so (so)
228	);
229
230	`endif
231
232
233	fflp_cam_sched fflp_cam_sched_inst (
234	.cclk (cclk),
235	.reset (reset),
236	.cam_srch_latency (cam_srch_latency),
237	.cam_srch_ratio (cam_srch_ratio),
238	.fwd_req (fwd_req),
239	.cpu_req_cam_acc (cpu_req_cam_acc),
240	.fc_fifo_space_avail (fc_fifo_space_avail),
241
242	.fwd_sched (fwd_sched),
243	.cpu_sched (cpu_sched)
244	);
245
246	fflp_cam_srch fflp_cam_srch_inst (
247	.cclk (cclk),
248	.reset (reset),
249	.pio_disable_cam (pio_disable_cam),
250	.cam_srch_latency (cam_srch_latency),
251	.fwd_sched (fwd_sched),
252	.cpu_sched (cpu_sched),
253	.key_bus (key_bus),
254	.fwd_info_bus (fwd_info_bus),
255	.cam_hit (cam_hit),
256	.cam_valid (cam_valid),
257	.cam_haddr (cam_haddr),
258	.pio_rd_vld (pio_rd_vld),
259	.cam_msk_dat_out (cam_msk_dat_out),
260	.am_din_reg_dout (am_din_reg_dout),
261	.pio_wen (pio_wen),
262	.pio_addr (pio_addr),
263	.pio_32b_mode (pio_32b_mode),
264	.pio_wr_data (pio_wr_data),
265
266	.cpu_req_cam_acc (cpu_req_cam_acc),
267	.ram_acc_type (ram_acc_type),
268	.kick_off_ram_ctrl (kick_off_ram_ctrl),
269	.cam_haddr_reg1_dout (cam_haddr_reg1_dout),
270	.cam_index (cam_index),
271	.cam_data_inp (cam_data_inp),
272	.cam_compare (cam_compare),
273	.cam_pio_wr (cam_pio_wr),
274	.cam_pio_rd (cam_pio_rd),
275	.cam_pio_sel (cam_pio_sel),
276	.matchout_5 (matchout_5),
277	.kick_off_ram_srch_4 (kick_off_ram_srch_4),
278	.kick_off_ram_srch_5 (kick_off_ram_srch_5),
279	.fwd_info_bus_2 (fwd_info_bus_2),
280	.key_ecc_data_2 (key_ecc_data_2),
281	.cam_key_reg0_dout (cam_key_reg0_dout),
282	.cam_key_reg1_dout (cam_key_reg1_dout),
283	.cam_key_reg2_dout (cam_key_reg2_dout),
284	.cam_key_reg3_dout (cam_key_reg3_dout),
285	.cam_key_mask_reg0_dout (cam_key_mask_reg0_dout),
286	.cam_key_mask_reg1_dout (cam_key_mask_reg1_dout),
287	.cam_key_mask_reg2_dout (cam_key_mask_reg2_dout),
288	.cam_key_mask_reg3_dout (cam_key_mask_reg3_dout),
289	.cam_cmd_stat_reg_dout (cam_cmd_stat_reg_dout)
290
291	);
292
293	fflp_ram_cntl fflp_ram_cntl_inst (
294	.cclk (cclk),
295	.reset (reset),
296	.ram_acc_type (ram_acc_type),
297	.kick_off_ram_ctrl (kick_off_ram_ctrl),
298	.cam_haddr_reg1_dout (cam_haddr_reg1_dout),
299	.cam_index (cam_index),
300	.cam_key_reg1_dout (cam_key_reg1_dout[41:0]),
301	.am_din (am_din),
302
303	.am_rd (am_rd),
304	.am_wr (am_wr),
305	.am_addr (am_addr),
306	.am_dout (am_dout),
307	.am_din_reg_dout (am_din_reg_dout)
308
309	);
310
311
312	fflp_hash_func fflp_hash_func_inst (
313	.cclk (cclk),
314	.reset (reset),
315	.fwd_info_hash_key (fwd_info_bus[361:0]),
316	.fwd_sched (fwd_sched),
317	.kick_off_ram_srch_4 (kick_off_ram_srch_4),
318	.h1_init_value_reg_dout (h1_init_value_reg_dout),
319	.h2_init_value_reg_dout (h2_init_value_reg_dout),
320
321	.hash_v1 (hash_v1),
322	.hash_v2 (hash_v2)
323
324	);
325
326	fflp_fwd_mstr fflp_fwd_mstr_inst (
327	.cclk (cclk),
328	.reset (reset),
329	.disable_chksum (disable_chksum),
330	.fc_fifo_ren_sync (fc_fifo_ren_sync),
331	.ext_fc_valid (ext_fc_valid),
332	.fwd_info_bus_2 (fwd_info_bus_2),
333	.key_ecc_data_2 (key_ecc_data_2),
334	.kick_off_ram_srch_5 (kick_off_ram_srch_5),
335	.matchout_5 (matchout_5),
336	.cam_haddr_reg1_dout (cam_haddr_reg1_dout),
337	.am_din_reg_dout (am_din_reg_dout),
338	.hash_v1 (hash_v1),
339	.hash_v2 (hash_v2),
340
341	.ecc_parity_status (ecc_parity_status),
342	.fc_fifo_space_avail (fc_fifo_space_avail),
343	.fc_fifo_empty (fc_fifo_empty),
344	.fc_fifo_dout (fc_fifo_dout)
345
346	);
347
348
349	endmodule
350
351
352
353
354