Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fflp_cam_srch.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /*project name: N2 */ | |
37 | /*module name: fflp_cam_srch */ | |
38 | /*description: */ | |
39 | /* Controls CAM accesses for both CPU commands and */ | |
40 | /* flow lookups */ | |
41 | /* */ | |
42 | /*parent module in: */ | |
43 | /*child modules in: fflp_cam_srch_sm */ | |
44 | /*interface modules: */ | |
45 | /*author name: Jeanne Cai */ | |
46 | /*date created: 10-03-04 */ | |
47 | /* */ | |
48 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
49 | /* Sun Proprietary and Confidential */ | |
50 | /* */ | |
51 | /*modifications: */ | |
52 | /* */ | |
53 | /**********************************************************************/ | |
54 | ||
55 | `include "fflp.h" | |
56 | ||
57 | module fflp_cam_srch | |
58 | ( | |
59 | cclk, | |
60 | reset, | |
61 | cam_srch_latency, | |
62 | pio_disable_cam, | |
63 | fwd_sched, | |
64 | cpu_sched, | |
65 | key_bus, | |
66 | fwd_info_bus, | |
67 | cam_hit, | |
68 | cam_valid, | |
69 | cam_haddr, | |
70 | pio_rd_vld, | |
71 | cam_msk_dat_out, | |
72 | am_din_reg_dout, | |
73 | pio_wen, | |
74 | pio_addr, | |
75 | pio_32b_mode, | |
76 | pio_wr_data, | |
77 | ||
78 | cpu_req_cam_acc, | |
79 | ram_acc_type, | |
80 | kick_off_ram_ctrl, | |
81 | cam_haddr_reg1_dout, | |
82 | cam_index, | |
83 | cam_data_inp, | |
84 | cam_compare, | |
85 | cam_pio_wr, | |
86 | cam_pio_rd, | |
87 | cam_pio_sel, | |
88 | matchout_5, | |
89 | kick_off_ram_srch_4, | |
90 | kick_off_ram_srch_5, | |
91 | fwd_info_bus_2, | |
92 | key_ecc_data_2, | |
93 | cam_key_reg0_dout, | |
94 | cam_key_reg1_dout, | |
95 | cam_key_reg2_dout, | |
96 | cam_key_reg3_dout, | |
97 | cam_key_mask_reg0_dout, | |
98 | cam_key_mask_reg1_dout, | |
99 | cam_key_mask_reg2_dout, | |
100 | cam_key_mask_reg3_dout, | |
101 | cam_cmd_stat_reg_dout | |
102 | ); | |
103 | ||
104 | input cclk; | |
105 | input reset; | |
106 | input pio_disable_cam; | |
107 | input[3:0] cam_srch_latency; | |
108 | input fwd_sched; | |
109 | input cpu_sched; | |
110 | input[199:0] key_bus; | |
111 | input[445:0] fwd_info_bus; | |
112 | input cam_hit; | |
113 | input cam_valid; | |
114 | input[9:0] cam_haddr; | |
115 | input pio_rd_vld; | |
116 | input[199:0] cam_msk_dat_out; | |
117 | input[41:0] am_din_reg_dout; | |
118 | input pio_wen; | |
119 | input[19:0] pio_addr; | |
120 | input pio_32b_mode; | |
121 | input[63:0] pio_wr_data; | |
122 | ||
123 | output cpu_req_cam_acc; | |
124 | output[1:0] ram_acc_type; | |
125 | output kick_off_ram_ctrl; | |
126 | output[9:0] cam_haddr_reg1_dout; | |
127 | output[9:0] cam_index; | |
128 | output[199:0] cam_data_inp; | |
129 | output cam_compare; | |
130 | output cam_pio_wr; | |
131 | output cam_pio_rd; | |
132 | output cam_pio_sel; | |
133 | output matchout_5; | |
134 | output kick_off_ram_srch_4; | |
135 | output kick_off_ram_srch_5; | |
136 | output[445:0] fwd_info_bus_2; | |
137 | output[103:0] key_ecc_data_2; | |
138 | output[7:0] cam_key_reg0_dout; | |
139 | output[63:0] cam_key_reg1_dout; | |
140 | output[63:0] cam_key_reg2_dout; | |
141 | output[63:0] cam_key_reg3_dout; | |
142 | output[7:0] cam_key_mask_reg0_dout; | |
143 | output[63:0] cam_key_mask_reg1_dout; | |
144 | output[63:0] cam_key_mask_reg2_dout; | |
145 | output[63:0] cam_key_mask_reg3_dout; | |
146 | output[20:0] cam_cmd_stat_reg_dout; | |
147 | ||
148 | wire srch_matchout_2; | |
149 | wire matchout_1_in; | |
150 | wire matchout_1; | |
151 | wire matchout_2; | |
152 | wire matchout_3; | |
153 | wire matchout_4; | |
154 | wire matchout_5; | |
155 | wire cpu_cmd_done; | |
156 | wire cpu_cmd_done_1; | |
157 | wire cpu_cmd_done_2; | |
158 | wire kick_off_ram_srch; | |
159 | wire kick_off_ram_srch_1; | |
160 | wire kick_off_ram_srch_2; | |
161 | wire kick_off_ram_srch_3; | |
162 | wire kick_off_ram_srch_4; | |
163 | wire kick_off_ram_srch_5; | |
164 | ||
165 | wire[445:0] fwd_info_bus_1; | |
166 | wire[445:0] fwd_info_bus_2; | |
167 | wire[103:0] key_ecc_data_1; | |
168 | wire[103:0] key_ecc_data_2; | |
169 | ||
170 | reg kick_off_ram_ctrl; | |
171 | reg[1:0] ram_acc_type; | |
172 | reg cpu_req_ram_done; | |
173 | ||
174 | wire do_srch_cycle; | |
175 | wire do_cpu_cycle; | |
176 | ||
177 | wire cpu_req_en; | |
178 | wire cpu_req_in; | |
179 | wire cpu_req; | |
180 | wire is_cpu_sched_en; | |
181 | wire is_cpu_sched_in; | |
182 | wire is_cpu_sched; | |
183 | ||
184 | wire cpu_req_ram_done_3_in; | |
185 | wire cpu_req_cam_rd_dly; | |
186 | wire cpu_req_cam_rd_done_1; | |
187 | wire cpu_req_cam_rd_done_2; | |
188 | wire cpu_req_cam_rd_done_3; | |
189 | wire cpu_req_cam_rd_done_4; | |
190 | wire cpu_req_cam_rd_done_5; | |
191 | wire cpu_req_cam_rd_done_6; | |
192 | wire cpu_req_cam_rd_done_7; | |
193 | wire cpu_req_cam_rd_done_8; | |
194 | wire cpu_req_ram_done_1; | |
195 | wire cpu_req_ram_done_2; | |
196 | wire cpu_req_ram_done_3; | |
197 | ||
198 | wire cam_key_reg0_en; | |
199 | wire[7:0] cam_key_reg0_in; | |
200 | wire[7:0] cam_key_reg0_dout; | |
201 | wire cam_key_reg1_en; | |
202 | wire[31:0] cam_key_reg1_in; | |
203 | wire cam_key_reg1_h_en; | |
204 | wire[31:0] cam_key_reg1_h_in; | |
205 | wire[63:0] cam_key_reg1_dout; | |
206 | wire cam_key_reg2_en; | |
207 | wire[31:0] cam_key_reg2_in; | |
208 | wire cam_key_reg2_h_en; | |
209 | wire[31:0] cam_key_reg2_h_in; | |
210 | wire[63:0] cam_key_reg2_dout; | |
211 | wire cam_key_reg3_en; | |
212 | wire[31:0] cam_key_reg3_in; | |
213 | wire cam_key_reg3_h_en; | |
214 | wire[31:0] cam_key_reg3_h_in; | |
215 | wire[63:0] cam_key_reg3_dout; | |
216 | wire cam_key_mask_reg0_en; | |
217 | wire[7:0] cam_key_mask_reg0_in; | |
218 | wire[7:0] cam_key_mask_reg0_dout; | |
219 | wire cam_key_mask_reg1_en; | |
220 | wire[31:0] cam_key_mask_reg1_in; | |
221 | wire cam_key_mask_reg1_h_en; | |
222 | wire[31:0] cam_key_mask_reg1_h_in; | |
223 | wire[63:0] cam_key_mask_reg1_dout; | |
224 | wire cam_key_mask_reg2_en; | |
225 | wire[31:0] cam_key_mask_reg2_in; | |
226 | wire cam_key_mask_reg2_h_en; | |
227 | wire[31:0] cam_key_mask_reg2_h_in; | |
228 | wire[63:0] cam_key_mask_reg2_dout; | |
229 | wire cam_key_mask_reg3_en; | |
230 | wire[31:0] cam_key_mask_reg3_in; | |
231 | wire cam_key_mask_reg3_h_en; | |
232 | wire[31:0] cam_key_mask_reg3_h_in; | |
233 | wire[63:0] cam_key_mask_reg3_dout; | |
234 | wire cam_cmd_stat_reg_en; | |
235 | wire[20:0] cam_cmd_stat_reg_in; | |
236 | //wire[20:0] cam_cmd_stat_reg_dout; | |
237 | ||
238 | reg[20:0] cam_cmd_stat_reg_dout; | |
239 | ||
240 | wire cam_pio_rd_in; | |
241 | wire cam_pio_sel_in; | |
242 | wire[199:0] cam_key_mask_data; | |
243 | wire[199:0] cam_key_data; | |
244 | wire[199:0] cam_key_data_mux; | |
245 | wire[199:0] data_inp_in; | |
246 | wire[199:0] cam_data_inp; | |
247 | wire cam_compare; | |
248 | wire cam_pio_wr; | |
249 | wire cam_pio_rd; | |
250 | wire cam_pio_sel; | |
251 | ||
252 | wire pio_rd_vld_1; | |
253 | wire[9:0] cam_haddr_reg1_dout; | |
254 | wire[199:0] cam_msk_dat_reg_dout; | |
255 | ||
256 | wire[9:0] cam_index; | |
257 | wire status_bit; | |
258 | wire[2:0] cpu_cmd; | |
259 | wire cpu_req_cam_rd; | |
260 | wire cpu_req_ram_rd; | |
261 | wire cpu_req_ram_wr; | |
262 | wire cpu_req_cam_acc; | |
263 | ||
264 | wire cam_match; | |
265 | wire[9:0] cam_loc; | |
266 | wire cpu_sched_done; | |
267 | wire cpu_req_done; | |
268 | wire[20:0] cam_ram_stat_dout; | |
269 | wire cpu_req_cam_rd_done; | |
270 | wire cam_pio_rd_sel; | |
271 | wire cam_key_reg_rd_en; | |
272 | wire cam_mask_reg_rd_en; | |
273 | ||
274 | wire cam_key_reg3_pio_wen; | |
275 | wire cam_key_reg2_pio_wen; | |
276 | wire cam_key_reg1_pio_wen; | |
277 | wire cam_key_reg0_pio_wen; | |
278 | wire cam_key_reg3_h_pio_wen; | |
279 | wire cam_key_reg2_h_pio_wen; | |
280 | wire cam_key_reg1_h_pio_wen; | |
281 | ||
282 | wire cam_key_mask_reg3_pio_wen; | |
283 | wire cam_key_mask_reg2_pio_wen; | |
284 | wire cam_key_mask_reg1_pio_wen; | |
285 | wire cam_key_mask_reg0_pio_wen; | |
286 | wire cam_key_mask_reg3_h_pio_wen; | |
287 | wire cam_key_mask_reg2_h_pio_wen; | |
288 | wire cam_key_mask_reg1_h_pio_wen; | |
289 | ||
290 | wire cam_cmd_stat_reg_pio_wen; | |
291 | ||
292 | wire cam_compare_sm; | |
293 | wire cam_pio_wr_sm; | |
294 | wire cam_pio_sel_sm; | |
295 | wire[1:0] data_inp_sel; | |
296 | wire data_inp_en; | |
297 | wire srch_wait_done; | |
298 | wire cpu_cmd_done_sm; | |
299 | wire kick_off_ram_srch_sm; | |
300 | wire new_cam_hit = cam_hit & cam_valid; | |
301 | ||
302 | ||
303 | /*********************************/ | |
304 | //CAM_RAM interface control | |
305 | /*********************************/ | |
306 | assign matchout_1 = matchout_1_in & !pio_disable_cam; | |
307 | assign srch_matchout_2 = (matchout_1 | matchout_2) & kick_off_ram_srch_2; | |
308 | ||
309 | dffr #(1) matchout1_reg (cclk, reset, new_cam_hit, matchout_1_in); | |
310 | dffr #(1) matchout2_reg (cclk, reset, matchout_1, matchout_2); | |
311 | dffr #(1) matchout3_reg (cclk, reset, srch_matchout_2, matchout_3); | |
312 | dffr #(1) matchout4_reg (cclk, reset, matchout_3, matchout_4); | |
313 | dffr #(1) matchout5_reg (cclk, reset, matchout_4, matchout_5); | |
314 | dffr #(1) cpu_cmd_done_reg (cclk, reset, cpu_cmd_done_sm, cpu_cmd_done); | |
315 | dffr #(1) cpu_cmd_done1_reg (cclk, reset, cpu_cmd_done, cpu_cmd_done_1); | |
316 | dffr #(1) cpu_cmd_done2_reg (cclk, reset, cpu_cmd_done_1, cpu_cmd_done_2); | |
317 | dffr #(1) kick_off_ram_srch_reg (cclk, reset, kick_off_ram_srch_sm, kick_off_ram_srch); | |
318 | dffr #(1) kick_off_ram_srch1_reg(cclk, reset, kick_off_ram_srch, kick_off_ram_srch_1); | |
319 | dffr #(1) kick_off_ram_srch2_reg(cclk, reset, kick_off_ram_srch_1, kick_off_ram_srch_2); | |
320 | dffr #(1) kick_off_ram_srch3_reg(cclk, reset, kick_off_ram_srch_2, kick_off_ram_srch_3); | |
321 | dffr #(1) kick_off_ram_srch4_reg(cclk, reset, kick_off_ram_srch_3, kick_off_ram_srch_4); | |
322 | dffr #(1) kick_off_ram_srch5_reg(cclk, reset, kick_off_ram_srch_4, kick_off_ram_srch_5); | |
323 | ||
324 | dffre #(446) fwd_info_bus_1_reg (cclk, reset, srch_wait_done, fwd_info_bus, fwd_info_bus_1); | |
325 | dffre #(446) fwd_info_bus_2_reg (cclk, reset, kick_off_ram_srch_4, fwd_info_bus_1, fwd_info_bus_2); | |
326 | dffre #(104) key_ecc_data_1_reg (cclk, reset, srch_wait_done, key_bus[103:0], key_ecc_data_1); | |
327 | dffre #(104) key_ecc_data_2_reg (cclk, reset, kick_off_ram_srch_4, key_ecc_data_1, key_ecc_data_2); | |
328 | ||
329 | always @ (kick_off_ram_srch_2 or kick_off_ram_srch_3 or | |
330 | kick_off_ram_srch_4 or kick_off_ram_srch_5 or | |
331 | srch_matchout_2 or cpu_req_ram_rd or cpu_req_ram_wr) | |
332 | begin | |
333 | if (srch_matchout_2) | |
334 | begin | |
335 | ram_acc_type = `RAM_RMW; | |
336 | kick_off_ram_ctrl = 1'b1; | |
337 | cpu_req_ram_done = 1'b0; | |
338 | end | |
339 | else if (kick_off_ram_srch_2 | kick_off_ram_srch_3 | kick_off_ram_srch_4 | kick_off_ram_srch_5) | |
340 | begin | |
341 | ram_acc_type = `RAM_RMW; | |
342 | kick_off_ram_ctrl = 1'b0; | |
343 | cpu_req_ram_done = 1'b0; | |
344 | end | |
345 | else if (cpu_req_ram_rd) | |
346 | begin | |
347 | ram_acc_type = `RAM_R; | |
348 | kick_off_ram_ctrl = 1'b1; | |
349 | cpu_req_ram_done = 1'b1; | |
350 | end | |
351 | else if (cpu_req_ram_wr) | |
352 | begin | |
353 | ram_acc_type = `RAM_W; | |
354 | kick_off_ram_ctrl = 1'b1; | |
355 | cpu_req_ram_done = 1'b1; | |
356 | end | |
357 | else | |
358 | begin | |
359 | ram_acc_type = `RAM_R; | |
360 | kick_off_ram_ctrl = 1'b0; | |
361 | cpu_req_ram_done = 1'b0; | |
362 | end | |
363 | end | |
364 | ||
365 | /**********************************/ | |
366 | //CPU Command Interface | |
367 | /**********************************/ | |
368 | assign cam_index = cam_cmd_stat_reg_dout[9:0]; | |
369 | assign status_bit = cam_cmd_stat_reg_dout[17]; | |
370 | assign cpu_cmd = cam_cmd_stat_reg_dout[20:18]; | |
371 | ||
372 | assign cpu_req_cam_rd = cpu_req & (cpu_cmd == `RD_CAM_KEY); | |
373 | assign cpu_req_ram_rd = cpu_req & (cpu_cmd == `RD_ASSOC_D); | |
374 | assign cpu_req_ram_wr = cpu_req & (cpu_cmd == `WR_ASSOC_D); | |
375 | assign cpu_req_cam_acc = cpu_req & !((cpu_cmd == `RD_CAM_KEY) | | |
376 | (cpu_cmd == `RD_ASSOC_D) | | |
377 | (cpu_cmd == `WR_ASSOC_D)); | |
378 | ||
379 | assign cam_match = (matchout_1 | matchout_2) & cpu_cmd_done_2; | |
380 | assign cam_loc = cam_match ? cam_haddr_reg1_dout[9:0] : cam_index[9:0]; | |
381 | assign cpu_sched_done = (cpu_sched | cpu_req_ram_done | cpu_req_cam_rd_done); | |
382 | assign cpu_req_done = (cpu_cmd_done_2 | cpu_req_ram_done_2 | cpu_req_cam_rd_done_8); | |
383 | assign cam_ram_stat_dout= {cpu_cmd[2:0], cpu_req_done, cam_match, 6'b0, cam_loc[9:0]}; | |
384 | ||
385 | assign cpu_req_en = cpu_sched_done | (!status_bit && !is_cpu_sched); | |
386 | assign cpu_req_in = cpu_sched_done ? 1'b0 : 1'b1; | |
387 | assign is_cpu_sched_en = cpu_sched_done | cpu_req_done; | |
388 | assign is_cpu_sched_in = cpu_sched_done ? 1'b1 : 1'b0; | |
389 | ||
390 | dffre #(1) cpu_req_reg (cclk, reset, cpu_req_en, cpu_req_in, cpu_req); | |
391 | dffre #(1) is_cpu_sched_reg (cclk, reset, is_cpu_sched_en, is_cpu_sched_in, is_cpu_sched); | |
392 | ||
393 | /********************************/ | |
394 | //TCAM Read, ASSOC_D Read | |
395 | /********************************/ | |
396 | assign cpu_req_ram_done_3_in = cpu_req_ram_done_2 & (cpu_cmd == `RD_ASSOC_D); | |
397 | ||
398 | dffr #(1) cpu_req_cam_rd_dly_reg (cclk, reset, cpu_req_cam_rd, cpu_req_cam_rd_dly); | |
399 | dffr #(1) cpu_req_cam_rd_done_1_reg (cclk, reset, cpu_req_cam_rd_done, cpu_req_cam_rd_done_1); | |
400 | dffr #(1) cpu_req_cam_rd_done_2_reg (cclk, reset, cpu_req_cam_rd_done_1, cpu_req_cam_rd_done_2); | |
401 | dffr #(1) cpu_req_cam_rd_done_3_reg (cclk, reset, cpu_req_cam_rd_done_2, cpu_req_cam_rd_done_3); | |
402 | dffr #(1) cpu_req_cam_rd_done_4_reg (cclk, reset, cpu_req_cam_rd_done_3, cpu_req_cam_rd_done_4); | |
403 | dffr #(1) cpu_req_cam_rd_done_5_reg (cclk, reset, cpu_req_cam_rd_done_4, cpu_req_cam_rd_done_5); | |
404 | dffr #(1) cpu_req_cam_rd_done_6_reg (cclk, reset, cpu_req_cam_rd_done_5, cpu_req_cam_rd_done_6); | |
405 | dffr #(1) cpu_req_cam_rd_done_7_reg (cclk, reset, cpu_req_cam_rd_done_6, cpu_req_cam_rd_done_7); | |
406 | dffr #(1) cpu_req_cam_rd_done_8_reg (cclk, reset, cpu_req_cam_rd_done_7, cpu_req_cam_rd_done_8); | |
407 | dffr #(1) cpu_req_ram_done_1_reg (cclk, reset, cpu_req_ram_done, cpu_req_ram_done_1); | |
408 | dffr #(1) cpu_req_ram_done_2_reg (cclk, reset, cpu_req_ram_done_1, cpu_req_ram_done_2); | |
409 | dffr #(1) cpu_req_ram_done_3_reg (cclk, reset, cpu_req_ram_done_3_in, cpu_req_ram_done_3); | |
410 | ||
411 | assign cpu_req_cam_rd_done = cpu_req_cam_rd & !cpu_req_cam_rd_dly; | |
412 | assign cam_pio_rd_sel = (cpu_req_cam_rd_done_2 | cpu_req_cam_rd_done_3) ? 1'b1 : 1'b0; | |
413 | ||
414 | assign cam_key_reg_rd_en = (cpu_req_cam_rd_done_5 | cpu_req_cam_rd_done_6) & pio_rd_vld_1; | |
415 | assign cam_mask_reg_rd_en = (cpu_req_cam_rd_done_7 | cpu_req_cam_rd_done_8) & pio_rd_vld_1; | |
416 | ||
417 | ||
418 | /********************************************/ | |
419 | //CAM-RAM PIO READ/WRITE | |
420 | /********************************************/ | |
421 | assign cam_key_reg0_pio_wen = pio_wen & (pio_addr == 20'ha0090); | |
422 | assign cam_key_reg1_pio_wen = pio_wen & (pio_addr == 20'ha0098); | |
423 | assign cam_key_reg2_pio_wen = pio_wen & (pio_addr == 20'ha00a0); | |
424 | assign cam_key_reg3_pio_wen = pio_wen & (pio_addr == 20'ha00a8); | |
425 | ||
426 | assign cam_key_reg1_h_pio_wen = pio_wen & ((pio_addr == 20'ha0098) & !pio_32b_mode | (pio_addr == 20'ha009c) & pio_32b_mode); | |
427 | assign cam_key_reg2_h_pio_wen = pio_wen & ((pio_addr == 20'ha00a0) & !pio_32b_mode | (pio_addr == 20'ha00a4) & pio_32b_mode); | |
428 | assign cam_key_reg3_h_pio_wen = pio_wen & ((pio_addr == 20'ha00a8) & !pio_32b_mode | (pio_addr == 20'ha00ac) & pio_32b_mode); | |
429 | ||
430 | assign cam_key_mask_reg0_pio_wen= pio_wen & (pio_addr == 20'ha00b0); | |
431 | assign cam_key_mask_reg1_pio_wen= pio_wen & (pio_addr == 20'ha00b8); | |
432 | assign cam_key_mask_reg2_pio_wen= pio_wen & (pio_addr == 20'ha00c0); | |
433 | assign cam_key_mask_reg3_pio_wen= pio_wen & (pio_addr == 20'ha00c8); | |
434 | ||
435 | assign cam_key_mask_reg1_h_pio_wen= pio_wen & ((pio_addr == 20'ha00b8) & !pio_32b_mode | (pio_addr == 20'ha00bc) & pio_32b_mode); | |
436 | assign cam_key_mask_reg2_h_pio_wen= pio_wen & ((pio_addr == 20'ha00c0) & !pio_32b_mode | (pio_addr == 20'ha00c4) & pio_32b_mode); | |
437 | assign cam_key_mask_reg3_h_pio_wen= pio_wen & ((pio_addr == 20'ha00c8) & !pio_32b_mode | (pio_addr == 20'ha00cc) & pio_32b_mode); | |
438 | ||
439 | assign cam_cmd_stat_reg_pio_wen = pio_wen & (pio_addr == 20'ha00d0); | |
440 | ||
441 | assign cam_key_reg0_en = cam_key_reg0_pio_wen | cam_key_reg_rd_en; | |
442 | assign cam_key_reg0_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[199:192] : pio_wr_data[7:0]; | |
443 | ||
444 | assign cam_key_reg1_en = cam_key_reg1_pio_wen | cam_key_reg_rd_en | cpu_req_ram_done_3; | |
445 | assign cam_key_reg1_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[159:128] : | |
446 | cpu_req_ram_done_3 ? am_din_reg_dout[31:0] : | |
447 | pio_wr_data[31:0]; | |
448 | ||
449 | assign cam_key_reg1_h_en = cam_key_reg1_h_pio_wen | cam_key_reg_rd_en | cpu_req_ram_done_3; | |
450 | assign cam_key_reg1_h_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[191:160] : | |
451 | cpu_req_ram_done_3 ? {22'b0, am_din_reg_dout[41:32]} : | |
452 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
453 | ||
454 | assign cam_key_reg2_en = cam_key_reg2_pio_wen | cam_key_reg_rd_en; | |
455 | assign cam_key_reg2_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[95:64] : pio_wr_data[31:0]; | |
456 | ||
457 | assign cam_key_reg2_h_en = cam_key_reg2_h_pio_wen | cam_key_reg_rd_en; | |
458 | assign cam_key_reg2_h_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[127:96] : | |
459 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
460 | ||
461 | assign cam_key_reg3_en = cam_key_reg3_pio_wen | cam_key_reg_rd_en; | |
462 | assign cam_key_reg3_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[31:0] : pio_wr_data[31:0]; | |
463 | ||
464 | assign cam_key_reg3_h_en = cam_key_reg3_h_pio_wen | cam_key_reg_rd_en; | |
465 | assign cam_key_reg3_h_in = cam_key_reg_rd_en ? cam_msk_dat_reg_dout[63:32] : | |
466 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
467 | ||
468 | ||
469 | assign cam_key_mask_reg0_en = cam_key_mask_reg0_pio_wen | cam_mask_reg_rd_en; | |
470 | assign cam_key_mask_reg0_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[199:192] : pio_wr_data[7:0]; | |
471 | ||
472 | assign cam_key_mask_reg1_en = cam_key_mask_reg1_pio_wen | cam_mask_reg_rd_en; | |
473 | assign cam_key_mask_reg1_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[159:128] : pio_wr_data[31:0]; | |
474 | ||
475 | assign cam_key_mask_reg1_h_en = cam_key_mask_reg1_h_pio_wen | cam_mask_reg_rd_en; | |
476 | assign cam_key_mask_reg1_h_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[191:160] : | |
477 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
478 | ||
479 | assign cam_key_mask_reg2_en = cam_key_mask_reg2_pio_wen | cam_mask_reg_rd_en; | |
480 | assign cam_key_mask_reg2_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[95:64] : pio_wr_data[31:0]; | |
481 | ||
482 | assign cam_key_mask_reg2_h_en = cam_key_mask_reg2_h_pio_wen | cam_mask_reg_rd_en; | |
483 | assign cam_key_mask_reg2_h_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[127:96] : | |
484 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
485 | ||
486 | assign cam_key_mask_reg3_en = cam_key_mask_reg3_pio_wen | cam_mask_reg_rd_en; | |
487 | assign cam_key_mask_reg3_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[31:0] : pio_wr_data[31:0]; | |
488 | ||
489 | assign cam_key_mask_reg3_h_en = cam_key_mask_reg3_h_pio_wen | cam_mask_reg_rd_en; | |
490 | assign cam_key_mask_reg3_h_in = cam_mask_reg_rd_en ? cam_msk_dat_reg_dout[63:32] : | |
491 | pio_32b_mode ? pio_wr_data[31:0] : pio_wr_data[63:32]; | |
492 | ||
493 | assign cam_cmd_stat_reg_en = cam_cmd_stat_reg_pio_wen | cpu_req_done; | |
494 | assign cam_cmd_stat_reg_in = cpu_req_done ? cam_ram_stat_dout[20:0] : {pio_wr_data[20:16], 6'b0, pio_wr_data[9:0]}; | |
495 | ||
496 | dffre #(8) cam_key_reg0 (cclk, reset, cam_key_reg0_en, cam_key_reg0_in, cam_key_reg0_dout[7:0]); | |
497 | dffre #(32) cam_key_reg1_l (cclk, reset, cam_key_reg1_en, cam_key_reg1_in, cam_key_reg1_dout[31:0]); | |
498 | dffre #(32) cam_key_reg2_l (cclk, reset, cam_key_reg2_en, cam_key_reg2_in, cam_key_reg2_dout[31:0]); | |
499 | dffre #(32) cam_key_reg3_l (cclk, reset, cam_key_reg3_en, cam_key_reg3_in, cam_key_reg3_dout[31:0]); | |
500 | dffre #(32) cam_key_reg1_h (cclk, reset, cam_key_reg1_h_en, cam_key_reg1_h_in, cam_key_reg1_dout[63:32]); | |
501 | dffre #(32) cam_key_reg2_h (cclk, reset, cam_key_reg2_h_en, cam_key_reg2_h_in, cam_key_reg2_dout[63:32]); | |
502 | dffre #(32) cam_key_reg3_h (cclk, reset, cam_key_reg3_h_en, cam_key_reg3_h_in, cam_key_reg3_dout[63:32]); | |
503 | ||
504 | dffre #(8) cam_key_mask_reg0 (cclk, reset, cam_key_mask_reg0_en, cam_key_mask_reg0_in, cam_key_mask_reg0_dout[7:0]); | |
505 | dffre #(32) cam_key_mask_reg1_l (cclk, reset, cam_key_mask_reg1_en, cam_key_mask_reg1_in, cam_key_mask_reg1_dout[31:0]); | |
506 | dffre #(32) cam_key_mask_reg2_l (cclk, reset, cam_key_mask_reg2_en, cam_key_mask_reg2_in, cam_key_mask_reg2_dout[31:0]); | |
507 | dffre #(32) cam_key_mask_reg3_l (cclk, reset, cam_key_mask_reg3_en, cam_key_mask_reg3_in, cam_key_mask_reg3_dout[31:0]); | |
508 | dffre #(32) cam_key_mask_reg1_h (cclk, reset, cam_key_mask_reg1_h_en, cam_key_mask_reg1_h_in, cam_key_mask_reg1_dout[63:32]); | |
509 | dffre #(32) cam_key_mask_reg2_h (cclk, reset, cam_key_mask_reg2_h_en, cam_key_mask_reg2_h_in, cam_key_mask_reg2_dout[63:32]); | |
510 | dffre #(32) cam_key_mask_reg3_h (cclk, reset, cam_key_mask_reg3_h_en, cam_key_mask_reg3_h_in, cam_key_mask_reg3_dout[63:32]); | |
511 | ||
512 | //dffre #(21) cam_cmd_stat_reg (cclk, reset, cam_cmd_stat_reg_en, cam_cmd_stat_reg_in, cam_cmd_stat_reg_dout); | |
513 | ||
514 | always @ (posedge cclk) | |
515 | if (reset) | |
516 | cam_cmd_stat_reg_dout <= 21'b0_0010_0000_0000_0000_0000; | |
517 | else if (cam_cmd_stat_reg_en) | |
518 | cam_cmd_stat_reg_dout <= cam_cmd_stat_reg_in; | |
519 | else | |
520 | cam_cmd_stat_reg_dout <= cam_cmd_stat_reg_dout; | |
521 | ||
522 | /********************************************/ | |
523 | //Search command decode | |
524 | /********************************************/ | |
525 | dffr #(1) do_srch_cycle_reg (cclk, reset, fwd_sched, do_srch_cycle); | |
526 | dffr #(1) do_cpu_cycle_reg (cclk, reset, cpu_sched, do_cpu_cycle); | |
527 | ||
528 | /*********************************/ | |
529 | //TCAM interface signals | |
530 | /*********************************/ | |
531 | assign cam_pio_rd_in = (cpu_req_cam_rd_done | cpu_req_cam_rd_done_1 | cpu_req_cam_rd_done_2 | cpu_req_cam_rd_done_3); | |
532 | assign cam_pio_sel_in = (cam_pio_sel_sm | cam_pio_rd_sel); | |
533 | ||
534 | assign cam_key_mask_data = {cam_key_mask_reg0_dout[7:0], cam_key_mask_reg1_dout[63:0], | |
535 | cam_key_mask_reg2_dout[63:0], cam_key_mask_reg3_dout[63:0]}; | |
536 | ||
537 | assign cam_key_data = {cam_key_reg0_dout[7:0], cam_key_reg1_dout[63:0], | |
538 | cam_key_reg2_dout[63:0], cam_key_reg3_dout[63:0]}; | |
539 | ||
540 | assign cam_key_data_mux = data_inp_sel[0] ? cam_key_mask_data : cam_key_data; | |
541 | ||
542 | assign data_inp_in = data_inp_sel[1] ? cam_key_data_mux[199:0] : key_bus[199:0]; | |
543 | ||
544 | dffre #(200) cam_data_inp_reg (cclk, reset, data_inp_en, data_inp_in, cam_data_inp); | |
545 | dffr #(1) cam_compare_reg (cclk, reset, cam_compare_sm, cam_compare); | |
546 | dffr #(1) cam_pio_wr_reg (cclk, reset, cam_pio_wr_sm, cam_pio_wr); | |
547 | dffr #(1) cam_pio_rd_reg (cclk, reset, cam_pio_rd_in, cam_pio_rd); | |
548 | dffr #(1) cam_pio_sel_reg (cclk, reset, cam_pio_sel_in, cam_pio_sel); | |
549 | ||
550 | dffre #(10) cam_haddr_reg1 (cclk, reset, cam_valid, cam_haddr[9:0], cam_haddr_reg1_dout); | |
551 | dffr #(200) cam_msk_dat_reg (cclk, reset, cam_msk_dat_out[199:0], cam_msk_dat_reg_dout); | |
552 | dffr #(1) pio_rd_vld_reg (cclk, reset, pio_rd_vld, pio_rd_vld_1); | |
553 | ||
554 | ||
555 | //instantiate state machine | |
556 | fflp_cam_srch_sm fflp_cam_srch_sm_inst | |
557 | ( | |
558 | .cclk (cclk), | |
559 | .reset (reset), | |
560 | .cam_srch_latency (cam_srch_latency), | |
561 | .do_srch_cycle (do_srch_cycle), | |
562 | .do_cpu_cycle (do_cpu_cycle), | |
563 | .cpu_cmd (cpu_cmd), | |
564 | ||
565 | .cam_compare_sm (cam_compare_sm), | |
566 | .cam_pio_wr_sm (cam_pio_wr_sm), | |
567 | .cam_pio_sel_sm (cam_pio_sel_sm), | |
568 | .data_inp_sel (data_inp_sel), | |
569 | .data_inp_en (data_inp_en), | |
570 | .srch_wait_done (srch_wait_done), | |
571 | .cpu_cmd_done_sm (cpu_cmd_done_sm), | |
572 | .kick_off_ram_srch_sm (kick_off_ram_srch_sm) | |
573 | ); | |
574 | ||
575 | `ifdef NEPTUNE | |
576 | wire [3:0] do_nad; | |
577 | wire [3:0] do_nor; | |
578 | wire [3:0] do_inv; | |
579 | wire [3:0] do_mux; | |
580 | wire [3:0] do_q; | |
581 | wire so; | |
582 | ||
583 | nep_spare_fflp spare_fflp_0 ( | |
584 | .di_nd3 ({1'h1, 1'h1, do_q[3]}), | |
585 | .di_nd2 ({1'h1, 1'h1, do_q[2]}), | |
586 | .di_nd1 ({1'h1, 1'h1, do_q[1]}), | |
587 | .di_nd0 ({1'h1, 1'h1, do_q[0]}), | |
588 | .di_nr3 ({1'h0, 1'h0}), | |
589 | .di_nr2 ({1'h0, 1'h0}), | |
590 | .di_nr1 ({1'h0, 1'h0}), | |
591 | .di_nr0 ({1'h0, 1'h0}), | |
592 | .di_inv (do_nad[3:0]), | |
593 | .di_mx3 ({1'h0, 1'h0}), | |
594 | .di_mx2 ({1'h0, 1'h0}), | |
595 | .di_mx1 ({1'h0, 1'h0}), | |
596 | .di_mx0 ({1'h0, 1'h0}), | |
597 | .mx_sel (do_nor[3:0]), | |
598 | .di_reg (do_inv[3:0]), | |
599 | .wt_ena (do_mux[3:0]), | |
600 | .rst ({reset,reset,reset,reset}), | |
601 | .si (1'h0), | |
602 | .se (1'h0), | |
603 | .clk (cclk), | |
604 | .do_nad (do_nad[3:0]), | |
605 | .do_nor (do_nor[3:0]), | |
606 | .do_inv (do_inv[3:0]), | |
607 | .do_mux (do_mux[3:0]), | |
608 | .do_q (do_q[3:0]), | |
609 | .so (so) | |
610 | ); | |
611 | ||
612 | `endif | |
613 | ||
614 | ||
615 | endmodule |