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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fflp_fcram_cntl_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /*project name: N2 */ | |
37 | /*module name: fflp_fcram_cntl_sm */ | |
38 | /*description: FCRAM access protocol */ | |
39 | /* */ | |
40 | /*parent module in: fflp_fcram_cntl */ | |
41 | /*child modules in: none */ | |
42 | /*interface modules: */ | |
43 | /*author name: Jeanne Cai */ | |
44 | /*date created: 04-08-04 */ | |
45 | /* */ | |
46 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
47 | /* Sun Proprietary and Confidential */ | |
48 | /* */ | |
49 | /*modifications: */ | |
50 | /* */ | |
51 | /* */ | |
52 | ||
53 | `include "fflp.h" | |
54 | module fflp_fcram_cntl_sm | |
55 | ( | |
56 | cclk, | |
57 | reset, | |
58 | fflp_init_done, | |
59 | fio_mstr_ready, | |
60 | fcram_refresh_timer_reg_dout, | |
61 | do_srch_cycle, | |
62 | do_cpu_cycle, | |
63 | cpu_cmd, | |
64 | cpu_bk0, | |
65 | cpu_bk1, | |
66 | ||
67 | fcram_cmd_sm, | |
68 | fcram_ba0_sm, | |
69 | fcram_ba1_sm, | |
70 | fcram_addr_sel, | |
71 | fcram_addr_en, | |
72 | fcram_ds_sm, | |
73 | // fcram_triz_en_sm, | |
74 | fflp_fcram_slv_update, | |
75 | power_on_wait_cnt_done_r, | |
76 | // fc_din_reg_en_sm, | |
77 | srch_burst_done_sm, | |
78 | cpu_burst_done_sm, | |
79 | fcram_sm_state | |
80 | ||
81 | ); | |
82 | ||
83 | input cclk; | |
84 | input reset; | |
85 | input fflp_init_done; | |
86 | input fio_mstr_ready; | |
87 | input[31:0] fcram_refresh_timer_reg_dout; | |
88 | input do_srch_cycle; | |
89 | input do_cpu_cycle; | |
90 | input cpu_cmd; | |
91 | input cpu_bk0; | |
92 | input cpu_bk1; | |
93 | ||
94 | output[1:0] fcram_cmd_sm; | |
95 | output fcram_ba0_sm; | |
96 | output fcram_ba1_sm; | |
97 | output[2:0] fcram_addr_sel; | |
98 | output fcram_addr_en; | |
99 | output fcram_ds_sm; | |
100 | //output fcram_triz_en_sm; | |
101 | output fflp_fcram_slv_update; | |
102 | output power_on_wait_cnt_done_r; | |
103 | //output fc_din_reg_en_sm; | |
104 | output srch_burst_done_sm; | |
105 | output cpu_burst_done_sm; | |
106 | output[4:0] fcram_sm_state; | |
107 | ||
108 | reg[1:0] fcram_cmd_sm; | |
109 | reg fcram_ba0_sm; | |
110 | reg fcram_ba1_sm; | |
111 | reg[2:0] fcram_addr_sel; | |
112 | reg fcram_addr_en; | |
113 | reg fcram_ds_sm; | |
114 | //reg fcram_triz_en_sm; | |
115 | //reg fc_din_reg_en_sm; | |
116 | reg inc_wait_cnt; | |
117 | reg inc_init_ref_cnt; | |
118 | reg fcram_ref_done; | |
119 | reg fcram_ref_wait; | |
120 | reg srch_irc_time_en; | |
121 | reg cpu_irc_time_en; | |
122 | reg irc_time_reset; | |
123 | reg srch_burst_done_sm; | |
124 | reg cpu_burst_done_sm; | |
125 | reg wait_time_done_cyc; | |
126 | reg irefc_time_done_cyc; | |
127 | reg init_wait_done_cyc; | |
128 | reg[4:0] next_state; | |
129 | ||
130 | wire[4:0] state; | |
131 | wire wait_time_done; | |
132 | wire irefc_time_done; | |
133 | wire fcram_init_done; | |
134 | wire init_wait_done; | |
135 | wire init_wait_done_pre; | |
136 | wire do_refresh_min; | |
137 | wire do_refresh_max; | |
138 | wire wait_cnt_reset; | |
139 | wire[8:0] wait_cnt_in; | |
140 | wire[8:0] wait_cnt; | |
141 | ||
142 | wire irc_time_done; | |
143 | wire irc_time_cnt_en; | |
144 | wire[2:0] irc_time_cnt_in; | |
145 | wire[2:0] irc_time_cnt; | |
146 | wire srch_irc_wait_en; | |
147 | wire srch_irc_wait_in; | |
148 | wire srch_irc_wait; | |
149 | wire cpu_irc_wait_en; | |
150 | wire cpu_irc_wait_in; | |
151 | wire cpu_irc_wait; | |
152 | ||
153 | wire init_ref_cnt_done; | |
154 | wire[1:0] init_ref_cnt_in; | |
155 | wire[1:0] init_ref_cnt; | |
156 | wire ref_tmax_cnt_done; | |
157 | wire[10:0] ref_tmax_cnt_in; | |
158 | wire[10:0] ref_tmax_cnt; | |
159 | wire ref_tmin_cnt_done; | |
160 | wire do_refresh_min_en; | |
161 | wire do_refresh_max_en; | |
162 | wire do_refresh_in; | |
163 | ||
164 | wire[1:0] cpu_bk; | |
165 | wire cpu_same_bk0; | |
166 | wire cpu_same_bk1; | |
167 | wire cpu_same_bk2; | |
168 | wire cpu_same_bk3; | |
169 | wire do_srch_cycle_w; | |
170 | wire do_cpu_cycle_w; | |
171 | wire srch_rwd_wait; | |
172 | wire do_cpu_cycle_wr; | |
173 | ||
174 | wire[10:0] pio_refresh_cycle_min; | |
175 | wire[10:0] pio_refresh_cycle_max; | |
176 | wire[10:0] refresh_cycle_min; | |
177 | wire[10:0] refresh_cycle_max; | |
178 | ||
179 | wire[15:0] power_on_wait_cnt_in; | |
180 | wire[15:0] power_on_wait_cnt; | |
181 | wire power_on_wait_cnt_done; | |
182 | wire power_on_wait_cnt_done_r; | |
183 | ||
184 | wire fio_slv_update_in; | |
185 | wire fflp_fcram_slv_update; | |
186 | ||
187 | wire[4:0] fcram_sm_state = state; | |
188 | ||
189 | assign pio_refresh_cycle_min = fcram_refresh_timer_reg_dout[10:0]; | |
190 | assign pio_refresh_cycle_max = fcram_refresh_timer_reg_dout[26:16]; | |
191 | assign refresh_cycle_min = (pio_refresh_cycle_min == 11'b0) ? 11'd136 : pio_refresh_cycle_min; | |
192 | assign refresh_cycle_max = (pio_refresh_cycle_max == 11'b0) ? 11'd1160 : pio_refresh_cycle_max; | |
193 | ||
194 | assign cpu_bk = {cpu_bk1, cpu_bk0}; | |
195 | assign cpu_same_bk0 = (cpu_bk == 2'b00); | |
196 | assign cpu_same_bk1 = (cpu_bk == 2'b01); | |
197 | assign cpu_same_bk2 = (cpu_bk == 2'b10); | |
198 | assign cpu_same_bk3 = (cpu_bk == 2'b11); | |
199 | ||
200 | assign do_srch_cycle_w = do_srch_cycle & (cpu_same_bk2 & (irc_time_cnt == 3'd0) | | |
201 | cpu_same_bk1 & !(&irc_time_cnt[1:0]) | | |
202 | cpu_same_bk0) & cpu_irc_wait; | |
203 | ||
204 | assign do_cpu_cycle_w = do_cpu_cycle & (cpu_same_bk1 & (irc_time_cnt == 3'd0) | | |
205 | cpu_same_bk2 & !(&irc_time_cnt[1:0]) | | |
206 | cpu_same_bk3) & srch_irc_wait; | |
207 | ||
208 | assign srch_rwd_wait = srch_irc_wait & (irc_time_cnt[2:1] == 2'b00); | |
209 | assign do_cpu_cycle_wr = do_cpu_cycle & cpu_cmd & srch_rwd_wait; //cpu writes bank0 | |
210 | ||
211 | //state machine states | |
212 | parameter | |
213 | IDLE = 5'd0, | |
214 | IPDA_WAIT1 = 5'd1, | |
215 | IPDA_WAIT2 = 5'd2, | |
216 | SET_MODE_REG = 5'd3, | |
217 | SET_MODE_REG_CYC2 = 5'd4, | |
218 | IRSC_TIME_WAIT1 = 5'd5, | |
219 | IRSC_TIME_WAIT2 = 5'd6, | |
220 | SET_EMODE_REG = 5'd7, | |
221 | SET_EMODE_REG_CYC2 = 5'd8, | |
222 | IRSC_TIME_WAIT3 = 5'd9, | |
223 | IRSC_TIME_WAIT4 = 5'd10, | |
224 | AUTO_REF = 5'd11, | |
225 | AUTO_REF_CYC2 = 5'd12, | |
226 | IREFC_TIME_WAIT = 5'd13, | |
227 | INIT_WAIT = 5'd14, | |
228 | READY = 5'd15, | |
229 | LOOKUP_CYC2 = 5'd16, | |
230 | LOOKUP_CYC3 = 5'd17, | |
231 | LOOKUP_CYC4 = 5'd18, | |
232 | LOOKUP_CYC5 = 5'd19, | |
233 | LOOKUP_CYC6 = 5'd20, | |
234 | LOOKUP_CYC7 = 5'd21, | |
235 | LOOKUP_CYC8 = 5'd22, | |
236 | IRC_TIME_WAIT = 5'd23, | |
237 | CPU_CYC2 = 5'd24; | |
238 | ||
239 | ||
240 | always @ ( | |
241 | state or cpu_cmd or fflp_init_done or | |
242 | do_srch_cycle or do_cpu_cycle or | |
243 | do_srch_cycle_w or do_cpu_cycle_w or | |
244 | do_cpu_cycle_wr or cpu_bk0 or cpu_bk1 or | |
245 | do_refresh_max or do_refresh_min or | |
246 | init_ref_cnt_done or fcram_init_done or | |
247 | fio_mstr_ready or power_on_wait_cnt_done_r or wait_cnt) | |
248 | ||
249 | begin | |
250 | fcram_cmd_sm = `DESL; | |
251 | fcram_ba0_sm = 1'b0; | |
252 | fcram_ba1_sm = 1'b0; | |
253 | fcram_addr_sel = 3'b000; | |
254 | fcram_addr_en = 1'b0; | |
255 | fcram_ds_sm = 1'b0; | |
256 | // fcram_triz_en_sm = 1'b0; | |
257 | // fc_din_reg_en_sm = 1'b0; | |
258 | inc_wait_cnt = 1'b0; | |
259 | inc_init_ref_cnt = 1'b0; | |
260 | fcram_ref_done = 1'b0; | |
261 | fcram_ref_wait = 1'b0; | |
262 | srch_irc_time_en = 1'b0; | |
263 | cpu_irc_time_en = 1'b0; | |
264 | irc_time_reset = 1'b0; | |
265 | srch_burst_done_sm = 1'b0; | |
266 | cpu_burst_done_sm = 1'b0; | |
267 | wait_time_done_cyc = 1'b0; | |
268 | irefc_time_done_cyc = 1'b0; | |
269 | init_wait_done_cyc = 1'b0; | |
270 | next_state = 5'b00000; | |
271 | ||
272 | case (state) //synopsys parallel_case full_case | |
273 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_fcram_cntl_sm:state" | |
274 | ||
275 | IDLE: | |
276 | begin | |
277 | fcram_cmd_sm = `DESL; | |
278 | fcram_ba0_sm = 1'b0; | |
279 | fcram_ba1_sm = 1'b0; | |
280 | fcram_addr_sel = 3'b000; | |
281 | fcram_addr_en = 1'b0; | |
282 | fcram_ds_sm = 1'b0; | |
283 | if (fflp_init_done & fio_mstr_ready & power_on_wait_cnt_done_r) | |
284 | next_state = IPDA_WAIT1; | |
285 | else | |
286 | next_state = IDLE; | |
287 | end | |
288 | ||
289 | IPDA_WAIT1: | |
290 | begin | |
291 | next_state = IPDA_WAIT2; | |
292 | end | |
293 | ||
294 | ||
295 | IPDA_WAIT2: | |
296 | begin | |
297 | next_state = SET_MODE_REG; | |
298 | end | |
299 | ||
300 | ||
301 | SET_MODE_REG: | |
302 | begin | |
303 | fcram_cmd_sm = `RDA; | |
304 | fcram_ba0_sm = 1'b0; | |
305 | fcram_ba1_sm = 1'b0; | |
306 | fcram_addr_sel = 3'b000; | |
307 | fcram_addr_en = 1'b1; | |
308 | fcram_ds_sm = 1'b0; | |
309 | next_state = SET_MODE_REG_CYC2; | |
310 | end | |
311 | ||
312 | SET_MODE_REG_CYC2: | |
313 | begin | |
314 | fcram_cmd_sm = `MRS; | |
315 | fcram_ba0_sm = 1'b0; //select mode reg | |
316 | fcram_ba1_sm = 1'b0; | |
317 | fcram_addr_sel = 3'b000; | |
318 | fcram_addr_en = 1'b1; | |
319 | fcram_ds_sm = 1'b0; | |
320 | next_state = IRSC_TIME_WAIT1; | |
321 | ||
322 | end | |
323 | ||
324 | IRSC_TIME_WAIT1: //wait IRSC = 7cyc | |
325 | begin | |
326 | fcram_cmd_sm = `DESL; | |
327 | fcram_ba0_sm = 1'b0; | |
328 | fcram_ba1_sm = 1'b0; | |
329 | fcram_addr_sel = 3'b000; | |
330 | fcram_addr_en = 1'b0; | |
331 | fcram_ds_sm = 1'b0; | |
332 | next_state = IRSC_TIME_WAIT2; | |
333 | end | |
334 | ||
335 | IRSC_TIME_WAIT2: | |
336 | begin | |
337 | fcram_cmd_sm = `DESL; | |
338 | fcram_ba0_sm = 1'b0; | |
339 | fcram_ba1_sm = 1'b0; | |
340 | fcram_addr_sel = 3'b000; | |
341 | fcram_addr_en = 1'b0; | |
342 | fcram_ds_sm = 1'b0; | |
343 | inc_wait_cnt = 1'b1; | |
344 | wait_time_done_cyc = 1'b1; | |
345 | if (wait_cnt[2]) | |
346 | next_state = SET_EMODE_REG; | |
347 | else | |
348 | next_state = state; | |
349 | end | |
350 | ||
351 | SET_EMODE_REG: | |
352 | begin | |
353 | fcram_cmd_sm = `RDA; | |
354 | fcram_ba0_sm = 1'b1; | |
355 | fcram_ba1_sm = 1'b0; | |
356 | fcram_addr_sel = 3'b001; | |
357 | fcram_addr_en = 1'b1; | |
358 | fcram_ds_sm = 1'b0; | |
359 | next_state = SET_EMODE_REG_CYC2; | |
360 | end | |
361 | ||
362 | SET_EMODE_REG_CYC2: | |
363 | begin | |
364 | fcram_cmd_sm = `MRS; | |
365 | fcram_ba0_sm = 1'b1; //select extended mode reg | |
366 | fcram_ba1_sm = 1'b0; | |
367 | fcram_addr_sel = 3'b001; | |
368 | fcram_addr_en = 1'b1; | |
369 | fcram_ds_sm = 1'b0; | |
370 | next_state = IRSC_TIME_WAIT3; | |
371 | end | |
372 | ||
373 | IRSC_TIME_WAIT3: //wait IRSC = 7cyc | |
374 | begin | |
375 | fcram_cmd_sm = `DESL; | |
376 | fcram_ba0_sm = 1'b0; | |
377 | fcram_ba1_sm = 1'b0; | |
378 | fcram_addr_sel = 3'b000; | |
379 | fcram_addr_en = 1'b0; | |
380 | fcram_ds_sm = 1'b0; | |
381 | next_state = IRSC_TIME_WAIT4; | |
382 | end | |
383 | ||
384 | IRSC_TIME_WAIT4: | |
385 | begin | |
386 | fcram_cmd_sm = `DESL; | |
387 | fcram_ba0_sm = 1'b0; | |
388 | fcram_ba1_sm = 1'b0; | |
389 | fcram_addr_sel = 3'b000; | |
390 | fcram_addr_en = 1'b0; | |
391 | fcram_ds_sm = 1'b0; | |
392 | inc_wait_cnt = 1'b1; | |
393 | wait_time_done_cyc = 1'b1; | |
394 | if (wait_cnt[2]) | |
395 | next_state = AUTO_REF; | |
396 | else | |
397 | next_state = state; | |
398 | end | |
399 | ||
400 | AUTO_REF: | |
401 | begin | |
402 | fcram_cmd_sm = `WRA; | |
403 | fcram_ba0_sm = 1'b0; | |
404 | fcram_ba1_sm = 1'b0; | |
405 | fcram_addr_sel = 3'b000; | |
406 | fcram_addr_en = 1'b0; | |
407 | fcram_ds_sm = 1'b0; | |
408 | fcram_ref_done = 1'b1; | |
409 | next_state = AUTO_REF_CYC2; | |
410 | end | |
411 | ||
412 | AUTO_REF_CYC2: | |
413 | begin | |
414 | fcram_cmd_sm = `REF; | |
415 | fcram_ba0_sm = 1'b0; | |
416 | fcram_ba1_sm = 1'b0; | |
417 | fcram_addr_sel = 3'b000; | |
418 | fcram_addr_en = 1'b0; | |
419 | fcram_ds_sm = 1'b0; | |
420 | inc_wait_cnt = 1'b1; | |
421 | next_state = IREFC_TIME_WAIT; | |
422 | end | |
423 | ||
424 | IREFC_TIME_WAIT: //25cyc | |
425 | begin | |
426 | fcram_cmd_sm = `DESL; | |
427 | fcram_ba0_sm = 1'b0; | |
428 | fcram_ba1_sm = 1'b0; | |
429 | fcram_addr_sel = 3'b000; | |
430 | fcram_ds_sm = 1'b0; | |
431 | inc_wait_cnt = 1'b1; | |
432 | fcram_ref_wait = 1'b1; | |
433 | irefc_time_done_cyc = 1'b1; | |
434 | if (fcram_init_done & (wait_cnt[4] & wait_cnt[3])) | |
435 | next_state = READY; | |
436 | else if (init_ref_cnt_done & (wait_cnt[4] & wait_cnt[3])) | |
437 | begin | |
438 | inc_init_ref_cnt= 1'b1; | |
439 | next_state = INIT_WAIT; | |
440 | end | |
441 | else if (wait_cnt[4] & wait_cnt[3]) | |
442 | begin | |
443 | inc_init_ref_cnt= 1'b1; | |
444 | next_state = AUTO_REF; | |
445 | end | |
446 | else | |
447 | next_state = state; | |
448 | end | |
449 | ||
450 | INIT_WAIT: //200 cyc | |
451 | begin | |
452 | fcram_cmd_sm = `DESL; | |
453 | fcram_ba0_sm = 1'b0; | |
454 | fcram_ba1_sm = 1'b0; | |
455 | fcram_addr_sel = 3'b000; | |
456 | fcram_ds_sm = 1'b0; | |
457 | inc_wait_cnt = 1'b1; | |
458 | init_wait_done_cyc = 1'b1; | |
459 | if (wait_cnt[8]) | |
460 | next_state = READY; | |
461 | else | |
462 | next_state = state; | |
463 | end | |
464 | ||
465 | READY: | |
466 | begin | |
467 | if (do_srch_cycle_w | do_cpu_cycle_w | do_cpu_cycle_wr) | |
468 | begin | |
469 | fcram_cmd_sm = `DESL; | |
470 | fcram_ba0_sm = 1'b0; | |
471 | fcram_ba1_sm = 1'b0; | |
472 | fcram_addr_sel = 3'b000; | |
473 | fcram_addr_en = 1'b0; | |
474 | fcram_ds_sm = 1'b0; | |
475 | next_state = state; | |
476 | end | |
477 | else if (do_srch_cycle) | |
478 | begin | |
479 | fcram_cmd_sm = `RDA; | |
480 | fcram_ba0_sm = 1'b0; | |
481 | fcram_ba1_sm = 1'b0; | |
482 | fcram_addr_sel = 3'b100; | |
483 | fcram_addr_en = 1'b1; | |
484 | fcram_ds_sm = 1'b0; | |
485 | // fcram_triz_en_sm = 1'b1; | |
486 | // fc_din_reg_en_sm = 1'b1; | |
487 | irc_time_reset = 1'b1; | |
488 | next_state = LOOKUP_CYC2; | |
489 | end | |
490 | else if (do_cpu_cycle) | |
491 | begin | |
492 | if (cpu_cmd) | |
493 | begin | |
494 | fcram_cmd_sm = `WRA; | |
495 | fcram_ba0_sm = cpu_bk0; | |
496 | fcram_ba1_sm = cpu_bk1; | |
497 | fcram_addr_sel = 3'b110; | |
498 | fcram_addr_en = 1'b1; | |
499 | fcram_ds_sm = 1'b1; | |
500 | irc_time_reset = 1'b1; | |
501 | cpu_burst_done_sm = 1'b1; | |
502 | next_state = CPU_CYC2; | |
503 | end | |
504 | else | |
505 | begin | |
506 | fcram_cmd_sm = `RDA; | |
507 | fcram_ba0_sm = cpu_bk0; | |
508 | fcram_ba1_sm = cpu_bk1; | |
509 | fcram_addr_sel = 3'b110; | |
510 | fcram_addr_en = 1'b1; | |
511 | fcram_ds_sm = 1'b0; | |
512 | // fcram_triz_en_sm = 1'b1; | |
513 | // fc_din_reg_en_sm = 1'b1; | |
514 | irc_time_reset = 1'b1; | |
515 | cpu_burst_done_sm = 1'b1; | |
516 | next_state = CPU_CYC2; | |
517 | end | |
518 | ||
519 | end | |
520 | else if (do_refresh_min) | |
521 | begin | |
522 | fcram_cmd_sm = `DESL; | |
523 | fcram_ba0_sm = 1'b0; | |
524 | fcram_ba1_sm = 1'b0; | |
525 | fcram_addr_sel = 3'b000; | |
526 | fcram_addr_en = 1'b0; | |
527 | fcram_ds_sm = 1'b0; | |
528 | irc_time_reset = 1'b1; | |
529 | next_state = IRC_TIME_WAIT; | |
530 | end | |
531 | else | |
532 | begin | |
533 | fcram_cmd_sm = `DESL; | |
534 | fcram_ba0_sm = 1'b0; | |
535 | fcram_ba1_sm = 1'b0; | |
536 | fcram_addr_sel = 3'b000; | |
537 | fcram_addr_en = 1'b0; | |
538 | fcram_ds_sm = 1'b0; | |
539 | next_state = state; | |
540 | end | |
541 | end | |
542 | ||
543 | LOOKUP_CYC2: | |
544 | begin | |
545 | fcram_cmd_sm = `LAL; | |
546 | fcram_ba0_sm = 1'b0; | |
547 | fcram_ba1_sm = 1'b0; | |
548 | fcram_addr_sel = 3'b101; | |
549 | fcram_addr_en = 1'b1; | |
550 | fcram_ds_sm = 1'b0; | |
551 | // fcram_triz_en_sm = 1'b1; | |
552 | // fc_din_reg_en_sm = 1'b1; | |
553 | next_state = LOOKUP_CYC3; | |
554 | end | |
555 | ||
556 | LOOKUP_CYC3: | |
557 | begin | |
558 | fcram_cmd_sm = `RDA; | |
559 | fcram_ba0_sm = 1'b1; | |
560 | fcram_ba1_sm = 1'b0; | |
561 | fcram_addr_sel = 3'b100; | |
562 | fcram_addr_en = 1'b1; | |
563 | fcram_ds_sm = 1'b0; | |
564 | // fcram_triz_en_sm = 1'b1; | |
565 | // fc_din_reg_en_sm = 1'b1; | |
566 | next_state = LOOKUP_CYC4; | |
567 | end | |
568 | ||
569 | LOOKUP_CYC4: | |
570 | begin | |
571 | fcram_cmd_sm = `LAL; | |
572 | fcram_ba0_sm = 1'b1; | |
573 | fcram_ba1_sm = 1'b0; | |
574 | fcram_addr_sel = 3'b101; | |
575 | fcram_addr_en = 1'b1; | |
576 | fcram_ds_sm = 1'b0; | |
577 | // fcram_triz_en_sm = 1'b1; | |
578 | // fc_din_reg_en_sm = 1'b1; | |
579 | next_state = LOOKUP_CYC5; | |
580 | end | |
581 | ||
582 | LOOKUP_CYC5: | |
583 | begin | |
584 | fcram_cmd_sm = `RDA; | |
585 | fcram_ba0_sm = 1'b0; | |
586 | fcram_ba1_sm = 1'b1; | |
587 | fcram_addr_sel = 3'b100; | |
588 | fcram_addr_en = 1'b1; | |
589 | fcram_ds_sm = 1'b0; | |
590 | // fcram_triz_en_sm = 1'b1; | |
591 | // fc_din_reg_en_sm = 1'b1; | |
592 | srch_burst_done_sm = 1'b1; | |
593 | next_state = LOOKUP_CYC6; | |
594 | end | |
595 | ||
596 | LOOKUP_CYC6: | |
597 | begin | |
598 | fcram_cmd_sm = `LAL; | |
599 | fcram_ba0_sm = 1'b0; | |
600 | fcram_ba1_sm = 1'b1; | |
601 | fcram_addr_sel = 3'b101; | |
602 | fcram_addr_en = 1'b1; | |
603 | fcram_ds_sm = 1'b0; | |
604 | // fcram_triz_en_sm = 1'b1; | |
605 | // fc_din_reg_en_sm = 1'b1; | |
606 | next_state = LOOKUP_CYC7; | |
607 | end | |
608 | ||
609 | LOOKUP_CYC7: | |
610 | begin | |
611 | fcram_cmd_sm = `RDA; | |
612 | fcram_ba0_sm = 1'b1; | |
613 | fcram_ba1_sm = 1'b1; | |
614 | fcram_addr_sel = 3'b100; | |
615 | fcram_addr_en = 1'b1; | |
616 | fcram_ds_sm = 1'b0; | |
617 | // fcram_triz_en_sm = 1'b1; | |
618 | // fc_din_reg_en_sm = 1'b1; | |
619 | next_state = LOOKUP_CYC8; | |
620 | end | |
621 | ||
622 | LOOKUP_CYC8: | |
623 | begin | |
624 | fcram_cmd_sm = `LAL; | |
625 | fcram_ba0_sm = 1'b1; | |
626 | fcram_ba1_sm = 1'b1; | |
627 | fcram_addr_sel = 3'b101; | |
628 | fcram_addr_en = 1'b1; | |
629 | fcram_ds_sm = 1'b0; | |
630 | // fcram_triz_en_sm = 1'b1; | |
631 | // fc_din_reg_en_sm = 1'b1; | |
632 | if (do_refresh_max) | |
633 | begin | |
634 | srch_irc_time_en = 1'b0; | |
635 | next_state = IRC_TIME_WAIT; | |
636 | end | |
637 | else | |
638 | begin | |
639 | srch_irc_time_en = 1'b1; | |
640 | next_state = READY; | |
641 | end | |
642 | end | |
643 | ||
644 | IRC_TIME_WAIT: //7 cyc | |
645 | begin | |
646 | fcram_cmd_sm = `DESL; | |
647 | fcram_ba0_sm = 1'b0; | |
648 | fcram_ba1_sm = 1'b0; | |
649 | fcram_addr_sel = 3'b000; | |
650 | fcram_addr_en = 1'b0; | |
651 | fcram_ds_sm = 1'b0; | |
652 | inc_wait_cnt = 1'b1; | |
653 | wait_time_done_cyc = 1'b1; | |
654 | if (wait_cnt[2]) | |
655 | next_state = AUTO_REF; | |
656 | else | |
657 | next_state = state; | |
658 | end | |
659 | ||
660 | CPU_CYC2: | |
661 | begin | |
662 | fcram_cmd_sm = `LAL; | |
663 | fcram_ba0_sm = cpu_bk0; | |
664 | fcram_ba0_sm = cpu_bk1; | |
665 | fcram_addr_sel = 3'b111; | |
666 | fcram_addr_en = 1'b1; | |
667 | if (cpu_cmd) | |
668 | begin | |
669 | fcram_ds_sm = 1'b1; | |
670 | // fcram_triz_en_sm= 1'b0; | |
671 | end | |
672 | else | |
673 | begin | |
674 | fcram_ds_sm = 1'b0; | |
675 | // fcram_triz_en_sm= 1'b1; | |
676 | end | |
677 | ||
678 | if (do_refresh_max) | |
679 | begin | |
680 | cpu_irc_time_en = 1'b0; | |
681 | next_state = IRC_TIME_WAIT; | |
682 | end | |
683 | else | |
684 | begin | |
685 | cpu_irc_time_en = 1'b1; | |
686 | next_state = READY; | |
687 | end | |
688 | end | |
689 | ||
690 | default: | |
691 | begin | |
692 | fcram_cmd_sm = `DESL; | |
693 | fcram_ba0_sm = 1'b0; | |
694 | fcram_ba0_sm = 1'b0; | |
695 | fcram_addr_sel = 3'b000; | |
696 | fcram_addr_en = 1'b0; | |
697 | fcram_ds_sm = 1'b0; | |
698 | next_state = READY; | |
699 | end | |
700 | ||
701 | endcase | |
702 | ||
703 | end | |
704 | ||
705 | assign wait_cnt_reset = (wait_time_done | irefc_time_done | init_wait_done); | |
706 | assign wait_cnt_in = wait_cnt_reset ? 9'b0 : (wait_cnt + 9'd1); | |
707 | assign wait_time_done = wait_time_done_cyc & wait_cnt[2]; | |
708 | assign irefc_time_done = irefc_time_done_cyc & (wait_cnt[4] & wait_cnt[3]); | |
709 | assign init_wait_done = init_wait_done_cyc & wait_cnt[8]; | |
710 | assign init_wait_done_pre = init_wait_done_cyc & (&wait_cnt[7:0]); | |
711 | ||
712 | assign irc_time_done = irc_time_cnt[2]; | |
713 | assign irc_time_cnt_en = (srch_irc_wait | cpu_irc_wait); | |
714 | assign irc_time_cnt_in = (irc_time_reset | irc_time_done) ? 3'b000 : (irc_time_cnt + 3'd1); | |
715 | assign srch_irc_wait_en = srch_irc_time_en | irc_time_reset | irc_time_done; | |
716 | assign srch_irc_wait_in = srch_irc_time_en ? 1'b1 : 1'b0; | |
717 | assign cpu_irc_wait_en = cpu_irc_time_en | irc_time_reset | irc_time_done; | |
718 | assign cpu_irc_wait_in = cpu_irc_time_en ? 1'b1 : 1'b0; | |
719 | ||
720 | assign init_ref_cnt_done = (init_ref_cnt[1:0] == 2'b10); | |
721 | assign init_ref_cnt_in = init_ref_cnt_done ? 2'b00 : (init_ref_cnt + 2'd1); | |
722 | ||
723 | //refresh max time 3.9us. When calculating number of cycles, need to have margin of | |
724 | //7(IRC) + 8(rd burst) + 7(IRC, between rd/wr -> ref) == 22 cycles, at least. | |
725 | ||
726 | //assign ref_tmin_cnt_done = ref_tmax_cnt[7] & ref_tmax_cnt[3]; //136x3=408ns | |
727 | //assign ref_tmax_cnt_done = ref_tmax_cnt[10] & ref_tmax_cnt[7] & ref_tmax_cnt[3]; //1160x3=3480ns | |
728 | ||
729 | assign ref_tmin_cnt_done = (ref_tmax_cnt == refresh_cycle_min); | |
730 | assign ref_tmax_cnt_done = (ref_tmax_cnt == refresh_cycle_max); | |
731 | assign ref_tmax_cnt_in = fcram_ref_done ? 11'b0 : | |
732 | ref_tmax_cnt_done ? ref_tmax_cnt : | |
733 | (ref_tmax_cnt + 11'd1); | |
734 | ||
735 | assign do_refresh_min_en = ref_tmin_cnt_done | fcram_ref_done; | |
736 | assign do_refresh_max_en = ref_tmax_cnt_done | fcram_ref_done; | |
737 | assign do_refresh_in = fcram_ref_done ? 1'b0 : 1'b1; | |
738 | ||
739 | assign fio_slv_update_in = fcram_ref_wait & ((wait_cnt[4:0] == 5'd15) | (wait_cnt[4:0] == 5'd14)) | | |
740 | init_wait_done | init_wait_done_pre; //almost end of refresh, make two cyc for fio fifo reset | |
741 | ||
742 | dffr #(5) state_reg (cclk, reset, next_state, state); | |
743 | dffre #(9) wait_cnt_reg (cclk, reset, inc_wait_cnt, wait_cnt_in, wait_cnt); | |
744 | dffre #(2) init_ref_cnt_reg (cclk, reset, inc_init_ref_cnt, init_ref_cnt_in, init_ref_cnt); | |
745 | dffre #(1) fcram_init_done_reg (cclk, reset, init_wait_done, init_wait_done, fcram_init_done); | |
746 | ||
747 | dffre #(3) irc_time_cnt_reg (cclk, reset, irc_time_cnt_en, irc_time_cnt_in, irc_time_cnt); | |
748 | dffre #(1) srch_irc_wait_reg (cclk, reset, srch_irc_wait_en, srch_irc_wait_in, srch_irc_wait); | |
749 | dffre #(1) cpu_irc_wait_reg (cclk, reset, cpu_irc_wait_en, cpu_irc_wait_in, cpu_irc_wait); | |
750 | ||
751 | dffre #(11) ref_tmax_cnt_reg (cclk, reset, fcram_init_done, ref_tmax_cnt_in, ref_tmax_cnt); | |
752 | dffre #(1) do_refresh_min_reg (cclk, reset, do_refresh_min_en, do_refresh_in, do_refresh_min); | |
753 | dffre #(1) do_refresh_max_reg (cclk, reset, do_refresh_max_en, do_refresh_in, do_refresh_max); | |
754 | ||
755 | dffr #(1) fio_slv_update_reg (cclk, reset, fio_slv_update_in, fflp_fcram_slv_update); | |
756 | ||
757 | /********************************/ | |
758 | //Long wait after power on, 200us | |
759 | /********************************/ | |
760 | ||
761 | assign power_on_wait_cnt_in = power_on_wait_cnt_done_r ? 16'b0 : (power_on_wait_cnt + 16'd1); | |
762 | assign power_on_wait_cnt_done = (&power_on_wait_cnt[15:0] | power_on_wait_cnt_done_r); | |
763 | ||
764 | dffr #(16) power_on_wait_reg (cclk, reset, power_on_wait_cnt_in, power_on_wait_cnt); | |
765 | dffr #(1) power_on_wait_done (cclk, reset, power_on_wait_cnt_done, power_on_wait_cnt_done_r); | |
766 | ||
767 | endmodule | |
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | ||
782 | ||
783 |