[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / fflp_fcram_top.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fflp_fcram_top.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/**********************************************************************/
/*project name:  N2                                                   */
/*module name:   fflp_fcram_top                                       */
/*description:   FCRAM protocol and flow classification               */
/*                                                                    */
/*parent module in:  fflp_top                                         */
/*child modules in:  fflp_fcram_cntl, fflp_fcram_sched,               */ 
/*                   fflp_merge_func                                  */
/*interface modules:                                                  */
/*author name:       Jeanne Cai                                       */
/*date created:      04-08-04                                         */
/*                                                                    */
/*              Copyright (c) 2004, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */
/*modifications:                                                      */
/*                                                                    */
/*                                                                    */

module fflp_fcram_top (
                        cclk,
                        reset,
			disable_chksum,
			pio_fio_latency,
			fcram_lookup_ratio,
                        fflp_init_done,
			fcram_refresh_timer_reg_dout,
                        flow_part_sel_reg0_dout,
                        flow_part_sel_reg1_dout,
                        flow_part_sel_reg2_dout,
                        flow_part_sel_reg3_dout,
                        flow_part_sel_reg4_dout,
                        flow_part_sel_reg5_dout,
                        flow_part_sel_reg6_dout,
                        flow_part_sel_reg7_dout,
                        hash_tbl_addr_reg0_dout,
                        hash_tbl_addr_reg1_dout,
                        hash_tbl_addr_reg2_dout,
                        hash_tbl_addr_reg3_dout,
                        hash_tbl_addr_reg4_dout,
                        hash_tbl_addr_reg5_dout,
                        hash_tbl_addr_reg6_dout,
                        hash_tbl_addr_reg7_dout,
                        hash_tbl_data_reg0_dout,
                        hash_tbl_data_reg1_dout,
                        hash_tbl_data_reg2_dout,
                        hash_tbl_data_reg3_dout,
                        hash_tbl_data_reg4_dout,
                        hash_tbl_data_reg5_dout,
                        hash_tbl_data_reg6_dout,
                        hash_tbl_data_reg7_dout,
			fcram_err_test_reg_dout,
                        cpu_req_part0_sel,
                        cpu_req_part1_sel,
                        cpu_req_part2_sel,
                        cpu_req_part3_sel,
                        cpu_req_part4_sel,
                        cpu_req_part5_sel,
                        cpu_req_part6_sel,
                        cpu_req_part7_sel,
                        pio_rd,
			pio_wr_data,
			pio_fio_cfg_reset,
			fio_cfg_addr_reg_dout,
			cpu_fio_req_sync,
                        fcram_driver_imp_ctrl,
			fcram_qs_mode,
			cpu_fcram_req_sync,
			fc_fifo_empty_sync,
			fflp_config_reg_wen_pulse_sync,
			debug_training_vector,
			pio_debug_data_sel,
			fc_fifo_dout,
			fcram_fflp_mstrready,
			fcram_fflp_fatal_err,
			fcram_fflp_data_ready,
			fcram_fflp_even_din,
                        fcram_fflp_odd_din,
			fcram_fflp_cfg_datrd,
			fcram_fflp_cfg_done,
			fcram_fflp_cfg_err,

			fflp_fcram_cfg_rst,
			fflp_fcram_cfg_sel,
			fflp_fcram_cfg_rd,
			fflp_fcram_cfg_addr,
			fflp_fcram_cfg_datwr,
			fflp_fcram_slv_update,
			fflp_fcram_rd_en,
			fflp_fcram_cs_l,
                        fflp_fcram_fn,
			fflp_fcram_pd_l,
                        fflp_fcram_ba0,
                        fflp_fcram_ba1,
                        fflp_fcram_addr,
                        fflp_fcram_ds,
                        fflp_fcram_triz_en_l,
                        fflp_fcram_even_dout,
                        fflp_fcram_odd_dout,
			cpu_fc_req_done,
			fc_rd_data_reg_dout,
			fc_rd_ecc_err,
			cpu_fio_req_done,
			cpu_fio_rd_data,
			fio_cal_rd_latency,
			fc_fifo_ren,
			zcp_wr,
			fflp_zcp_data,
			fc_err_status,
			fflp_debug_port

			);

input		cclk;
input		reset;
input		disable_chksum;
input[1:0]	pio_fio_latency;
input[3:0]	fcram_lookup_ratio;
input		fflp_init_done;
input[31:0]	fcram_refresh_timer_reg_dout;
input[9:0]      flow_part_sel_reg0_dout;
input[9:0]      flow_part_sel_reg1_dout;
input[9:0]      flow_part_sel_reg2_dout;
input[9:0]      flow_part_sel_reg3_dout;
input[9:0]      flow_part_sel_reg4_dout;
input[9:0]      flow_part_sel_reg5_dout;
input[9:0]      flow_part_sel_reg6_dout;
input[9:0]      flow_part_sel_reg7_dout;
input[23:0]     hash_tbl_addr_reg0_dout;
input[23:0]     hash_tbl_addr_reg1_dout;
input[23:0]     hash_tbl_addr_reg2_dout;
input[23:0]     hash_tbl_addr_reg3_dout;
input[23:0]     hash_tbl_addr_reg4_dout;
input[23:0]     hash_tbl_addr_reg5_dout;
input[23:0]     hash_tbl_addr_reg6_dout;
input[23:0]     hash_tbl_addr_reg7_dout;
input[63:0]     hash_tbl_data_reg0_dout;
input[63:0]     hash_tbl_data_reg1_dout;
input[63:0]     hash_tbl_data_reg2_dout;
input[63:0]     hash_tbl_data_reg3_dout;
input[63:0]     hash_tbl_data_reg4_dout;
input[63:0]     hash_tbl_data_reg5_dout;
input[63:0]     hash_tbl_data_reg6_dout;
input[63:0]     hash_tbl_data_reg7_dout;
input[71:0]	fcram_err_test_reg_dout;
input           cpu_req_part0_sel;
input           cpu_req_part1_sel;
input           cpu_req_part2_sel;
input           cpu_req_part3_sel;
input           cpu_req_part4_sel;
input           cpu_req_part5_sel;
input           cpu_req_part6_sel;
input           cpu_req_part7_sel;
input           pio_rd;
input[15:0]	pio_wr_data;
input		pio_fio_cfg_reset;
input[7:0]	fio_cfg_addr_reg_dout;
input		cpu_fio_req_sync;
input[3:0]      fcram_driver_imp_ctrl;
input		fcram_qs_mode;
input		cpu_fcram_req_sync;
input		fc_fifo_empty_sync;
input		fflp_config_reg_wen_pulse_sync;
input[31:0]	debug_training_vector;
input[2:0]	pio_debug_data_sel;
input[512:0]	fc_fifo_dout;
input		fcram_fflp_mstrready;
input		fcram_fflp_fatal_err;
input[3:0]	fcram_fflp_data_ready;
input[35:0]	fcram_fflp_even_din;
input[35:0]	fcram_fflp_odd_din;
input[15:0]	fcram_fflp_cfg_datrd;
input		fcram_fflp_cfg_done;
input		fcram_fflp_cfg_err;

output		fflp_fcram_cfg_rst;
output		fflp_fcram_cfg_sel;
output		fflp_fcram_cfg_rd;
output[7:0]	fflp_fcram_cfg_addr;
output[15:0]	fflp_fcram_cfg_datwr;
output		fflp_fcram_slv_update;
output[1:0]	fflp_fcram_rd_en;
output          fflp_fcram_cs_l;
output          fflp_fcram_fn;
output		fflp_fcram_pd_l;
output          fflp_fcram_ba0;
output          fflp_fcram_ba1;
output[14:0]    fflp_fcram_addr;
output[1:0]     fflp_fcram_ds;
output[1:0]     fflp_fcram_triz_en_l;
output[35:0]    fflp_fcram_even_dout;
output[35:0]    fflp_fcram_odd_dout;
output          cpu_fc_req_done;
output[71:0]    fc_rd_data_reg_dout;
output		fc_rd_ecc_err;
output		cpu_fio_req_done;
output[31:0]	cpu_fio_rd_data;
output[7:0]	fio_cal_rd_latency;
output		fc_fifo_ren;
output          zcp_wr;
output[215:0]   fflp_zcp_data;
output[33:0]	fc_err_status;
output[31:0]	fflp_debug_port;

wire		srch_no_fc_done;
wire		fwd_sched;
wire		do_srch_cycle;
wire		do_cpu_cycle;

wire            fflp_fcram_cfg_rst;
wire            fflp_fcram_cfg_sel;
wire            fflp_fcram_cfg_rd;
wire[7:0]       fflp_fcram_cfg_addr;
wire[15:0]      fflp_fcram_cfg_datwr;
wire		fflp_fcram_slv_update;
wire[1:0]	fflp_fcram_rd_en;
wire		fflp_fcram_cs_l;
wire		fflp_fcram_fn;
wire		fflp_fcram_pd_l;
wire		fflp_fcram_ba0;
wire		fflp_fcram_ba1;
wire[14:0]	fflp_fcram_addr;
wire[1:0]	fflp_fcram_ds;
wire[1:0]	fflp_fcram_triz_en_l;
wire[35:0]	fflp_fcram_even_dout;
wire[35:0]	fflp_fcram_odd_dout;
wire[71:0]	fc_din_reg_dout_r;
wire		ecc_check_err_r;
wire		ecc_corr_err_r;
wire		fio_no_fatal_err;
wire		srch_burst_done;
wire		cpu_burst_done_sm;
wire[4:0]	fcram_sm_state;
wire		srch_burst_done_2;
wire		srch_fio_wait_6;
wire		srch_fio_rd_en_4;
wire		cpu_fc_req_done;
wire[71:0]	fc_rd_data_reg_dout;
wire		fc_rd_ecc_err;
wire		cpu_fio_req_done;
wire[31:0]	cpu_fio_rd_data;
wire[7:0]	fio_cal_rd_latency;

wire[19:0]	merg_bus_0_hash_v1;
wire[2:0]	merg_bus_0_rdc_tbl_num;
wire		merg_bus_1_fc_lookup;
wire		fc_fifo_ren;
wire		zcp_wr;
wire[215:0]	fflp_zcp_data;
wire[33:0]	fc_err_status;
wire[31:0]	fflp_debug_port;

`ifdef NEPTUNE
wire      [3:0] do_nad;
wire      [3:0] do_nor;
wire      [3:0] do_inv;
wire      [3:0] do_mux;
wire      [3:0] do_q;
wire            so;

nep_spare_fflp spare_fflp_0 (
                             .di_nd3     ({1'h1, 1'h1, do_q[3]}),
                             .di_nd2     ({1'h1, 1'h1, do_q[2]}),
                             .di_nd1     ({1'h1, 1'h1, do_q[1]}),
                             .di_nd0     ({1'h1, 1'h1, do_q[0]}),
                             .di_nr3     ({1'h0, 1'h0}),
                             .di_nr2     ({1'h0, 1'h0}),
                             .di_nr1     ({1'h0, 1'h0}),
                             .di_nr0     ({1'h0, 1'h0}),
                             .di_inv     (do_nad[3:0]),
                             .di_mx3     ({1'h0, 1'h0}),
                             .di_mx2     ({1'h0, 1'h0}),
                             .di_mx1     ({1'h0, 1'h0}),
                             .di_mx0     ({1'h0, 1'h0}),
                             .mx_sel     (do_nor[3:0]),
                             .di_reg     (do_inv[3:0]),
                             .wt_ena     (do_mux[3:0]),
                             .rst        ({reset,reset,reset,reset}),
                             .si         (1'h0),
                             .se         (1'h0),
                             .clk        (cclk),
                             .do_nad     (do_nad[3:0]),
                             .do_nor     (do_nor[3:0]),
                             .do_inv     (do_inv[3:0]),
                             .do_mux     (do_mux[3:0]),
                             .do_q       (do_q[3:0]),
                             .so         (so)
                            );

`endif


fflp_fcram_sched	fflp_fcram_sched_inst
				(
				.cclk			(cclk),
				.reset			(reset),
				.fcram_lookup_ratio	(fcram_lookup_ratio),
				.cpu_fcram_req_sync	(cpu_fcram_req_sync),
				.fc_fifo_empty_sync	(fc_fifo_empty_sync),
				.fc_fifo_fc_lookup	(fc_fifo_dout[498]),
				.srch_burst_done	(srch_burst_done),
				.cpu_burst_done_sm	(cpu_burst_done_sm),

				.srch_no_fc_done	(srch_no_fc_done),
				.fwd_sched		(fwd_sched),
				.do_srch_cycle		(do_srch_cycle),
				.do_cpu_cycle		(do_cpu_cycle),
				.fc_fifo_ren		(fc_fifo_ren)

				);


fflp_fcram_cntl		fflp_fcram_cntl_inst
				(
				.cclk				(cclk),
				.reset				(reset),
				.disable_chksum			(disable_chksum),
				.pio_fio_latency		(pio_fio_latency),
				.fflp_init_done			(fflp_init_done),
				.fcram_refresh_timer_reg_dout	(fcram_refresh_timer_reg_dout),
				.flow_part_sel_reg0_dout	(flow_part_sel_reg0_dout),
				.flow_part_sel_reg1_dout	(flow_part_sel_reg1_dout),
				.flow_part_sel_reg2_dout	(flow_part_sel_reg2_dout),
				.flow_part_sel_reg3_dout	(flow_part_sel_reg3_dout),
				.flow_part_sel_reg4_dout	(flow_part_sel_reg4_dout),
				.flow_part_sel_reg5_dout	(flow_part_sel_reg5_dout),
				.flow_part_sel_reg6_dout	(flow_part_sel_reg6_dout),
				.flow_part_sel_reg7_dout	(flow_part_sel_reg7_dout),
				.hash_tbl_addr_reg0_dout	(hash_tbl_addr_reg0_dout),
				.hash_tbl_addr_reg1_dout	(hash_tbl_addr_reg1_dout),
				.hash_tbl_addr_reg2_dout	(hash_tbl_addr_reg2_dout),
				.hash_tbl_addr_reg3_dout	(hash_tbl_addr_reg3_dout),
				.hash_tbl_addr_reg4_dout	(hash_tbl_addr_reg4_dout),
				.hash_tbl_addr_reg5_dout	(hash_tbl_addr_reg5_dout),
				.hash_tbl_addr_reg6_dout	(hash_tbl_addr_reg6_dout),
				.hash_tbl_addr_reg7_dout	(hash_tbl_addr_reg7_dout),
				.hash_tbl_data_reg0_dout	(hash_tbl_data_reg0_dout),
				.hash_tbl_data_reg1_dout	(hash_tbl_data_reg1_dout),
				.hash_tbl_data_reg2_dout	(hash_tbl_data_reg2_dout),
				.hash_tbl_data_reg3_dout	(hash_tbl_data_reg3_dout),
				.hash_tbl_data_reg4_dout	(hash_tbl_data_reg4_dout),
				.hash_tbl_data_reg5_dout	(hash_tbl_data_reg5_dout),
				.hash_tbl_data_reg6_dout	(hash_tbl_data_reg6_dout),
				.hash_tbl_data_reg7_dout	(hash_tbl_data_reg7_dout),
				.fcram_err_test_reg_dout	(fcram_err_test_reg_dout),
				.cpu_req_part0_sel		(cpu_req_part0_sel),
				.cpu_req_part1_sel		(cpu_req_part1_sel),
				.cpu_req_part2_sel		(cpu_req_part2_sel),
				.cpu_req_part3_sel		(cpu_req_part3_sel),
				.cpu_req_part4_sel		(cpu_req_part4_sel),
				.cpu_req_part5_sel		(cpu_req_part5_sel),
				.cpu_req_part6_sel		(cpu_req_part6_sel),
				.cpu_req_part7_sel		(cpu_req_part7_sel),
				.pio_rd				(pio_rd),
				.pio_wr_data			(pio_wr_data),
				.pio_fio_cfg_reset		(pio_fio_cfg_reset),
				.fio_cfg_addr_reg_dout		(fio_cfg_addr_reg_dout),
				.cpu_fio_req_sync		(cpu_fio_req_sync),
				.fcram_driver_imp_ctrl		(fcram_driver_imp_ctrl),
				.fcram_qs_mode			(fcram_qs_mode),
				.srch_no_fc_done		(srch_no_fc_done),
				.do_srch_cycle			(do_srch_cycle),
				.do_cpu_cycle			(do_cpu_cycle),
				.merg_bus_0_hash_v1		(merg_bus_0_hash_v1),
				.merg_bus_0_rdc_tbl_num		(merg_bus_0_rdc_tbl_num),
				.merg_bus_1_fc_lookup		(merg_bus_1_fc_lookup),
				.fcram_fflp_mstrready		(fcram_fflp_mstrready),
				.fcram_fflp_fatal_err		(fcram_fflp_fatal_err),
				.fcram_fflp_data_ready		(fcram_fflp_data_ready),
				.fcram_fflp_even_din		(fcram_fflp_even_din),
				.fcram_fflp_odd_din		(fcram_fflp_odd_din),
				.fcram_fflp_cfg_datrd		(fcram_fflp_cfg_datrd),
				.fcram_fflp_cfg_done		(fcram_fflp_cfg_done),
				.fcram_fflp_cfg_err		(fcram_fflp_cfg_err),

				.fflp_fcram_cfg_rst		(fflp_fcram_cfg_rst),
				.fflp_fcram_cfg_sel		(fflp_fcram_cfg_sel),
				.fflp_fcram_cfg_rd		(fflp_fcram_cfg_rd),
				.fflp_fcram_cfg_addr		(fflp_fcram_cfg_addr),
				.fflp_fcram_cfg_datwr		(fflp_fcram_cfg_datwr),
				.fflp_fcram_slv_update		(fflp_fcram_slv_update),
				.fflp_fcram_rd_en		(fflp_fcram_rd_en),
				.fflp_fcram_cs_l		(fflp_fcram_cs_l),
				.fflp_fcram_fn			(fflp_fcram_fn),
				.fflp_fcram_pd_l		(fflp_fcram_pd_l),
				.fflp_fcram_ba0			(fflp_fcram_ba0),
				.fflp_fcram_ba1			(fflp_fcram_ba1),
				.fflp_fcram_addr		(fflp_fcram_addr),
				.fflp_fcram_ds			(fflp_fcram_ds),
				.fflp_fcram_triz_en_l		(fflp_fcram_triz_en_l),
				.fflp_fcram_even_dout		(fflp_fcram_even_dout),
				.fflp_fcram_odd_dout		(fflp_fcram_odd_dout),
				.fc_din_reg_dout_r		(fc_din_reg_dout_r),
				.ecc_check_err_r		(ecc_check_err_r),
				.ecc_corr_err_r			(ecc_corr_err_r),
				.fio_no_fatal_err		(fio_no_fatal_err),
				.srch_burst_done		(srch_burst_done),
				.cpu_burst_done_sm		(cpu_burst_done_sm),
				.fcram_sm_state			(fcram_sm_state),
				.srch_burst_done_2		(srch_burst_done_2),
				.srch_fio_wait_6		(srch_fio_wait_6),
				.srch_fio_rd_en_4		(srch_fio_rd_en_4),
				.cpu_fc_req_done		(cpu_fc_req_done),
				.fc_rd_data_reg_dout		(fc_rd_data_reg_dout),
				.fc_rd_ecc_err			(fc_rd_ecc_err),
				.cpu_fio_req_done		(cpu_fio_req_done),
				.cpu_fio_rd_data		(cpu_fio_rd_data),
				.fio_cal_rd_latency		(fio_cal_rd_latency)

				);


fflp_merge_func		fflp_merge_func_inst
				(
				.cclk				(cclk),
				.reset				(reset),
				.fwd_sched			(fwd_sched),
				.fc_fifo_dout			(fc_fifo_dout),
				.fc_din_reg_dout_r		(fc_din_reg_dout_r),
				.ecc_check_err_r		(ecc_check_err_r),
				.ecc_corr_err_r			(ecc_corr_err_r),
				.fio_no_fatal_err		(fio_no_fatal_err),
				.srch_burst_done_2		(srch_burst_done_2),
				.srch_fio_wait_6		(srch_fio_wait_6),
				.srch_fio_rd_en_4		(srch_fio_rd_en_4),
				.fcram_sm_state			(fcram_sm_state),
				.fflp_config_reg_wen_pulse_sync	(fflp_config_reg_wen_pulse_sync),
				.debug_training_vector		(debug_training_vector),
				.pio_debug_data_sel		(pio_debug_data_sel),
	
				.merg_bus_0_hash_v1             (merg_bus_0_hash_v1),
                                .merg_bus_0_rdc_tbl_num         (merg_bus_0_rdc_tbl_num),
				.merg_bus_1_fc_lookup		(merg_bus_1_fc_lookup),
				.zcp_wr				(zcp_wr),
				.fflp_zcp_data			(fflp_zcp_data),
				.fc_err_status			(fc_err_status),
				.fflp_debug_port		(fflp_debug_port)

				);


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: fflp_fcram_top.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
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	9	// This program is free software; you can redistribute it and/or modify
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	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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	34	// ========== Copyright Header End ============================================
	35	/**********************************************************************/
	36	/project name: N2 /
	37	/module name: fflp_fcram_top /
	38	/description: FCRAM protocol and flow classification /
	39	/* */
	40	/parent module in: fflp_top /
	41	/child modules in: fflp_fcram_cntl, fflp_fcram_sched, /
	42	/* fflp_merge_func */
	43	/interface modules: /
	44	/author name: Jeanne Cai /
	45	/date created: 04-08-04 /
	46	/* */
	47	/* Copyright (c) 2004, Sun Microsystems, Inc. */
	48	/* Sun Proprietary and Confidential */
	49	/* */
	50	/modifications: /
	51	/* */
	52	/* */
	53
	54	module fflp_fcram_top (
	55	cclk,
	56	reset,
	57	disable_chksum,
	58	pio_fio_latency,
	59	fcram_lookup_ratio,
	60	fflp_init_done,
	61	fcram_refresh_timer_reg_dout,
	62	flow_part_sel_reg0_dout,
	63	flow_part_sel_reg1_dout,
	64	flow_part_sel_reg2_dout,
65	flow_part_sel_reg3_dout,
66	flow_part_sel_reg4_dout,
67	flow_part_sel_reg5_dout,
68	flow_part_sel_reg6_dout,
69	flow_part_sel_reg7_dout,
70	hash_tbl_addr_reg0_dout,
71	hash_tbl_addr_reg1_dout,
72	hash_tbl_addr_reg2_dout,
73	hash_tbl_addr_reg3_dout,
74	hash_tbl_addr_reg4_dout,
75	hash_tbl_addr_reg5_dout,
76	hash_tbl_addr_reg6_dout,
77	hash_tbl_addr_reg7_dout,
78	hash_tbl_data_reg0_dout,
79	hash_tbl_data_reg1_dout,
80	hash_tbl_data_reg2_dout,
81	hash_tbl_data_reg3_dout,
82	hash_tbl_data_reg4_dout,
83	hash_tbl_data_reg5_dout,
84	hash_tbl_data_reg6_dout,
85	hash_tbl_data_reg7_dout,
86	fcram_err_test_reg_dout,
87	cpu_req_part0_sel,
88	cpu_req_part1_sel,
89	cpu_req_part2_sel,
90	cpu_req_part3_sel,
91	cpu_req_part4_sel,
92	cpu_req_part5_sel,
93	cpu_req_part6_sel,
94	cpu_req_part7_sel,
95	pio_rd,
96	pio_wr_data,
97	pio_fio_cfg_reset,
98	fio_cfg_addr_reg_dout,
99	cpu_fio_req_sync,
100	fcram_driver_imp_ctrl,
101	fcram_qs_mode,
102	cpu_fcram_req_sync,
103	fc_fifo_empty_sync,
104	fflp_config_reg_wen_pulse_sync,
105	debug_training_vector,
106	pio_debug_data_sel,
107	fc_fifo_dout,
108	fcram_fflp_mstrready,
109	fcram_fflp_fatal_err,
110	fcram_fflp_data_ready,
111	fcram_fflp_even_din,
112	fcram_fflp_odd_din,
113	fcram_fflp_cfg_datrd,
114	fcram_fflp_cfg_done,
115	fcram_fflp_cfg_err,
116
117	fflp_fcram_cfg_rst,
118	fflp_fcram_cfg_sel,
119	fflp_fcram_cfg_rd,
120	fflp_fcram_cfg_addr,
121	fflp_fcram_cfg_datwr,
122	fflp_fcram_slv_update,
123	fflp_fcram_rd_en,
124	fflp_fcram_cs_l,
125	fflp_fcram_fn,
126	fflp_fcram_pd_l,
127	fflp_fcram_ba0,
128	fflp_fcram_ba1,
129	fflp_fcram_addr,
130	fflp_fcram_ds,
131	fflp_fcram_triz_en_l,
132	fflp_fcram_even_dout,
133	fflp_fcram_odd_dout,
134	cpu_fc_req_done,
135	fc_rd_data_reg_dout,
136	fc_rd_ecc_err,
137	cpu_fio_req_done,
138	cpu_fio_rd_data,
139	fio_cal_rd_latency,
140	fc_fifo_ren,
141	zcp_wr,
142	fflp_zcp_data,
143	fc_err_status,
144	fflp_debug_port
145
146	);
147
148	input cclk;
149	input reset;
150	input disable_chksum;
151	input[1:0] pio_fio_latency;
152	input[3:0] fcram_lookup_ratio;
153	input fflp_init_done;
154	input[31:0] fcram_refresh_timer_reg_dout;
155	input[9:0] flow_part_sel_reg0_dout;
156	input[9:0] flow_part_sel_reg1_dout;
157	input[9:0] flow_part_sel_reg2_dout;
158	input[9:0] flow_part_sel_reg3_dout;
159	input[9:0] flow_part_sel_reg4_dout;
160	input[9:0] flow_part_sel_reg5_dout;
161	input[9:0] flow_part_sel_reg6_dout;
162	input[9:0] flow_part_sel_reg7_dout;
163	input[23:0] hash_tbl_addr_reg0_dout;
164	input[23:0] hash_tbl_addr_reg1_dout;
165	input[23:0] hash_tbl_addr_reg2_dout;
166	input[23:0] hash_tbl_addr_reg3_dout;
167	input[23:0] hash_tbl_addr_reg4_dout;
168	input[23:0] hash_tbl_addr_reg5_dout;
169	input[23:0] hash_tbl_addr_reg6_dout;
170	input[23:0] hash_tbl_addr_reg7_dout;
171	input[63:0] hash_tbl_data_reg0_dout;
172	input[63:0] hash_tbl_data_reg1_dout;
173	input[63:0] hash_tbl_data_reg2_dout;
174	input[63:0] hash_tbl_data_reg3_dout;
175	input[63:0] hash_tbl_data_reg4_dout;
176	input[63:0] hash_tbl_data_reg5_dout;
177	input[63:0] hash_tbl_data_reg6_dout;
178	input[63:0] hash_tbl_data_reg7_dout;
179	input[71:0] fcram_err_test_reg_dout;
180	input cpu_req_part0_sel;
181	input cpu_req_part1_sel;
182	input cpu_req_part2_sel;
183	input cpu_req_part3_sel;
184	input cpu_req_part4_sel;
185	input cpu_req_part5_sel;
186	input cpu_req_part6_sel;
187	input cpu_req_part7_sel;
188	input pio_rd;
189	input[15:0] pio_wr_data;
190	input pio_fio_cfg_reset;
191	input[7:0] fio_cfg_addr_reg_dout;
192	input cpu_fio_req_sync;
193	input[3:0] fcram_driver_imp_ctrl;
194	input fcram_qs_mode;
195	input cpu_fcram_req_sync;
196	input fc_fifo_empty_sync;
197	input fflp_config_reg_wen_pulse_sync;
198	input[31:0] debug_training_vector;
199	input[2:0] pio_debug_data_sel;
200	input[512:0] fc_fifo_dout;
201	input fcram_fflp_mstrready;
202	input fcram_fflp_fatal_err;
203	input[3:0] fcram_fflp_data_ready;
204	input[35:0] fcram_fflp_even_din;
205	input[35:0] fcram_fflp_odd_din;
206	input[15:0] fcram_fflp_cfg_datrd;
207	input fcram_fflp_cfg_done;
208	input fcram_fflp_cfg_err;
209
210	output fflp_fcram_cfg_rst;
211	output fflp_fcram_cfg_sel;
212	output fflp_fcram_cfg_rd;
213	output[7:0] fflp_fcram_cfg_addr;
214	output[15:0] fflp_fcram_cfg_datwr;
215	output fflp_fcram_slv_update;
216	output[1:0] fflp_fcram_rd_en;
217	output fflp_fcram_cs_l;
218	output fflp_fcram_fn;
219	output fflp_fcram_pd_l;
220	output fflp_fcram_ba0;
221	output fflp_fcram_ba1;
222	output[14:0] fflp_fcram_addr;
223	output[1:0] fflp_fcram_ds;
224	output[1:0] fflp_fcram_triz_en_l;
225	output[35:0] fflp_fcram_even_dout;
226	output[35:0] fflp_fcram_odd_dout;
227	output cpu_fc_req_done;
228	output[71:0] fc_rd_data_reg_dout;
229	output fc_rd_ecc_err;
230	output cpu_fio_req_done;
231	output[31:0] cpu_fio_rd_data;
232	output[7:0] fio_cal_rd_latency;
233	output fc_fifo_ren;
234	output zcp_wr;
235	output[215:0] fflp_zcp_data;
236	output[33:0] fc_err_status;
237	output[31:0] fflp_debug_port;
238
239	wire srch_no_fc_done;
240	wire fwd_sched;
241	wire do_srch_cycle;
242	wire do_cpu_cycle;
243
244	wire fflp_fcram_cfg_rst;
245	wire fflp_fcram_cfg_sel;
246	wire fflp_fcram_cfg_rd;
247	wire[7:0] fflp_fcram_cfg_addr;
248	wire[15:0] fflp_fcram_cfg_datwr;
249	wire fflp_fcram_slv_update;
250	wire[1:0] fflp_fcram_rd_en;
251	wire fflp_fcram_cs_l;
252	wire fflp_fcram_fn;
253	wire fflp_fcram_pd_l;
254	wire fflp_fcram_ba0;
255	wire fflp_fcram_ba1;
256	wire[14:0] fflp_fcram_addr;
257	wire[1:0] fflp_fcram_ds;
258	wire[1:0] fflp_fcram_triz_en_l;
259	wire[35:0] fflp_fcram_even_dout;
260	wire[35:0] fflp_fcram_odd_dout;
261	wire[71:0] fc_din_reg_dout_r;
262	wire ecc_check_err_r;
263	wire ecc_corr_err_r;
264	wire fio_no_fatal_err;
265	wire srch_burst_done;
266	wire cpu_burst_done_sm;
267	wire[4:0] fcram_sm_state;
268	wire srch_burst_done_2;
269	wire srch_fio_wait_6;
270	wire srch_fio_rd_en_4;
271	wire cpu_fc_req_done;
272	wire[71:0] fc_rd_data_reg_dout;
273	wire fc_rd_ecc_err;
274	wire cpu_fio_req_done;
275	wire[31:0] cpu_fio_rd_data;
276	wire[7:0] fio_cal_rd_latency;
277
278	wire[19:0] merg_bus_0_hash_v1;
279	wire[2:0] merg_bus_0_rdc_tbl_num;
280	wire merg_bus_1_fc_lookup;
281	wire fc_fifo_ren;
282	wire zcp_wr;
283	wire[215:0] fflp_zcp_data;
284	wire[33:0] fc_err_status;
285	wire[31:0] fflp_debug_port;
286
287	`ifdef NEPTUNE
288	wire [3:0] do_nad;
289	wire [3:0] do_nor;
290	wire [3:0] do_inv;
291	wire [3:0] do_mux;
292	wire [3:0] do_q;
293	wire so;
294
295	nep_spare_fflp spare_fflp_0 (
296	.di_nd3 ({1'h1, 1'h1, do_q[3]}),
297	.di_nd2 ({1'h1, 1'h1, do_q[2]}),
298	.di_nd1 ({1'h1, 1'h1, do_q[1]}),
299	.di_nd0 ({1'h1, 1'h1, do_q[0]}),
300	.di_nr3 ({1'h0, 1'h0}),
301	.di_nr2 ({1'h0, 1'h0}),
302	.di_nr1 ({1'h0, 1'h0}),
303	.di_nr0 ({1'h0, 1'h0}),
304	.di_inv (do_nad[3:0]),
305	.di_mx3 ({1'h0, 1'h0}),
306	.di_mx2 ({1'h0, 1'h0}),
307	.di_mx1 ({1'h0, 1'h0}),
308	.di_mx0 ({1'h0, 1'h0}),
309	.mx_sel (do_nor[3:0]),
310	.di_reg (do_inv[3:0]),
311	.wt_ena (do_mux[3:0]),
312	.rst ({reset,reset,reset,reset}),
313	.si (1'h0),
314	.se (1'h0),
315	.clk (cclk),
316	.do_nad (do_nad[3:0]),
317	.do_nor (do_nor[3:0]),
318	.do_inv (do_inv[3:0]),
319	.do_mux (do_mux[3:0]),
320	.do_q (do_q[3:0]),
321	.so (so)
322	);
323
324	`endif
325
326
327	fflp_fcram_sched fflp_fcram_sched_inst
328	(
329	.cclk (cclk),
330	.reset (reset),
331	.fcram_lookup_ratio (fcram_lookup_ratio),
332	.cpu_fcram_req_sync (cpu_fcram_req_sync),
333	.fc_fifo_empty_sync (fc_fifo_empty_sync),
334	.fc_fifo_fc_lookup (fc_fifo_dout[498]),
335	.srch_burst_done (srch_burst_done),
336	.cpu_burst_done_sm (cpu_burst_done_sm),
337
338	.srch_no_fc_done (srch_no_fc_done),
339	.fwd_sched (fwd_sched),
340	.do_srch_cycle (do_srch_cycle),
341	.do_cpu_cycle (do_cpu_cycle),
342	.fc_fifo_ren (fc_fifo_ren)
343
344	);
345
346
347	fflp_fcram_cntl fflp_fcram_cntl_inst
348	(
349	.cclk (cclk),
350	.reset (reset),
351	.disable_chksum (disable_chksum),
352	.pio_fio_latency (pio_fio_latency),
353	.fflp_init_done (fflp_init_done),
354	.fcram_refresh_timer_reg_dout (fcram_refresh_timer_reg_dout),
355	.flow_part_sel_reg0_dout (flow_part_sel_reg0_dout),
356	.flow_part_sel_reg1_dout (flow_part_sel_reg1_dout),
357	.flow_part_sel_reg2_dout (flow_part_sel_reg2_dout),
358	.flow_part_sel_reg3_dout (flow_part_sel_reg3_dout),
359	.flow_part_sel_reg4_dout (flow_part_sel_reg4_dout),
360	.flow_part_sel_reg5_dout (flow_part_sel_reg5_dout),
361	.flow_part_sel_reg6_dout (flow_part_sel_reg6_dout),
362	.flow_part_sel_reg7_dout (flow_part_sel_reg7_dout),
363	.hash_tbl_addr_reg0_dout (hash_tbl_addr_reg0_dout),
364	.hash_tbl_addr_reg1_dout (hash_tbl_addr_reg1_dout),
365	.hash_tbl_addr_reg2_dout (hash_tbl_addr_reg2_dout),
366	.hash_tbl_addr_reg3_dout (hash_tbl_addr_reg3_dout),
367	.hash_tbl_addr_reg4_dout (hash_tbl_addr_reg4_dout),
368	.hash_tbl_addr_reg5_dout (hash_tbl_addr_reg5_dout),
369	.hash_tbl_addr_reg6_dout (hash_tbl_addr_reg6_dout),
370	.hash_tbl_addr_reg7_dout (hash_tbl_addr_reg7_dout),
371	.hash_tbl_data_reg0_dout (hash_tbl_data_reg0_dout),
372	.hash_tbl_data_reg1_dout (hash_tbl_data_reg1_dout),
373	.hash_tbl_data_reg2_dout (hash_tbl_data_reg2_dout),
374	.hash_tbl_data_reg3_dout (hash_tbl_data_reg3_dout),
375	.hash_tbl_data_reg4_dout (hash_tbl_data_reg4_dout),
376	.hash_tbl_data_reg5_dout (hash_tbl_data_reg5_dout),
377	.hash_tbl_data_reg6_dout (hash_tbl_data_reg6_dout),
378	.hash_tbl_data_reg7_dout (hash_tbl_data_reg7_dout),
379	.fcram_err_test_reg_dout (fcram_err_test_reg_dout),
380	.cpu_req_part0_sel (cpu_req_part0_sel),
381	.cpu_req_part1_sel (cpu_req_part1_sel),
382	.cpu_req_part2_sel (cpu_req_part2_sel),
383	.cpu_req_part3_sel (cpu_req_part3_sel),
384	.cpu_req_part4_sel (cpu_req_part4_sel),
385	.cpu_req_part5_sel (cpu_req_part5_sel),
386	.cpu_req_part6_sel (cpu_req_part6_sel),
387	.cpu_req_part7_sel (cpu_req_part7_sel),
388	.pio_rd (pio_rd),
389	.pio_wr_data (pio_wr_data),
390	.pio_fio_cfg_reset (pio_fio_cfg_reset),
391	.fio_cfg_addr_reg_dout (fio_cfg_addr_reg_dout),
392	.cpu_fio_req_sync (cpu_fio_req_sync),
393	.fcram_driver_imp_ctrl (fcram_driver_imp_ctrl),
394	.fcram_qs_mode (fcram_qs_mode),
395	.srch_no_fc_done (srch_no_fc_done),
396	.do_srch_cycle (do_srch_cycle),
397	.do_cpu_cycle (do_cpu_cycle),
398	.merg_bus_0_hash_v1 (merg_bus_0_hash_v1),
399	.merg_bus_0_rdc_tbl_num (merg_bus_0_rdc_tbl_num),
400	.merg_bus_1_fc_lookup (merg_bus_1_fc_lookup),
401	.fcram_fflp_mstrready (fcram_fflp_mstrready),
402	.fcram_fflp_fatal_err (fcram_fflp_fatal_err),
403	.fcram_fflp_data_ready (fcram_fflp_data_ready),
404	.fcram_fflp_even_din (fcram_fflp_even_din),
405	.fcram_fflp_odd_din (fcram_fflp_odd_din),
406	.fcram_fflp_cfg_datrd (fcram_fflp_cfg_datrd),
407	.fcram_fflp_cfg_done (fcram_fflp_cfg_done),
408	.fcram_fflp_cfg_err (fcram_fflp_cfg_err),
409
410	.fflp_fcram_cfg_rst (fflp_fcram_cfg_rst),
411	.fflp_fcram_cfg_sel (fflp_fcram_cfg_sel),
412	.fflp_fcram_cfg_rd (fflp_fcram_cfg_rd),
413	.fflp_fcram_cfg_addr (fflp_fcram_cfg_addr),
414	.fflp_fcram_cfg_datwr (fflp_fcram_cfg_datwr),
415	.fflp_fcram_slv_update (fflp_fcram_slv_update),
416	.fflp_fcram_rd_en (fflp_fcram_rd_en),
417	.fflp_fcram_cs_l (fflp_fcram_cs_l),
418	.fflp_fcram_fn (fflp_fcram_fn),
419	.fflp_fcram_pd_l (fflp_fcram_pd_l),
420	.fflp_fcram_ba0 (fflp_fcram_ba0),
421	.fflp_fcram_ba1 (fflp_fcram_ba1),
422	.fflp_fcram_addr (fflp_fcram_addr),
423	.fflp_fcram_ds (fflp_fcram_ds),
424	.fflp_fcram_triz_en_l (fflp_fcram_triz_en_l),
425	.fflp_fcram_even_dout (fflp_fcram_even_dout),
426	.fflp_fcram_odd_dout (fflp_fcram_odd_dout),
427	.fc_din_reg_dout_r (fc_din_reg_dout_r),
428	.ecc_check_err_r (ecc_check_err_r),
429	.ecc_corr_err_r (ecc_corr_err_r),
430	.fio_no_fatal_err (fio_no_fatal_err),
431	.srch_burst_done (srch_burst_done),
432	.cpu_burst_done_sm (cpu_burst_done_sm),
433	.fcram_sm_state (fcram_sm_state),
434	.srch_burst_done_2 (srch_burst_done_2),
435	.srch_fio_wait_6 (srch_fio_wait_6),
436	.srch_fio_rd_en_4 (srch_fio_rd_en_4),
437	.cpu_fc_req_done (cpu_fc_req_done),
438	.fc_rd_data_reg_dout (fc_rd_data_reg_dout),
439	.fc_rd_ecc_err (fc_rd_ecc_err),
440	.cpu_fio_req_done (cpu_fio_req_done),
441	.cpu_fio_rd_data (cpu_fio_rd_data),
442	.fio_cal_rd_latency (fio_cal_rd_latency)
443
444	);
445
446
447	fflp_merge_func fflp_merge_func_inst
448	(
449	.cclk (cclk),
450	.reset (reset),
451	.fwd_sched (fwd_sched),
452	.fc_fifo_dout (fc_fifo_dout),
453	.fc_din_reg_dout_r (fc_din_reg_dout_r),
454	.ecc_check_err_r (ecc_check_err_r),
455	.ecc_corr_err_r (ecc_corr_err_r),
456	.fio_no_fatal_err (fio_no_fatal_err),
457	.srch_burst_done_2 (srch_burst_done_2),
458	.srch_fio_wait_6 (srch_fio_wait_6),
459	.srch_fio_rd_en_4 (srch_fio_rd_en_4),
460	.fcram_sm_state (fcram_sm_state),
461	.fflp_config_reg_wen_pulse_sync (fflp_config_reg_wen_pulse_sync),
462	.debug_training_vector (debug_training_vector),
463	.pio_debug_data_sel (pio_debug_data_sel),
464
465	.merg_bus_0_hash_v1 (merg_bus_0_hash_v1),
466	.merg_bus_0_rdc_tbl_num (merg_bus_0_rdc_tbl_num),
467	.merg_bus_1_fc_lookup (merg_bus_1_fc_lookup),
468	.zcp_wr (zcp_wr),
469	.fflp_zcp_data (fflp_zcp_data),
470	.fc_err_status (fc_err_status),
471	.fflp_debug_port (fflp_debug_port)
472
473	);
474
475
476	endmodule
477