Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / fflp_hash_func.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fflp_hash_func.v
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35/**********************************************************************/
36/*project name: N2 */
37/*module name: fflp_hash_func */
38/*description: Pipeline for hash algorithm CRC-32C and CRC-CCITT */
39/* CRC-32C: */
40/* x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+ */
41/* x^14+x^13+x^11+x^10+x^9+x^8+x^6+1 */
42/* */
43/* CRC-CCITT: */
44/* x^16+x^12+x^5+1 */
45/* */
46/*parent module in: */
47/*child modules in: fflp_CRC32_D64, fflp_CRC16_D64 */
48/*interface modules: */
49/*author name: Jeanne Cai */
50/*date created: 25-05-04 */
51/* */
52/* Copyright (c) 2004, Sun Microsystems, Inc. */
53/* Sun Proprietary and Confidential */
54/* */
55/*modifications: */
56/* */
57/**********************************************************************/
58
59module fflp_hash_func
60 (
61 cclk,
62 reset,
63 fwd_info_hash_key,
64 fwd_sched,
65 kick_off_ram_srch_4,
66 h1_init_value_reg_dout,
67 h2_init_value_reg_dout,
68
69 hash_v1,
70 hash_v2
71
72 );
73
74input cclk;
75input reset;
76input[361:0] fwd_info_hash_key;
77input fwd_sched;
78input kick_off_ram_srch_4;
79input[31:0] h1_init_value_reg_dout;
80input[15:0] h2_init_value_reg_dout;
81
82output[19:0] hash_v1;
83output[15:0] hash_v2;
84
85wire crc_cyc0;
86wire crc_cyc1;
87wire crc_cyc2;
88wire crc_cyc3;
89wire crc_cyc4;
90wire crc_cyc5;
91
92wire[383:0] hash_key;
93wire[63:0] hash_data0;
94wire[63:0] hash_data1;
95wire[63:0] hash_data2;
96wire[63:0] hash_data3;
97wire[63:0] hash_data4;
98wire[63:0] hash_data5;
99wire[63:0] hash_data5_r;
100
101wire[31:0] new1_crc0;
102wire[31:0] new1_crc1;
103wire[31:0] new1_crc2;
104wire[31:0] new1_crc3;
105wire[31:0] new1_crc4;
106wire[31:0] new1_crc5;
107
108wire[31:0] new1_crc0_r;
109wire[31:0] new1_crc1_r;
110wire[31:0] new1_crc2_r;
111wire[31:0] new1_crc3_r;
112wire[31:0] new1_crc4_r;
113wire[31:0] new1_crc5_r;
114wire[19:0] hash_v1;
115
116wire[15:0] new2_crc0;
117wire[15:0] new2_crc1;
118wire[15:0] new2_crc2;
119wire[15:0] new2_crc3;
120wire[15:0] new2_crc4;
121wire[15:0] new2_crc5;
122
123wire[15:0] new2_crc0_r;
124wire[15:0] new2_crc1_r;
125wire[15:0] new2_crc2_r;
126wire[15:0] new2_crc3_r;
127wire[15:0] new2_crc4_r;
128wire[15:0] new2_crc5_r;
129wire[15:0] hash_v2;
130
131wire[31:0] init_crc1;
132wire[15:0] init_crc2;
133
134assign init_crc1 = h1_init_value_reg_dout;
135assign init_crc2 = h2_init_value_reg_dout;
136
137assign hash_key = {fwd_info_hash_key, 22'b0};
138assign hash_data0 = hash_key[63:0];
139assign hash_data1 = hash_key[127:64];
140assign hash_data2 = hash_key[191:128];
141assign hash_data3 = hash_key[255:192];
142assign hash_data4 = hash_key[319:256];
143assign hash_data5 = hash_key[383:320];
144
145fflp_CRC32_D64 hash1_stage0 (.Data (hash_data0), .CRC (init_crc1), .NewCRC (new1_crc0));
146fflp_CRC32_D64 hash1_stage1 (.Data (hash_data1), .CRC (new1_crc0_r), .NewCRC (new1_crc1));
147fflp_CRC32_D64 hash1_stage2 (.Data (hash_data2), .CRC (new1_crc1_r), .NewCRC (new1_crc2));
148fflp_CRC32_D64 hash1_stage3 (.Data (hash_data3), .CRC (new1_crc2_r), .NewCRC (new1_crc3));
149fflp_CRC32_D64 hash1_stage4 (.Data (hash_data4), .CRC (new1_crc3_r), .NewCRC (new1_crc4));
150fflp_CRC32_D64 hash1_stage5 (.Data (hash_data5_r), .CRC (new1_crc4_r), .NewCRC (new1_crc5));
151
152fflp_CRC16_D64 hash2_stage0 (.Data (hash_data0), .CRC (init_crc2), .NewCRC (new2_crc0));
153fflp_CRC16_D64 hash2_stage1 (.Data (hash_data1), .CRC (new2_crc0_r), .NewCRC (new2_crc1));
154fflp_CRC16_D64 hash2_stage2 (.Data (hash_data2), .CRC (new2_crc1_r), .NewCRC (new2_crc2));
155fflp_CRC16_D64 hash2_stage3 (.Data (hash_data3), .CRC (new2_crc2_r), .NewCRC (new2_crc3));
156fflp_CRC16_D64 hash2_stage4 (.Data (hash_data4), .CRC (new2_crc3_r), .NewCRC (new2_crc4));
157fflp_CRC16_D64 hash2_stage5 (.Data (hash_data5_r), .CRC (new2_crc4_r), .NewCRC (new2_crc5));
158
159
160dffre #(64) hash_data5_reg (cclk, reset, crc_cyc4, hash_data5, hash_data5_r);
161
162dffr #(1) crc_cyc0_reg (cclk, reset, fwd_sched, crc_cyc0);
163dffr #(1) crc_cyc1_reg (cclk, reset, crc_cyc0, crc_cyc1);
164dffr #(1) crc_cyc2_reg (cclk, reset, crc_cyc1, crc_cyc2);
165dffr #(1) crc_cyc3_reg (cclk, reset, crc_cyc2, crc_cyc3);
166dffr #(1) crc_cyc4_reg (cclk, reset, crc_cyc3, crc_cyc4);
167dffr #(1) crc_cyc5_reg (cclk, reset, crc_cyc4, crc_cyc5);
168
169dffre #(32) new1_crc0_reg (cclk, reset, crc_cyc0, new1_crc0, new1_crc0_r);
170dffre #(32) new1_crc1_reg (cclk, reset, crc_cyc1, new1_crc1, new1_crc1_r);
171dffre #(32) new1_crc2_reg (cclk, reset, crc_cyc2, new1_crc2, new1_crc2_r);
172dffre #(32) new1_crc3_reg (cclk, reset, crc_cyc3, new1_crc3, new1_crc3_r);
173dffre #(32) new1_crc4_reg (cclk, reset, crc_cyc4, new1_crc4, new1_crc4_r);
174dffre #(32) new1_crc5_reg (cclk, reset, crc_cyc5, new1_crc5, new1_crc5_r);
175
176dffre #(16) new2_crc0_reg (cclk, reset, crc_cyc0, new2_crc0, new2_crc0_r);
177dffre #(16) new2_crc1_reg (cclk, reset, crc_cyc1, new2_crc1, new2_crc1_r);
178dffre #(16) new2_crc2_reg (cclk, reset, crc_cyc2, new2_crc2, new2_crc2_r);
179dffre #(16) new2_crc3_reg (cclk, reset, crc_cyc3, new2_crc3, new2_crc3_r);
180dffre #(16) new2_crc4_reg (cclk, reset, crc_cyc4, new2_crc4, new2_crc4_r);
181dffre #(16) new2_crc5_reg (cclk, reset, crc_cyc5, new2_crc5, new2_crc5_r);
182
183dffre #(20) hash_v1_reg (cclk, reset, kick_off_ram_srch_4, new1_crc5_r[19:0], hash_v1);
184dffre #(16) hash_v2_reg (cclk, reset, kick_off_ram_srch_4, new2_crc5_r, hash_v2);
185
186
187
188endmodule