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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / fflp_hdr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fflp_hdr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/**********************************************************************/
36/*project name: NIU */
37/*module name: fflp_hdr */
38/*description: datapath for header buss and information decoded */
39/* from them */
40/* */
41/*parent module in: fflp.v */
42/*child modules in: none */
43/*interface modules: */
44/*author name: Jeanne Cai */
45/*date created: 03-22_2004 */
46/* */
47/* Copyright (c) 2004, Sun Microsystems, Inc. */
48/* Sun Proprietary and Confidential */
49/* */
50/*modifications: */
51/**********************************************************************/
52
53module fflp_hdr (
54 cclk,
55 reset,
56 ipp_fflp_dvalid,
57 ipp_fflp_data,
58 ipp_fflp_mac_default,
59 ipp_fflp_mac_port,
60 snap_en,
61 disable_chksum,
62 class2_hdr_byte_value,
63 class3_hdr_byte_value,
64 class4_hdr_byte_value,
65 class5_hdr_byte_value,
66 class6_hdr_byte_value,
67 class7_hdr_byte_value,
68 class_action_reg4_dout,
69 class_action_reg5_dout,
70 class_action_reg6_dout,
71 class_action_reg7_dout,
72 class_action_reg8_dout,
73 class_action_reg9_dout,
74 class_action_reg10_dout,
75 class_action_reg11_dout,
76 class_action_reg12_dout,
77 class_action_reg13_dout,
78 class_action_reg14_dout,
79 class_action_reg15_dout,
80 f_key_class_action_reg4_dout,
81 f_key_class_action_reg5_dout,
82 f_key_class_action_reg6_dout,
83 f_key_class_action_reg7_dout,
84 f_key_class_action_reg8_dout,
85 f_key_class_action_reg9_dout,
86 f_key_class_action_reg10_dout,
87 f_key_class_action_reg11_dout,
88 f_key_class_action_reg12_dout,
89 f_key_class_action_reg13_dout,
90 f_key_class_action_reg14_dout,
91 f_key_class_action_reg15_dout,
92 hdr_ctrl_bit_mask_reg_dout,
93 cpu_vlan_req,
94 cpu_vlan_rd,
95 cpu_vlan_wr,
96 cpu_vlan_addr,
97 vlan_tbl_rd_din,
98 fwd_sched,
99
100 fflp_ipp_ready,
101 fflp_ipp_dvalid,
102 fflp_ipp_data,
103 fwd_req,
104 key_bus,
105 fwd_info_bus,
106 vlan_tbl_cs,
107 vlan_tbl_wr,
108 vlan_tbl_addr,
109 vlan_tbl_din_reg_dout,
110 vlan_parity_err_log_en,
111 vlan_tag_id,
112 cpu_vlan_gnt_3
113
114 );
115
116input cclk;
117input reset;
118input ipp_fflp_dvalid;
119input[127:0] ipp_fflp_data;
120input[11:0] ipp_fflp_mac_default;
121input[1:0] ipp_fflp_mac_port;
122input snap_en;
123input disable_chksum;
124input[16:0] class2_hdr_byte_value;
125input[16:0] class3_hdr_byte_value;
126input[25:0] class4_hdr_byte_value;
127input[25:0] class5_hdr_byte_value;
128input[25:0] class6_hdr_byte_value;
129input[25:0] class7_hdr_byte_value;
130input[2:0] class_action_reg4_dout;
131input[2:0] class_action_reg5_dout;
132input[2:0] class_action_reg6_dout;
133input[2:0] class_action_reg7_dout;
134input[2:0] class_action_reg8_dout;
135input[2:0] class_action_reg9_dout;
136input[2:0] class_action_reg10_dout;
137input[2:0] class_action_reg11_dout;
138input[2:0] class_action_reg12_dout;
139input[2:0] class_action_reg13_dout;
140input[2:0] class_action_reg14_dout;
141input[2:0] class_action_reg15_dout;
142input[9:0] f_key_class_action_reg4_dout;
143input[9:0] f_key_class_action_reg5_dout;
144input[9:0] f_key_class_action_reg6_dout;
145input[9:0] f_key_class_action_reg7_dout;
146input[9:0] f_key_class_action_reg8_dout;
147input[9:0] f_key_class_action_reg9_dout;
148input[9:0] f_key_class_action_reg10_dout;
149input[9:0] f_key_class_action_reg11_dout;
150input[9:0] f_key_class_action_reg12_dout;
151input[9:0] f_key_class_action_reg13_dout;
152input[9:0] f_key_class_action_reg14_dout;
153input[9:0] f_key_class_action_reg15_dout;
154input[11:0] hdr_ctrl_bit_mask_reg_dout;
155input cpu_vlan_req;
156input cpu_vlan_rd;
157input cpu_vlan_wr;
158input[11:0] cpu_vlan_addr;
159input[17:0] vlan_tbl_rd_din;
160input fwd_sched;
161
162output fflp_ipp_ready;
163output[3:0] fflp_ipp_dvalid;
164output[15:0] fflp_ipp_data;
165output fwd_req;
166output[199:0] key_bus;
167output[445:0] fwd_info_bus;
168output vlan_tbl_cs;
169output vlan_tbl_wr;
170output[11:0] vlan_tbl_addr;
171output[17:0] vlan_tbl_din_reg_dout;
172output vlan_parity_err_log_en;
173output[11:0] vlan_tag_id;
174output cpu_vlan_gnt_3;
175
176wire fflp_ipp_ready;
177wire[3:0] fflp_ipp_dvalid;
178wire[15:0] fflp_ipp_data;
179wire fwd_req;
180wire[199:0] key_bus;
181wire[445:0] fwd_info_bus;
182wire vlan_tbl_cs;
183wire vlan_tbl_wr;
184wire[11:0] vlan_tbl_addr;
185wire[17:0] vlan_tbl_din_reg_dout;
186wire vlan_parity_err_log_en;
187wire[11:0] vlan_tag_id;
188wire cpu_vlan_gnt_3;
189
190wire hdr_fifo_space_avail;
191wire hdr_fifo_full;
192
193wire shft0_reg_en;
194wire shft1_reg_en;
195wire shft2_reg_en;
196wire shft3_reg_en;
197wire shft4_reg_en;
198wire shft5_reg_en;
199wire shft6_reg_en;
200wire shft7_reg_en;
201wire hdr_shft_done;
202
203
204fflp_hdr_dp fflp_hdr_dp_inst (
205 .cclk (cclk),
206 .reset (reset),
207 .ipp_fflp_data (ipp_fflp_data),
208 .ipp_fflp_mac_default (ipp_fflp_mac_default),
209 .ipp_fflp_mac_port (ipp_fflp_mac_port),
210 .shft0_reg_en (shft0_reg_en),
211 .shft1_reg_en (shft1_reg_en),
212 .shft2_reg_en (shft2_reg_en),
213 .shft3_reg_en (shft3_reg_en),
214 .shft4_reg_en (shft4_reg_en),
215 .shft5_reg_en (shft5_reg_en),
216 .shft6_reg_en (shft6_reg_en),
217 .shft7_reg_en (shft7_reg_en),
218 .hdr_shft_done (hdr_shft_done),
219 .fwd_sched (fwd_sched),
220 .snap_en (snap_en),
221 .disable_chksum (disable_chksum),
222 .class2_hdr_byte_value (class2_hdr_byte_value),
223 .class3_hdr_byte_value (class3_hdr_byte_value),
224 .class4_hdr_byte_value (class4_hdr_byte_value),
225 .class5_hdr_byte_value (class5_hdr_byte_value),
226 .class6_hdr_byte_value (class6_hdr_byte_value),
227 .class7_hdr_byte_value (class7_hdr_byte_value),
228 .class_action_reg4_dout (class_action_reg4_dout),
229 .class_action_reg5_dout (class_action_reg5_dout),
230 .class_action_reg6_dout (class_action_reg6_dout),
231 .class_action_reg7_dout (class_action_reg7_dout),
232 .class_action_reg8_dout (class_action_reg8_dout),
233 .class_action_reg9_dout (class_action_reg9_dout),
234 .class_action_reg10_dout (class_action_reg10_dout),
235 .class_action_reg11_dout (class_action_reg11_dout),
236 .class_action_reg12_dout (class_action_reg12_dout),
237 .class_action_reg13_dout (class_action_reg13_dout),
238 .class_action_reg14_dout (class_action_reg14_dout),
239 .class_action_reg15_dout (class_action_reg15_dout),
240 .f_key_class_action_reg4_dout (f_key_class_action_reg4_dout),
241 .f_key_class_action_reg5_dout (f_key_class_action_reg5_dout),
242 .f_key_class_action_reg6_dout (f_key_class_action_reg6_dout),
243 .f_key_class_action_reg7_dout (f_key_class_action_reg7_dout),
244 .f_key_class_action_reg8_dout (f_key_class_action_reg8_dout),
245 .f_key_class_action_reg9_dout (f_key_class_action_reg9_dout),
246 .f_key_class_action_reg10_dout (f_key_class_action_reg10_dout),
247 .f_key_class_action_reg11_dout (f_key_class_action_reg11_dout),
248 .f_key_class_action_reg12_dout (f_key_class_action_reg12_dout),
249 .f_key_class_action_reg13_dout (f_key_class_action_reg13_dout),
250 .f_key_class_action_reg14_dout (f_key_class_action_reg14_dout),
251 .f_key_class_action_reg15_dout (f_key_class_action_reg15_dout),
252 .hdr_ctrl_bit_mask_reg_dout (hdr_ctrl_bit_mask_reg_dout),
253 .cpu_vlan_req (cpu_vlan_req),
254 .cpu_vlan_rd (cpu_vlan_rd),
255 .cpu_vlan_wr (cpu_vlan_wr),
256 .cpu_vlan_addr (cpu_vlan_addr),
257 .vlan_tbl_rd_din (vlan_tbl_rd_din),
258
259 .fwd_req (fwd_req),
260 .key_bus (key_bus),
261 .fwd_info_bus (fwd_info_bus),
262 .hdr_fifo_space_avail (hdr_fifo_space_avail),
263 .hdr_fifo_full (hdr_fifo_full),
264 .fflp_ipp_dvalid (fflp_ipp_dvalid),
265 .fflp_ipp_data (fflp_ipp_data),
266 .vlan_tbl_cs (vlan_tbl_cs),
267 .vlan_tbl_wr (vlan_tbl_wr),
268 .vlan_tbl_addr (vlan_tbl_addr),
269 .vlan_tbl_din_reg_dout (vlan_tbl_din_reg_dout),
270 .vlan_parity_err_log_en (vlan_parity_err_log_en),
271 .vlan_tag_id (vlan_tag_id),
272 .cpu_vlan_gnt_3 (cpu_vlan_gnt_3)
273
274 );
275
276
277
278fflp_hdr_cntl fflp_hdr_cntl_inst (
279 .cclk (cclk),
280 .reset (reset),
281 .ipp_fflp_dvalid (ipp_fflp_dvalid),
282 .hdr_fifo_space_avail (hdr_fifo_space_avail),
283 .hdr_fifo_full (hdr_fifo_full),
284
285 .fflp_ipp_ready (fflp_ipp_ready),
286 .shft0_reg_en (shft0_reg_en),
287 .shft1_reg_en (shft1_reg_en),
288 .shft2_reg_en (shft2_reg_en),
289 .shft3_reg_en (shft3_reg_en),
290 .shft4_reg_en (shft4_reg_en),
291 .shft5_reg_en (shft5_reg_en),
292 .shft6_reg_en (shft6_reg_en),
293 .shft7_reg_en (shft7_reg_en),
294 .hdr_shft_done (hdr_shft_done)
295
296 );
297
298endmodule
299
Full OpenSPARC design & verification tarball including full HDL.