[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / mac_pio_intf.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mac_pio_intf.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/*%W%	%G%*/

/*************************************************************************
 *
 * File Name    : mac_pio_intf.v
 * Author Name  : John Lo
 * Description  : It contains mac pio interface mux and demux logic.
 * Parent Module: mac
 * Child  Module: 
 * Interface Mod: many.
 * Date Created : 1/31/02
 *
 * Copyright (c) 2020, Sun Microsystems, Inc. 
 * Sun Proprietary and Confidential   
 *
 * Modification : 4/1/2004 -by John Lo
 *                1. Changed address bus width from 
 *                   16 bits to 19 bits for pio_clients_addr.
 *                2. Support both 32 bit and 64 bit addressing.
 *                3. Changed PIO read/write data bus from
 *                   32 bits to 64 bits.
 *                   The MSB 32 bits are "0". 
 * 
 * Synthesis Notes: 
 * 
 *************************************************************************/

module mac_pio_intf (
clk,
niu_reset_l,
// global broadcast signals
pio_clients_addr,
pio_clients_rd,
pio_clients_wdata,
// designated signals
pio_mac_sel,
mac_pio_ack,
mac_pio_rdata,
// individual internal inputs
// port 0
pio_err_xmac0,
ack_xmac0,
rdata_xmac0,
pio_err_xpcs0,
ack_xpcs0,
rdata_xpcs0,
pio_err_pcs0,
ack_pcs0,
rdata_pcs0,
// port 1
pio_err_xmac1,
ack_xmac1,
rdata_xmac1,
pio_err_xpcs1,
ack_xpcs1,
rdata_xpcs1,
pio_err_pcs1,
ack_pcs1,
rdata_pcs1,
// port 2
pio_err_bmac2,
ack_bmac2,
rdata_bmac2,
pio_err_pcs2,
ack_pcs2,
rdata_pcs2,
// port 3
pio_err_bmac3,
ack_bmac3,
rdata_bmac3,
pio_err_pcs3,
ack_pcs3,
rdata_pcs3,
// esr
pio_err_esr,
ack_esr,
rdata_esr,
// mif
pio_err_mif,
ack_mif,
rdata_mif,
// port 0 interrupts
txmac_interrupt0,
rxmac_interrupt0,
xmac_fc_interrupt0,
xpcs_interrupt0,
pcs_int0,	  // pcs link down interrupt, secondary interrupt
// port 1 interrupts
txmac_interrupt1,
rxmac_interrupt1,
xmac_fc_interrupt1,
xpcs_interrupt1,
pcs_int1,	  // pcs link down interrupt, secondary interrupt
// port 2 interrupts
bm_tx_interrupt2,
bm_rx_interrupt2,
bm_control_interrupt2,
pcs_int2,	  // pcs link down interrupt, secondary interrupt
// port 3 interrupts
bm_tx_interrupt3,
bm_rx_interrupt3,
bm_control_interrupt3,
pcs_int3,	  // pcs link down interrupt, secondary interrupt
//
xmac_debug0,
xpcs_debug0,
mac_debug_sel0,
xmac_debug1,
xpcs_debug1,
esrctl_debug,
// outputs
reset,
mac_debug_port,
sel_xmac0,
sel_xpcs0,
sel_pcs0 ,
sel_xmac1,
sel_xpcs1,
sel_pcs1 ,
sel_bmac2,
sel_pcs2 ,
sel_bmac3,
sel_pcs3 ,
sel_esr,
sel_mif,
pio_addr,
pio_rd,
pio_wdata,
mac_pio_intr0,// port 0 interrupt
mac_pio_intr1,// port 1 interrupt
mac_pio_intr2,// port 2 interrupt
mac_pio_intr3,// port 3 interrupt
mac_pio_err
	);
   
   input           clk;
   input           niu_reset_l;
                   // global broadcast signals
   input [19:0]    pio_clients_addr;
   input 	   pio_clients_rd;
   input [31:0]    pio_clients_wdata;
                   // designated signals
   input 	   pio_mac_sel;
   output 	   mac_pio_ack;
   output [63:0]   mac_pio_rdata;
                   // individual internal inputs
                   // port 0
   input 	   pio_err_xmac0;
   input 	   ack_xmac0;
   input [31:0]    rdata_xmac0;
   input 	   pio_err_xpcs0;
   input 	   ack_xpcs0;
   input [31:0]    rdata_xpcs0;
   input 	   pio_err_pcs0;
   input 	   ack_pcs0;
   input [31:0]    rdata_pcs0;
                   // port 1
   input 	   pio_err_xmac1;
   input 	   ack_xmac1;
   input [31:0]    rdata_xmac1;
   input 	   pio_err_xpcs1;
   input 	   ack_xpcs1;
   input [31:0]    rdata_xpcs1;
   input 	   pio_err_pcs1;
   input 	   ack_pcs1;
   input [31:0]    rdata_pcs1;
                   // port 2
   input 	   pio_err_bmac2;
   input 	   ack_bmac2;
   input [31:0]    rdata_bmac2;
   input 	   pio_err_pcs2;
   input 	   ack_pcs2;
   input [31:0]    rdata_pcs2;
                   // port 3
   input 	   pio_err_bmac3;
   input 	   ack_bmac3;
   input [31:0]    rdata_bmac3;
   input 	   pio_err_pcs3;
   input 	   ack_pcs3;
   input [31:0]    rdata_pcs3;
                   // esr
   input 	   pio_err_esr;
   input 	   ack_esr;
   input [31:0]    rdata_esr;
                   // mif
   input 	   pio_err_mif;
   input 	   ack_mif;
   input [31:0]    rdata_mif;
                   // port 0 interrupts
   input  	   txmac_interrupt0;
   input  	   rxmac_interrupt0;
   input  	   xmac_fc_interrupt0;
   input  	   xpcs_interrupt0;
   input 	   pcs_int0;	  // pcs link down interrupt, secondary interrupt
                   // port 1 interrupts
   input  	   txmac_interrupt1;
   input  	   rxmac_interrupt1;
   input  	   xmac_fc_interrupt1;
   input  	   xpcs_interrupt1;
   input 	   pcs_int1;	  // pcs link down interrupt, secondary interrupt
                   // port 2 interrupts
   input 	   bm_tx_interrupt2;
   input 	   bm_rx_interrupt2;
   input 	   bm_control_interrupt2;
   input 	   pcs_int2;	  // pcs link down interrupt, secondary interrupt
                   // port 3 interrupts
   input 	   bm_tx_interrupt3;
   input 	   bm_rx_interrupt3;
   input 	   bm_control_interrupt3;
   input 	   pcs_int3;	  // pcs link down interrupt, secondary interrupt
                   //
   input [31:0]	   xmac_debug0;
   input [31:0]	   xpcs_debug0;
   input [2:0] 	   mac_debug_sel0;
   input [31:0]	   xmac_debug1;
   input [31:0]	   xpcs_debug1;
   input [31:0]    esrctl_debug;
                   // outputs
   output 	   reset;
   output [31:0]   mac_debug_port;
   output          sel_xmac0;
   output          sel_xpcs0;
   output          sel_pcs0 ;
   output          sel_xmac1;
   output          sel_xpcs1;
   output          sel_pcs1 ;
   output          sel_bmac2;
   output          sel_pcs2 ;
   output          sel_bmac3;
   output          sel_pcs3 ;
   output 	   sel_esr;
   output 	   sel_mif;
   output [16:0]   pio_addr;
   output 	   pio_rd;
   output [31:0]   pio_wdata;
   output 	   mac_pio_intr0;// port 0 interrupt
   output 	   mac_pio_intr1;// port 1 interrupt
   output 	   mac_pio_intr2;// port 2 interrupt
   output 	   mac_pio_intr3;// port 3 interrupt
   output 	   mac_pio_err;
   
// xmac    address range: [8:0] x2 -> reserve 1 bit -> 10
// big_mac address range: [8:0] x2 -> 
// xpcs    address range: [6:0] x2 -> 
// pcs     address range: [6:0] x4 -> 
// ---------------------------------
// total   address range:
// 8K is enough
   wire 	   niu_reset_l;
   wire 	   reset;
   wire 	   reset_l;
   reg 		   pio_ack;
   reg   [31:0]    pio_rdata;
   reg 		   pio_err;
   wire 	   pio_sel;
   wire 	   pio_sel_pls;
   wire 	   pio_sel_pls_d1;
   wire 	   pio_sel_pls_d2;
   wire  [16:0]    pio_addr;
   wire 	   pio_rd;
   wire  [31:0]    pio_wdata;
                   // pio global signals

   wire  [19:0]    pio_clients_addr;
   wire  [31:0]    pio_clients_wdata;
   wire 	   pio_clients_rd;
                   // designated signals
   wire  	   pio_mac_sel;
   wire   	   mac_pio_ack;
   wire  [63:0]    mac_pio_rdata;
   wire   	   mac_pio_err;
                   // individual internal wire
   wire  [31:0]    rdata_xmac0;
   wire  [31:0]    rdata_xpcs0;
   wire  [31:0]    rdata_pcs0;
   wire  [31:0]    rdata_xmac1;
   wire  [31:0]    rdata_xpcs1;
   wire  [31:0]    rdata_pcs1;
   wire  [31:0]    rdata_bmac2;
   wire  [31:0]    rdata_pcs2;
   wire  [31:0]    rdata_bmac3;
   wire  [31:0]    rdata_pcs3;
   wire  [31:0]    rdata_esr;
   wire  [31:0]    rdata_mif;
   wire  [31:0]	   xmac_debug0;
   wire  [31:0]	   xpcs_debug0;
   wire  [2:0] 	   mac_debug_sel0;
   wire  [31:0]	   xmac_debug1;
   wire  [31:0]	   xpcs_debug1;


// register the input signals:
   // vlint flag_dangling_net_within_module off
   // vlint flag_net_has_no_load off
   wire [19:0] 	   pio_clients_addr_64bit;
   // vlint flag_net_has_no_load on
   // vlint flag_dangling_net_within_module on

SYNC_CELL    reset_SYNC_CELL(.D(niu_reset_l),.CP(clk),.Q(reset_l));

   assign 	   reset = ~reset_l;
   
RegDff #(1)  pio_sel_RegDff(  
                     .din(pio_mac_sel),
                     .clk(clk),
                     .qout(pio_sel));

pls_gen pio_sel_pls_gen(.clk(clk),.in(pio_sel),.out(pio_sel_pls));

RegDff #(1) pio_sel_pls_d1_RegDff(.din(pio_sel_pls),.clk(clk),.qout(pio_sel_pls_d1));
RegDff #(1) pio_sel_pls_d2_RegDff(.din(pio_sel_pls_d1),.clk(clk),.qout(pio_sel_pls_d2));

RegDff #(20) pio_clients_addr_64bit_RegDff(  
                     .din(pio_clients_addr[19:0]),
                     .clk(clk),
                     .qout(pio_clients_addr_64bit[19:0]));

assign   pio_addr[16:0] = pio_clients_addr_64bit[16:0];

RegDff #(1)  pio_rd_RegDff(  
                     .din(pio_clients_rd),
                     .clk(clk),
                     .qout(pio_rd));

RegDff #(32) pio_wdata_RegDff(  
                     .din(pio_clients_wdata[31:0]),
                     .clk(clk),
                     .qout(pio_wdata[31:0]));

   wire  sel_xmac0 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XMAC0_ADDR_OFFSET);
   wire  sel_xpcs0 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XPCS0_ADDR_OFFSET);
   wire  sel_pcs0  = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS0_ADDR_OFFSET);
   wire  sel_xmac1 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XMAC1_ADDR_OFFSET);
   wire  sel_xpcs1 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XPCS1_ADDR_OFFSET);
   wire  sel_pcs1  = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS1_ADDR_OFFSET);
   wire  sel_bmac2 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `BMAC2_ADDR_OFFSET);
   wire  sel_pcs2  = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS2_ADDR_OFFSET);
   wire  sel_bmac3 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `BMAC3_ADDR_OFFSET);
   wire  sel_pcs3  = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS3_ADDR_OFFSET);
   wire  sel_esr   = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `ESR_ADDR_OFFSET);
   wire  sel_mif   = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `MIF_ADDR_OFFSET);
   
   wire  mac_pio_interrupt0= txmac_interrupt0      |
                             rxmac_interrupt0      |
                             xmac_fc_interrupt0    |
                             xpcs_interrupt0       |
                             pcs_int0              ;

   wire  mac_pio_interrupt1= txmac_interrupt1      |
                             rxmac_interrupt1      |
                             xmac_fc_interrupt1    |
                             xpcs_interrupt1       |
                             pcs_int1              ;

   wire  mac_pio_interrupt2= bm_tx_interrupt2      |
                             bm_rx_interrupt2      |
                             bm_control_interrupt2 |
                             pcs_int2;

   wire  mac_pio_interrupt3= bm_tx_interrupt3      |
                             bm_rx_interrupt3      |
                             bm_control_interrupt3 |
                             pcs_int3;

   FD1 mac_pio_intr0_FD1(.CP(clk),.D(mac_pio_interrupt0), 
                                  .Q(mac_pio_intr0));
   FD1 mac_pio_intr1_FD1(.CP(clk),.D(mac_pio_interrupt1), 
                                  .Q(mac_pio_intr1));
   FD1 mac_pio_intr2_FD1(.CP(clk),.D(mac_pio_interrupt2), 
                                  .Q(mac_pio_intr2));
   FD1 mac_pio_intr3_FD1(.CP(clk),.D(mac_pio_interrupt3), 
                                  .Q(mac_pio_intr3));
   
always @ (/*AUTOSENSE*/ack_bmac2 or ack_bmac3 or ack_esr or ack_mif
	  or ack_pcs0 or ack_pcs1 or ack_pcs2 or ack_pcs3 or ack_xmac0
	  or ack_xmac1 or ack_xpcs0 or ack_xpcs1 or pio_addr
	  or pio_err_bmac2 or pio_err_bmac3 or pio_err_esr
	  or pio_err_mif or pio_err_pcs0 or pio_err_pcs1
	  or pio_err_pcs2 or pio_err_pcs3 or pio_err_xmac0
	  or pio_err_xmac1 or pio_err_xpcs0 or pio_err_xpcs1
	  or pio_sel or pio_sel_pls_d2 or rdata_bmac2 or rdata_bmac3
	  or rdata_esr or rdata_mif or rdata_pcs0 or rdata_pcs1
	  or rdata_pcs2 or rdata_pcs3 or rdata_xmac0 or rdata_xmac1
	  or rdata_xpcs0 or rdata_xpcs1 or sel_bmac2 or sel_bmac3
	  or sel_esr or sel_mif or sel_pcs0 or sel_pcs1 or sel_pcs2
	  or sel_pcs3 or sel_xmac0 or sel_xmac1 or sel_xpcs0
	  or sel_xpcs1)
begin
  if ((pio_sel) & (~pio_addr[2]))
    case ({sel_xmac0,sel_xpcs0,sel_pcs0,
           sel_xmac1,sel_xpcs1,sel_pcs1,
           sel_bmac2,sel_pcs2,
           sel_bmac3,sel_pcs3,
           sel_esr,  sel_mif})
      12'b1000_0000_0000: begin                                        
                            pio_ack         =  ack_xmac0;             
                            pio_rdata       =  rdata_xmac0;     
                            pio_err         =  pio_err_xmac0;         
                          end                                          
      12'b0100_0000_0000: begin                                        
                            pio_ack         =  ack_xpcs0;             
                            pio_rdata       =  rdata_xpcs0;     
                            pio_err         =  pio_err_xpcs0;         
                          end                                          
      12'b0010_0000_0000: begin                                         
                            pio_ack         =  ack_pcs0;             
                            pio_rdata       =  rdata_pcs0;     
                            pio_err         =  pio_err_pcs0;           
                          end                                           
      12'b0001_0000_0000: begin                                        
                            pio_ack         =  ack_xmac1;             
                            pio_rdata       =  rdata_xmac1;     
                            pio_err         =  pio_err_xmac1;         
                          end                                          
      12'b0000_1000_0000: begin                                        
                            pio_ack         =  ack_xpcs1;             
                            pio_rdata       =  rdata_xpcs1;     
                            pio_err         =  pio_err_xpcs1;         
                          end                                          
      12'b0000_0100_0000: begin                                         
                            pio_ack         =  ack_pcs1;             
                            pio_rdata       =  rdata_pcs1;     
                            pio_err         =  pio_err_pcs1;           
                          end                                           
      12'b0000_0010_0000: begin                                         
                            pio_ack         =  ack_bmac2;             
                            pio_rdata       =  rdata_bmac2;     
                            pio_err         =  pio_err_bmac2;         
                          end                                           
      12'b0000_0001_0000: begin                                         
                            pio_ack         =  ack_pcs2;              
                            pio_rdata       =  rdata_pcs2;      
                            pio_err         =  pio_err_pcs2;          
                          end                                           
      12'b0000_0000_1000: begin                                         
                            pio_ack         =  ack_bmac3;             
                            pio_rdata       =  rdata_bmac3;     
                            pio_err         =  pio_err_bmac3;         
                          end                                           
      12'b0000_0000_0100: begin                                         
                            pio_ack         =  ack_pcs3;              
                            pio_rdata       =  rdata_pcs3;      
                            pio_err         =  pio_err_pcs3;          
                          end                                           
      12'b0000_0000_0010: begin		                       
                            pio_ack         =  ack_esr;              
                            pio_rdata       =  rdata_esr;      
                            pio_err         =  pio_err_esr;          
                          end 
      12'b0000_0000_0001: begin		                       
                            pio_ack         =  ack_mif;              
                            pio_rdata       =  rdata_mif;      
                            pio_err         =  pio_err_mif;          
                          end 
      default:            begin
                            pio_ack         =  pio_sel_pls_d2;
                            pio_rdata       =  32'hdead_beef;
                            pio_err         =  pio_sel_pls_d2;
                          end 
    endcase // case({sel_xmac0,sel_xpcs0,sel_pcs0,...
   // accessing reserved upper 32 bit field.
   // write operation is silent drop without pio_err
   // read  operation rdata is always zeros.
  else if (pio_sel & pio_addr[2]) 
                          begin
                            pio_ack         =  pio_sel_pls_d2;
                            pio_rdata       =  32'b0;
                            pio_err         =  1'b0;
                          end 
  else                    begin
                            pio_ack         =  1'b0;
                            pio_rdata       =  32'hdead_beef;
                            pio_err         =  1'b0;
                          end 
end // always @ (...
   
    
RegDff #(64) mac_pio_rdata_RegDff(.din({32'b0,pio_rdata[31:0]}),
                                  .clk(clk),   
                                  .qout(mac_pio_rdata[63:0])); 
   
FD1          mac_pio_err_FD1(.CP(clk),.D(pio_err), 
                             .Q(mac_pio_err));

FD1          mac_pio_ack_FD1(.CP(clk),.D(pio_ack), 
                             .Q(mac_pio_ack));


// debug
   reg  [31:0] mac_debug_port;
   
always @ (/*AUTOSENSE*/esrctl_debug or mac_debug_sel0 or xmac_debug0
	  or xmac_debug1 or xpcs_debug0 or xpcs_debug1)
 case (mac_debug_sel0)  // synopsys parallel_case full_case infer_mux
   3'h0:     mac_debug_port = xmac_debug0;
   3'h1:     mac_debug_port = xpcs_debug0;
   3'h2:     mac_debug_port = xmac_debug1;
   3'h3:     mac_debug_port = xpcs_debug1;
   3'h4:     mac_debug_port = esrctl_debug;
   default:  mac_debug_port = xmac_debug0;
 endcase // casex(mac_debug_sel)
   
   
endmodule // mac_pio_intf
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: mac_pio_intf.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/%W% %G%/
	36
	37	/*************************************************************************
	38	*
	39	* File Name : mac_pio_intf.v
	40	* Author Name : John Lo
	41	* Description : It contains mac pio interface mux and demux logic.
	42	* Parent Module: mac
	43	* Child Module:
	44	* Interface Mod: many.
	45	* Date Created : 1/31/02
	46	*
	47	* Copyright (c) 2020, Sun Microsystems, Inc.
	48	* Sun Proprietary and Confidential
	49	*
	50	* Modification : 4/1/2004 -by John Lo
	51	* 1. Changed address bus width from
	52	* 16 bits to 19 bits for pio_clients_addr.
	53	* 2. Support both 32 bit and 64 bit addressing.
	54	* 3. Changed PIO read/write data bus from
	55	* 32 bits to 64 bits.
	56	* The MSB 32 bits are "0".
	57	*
	58	* Synthesis Notes:
	59	*
	60	*************************************************************************/
	61
	62	module mac_pio_intf (
	63	clk,
	64	niu_reset_l,
65	// global broadcast signals
66	pio_clients_addr,
67	pio_clients_rd,
68	pio_clients_wdata,
69	// designated signals
70	pio_mac_sel,
71	mac_pio_ack,
72	mac_pio_rdata,
73	// individual internal inputs
74	// port 0
75	pio_err_xmac0,
76	ack_xmac0,
77	rdata_xmac0,
78	pio_err_xpcs0,
79	ack_xpcs0,
80	rdata_xpcs0,
81	pio_err_pcs0,
82	ack_pcs0,
83	rdata_pcs0,
84	// port 1
85	pio_err_xmac1,
86	ack_xmac1,
87	rdata_xmac1,
88	pio_err_xpcs1,
89	ack_xpcs1,
90	rdata_xpcs1,
91	pio_err_pcs1,
92	ack_pcs1,
93	rdata_pcs1,
94	// port 2
95	pio_err_bmac2,
96	ack_bmac2,
97	rdata_bmac2,
98	pio_err_pcs2,
99	ack_pcs2,
100	rdata_pcs2,
101	// port 3
102	pio_err_bmac3,
103	ack_bmac3,
104	rdata_bmac3,
105	pio_err_pcs3,
106	ack_pcs3,
107	rdata_pcs3,
108	// esr
109	pio_err_esr,
110	ack_esr,
111	rdata_esr,
112	// mif
113	pio_err_mif,
114	ack_mif,
115	rdata_mif,
116	// port 0 interrupts
117	txmac_interrupt0,
118	rxmac_interrupt0,
119	xmac_fc_interrupt0,
120	xpcs_interrupt0,
121	pcs_int0, // pcs link down interrupt, secondary interrupt
122	// port 1 interrupts
123	txmac_interrupt1,
124	rxmac_interrupt1,
125	xmac_fc_interrupt1,
126	xpcs_interrupt1,
127	pcs_int1, // pcs link down interrupt, secondary interrupt
128	// port 2 interrupts
129	bm_tx_interrupt2,
130	bm_rx_interrupt2,
131	bm_control_interrupt2,
132	pcs_int2, // pcs link down interrupt, secondary interrupt
133	// port 3 interrupts
134	bm_tx_interrupt3,
135	bm_rx_interrupt3,
136	bm_control_interrupt3,
137	pcs_int3, // pcs link down interrupt, secondary interrupt
138	//
139	xmac_debug0,
140	xpcs_debug0,
141	mac_debug_sel0,
142	xmac_debug1,
143	xpcs_debug1,
144	esrctl_debug,
145	// outputs
146	reset,
147	mac_debug_port,
148	sel_xmac0,
149	sel_xpcs0,
150	sel_pcs0 ,
151	sel_xmac1,
152	sel_xpcs1,
153	sel_pcs1 ,
154	sel_bmac2,
155	sel_pcs2 ,
156	sel_bmac3,
157	sel_pcs3 ,
158	sel_esr,
159	sel_mif,
160	pio_addr,
161	pio_rd,
162	pio_wdata,
163	mac_pio_intr0,// port 0 interrupt
164	mac_pio_intr1,// port 1 interrupt
165	mac_pio_intr2,// port 2 interrupt
166	mac_pio_intr3,// port 3 interrupt
167	mac_pio_err
168	);
169
170	input clk;
171	input niu_reset_l;
172	// global broadcast signals
173	input [19:0] pio_clients_addr;
174	input pio_clients_rd;
175	input [31:0] pio_clients_wdata;
176	// designated signals
177	input pio_mac_sel;
178	output mac_pio_ack;
179	output [63:0] mac_pio_rdata;
180	// individual internal inputs
181	// port 0
182	input pio_err_xmac0;
183	input ack_xmac0;
184	input [31:0] rdata_xmac0;
185	input pio_err_xpcs0;
186	input ack_xpcs0;
187	input [31:0] rdata_xpcs0;
188	input pio_err_pcs0;
189	input ack_pcs0;
190	input [31:0] rdata_pcs0;
191	// port 1
192	input pio_err_xmac1;
193	input ack_xmac1;
194	input [31:0] rdata_xmac1;
195	input pio_err_xpcs1;
196	input ack_xpcs1;
197	input [31:0] rdata_xpcs1;
198	input pio_err_pcs1;
199	input ack_pcs1;
200	input [31:0] rdata_pcs1;
201	// port 2
202	input pio_err_bmac2;
203	input ack_bmac2;
204	input [31:0] rdata_bmac2;
205	input pio_err_pcs2;
206	input ack_pcs2;
207	input [31:0] rdata_pcs2;
208	// port 3
209	input pio_err_bmac3;
210	input ack_bmac3;
211	input [31:0] rdata_bmac3;
212	input pio_err_pcs3;
213	input ack_pcs3;
214	input [31:0] rdata_pcs3;
215	// esr
216	input pio_err_esr;
217	input ack_esr;
218	input [31:0] rdata_esr;
219	// mif
220	input pio_err_mif;
221	input ack_mif;
222	input [31:0] rdata_mif;
223	// port 0 interrupts
224	input txmac_interrupt0;
225	input rxmac_interrupt0;
226	input xmac_fc_interrupt0;
227	input xpcs_interrupt0;
228	input pcs_int0; // pcs link down interrupt, secondary interrupt
229	// port 1 interrupts
230	input txmac_interrupt1;
231	input rxmac_interrupt1;
232	input xmac_fc_interrupt1;
233	input xpcs_interrupt1;
234	input pcs_int1; // pcs link down interrupt, secondary interrupt
235	// port 2 interrupts
236	input bm_tx_interrupt2;
237	input bm_rx_interrupt2;
238	input bm_control_interrupt2;
239	input pcs_int2; // pcs link down interrupt, secondary interrupt
240	// port 3 interrupts
241	input bm_tx_interrupt3;
242	input bm_rx_interrupt3;
243	input bm_control_interrupt3;
244	input pcs_int3; // pcs link down interrupt, secondary interrupt
245	//
246	input [31:0] xmac_debug0;
247	input [31:0] xpcs_debug0;
248	input [2:0] mac_debug_sel0;
249	input [31:0] xmac_debug1;
250	input [31:0] xpcs_debug1;
251	input [31:0] esrctl_debug;
252	// outputs
253	output reset;
254	output [31:0] mac_debug_port;
255	output sel_xmac0;
256	output sel_xpcs0;
257	output sel_pcs0 ;
258	output sel_xmac1;
259	output sel_xpcs1;
260	output sel_pcs1 ;
261	output sel_bmac2;
262	output sel_pcs2 ;
263	output sel_bmac3;
264	output sel_pcs3 ;
265	output sel_esr;
266	output sel_mif;
267	output [16:0] pio_addr;
268	output pio_rd;
269	output [31:0] pio_wdata;
270	output mac_pio_intr0;// port 0 interrupt
271	output mac_pio_intr1;// port 1 interrupt
272	output mac_pio_intr2;// port 2 interrupt
273	output mac_pio_intr3;// port 3 interrupt
274	output mac_pio_err;
275
276	// xmac address range: [8:0] x2 -> reserve 1 bit -> 10
277	// big_mac address range: [8:0] x2 ->
278	// xpcs address range: [6:0] x2 ->
279	// pcs address range: [6:0] x4 ->
280	// ---------------------------------
281	// total address range:
282	// 8K is enough
283	wire niu_reset_l;
284	wire reset;
285	wire reset_l;
286	reg pio_ack;
287	reg [31:0] pio_rdata;
288	reg pio_err;
289	wire pio_sel;
290	wire pio_sel_pls;
291	wire pio_sel_pls_d1;
292	wire pio_sel_pls_d2;
293	wire [16:0] pio_addr;
294	wire pio_rd;
295	wire [31:0] pio_wdata;
296	// pio global signals
297
298	wire [19:0] pio_clients_addr;
299	wire [31:0] pio_clients_wdata;
300	wire pio_clients_rd;
301	// designated signals
302	wire pio_mac_sel;
303	wire mac_pio_ack;
304	wire [63:0] mac_pio_rdata;
305	wire mac_pio_err;
306	// individual internal wire
307	wire [31:0] rdata_xmac0;
308	wire [31:0] rdata_xpcs0;
309	wire [31:0] rdata_pcs0;
310	wire [31:0] rdata_xmac1;
311	wire [31:0] rdata_xpcs1;
312	wire [31:0] rdata_pcs1;
313	wire [31:0] rdata_bmac2;
314	wire [31:0] rdata_pcs2;
315	wire [31:0] rdata_bmac3;
316	wire [31:0] rdata_pcs3;
317	wire [31:0] rdata_esr;
318	wire [31:0] rdata_mif;
319	wire [31:0] xmac_debug0;
320	wire [31:0] xpcs_debug0;
321	wire [2:0] mac_debug_sel0;
322	wire [31:0] xmac_debug1;
323	wire [31:0] xpcs_debug1;
324
325
326	// register the input signals:
327	// vlint flag_dangling_net_within_module off
328	// vlint flag_net_has_no_load off
329	wire [19:0] pio_clients_addr_64bit;
330	// vlint flag_net_has_no_load on
331	// vlint flag_dangling_net_within_module on
332
333	SYNC_CELL reset_SYNC_CELL(.D(niu_reset_l),.CP(clk),.Q(reset_l));
334
335	assign reset = ~reset_l;
336
337	RegDff #(1) pio_sel_RegDff(
338	.din(pio_mac_sel),
339	.clk(clk),
340	.qout(pio_sel));
341
342	pls_gen pio_sel_pls_gen(.clk(clk),.in(pio_sel),.out(pio_sel_pls));
343
344	RegDff #(1) pio_sel_pls_d1_RegDff(.din(pio_sel_pls),.clk(clk),.qout(pio_sel_pls_d1));
345	RegDff #(1) pio_sel_pls_d2_RegDff(.din(pio_sel_pls_d1),.clk(clk),.qout(pio_sel_pls_d2));
346
347	RegDff #(20) pio_clients_addr_64bit_RegDff(
348	.din(pio_clients_addr[19:0]),
349	.clk(clk),
350	.qout(pio_clients_addr_64bit[19:0]));
351
352	assign pio_addr[16:0] = pio_clients_addr_64bit[16:0];
353
354	RegDff #(1) pio_rd_RegDff(
355	.din(pio_clients_rd),
356	.clk(clk),
357	.qout(pio_rd));
358
359	RegDff #(32) pio_wdata_RegDff(
360	.din(pio_clients_wdata[31:0]),
361	.clk(clk),
362	.qout(pio_wdata[31:0]));
363
364	wire sel_xmac0 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XMAC0_ADDR_OFFSET);
365	wire sel_xpcs0 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XPCS0_ADDR_OFFSET);
366	wire sel_pcs0 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS0_ADDR_OFFSET);
367	wire sel_xmac1 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XMAC1_ADDR_OFFSET);
368	wire sel_xpcs1 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `XPCS1_ADDR_OFFSET);
369	wire sel_pcs1 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS1_ADDR_OFFSET);
370	wire sel_bmac2 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `BMAC2_ADDR_OFFSET);
371	wire sel_pcs2 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS2_ADDR_OFFSET);
372	wire sel_bmac3 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `BMAC3_ADDR_OFFSET);
373	wire sel_pcs3 = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `PCS3_ADDR_OFFSET);
374	wire sel_esr = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `ESR_ADDR_OFFSET);
375	wire sel_mif = pio_sel & (~pio_addr[2]) & (pio_addr[16:13] == `MIF_ADDR_OFFSET);
376
377	wire mac_pio_interrupt0= txmac_interrupt0 \|
378	rxmac_interrupt0 \|
379	xmac_fc_interrupt0 \|
380	xpcs_interrupt0 \|
381	pcs_int0 ;
382
383	wire mac_pio_interrupt1= txmac_interrupt1 \|
384	rxmac_interrupt1 \|
385	xmac_fc_interrupt1 \|
386	xpcs_interrupt1 \|
387	pcs_int1 ;
388
389	wire mac_pio_interrupt2= bm_tx_interrupt2 \|
390	bm_rx_interrupt2 \|
391	bm_control_interrupt2 \|
392	pcs_int2;
393
394	wire mac_pio_interrupt3= bm_tx_interrupt3 \|
395	bm_rx_interrupt3 \|
396	bm_control_interrupt3 \|
397	pcs_int3;
398
399	FD1 mac_pio_intr0_FD1(.CP(clk),.D(mac_pio_interrupt0),
400	.Q(mac_pio_intr0));
401	FD1 mac_pio_intr1_FD1(.CP(clk),.D(mac_pio_interrupt1),
402	.Q(mac_pio_intr1));
403	FD1 mac_pio_intr2_FD1(.CP(clk),.D(mac_pio_interrupt2),
404	.Q(mac_pio_intr2));
405	FD1 mac_pio_intr3_FD1(.CP(clk),.D(mac_pio_interrupt3),
406	.Q(mac_pio_intr3));
407
408	always @ (/AUTOSENSE/ack_bmac2 or ack_bmac3 or ack_esr or ack_mif
409	or ack_pcs0 or ack_pcs1 or ack_pcs2 or ack_pcs3 or ack_xmac0
410	or ack_xmac1 or ack_xpcs0 or ack_xpcs1 or pio_addr
411	or pio_err_bmac2 or pio_err_bmac3 or pio_err_esr
412	or pio_err_mif or pio_err_pcs0 or pio_err_pcs1
413	or pio_err_pcs2 or pio_err_pcs3 or pio_err_xmac0
414	or pio_err_xmac1 or pio_err_xpcs0 or pio_err_xpcs1
415	or pio_sel or pio_sel_pls_d2 or rdata_bmac2 or rdata_bmac3
416	or rdata_esr or rdata_mif or rdata_pcs0 or rdata_pcs1
417	or rdata_pcs2 or rdata_pcs3 or rdata_xmac0 or rdata_xmac1
418	or rdata_xpcs0 or rdata_xpcs1 or sel_bmac2 or sel_bmac3
419	or sel_esr or sel_mif or sel_pcs0 or sel_pcs1 or sel_pcs2
420	or sel_pcs3 or sel_xmac0 or sel_xmac1 or sel_xpcs0
421	or sel_xpcs1)
422	begin
423	if ((pio_sel) & (~pio_addr[2]))
424	case ({sel_xmac0,sel_xpcs0,sel_pcs0,
425	sel_xmac1,sel_xpcs1,sel_pcs1,
426	sel_bmac2,sel_pcs2,
427	sel_bmac3,sel_pcs3,
428	sel_esr, sel_mif})
429	12'b1000_0000_0000: begin
430	pio_ack = ack_xmac0;
431	pio_rdata = rdata_xmac0;
432	pio_err = pio_err_xmac0;
433	end
434	12'b0100_0000_0000: begin
435	pio_ack = ack_xpcs0;
436	pio_rdata = rdata_xpcs0;
437	pio_err = pio_err_xpcs0;
438	end
439	12'b0010_0000_0000: begin
440	pio_ack = ack_pcs0;
441	pio_rdata = rdata_pcs0;
442	pio_err = pio_err_pcs0;
443	end
444	12'b0001_0000_0000: begin
445	pio_ack = ack_xmac1;
446	pio_rdata = rdata_xmac1;
447	pio_err = pio_err_xmac1;
448	end
449	12'b0000_1000_0000: begin
450	pio_ack = ack_xpcs1;
451	pio_rdata = rdata_xpcs1;
452	pio_err = pio_err_xpcs1;
453	end
454	12'b0000_0100_0000: begin
455	pio_ack = ack_pcs1;
456	pio_rdata = rdata_pcs1;
457	pio_err = pio_err_pcs1;
458	end
459	12'b0000_0010_0000: begin
460	pio_ack = ack_bmac2;
461	pio_rdata = rdata_bmac2;
462	pio_err = pio_err_bmac2;
463	end
464	12'b0000_0001_0000: begin
465	pio_ack = ack_pcs2;
466	pio_rdata = rdata_pcs2;
467	pio_err = pio_err_pcs2;
468	end
469	12'b0000_0000_1000: begin
470	pio_ack = ack_bmac3;
471	pio_rdata = rdata_bmac3;
472	pio_err = pio_err_bmac3;
473	end
474	12'b0000_0000_0100: begin
475	pio_ack = ack_pcs3;
476	pio_rdata = rdata_pcs3;
477	pio_err = pio_err_pcs3;
478	end
479	12'b0000_0000_0010: begin
480	pio_ack = ack_esr;
481	pio_rdata = rdata_esr;
482	pio_err = pio_err_esr;
483	end
484	12'b0000_0000_0001: begin
485	pio_ack = ack_mif;
486	pio_rdata = rdata_mif;
487	pio_err = pio_err_mif;
488	end
489	default: begin
490	pio_ack = pio_sel_pls_d2;
491	pio_rdata = 32'hdead_beef;
492	pio_err = pio_sel_pls_d2;
493	end
494	endcase // case({sel_xmac0,sel_xpcs0,sel_pcs0,...
495	// accessing reserved upper 32 bit field.
496	// write operation is silent drop without pio_err
497	// read operation rdata is always zeros.
498	else if (pio_sel & pio_addr[2])
499	begin
500	pio_ack = pio_sel_pls_d2;
501	pio_rdata = 32'b0;
502	pio_err = 1'b0;
503	end
504	else begin
505	pio_ack = 1'b0;
506	pio_rdata = 32'hdead_beef;
507	pio_err = 1'b0;
508	end
509	end // always @ (...
510
511
512	RegDff #(64) mac_pio_rdata_RegDff(.din({32'b0,pio_rdata[31:0]}),
513	.clk(clk),
514	.qout(mac_pio_rdata[63:0]));
515
516	FD1 mac_pio_err_FD1(.CP(clk),.D(pio_err),
517	.Q(mac_pio_err));
518
519	FD1 mac_pio_ack_FD1(.CP(clk),.D(pio_ack),
520	.Q(mac_pio_ack));
521
522
523	// debug
524	reg [31:0] mac_debug_port;
525
526	always @ (/AUTOSENSE/esrctl_debug or mac_debug_sel0 or xmac_debug0
527	or xmac_debug1 or xpcs_debug0 or xpcs_debug1)
528	case (mac_debug_sel0) // synopsys parallel_case full_case infer_mux
529	3'h0: mac_debug_port = xmac_debug0;
530	3'h1: mac_debug_port = xpcs_debug0;
531	3'h2: mac_debug_port = xmac_debug1;
532	3'h3: mac_debug_port = xpcs_debug1;
533	3'h4: mac_debug_port = esrctl_debug;
534	default: mac_debug_port = xmac_debug0;
535	endcase // casex(mac_debug_sel)
536
537
538	endmodule // mac_pio_intf
539
540