Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / mgrlm_sm.v
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2//
3// OpenSPARC T2 Processor File: mgrlm_sm.v
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35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : mgrlm_sm
40 * Author Name : John Lo
41 * Description :
42 * Parent Module: rx_mii_gmii
43 * Child Module:
44 * Interface Mod:
45 * Date Created : 10/4/00
46 *
47 * Copyright (c) 2002, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 *************************************************************************/
55
56module mgrlm_sm (
57 rx_nbclk,
58 rx_reset_nbclk,
59 rx_enable_nbclk,
60 rx_det_sfd, // ipg_done and rx_det_S are level signals.
61 rx_det_eop_lv, // rx_det_sfd is level signals.
62 rx_heart_beat,
63 rxfifo_full_nbclk,
64// outputs
65 load_ok_state,
66 adjust_rx_heart_beat, // should be a pulse
67 mgrlm_state
68 );
69 input rx_nbclk;
70 input rx_reset_nbclk;
71 input rx_enable_nbclk;
72 input rx_det_sfd;
73 input rx_det_eop_lv;
74 input rx_heart_beat;
75 input rxfifo_full_nbclk;
76 output load_ok_state;
77 output adjust_rx_heart_beat; // should be a pulse
78 output mgrlm_state;
79
80 reg adjust_rx_heart_beat;
81 reg nx_mgrlm_state;
82 wire mgrlm_state;
83 wire load_ok_state;
84
85 parameter IDLE = 1'b0,
86 PAYLOAD = 1'b1;
87
88 assign load_ok_state = (mgrlm_state == PAYLOAD);
89
90// comb part
91always @ (mgrlm_state or rx_det_sfd or rx_enable_nbclk or
92 rxfifo_full_nbclk or rx_det_eop_lv or rx_heart_beat)
93 begin
94 nx_mgrlm_state = IDLE;
95 adjust_rx_heart_beat = 0; // should be a pulse
96
97 casex(mgrlm_state)
98 IDLE: if (rx_det_sfd & rx_enable_nbclk & (~rxfifo_full_nbclk))
99 begin
100 nx_mgrlm_state = PAYLOAD;
101 adjust_rx_heart_beat = 1;
102 end
103 else nx_mgrlm_state = mgrlm_state; // stay
104
105 PAYLOAD: if ((rx_det_eop_lv & rx_heart_beat) | rxfifo_full_nbclk)
106 nx_mgrlm_state = IDLE;
107 else nx_mgrlm_state = mgrlm_state; // stay
108 endcase // casex(mgrlm_state)
109 end
110
111// seq part
112RegRst #(1) mgrlm_state_RegRst(.clk(rx_nbclk),
113 .reset(rx_reset_nbclk),
114 .din(nx_mgrlm_state),
115 .qout(mgrlm_state));
116
117endmodule // mgrlm_sm