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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_txd_blatch.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /***************************************************************** | |
38 | * | |
39 | * File Name : n2_txd_blatch.v | |
40 | * Author Name : John Lo | |
41 | * Description : This is n2 specific. To latch the outgoing | |
42 | * transmit side data to serdes to help on fixing | |
43 | * the hold time issue. | |
44 | * | |
45 | * Parent Module: sphy_dpath2 | |
46 | * Child Module: | |
47 | * Interface Mod: | |
48 | * Date Created : 8/29/05 | |
49 | * | |
50 | * Design Notes: | |
51 | * | |
52 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
53 | * Sun Proprietary and Confidential | |
54 | * | |
55 | ||
56 | * Synthesis Notes: | |
57 | * | |
58 | * | |
59 | ****************************************************************/ | |
60 | ||
61 | module n2_txd_blatch ( /*AUTOARG*/ | |
62 | // Outputs | |
63 | xtx_code_group_reg_latch, tx_code_group_latch, | |
64 | // Inputs | |
65 | tx_nbclk, tx_clk_312mhz, xtx_code_group_reg, tx_code_group | |
66 | ); | |
67 | ||
68 | input tx_nbclk; | |
69 | input tx_clk_312mhz; | |
70 | input [39:0] xtx_code_group_reg; | |
71 | input [9:0] tx_code_group; | |
72 | output [39:0] xtx_code_group_reg_latch; | |
73 | output [9:0] tx_code_group_latch; | |
74 | ||
75 | ||
76 | // vlint flag_unmatched_port_connect_in_inst off | |
77 | // vlint flag_null_instance_port off | |
78 | // xpcs | |
79 | cl_a1_blatch_4x xtx_blatch_39 ( .latout(xtx_code_group_reg_latch[39]), .so(), .d(xtx_code_group_reg[39]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
80 | cl_a1_blatch_4x xtx_blatch_38 ( .latout(xtx_code_group_reg_latch[38]), .so(), .d(xtx_code_group_reg[38]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
81 | cl_a1_blatch_4x xtx_blatch_37 ( .latout(xtx_code_group_reg_latch[37]), .so(), .d(xtx_code_group_reg[37]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
82 | cl_a1_blatch_4x xtx_blatch_36 ( .latout(xtx_code_group_reg_latch[36]), .so(), .d(xtx_code_group_reg[36]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
83 | cl_a1_blatch_4x xtx_blatch_35 ( .latout(xtx_code_group_reg_latch[35]), .so(), .d(xtx_code_group_reg[35]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
84 | cl_a1_blatch_4x xtx_blatch_34 ( .latout(xtx_code_group_reg_latch[34]), .so(), .d(xtx_code_group_reg[34]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
85 | cl_a1_blatch_4x xtx_blatch_33 ( .latout(xtx_code_group_reg_latch[33]), .so(), .d(xtx_code_group_reg[33]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
86 | cl_a1_blatch_4x xtx_blatch_32 ( .latout(xtx_code_group_reg_latch[32]), .so(), .d(xtx_code_group_reg[32]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
87 | cl_a1_blatch_4x xtx_blatch_31 ( .latout(xtx_code_group_reg_latch[31]), .so(), .d(xtx_code_group_reg[31]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
88 | cl_a1_blatch_4x xtx_blatch_30 ( .latout(xtx_code_group_reg_latch[30]), .so(), .d(xtx_code_group_reg[30]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
89 | cl_a1_blatch_4x xtx_blatch_29 ( .latout(xtx_code_group_reg_latch[29]), .so(), .d(xtx_code_group_reg[29]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
90 | cl_a1_blatch_4x xtx_blatch_28 ( .latout(xtx_code_group_reg_latch[28]), .so(), .d(xtx_code_group_reg[28]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
91 | cl_a1_blatch_4x xtx_blatch_27 ( .latout(xtx_code_group_reg_latch[27]), .so(), .d(xtx_code_group_reg[27]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
92 | cl_a1_blatch_4x xtx_blatch_26 ( .latout(xtx_code_group_reg_latch[26]), .so(), .d(xtx_code_group_reg[26]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
93 | cl_a1_blatch_4x xtx_blatch_25 ( .latout(xtx_code_group_reg_latch[25]), .so(), .d(xtx_code_group_reg[25]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
94 | cl_a1_blatch_4x xtx_blatch_24 ( .latout(xtx_code_group_reg_latch[24]), .so(), .d(xtx_code_group_reg[24]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
95 | cl_a1_blatch_4x xtx_blatch_23 ( .latout(xtx_code_group_reg_latch[23]), .so(), .d(xtx_code_group_reg[23]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
96 | cl_a1_blatch_4x xtx_blatch_22 ( .latout(xtx_code_group_reg_latch[22]), .so(), .d(xtx_code_group_reg[22]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
97 | cl_a1_blatch_4x xtx_blatch_21 ( .latout(xtx_code_group_reg_latch[21]), .so(), .d(xtx_code_group_reg[21]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
98 | cl_a1_blatch_4x xtx_blatch_20 ( .latout(xtx_code_group_reg_latch[20]), .so(), .d(xtx_code_group_reg[20]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
99 | cl_a1_blatch_4x xtx_blatch_19 ( .latout(xtx_code_group_reg_latch[19]), .so(), .d(xtx_code_group_reg[19]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
100 | cl_a1_blatch_4x xtx_blatch_18 ( .latout(xtx_code_group_reg_latch[18]), .so(), .d(xtx_code_group_reg[18]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
101 | cl_a1_blatch_4x xtx_blatch_17 ( .latout(xtx_code_group_reg_latch[17]), .so(), .d(xtx_code_group_reg[17]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
102 | cl_a1_blatch_4x xtx_blatch_16 ( .latout(xtx_code_group_reg_latch[16]), .so(), .d(xtx_code_group_reg[16]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
103 | cl_a1_blatch_4x xtx_blatch_15 ( .latout(xtx_code_group_reg_latch[15]), .so(), .d(xtx_code_group_reg[15]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
104 | cl_a1_blatch_4x xtx_blatch_14 ( .latout(xtx_code_group_reg_latch[14]), .so(), .d(xtx_code_group_reg[14]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
105 | cl_a1_blatch_4x xtx_blatch_13 ( .latout(xtx_code_group_reg_latch[13]), .so(), .d(xtx_code_group_reg[13]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
106 | cl_a1_blatch_4x xtx_blatch_12 ( .latout(xtx_code_group_reg_latch[12]), .so(), .d(xtx_code_group_reg[12]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
107 | cl_a1_blatch_4x xtx_blatch_11 ( .latout(xtx_code_group_reg_latch[11]), .so(), .d(xtx_code_group_reg[11]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
108 | cl_a1_blatch_4x xtx_blatch_10 ( .latout(xtx_code_group_reg_latch[10]), .so(), .d(xtx_code_group_reg[10]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
109 | cl_a1_blatch_4x xtx_blatch_9 ( .latout(xtx_code_group_reg_latch[9 ]), .so(), .d(xtx_code_group_reg[9 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
110 | cl_a1_blatch_4x xtx_blatch_8 ( .latout(xtx_code_group_reg_latch[8 ]), .so(), .d(xtx_code_group_reg[8 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
111 | cl_a1_blatch_4x xtx_blatch_7 ( .latout(xtx_code_group_reg_latch[7 ]), .so(), .d(xtx_code_group_reg[7 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
112 | cl_a1_blatch_4x xtx_blatch_6 ( .latout(xtx_code_group_reg_latch[6 ]), .so(), .d(xtx_code_group_reg[6 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
113 | cl_a1_blatch_4x xtx_blatch_5 ( .latout(xtx_code_group_reg_latch[5 ]), .so(), .d(xtx_code_group_reg[5 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
114 | cl_a1_blatch_4x xtx_blatch_4 ( .latout(xtx_code_group_reg_latch[4 ]), .so(), .d(xtx_code_group_reg[4 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
115 | cl_a1_blatch_4x xtx_blatch_3 ( .latout(xtx_code_group_reg_latch[3 ]), .so(), .d(xtx_code_group_reg[3 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
116 | cl_a1_blatch_4x xtx_blatch_2 ( .latout(xtx_code_group_reg_latch[2 ]), .so(), .d(xtx_code_group_reg[2 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
117 | cl_a1_blatch_4x xtx_blatch_1 ( .latout(xtx_code_group_reg_latch[1 ]), .so(), .d(xtx_code_group_reg[1 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
118 | cl_a1_blatch_4x xtx_blatch_0 ( .latout(xtx_code_group_reg_latch[0 ]), .so(), .d(xtx_code_group_reg[0 ]), .l1clk(tx_clk_312mhz), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
119 | ||
120 | // pcs | |
121 | cl_a1_blatch_4x tx_blatch_9 ( .latout( tx_code_group_latch[9 ]), .so(), .d(tx_code_group[9 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
122 | cl_a1_blatch_4x tx_blatch_8 ( .latout( tx_code_group_latch[8 ]), .so(), .d(tx_code_group[8 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
123 | cl_a1_blatch_4x tx_blatch_7 ( .latout( tx_code_group_latch[7 ]), .so(), .d(tx_code_group[7 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
124 | cl_a1_blatch_4x tx_blatch_6 ( .latout( tx_code_group_latch[6 ]), .so(), .d(tx_code_group[6 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
125 | cl_a1_blatch_4x tx_blatch_5 ( .latout( tx_code_group_latch[5 ]), .so(), .d(tx_code_group[5 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
126 | cl_a1_blatch_4x tx_blatch_4 ( .latout( tx_code_group_latch[4 ]), .so(), .d(tx_code_group[4 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
127 | cl_a1_blatch_4x tx_blatch_3 ( .latout( tx_code_group_latch[3 ]), .so(), .d(tx_code_group[3 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
128 | cl_a1_blatch_4x tx_blatch_2 ( .latout( tx_code_group_latch[2 ]), .so(), .d(tx_code_group[2 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
129 | cl_a1_blatch_4x tx_blatch_1 ( .latout( tx_code_group_latch[1 ]), .so(), .d(tx_code_group[1 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
130 | cl_a1_blatch_4x tx_blatch_0 ( .latout( tx_code_group_latch[0 ]), .so(), .d(tx_code_group[0 ]), .l1clk(tx_nbclk), .si(1'b0), .siclk(1'b0), .soclk(1'b0)); | |
131 | ||
132 | // vlint flag_null_instance_port on | |
133 | // vlint flag_unmatched_port_connect_in_inst on | |
134 | ||
135 | endmodule // n2_txd_blatch | |
136 |