Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_cam_128x200.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_cam_128x200.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
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13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
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34// ========== Copyright Header End ============================================
35
36/**********************************************************
37***********************************************************
38
39 Project : Niu
40
41 File name : niu_cam_128x200.v
42
43 Module(s) name : niu_cam_128x200
44
45 Parent modules : niu_rxc
46
47 Child modules : n2_niu_tc_128x200s_cust
48
49 Author's name : George Chu
50
51 Date : April. 2004
52
53 Description :
54
55 Synthesis Notes:
56
57 Modification History:
58 Date Description
59 ---- -----------
60
61************************************************************
62***********************************************************/
63
64`timescale 1ns/10ps
65
66module niu_cam_128x200 (
67 tcu_aclk,
68 tcu_bclk,
69 tcu_se_scancollar_in,
70 tcu_se_scancollar_out,
71 tcu_array_wr_inhibit,
72 scan_in,
73 scan_out,
74 clk,
75 mbi_wdata,
76 mbi_rw_adr,
77 mbi_pio_sel,
78 mbi_wr_en,
79 mbi_rd_en,
80 mbi_compare,
81 mbi_run,
82 data_inp,
83 cam_compare,
84 pio_wt,
85 pio_rd,
86 pio_sel,
87 cam_index,
88 reset,
89 cam_valid,
90 cam_hit,
91 cam_haddr,
92 pio_rd_vld,
93 msk_dat_out
94 );
95
96parameter DATA_WIDTH_MINUS1 = 199;
97parameter ADDR_WIDTH_MINUS1 = 6;
98
99input tcu_aclk;
100input tcu_bclk;
101input tcu_se_scancollar_in;
102input tcu_se_scancollar_out;
103input tcu_array_wr_inhibit;
104input scan_in;
105output scan_out;
106
107input clk;
108
109input [DATA_WIDTH_MINUS1:0] mbi_wdata;
110input [ADDR_WIDTH_MINUS1:0] mbi_rw_adr;
111input mbi_pio_sel;
112input mbi_wr_en;
113input mbi_rd_en;
114input mbi_compare;
115input mbi_run;
116
117input [DATA_WIDTH_MINUS1:0] data_inp;
118input cam_compare;
119input pio_wt;
120input pio_rd;
121input pio_sel;
122input [ADDR_WIDTH_MINUS1:0] cam_index;
123input reset;
124output cam_valid;
125output cam_hit;
126output [ADDR_WIDTH_MINUS1:0] cam_haddr;
127output pio_rd_vld;
128output [DATA_WIDTH_MINUS1:0] msk_dat_out;
129
130wire cam_valid;
131wire cam_hit;
132wire [ADDR_WIDTH_MINUS1:0] cam_haddr;
133wire pio_rd_vld;
134wire [DATA_WIDTH_MINUS1:0] msk_dat_out;
135wire scan_out;
136
137wire mux_pio_sel;
138wire mux_wr_en;
139wire [ADDR_WIDTH_MINUS1:0] mux_rw_adr;
140wire mux_rd_en;
141wire [DATA_WIDTH_MINUS1:0] mux_wdata;
142wire mux_compare;
143
144 assign mux_wdata = mbi_run ? mbi_wdata : data_inp;
145 assign mux_rw_adr = mbi_run ? mbi_rw_adr : cam_index;
146 assign mux_pio_sel= mbi_run ? mbi_pio_sel: pio_sel;
147 assign mux_wr_en = mbi_run ? mbi_wr_en : pio_wt;
148 assign mux_rd_en = mbi_run ? mbi_rd_en : pio_rd;
149 assign mux_compare= mbi_run ? mbi_compare: cam_compare;
150
151 n2_niu_tc_128x200s_cust cam_128x200_0 (
152 .data_inp (mux_wdata),
153 .cam_compare (mux_compare),
154 .pio_wt (mux_wr_en),
155 .pio_rd (mux_rd_en),
156 .pio_sel (mux_pio_sel),
157 .cam_index (mux_rw_adr[6:0]),
158 .reset (reset),
159 .clk (clk),
160 .tcu_se_scancollar_in (tcu_se_scancollar_in),
161 .tcu_se_scancollar_out (tcu_se_scancollar_out),
162 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
163 .tcu_aclk (tcu_aclk),
164 .tcu_bclk (tcu_bclk),
165 .tcu_pce_ov (1'h1),
166 .pce (1'h1),
167 .scan_in (scan_in),
168 .scan_out (scan_out),
169 .cam_valid (cam_valid),
170 .cam_hit (cam_hit),
171 .cam_haddr (cam_haddr[6:0]),
172 .pio_rd_vld (pio_rd_vld),
173 .msk_dat_out (msk_dat_out[199:0])
174 );
175
176endmodule