projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_dmc_cache_dataFetch.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_dmc_cache_dataFetch.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*********************************************************************
36 *
37 *
38 * Orignal Author(s): Arvind Srinivasan
39 * Modifier(s):
40 * Project(s): Neptune
41 *
42 * Copyright (c) 2004 Sun Microsystems, Inc.
43 *
44 * All Rights Reserved.
45 *
46 * This verilog model is the confidential and proprietary property of
47 * Sun Microsystems, Inc., and the possession or use of this model
48 * requires a written license from Sun Microsystems, Inc.
49 *
50 **********************************************************************/
51
52`include "txc_defines.h"
53`include "niu_dmc_reg_defines.h"
54
55module niu_dmc_cache_dataFetch ( /*AUTOJUNK*/
56`ifdef NEPTUNE
57`else
58 tcu_aclk,
59 tcu_bclk,
60 tcu_se_scancollar_in,
61 tcu_se_scancollar_out,
62 tcu_array_wr_inhibit,
63 tds_tdmc_mbist_scan_in,
64 tds_tdmc_mbist_scan_out,
65 tcu_mbist_bisi_en,
66 tcu_mbist_user_mode,
67 tcu_tds_tdmc_mbist_start,
68 tds_tdmc_tcu_mbist_fail,
69 tds_tdmc_tcu_mbist_done,
70 tcu_scan_en,
71 l2clk_2x,
72 iol2clk,
73 hdr_sram_rvalue_tdmc,
74 hdr_sram_rid_tdmc,
75 hdr_sram_wr_en_tdmc,
76 hdr_sram_red_clr_tdmc,
77 sram_hdr_read_data_tdmc,
78 tds_tcu_dmo_data_out,
79 sram_reset,
80
81`endif // !ifdef NEPTUNE
82 // Outputs
83 TxCacheFetchState, DMC_TxCache_SMX_Req,
84 DMC_TxCache_SMX_Req_Port_Num, DMC_TxCache_SMX_Req_DMA_Num,
85 DMC_TxCache_SMX_Req_Cmd, DMC_TxCache_SMX_Req_Length,
86 DMC_TxCache_SMX_Req_Address, tdmc_arb1_req_func_num,
87 DMC_TxCache_SMX_Resp_Accept, txpref_dma_nack_resp,
88 txpref_nack_resp, txpref_nack_rd_addr, dmc_txc_dma0_active,
89 dmc_txc_dma0_eoflist, dmc_txc_dma0_gotnxtdesc,
90 dmc_txc_dma0_descriptor, dmc_txc_dma0_cacheready,
91 dmc_txc_dma0_partial, dmc_txc_dma0_reset_scheduled,
92 tx_rng_head_dma0,
93 dma0_clear_reset, tx_dma_cfg_dma0_stop_state,
94 ShadowRingCurrentPtr_DMA0, set_pref_buf_par_err_dma0,
95 set_pkt_part_err_dma0, pkt_part_error_address_dma0,
96 set_conf_part_error_dma0, dmc_txc_dma1_active,
97 dmc_txc_dma1_eoflist, dmc_txc_dma1_gotnxtdesc,
98 dmc_txc_dma1_descriptor, dmc_txc_dma1_cacheready,
99 dmc_txc_dma1_partial, dmc_txc_dma1_reset_scheduled,
100 tx_rng_head_dma1,
101 dma1_clear_reset, tx_dma_cfg_dma1_stop_state,
102 ShadowRingCurrentPtr_DMA1, set_pref_buf_par_err_dma1,
103 set_pkt_part_err_dma1, pkt_part_error_address_dma1,
104 set_conf_part_error_dma1, dmc_txc_dma2_active,
105 dmc_txc_dma2_eoflist, dmc_txc_dma2_gotnxtdesc,
106 dmc_txc_dma2_descriptor, dmc_txc_dma2_cacheready,
107 dmc_txc_dma2_partial, dmc_txc_dma2_reset_scheduled,
108 tx_rng_head_dma2,
109 dma2_clear_reset, tx_dma_cfg_dma2_stop_state,
110 ShadowRingCurrentPtr_DMA2, set_pref_buf_par_err_dma2,
111 set_pkt_part_err_dma2, pkt_part_error_address_dma2,
112 set_conf_part_error_dma2, dmc_txc_dma3_active,
113 dmc_txc_dma3_eoflist, dmc_txc_dma3_gotnxtdesc,
114 dmc_txc_dma3_descriptor, dmc_txc_dma3_cacheready,
115 dmc_txc_dma3_partial, dmc_txc_dma3_reset_scheduled,
116 tx_rng_head_dma3,
117 dma3_clear_reset, tx_dma_cfg_dma3_stop_state,
118 ShadowRingCurrentPtr_DMA3, set_pref_buf_par_err_dma3,
119 set_pkt_part_err_dma3, pkt_part_error_address_dma3,
120 set_conf_part_error_dma3, dmc_txc_dma4_active,
121 dmc_txc_dma4_eoflist, dmc_txc_dma4_gotnxtdesc,
122 dmc_txc_dma4_descriptor, dmc_txc_dma4_cacheready,
123 dmc_txc_dma4_partial, dmc_txc_dma4_reset_scheduled,
124 tx_rng_head_dma4,
125 dma4_clear_reset, tx_dma_cfg_dma4_stop_state,
126 ShadowRingCurrentPtr_DMA4, set_pref_buf_par_err_dma4,
127 set_pkt_part_err_dma4, pkt_part_error_address_dma4,
128 set_conf_part_error_dma4, dmc_txc_dma5_active,
129 dmc_txc_dma5_eoflist, dmc_txc_dma5_gotnxtdesc,
130 dmc_txc_dma5_descriptor, dmc_txc_dma5_cacheready,
131 dmc_txc_dma5_partial, dmc_txc_dma5_reset_scheduled,
132 tx_rng_head_dma5,
133 dma5_clear_reset, tx_dma_cfg_dma5_stop_state,
134 ShadowRingCurrentPtr_DMA5, set_pref_buf_par_err_dma5,
135 set_pkt_part_err_dma5, pkt_part_error_address_dma5,
136 set_conf_part_error_dma5, dmc_txc_dma6_active,
137 dmc_txc_dma6_eoflist, dmc_txc_dma6_gotnxtdesc,
138 dmc_txc_dma6_descriptor, dmc_txc_dma6_cacheready,
139 dmc_txc_dma6_partial, dmc_txc_dma6_reset_scheduled,
140 tx_rng_head_dma6,
141 dma6_clear_reset, tx_dma_cfg_dma6_stop_state,
142 ShadowRingCurrentPtr_DMA6, set_pref_buf_par_err_dma6,
143 set_pkt_part_err_dma6, pkt_part_error_address_dma6,
144 set_conf_part_error_dma6, dmc_txc_dma7_active,
145 dmc_txc_dma7_eoflist, dmc_txc_dma7_gotnxtdesc,
146 dmc_txc_dma7_descriptor, dmc_txc_dma7_cacheready,
147 dmc_txc_dma7_partial, dmc_txc_dma7_reset_scheduled,
148 tx_rng_head_dma7,
149 dma7_clear_reset, tx_dma_cfg_dma7_stop_state,
150 ShadowRingCurrentPtr_DMA7, set_pref_buf_par_err_dma7,
151 set_pkt_part_err_dma7, pkt_part_error_address_dma7,
152 set_conf_part_error_dma7, dmc_txc_dma8_active,
153 dmc_txc_dma8_eoflist, dmc_txc_dma8_gotnxtdesc,
154 dmc_txc_dma8_descriptor, dmc_txc_dma8_cacheready,
155 dmc_txc_dma8_partial, dmc_txc_dma8_reset_scheduled,
156 tx_rng_head_dma8,
157 dma8_clear_reset, tx_dma_cfg_dma8_stop_state,
158 ShadowRingCurrentPtr_DMA8, set_pref_buf_par_err_dma8,
159 set_pkt_part_err_dma8, pkt_part_error_address_dma8,
160 set_conf_part_error_dma8, dmc_txc_dma9_active,
161 dmc_txc_dma9_eoflist, dmc_txc_dma9_gotnxtdesc,
162 dmc_txc_dma9_descriptor, dmc_txc_dma9_cacheready,
163 dmc_txc_dma9_partial, dmc_txc_dma9_reset_scheduled,
164 tx_rng_head_dma9,
165 dma9_clear_reset, tx_dma_cfg_dma9_stop_state,
166 ShadowRingCurrentPtr_DMA9, set_pref_buf_par_err_dma9,
167 set_pkt_part_err_dma9, pkt_part_error_address_dma9,
168 set_conf_part_error_dma9, dmc_txc_dma10_active,
169 dmc_txc_dma10_eoflist,
170 dmc_txc_dma10_gotnxtdesc, dmc_txc_dma10_descriptor,
171 dmc_txc_dma10_cacheready, dmc_txc_dma10_partial,
172 dmc_txc_dma10_reset_scheduled,
173 tx_rng_head_dma10, dma10_clear_reset,
174 tx_dma_cfg_dma10_stop_state, ShadowRingCurrentPtr_DMA10,
175 set_pref_buf_par_err_dma10, set_pkt_part_err_dma10,
176 pkt_part_error_address_dma10, set_conf_part_error_dma10,
177 dmc_txc_dma11_active, dmc_txc_dma11_eoflist,
178 dmc_txc_dma11_gotnxtdesc, dmc_txc_dma11_descriptor,
179 dmc_txc_dma11_cacheready, dmc_txc_dma11_partial,
180 dmc_txc_dma11_reset_scheduled,
181 tx_rng_head_dma11, dma11_clear_reset,
182 tx_dma_cfg_dma11_stop_state, ShadowRingCurrentPtr_DMA11,
183 set_pref_buf_par_err_dma11, set_pkt_part_err_dma11,
184 pkt_part_error_address_dma11, set_conf_part_error_dma11,
185 dmc_txc_dma12_active, dmc_txc_dma12_eoflist,
186 dmc_txc_dma12_gotnxtdesc, dmc_txc_dma12_descriptor,
187 dmc_txc_dma12_cacheready, dmc_txc_dma12_partial,
188 dmc_txc_dma12_reset_scheduled,
189 tx_rng_head_dma12, dma12_clear_reset,
190 tx_dma_cfg_dma12_stop_state, ShadowRingCurrentPtr_DMA12,
191 set_pref_buf_par_err_dma12, set_pkt_part_err_dma12,
192 pkt_part_error_address_dma12, set_conf_part_error_dma12,
193 dmc_txc_dma13_active, dmc_txc_dma13_eoflist,
194 dmc_txc_dma13_gotnxtdesc, dmc_txc_dma13_descriptor,
195 dmc_txc_dma13_cacheready, dmc_txc_dma13_partial,
196 dmc_txc_dma13_reset_scheduled,
197 tx_rng_head_dma13, dma13_clear_reset,
198 tx_dma_cfg_dma13_stop_state, ShadowRingCurrentPtr_DMA13,
199 set_pref_buf_par_err_dma13, set_pkt_part_err_dma13,
200 pkt_part_error_address_dma13, set_conf_part_error_dma13,
201 dmc_txc_dma14_active, dmc_txc_dma14_eoflist,
202 dmc_txc_dma14_gotnxtdesc, dmc_txc_dma14_descriptor,
203 dmc_txc_dma14_cacheready, dmc_txc_dma14_partial,
204 dmc_txc_dma14_reset_scheduled,
205 tx_rng_head_dma14, dma14_clear_reset,
206 tx_dma_cfg_dma14_stop_state, ShadowRingCurrentPtr_DMA14,
207 set_pref_buf_par_err_dma14, set_pkt_part_err_dma14,
208 pkt_part_error_address_dma14, set_conf_part_error_dma14,
209 dmc_txc_dma15_active, dmc_txc_dma15_eoflist,
210 dmc_txc_dma15_gotnxtdesc, dmc_txc_dma15_descriptor,
211 dmc_txc_dma15_cacheready, dmc_txc_dma15_partial,
212 dmc_txc_dma15_reset_scheduled,
213 tx_rng_head_dma15, dma15_clear_reset,
214 tx_dma_cfg_dma15_stop_state, ShadowRingCurrentPtr_DMA15,
215 set_pref_buf_par_err_dma15, set_pkt_part_err_dma15,
216 pkt_part_error_address_dma15, set_conf_part_error_dma15,
217 set_tx_ring_oflow_dma0, set_tx_ring_oflow_dma1, set_tx_ring_oflow_dma2,
218 set_tx_ring_oflow_dma3, set_tx_ring_oflow_dma4, set_tx_ring_oflow_dma5,
219 set_tx_ring_oflow_dma6, set_tx_ring_oflow_dma7, set_tx_ring_oflow_dma8,
220 set_tx_ring_oflow_dma9, set_tx_ring_oflow_dma10, set_tx_ring_oflow_dma11,
221 set_tx_ring_oflow_dma12, set_tx_ring_oflow_dma13, set_tx_ring_oflow_dma14,
222 set_tx_ring_oflow_dma15,
223
224 dma0_debug_port, dma1_debug_port, dma2_debug_port, dma3_debug_port,
225 dma4_debug_port, dma5_debug_port, dma6_debug_port, dma7_debug_port,
226 dma8_debug_port, dma9_debug_port, dma10_debug_port, dma11_debug_port,
227 dma12_debug_port, dma13_debug_port, dma14_debug_port, dma15_debug_port,
228
229`ifdef NEPTUNE
230
231 dmc_txc_dma16_active, dmc_txc_dma16_eoflist,
232 dmc_txc_dma16_gotnxtdesc, dmc_txc_dma16_descriptor,
233 dmc_txc_dma16_cacheready, dmc_txc_dma16_partial,
234 dmc_txc_dma16_reset_scheduled,
235 tx_rng_head_dma16, dma16_clear_reset,
236 tx_dma_cfg_dma16_stop_state, ShadowRingCurrentPtr_DMA16,
237 set_pref_buf_par_err_dma16, set_pkt_part_err_dma16,
238 pkt_part_error_address_dma16, set_conf_part_error_dma16,
239 dmc_txc_dma17_active, dmc_txc_dma17_eoflist,
240 dmc_txc_dma17_gotnxtdesc, dmc_txc_dma17_descriptor,
241 dmc_txc_dma17_cacheready, dmc_txc_dma17_partial,
242 dmc_txc_dma17_reset_scheduled,
243 tx_rng_head_dma17, dma17_clear_reset,
244 tx_dma_cfg_dma17_stop_state, ShadowRingCurrentPtr_DMA17,
245 set_pref_buf_par_err_dma17, set_pkt_part_err_dma17,
246 pkt_part_error_address_dma17, set_conf_part_error_dma17,
247 dmc_txc_dma18_active, dmc_txc_dma18_eoflist,
248 dmc_txc_dma18_gotnxtdesc, dmc_txc_dma18_descriptor,
249 dmc_txc_dma18_cacheready, dmc_txc_dma18_partial,
250 dmc_txc_dma18_reset_scheduled,
251 tx_rng_head_dma18, dma18_clear_reset,
252 tx_dma_cfg_dma18_stop_state, ShadowRingCurrentPtr_DMA18,
253 set_pref_buf_par_err_dma18, set_pkt_part_err_dma18,
254 pkt_part_error_address_dma18, set_conf_part_error_dma18,
255 dmc_txc_dma19_active, dmc_txc_dma19_eoflist,
256 dmc_txc_dma19_gotnxtdesc, dmc_txc_dma19_descriptor,
257 dmc_txc_dma19_cacheready, dmc_txc_dma19_partial,
258 dmc_txc_dma19_reset_scheduled,
259 tx_rng_head_dma19, dma19_clear_reset,
260 tx_dma_cfg_dma19_stop_state, ShadowRingCurrentPtr_DMA19,
261 set_pref_buf_par_err_dma19, set_pkt_part_err_dma19,
262 pkt_part_error_address_dma19, set_conf_part_error_dma19,
263 dmc_txc_dma20_active, dmc_txc_dma20_eoflist,
264 dmc_txc_dma20_gotnxtdesc, dmc_txc_dma20_descriptor,
265 dmc_txc_dma20_cacheready, dmc_txc_dma20_partial,
266 dmc_txc_dma20_reset_scheduled,
267 tx_rng_head_dma20, dma20_clear_reset,
268 tx_dma_cfg_dma20_stop_state, ShadowRingCurrentPtr_DMA20,
269 set_pref_buf_par_err_dma20, set_pkt_part_err_dma20,
270 pkt_part_error_address_dma20, set_conf_part_error_dma20,
271 dmc_txc_dma21_active, dmc_txc_dma21_eoflist,
272 dmc_txc_dma21_gotnxtdesc, dmc_txc_dma21_descriptor,
273 dmc_txc_dma21_cacheready, dmc_txc_dma21_partial,
274 dmc_txc_dma21_reset_scheduled,
275 tx_rng_head_dma21, dma21_clear_reset,
276 tx_dma_cfg_dma21_stop_state, ShadowRingCurrentPtr_DMA21,
277 set_pref_buf_par_err_dma21, set_pkt_part_err_dma21,
278 pkt_part_error_address_dma21, set_conf_part_error_dma21,
279 dmc_txc_dma22_active, dmc_txc_dma22_eoflist,
280 dmc_txc_dma22_gotnxtdesc, dmc_txc_dma22_descriptor,
281 dmc_txc_dma22_cacheready, dmc_txc_dma22_partial,
282 dmc_txc_dma22_reset_scheduled,
283 tx_rng_head_dma22, dma22_clear_reset,
284 tx_dma_cfg_dma22_stop_state, ShadowRingCurrentPtr_DMA22,
285 set_pref_buf_par_err_dma22, set_pkt_part_err_dma22,
286 pkt_part_error_address_dma22, set_conf_part_error_dma22,
287 dmc_txc_dma23_active, dmc_txc_dma23_eoflist,
288 dmc_txc_dma23_gotnxtdesc, dmc_txc_dma23_descriptor,
289 dmc_txc_dma23_cacheready, dmc_txc_dma23_partial,
290 dmc_txc_dma23_reset_scheduled,
291 tx_rng_head_dma23, dma23_clear_reset,
292 tx_dma_cfg_dma23_stop_state, ShadowRingCurrentPtr_DMA23,
293 set_pref_buf_par_err_dma23, set_pkt_part_err_dma23,
294 pkt_part_error_address_dma23, set_conf_part_error_dma23,
295 set_tx_ring_oflow_dma16, set_tx_ring_oflow_dma17, set_tx_ring_oflow_dma18,
296 set_tx_ring_oflow_dma19, set_tx_ring_oflow_dma20, set_tx_ring_oflow_dma21,
297 set_tx_ring_oflow_dma22, set_tx_ring_oflow_dma23,
298
299 dma16_debug_port, dma17_debug_port, dma18_debug_port, dma19_debug_port,
300 dma20_debug_port, dma21_debug_port, dma22_debug_port, dma23_debug_port,
301
302`endif // ifdef NEPTUNE
303
304 // Inputs
305 SMX_DMC_TxCache_Req_Ack, SMX_DMC_TxCache_Resp_Rdy,
306 SMX_DMC_TxCache_Resp_Complete, SMX_DMC_TxCache_Trans_Complete,
307 SMX_DMC_TxCache_Resp_Data_Valid, SMX_DMC_TxCache_Resp_DMA_Num,
308 SMX_DMC_TxCache_Resp_ByteEnables,
309 SMX_DMC_TxCache_Resp_Data_Length, SMX_DMC_TxCache_Resp_Address,
310 SMX_DMC_TxCache_Resp_Data, meta_dmc_resp_cmd,
311 meta_dmc_resp_cmd_status, meta_dmc_data_status,
312 parity_corrupt_config, dmc_txc_tx_addr_md,
313 txc_dmc_dma0_getnxtdesc, txc_dmc_dma0_inc_head,
314 txc_dmc_dma0_reset_done, tx_rng_cfg_dma0_len,
315 tx_rng_cfg_dma0_staddr, tx_rng_tail_dma0, tx_dma_cfg_dma0_rst,
316 tx_dma_cfg_dma0_stall, tx_dma_cfg_dma0_stop, page0_mask_dma0,
317 page0_value_dma0, page0_reloc_dma0, page0_valid_dma0,
318 page1_mask_dma0, page1_value_dma0, page1_reloc_dma0,
319 page1_valid_dma0, dmc_txc_dma0_page_handle, dmc_txc_dma0_func_num,
320 txc_dmc_dma1_getnxtdesc, txc_dmc_dma1_inc_head,
321 txc_dmc_dma1_reset_done, tx_rng_cfg_dma1_len,
322 tx_rng_cfg_dma1_staddr, tx_rng_tail_dma1, tx_dma_cfg_dma1_rst,
323 tx_dma_cfg_dma1_stall, tx_dma_cfg_dma1_stop, page0_mask_dma1,
324 page0_value_dma1, page0_reloc_dma1, page0_valid_dma1,
325 page1_mask_dma1, page1_value_dma1, page1_reloc_dma1,
326 page1_valid_dma1, dmc_txc_dma1_page_handle, dmc_txc_dma1_func_num,
327 txc_dmc_dma2_getnxtdesc, txc_dmc_dma2_inc_head,
328 txc_dmc_dma2_reset_done, tx_rng_cfg_dma2_len,
329 tx_rng_cfg_dma2_staddr, tx_rng_tail_dma2, tx_dma_cfg_dma2_rst,
330 tx_dma_cfg_dma2_stall, tx_dma_cfg_dma2_stop, page0_mask_dma2,
331 page0_value_dma2, page0_reloc_dma2, page0_valid_dma2,
332 page1_mask_dma2, page1_value_dma2, page1_reloc_dma2,
333 page1_valid_dma2, dmc_txc_dma2_page_handle, dmc_txc_dma2_func_num,
334 txc_dmc_dma3_getnxtdesc, txc_dmc_dma3_inc_head,
335 txc_dmc_dma3_reset_done, tx_rng_cfg_dma3_len,
336 tx_rng_cfg_dma3_staddr, tx_rng_tail_dma3, tx_dma_cfg_dma3_rst,
337 tx_dma_cfg_dma3_stall, tx_dma_cfg_dma3_stop, page0_mask_dma3,
338 page0_value_dma3, page0_reloc_dma3, page0_valid_dma3,
339 page1_mask_dma3, page1_value_dma3, page1_reloc_dma3,
340 page1_valid_dma3, dmc_txc_dma3_page_handle, dmc_txc_dma3_func_num,
341 txc_dmc_dma4_getnxtdesc, txc_dmc_dma4_inc_head,
342 txc_dmc_dma4_reset_done, tx_rng_cfg_dma4_len,
343 tx_rng_cfg_dma4_staddr, tx_rng_tail_dma4, tx_dma_cfg_dma4_rst,
344 tx_dma_cfg_dma4_stall, tx_dma_cfg_dma4_stop, page0_mask_dma4,
345 page0_value_dma4, page0_reloc_dma4, page0_valid_dma4,
346 page1_mask_dma4, page1_value_dma4, page1_reloc_dma4,
347 page1_valid_dma4, dmc_txc_dma4_page_handle, dmc_txc_dma4_func_num,
348 txc_dmc_dma5_getnxtdesc, txc_dmc_dma5_inc_head,
349 txc_dmc_dma5_reset_done, tx_rng_cfg_dma5_len,
350 tx_rng_cfg_dma5_staddr, tx_rng_tail_dma5, tx_dma_cfg_dma5_rst,
351 tx_dma_cfg_dma5_stall, tx_dma_cfg_dma5_stop, page0_mask_dma5,
352 page0_value_dma5, page0_reloc_dma5, page0_valid_dma5,
353 page1_mask_dma5, page1_value_dma5, page1_reloc_dma5,
354 page1_valid_dma5, dmc_txc_dma5_page_handle, dmc_txc_dma5_func_num,
355 txc_dmc_dma6_getnxtdesc, txc_dmc_dma6_inc_head,
356 txc_dmc_dma6_reset_done, tx_rng_cfg_dma6_len,
357 tx_rng_cfg_dma6_staddr, tx_rng_tail_dma6, tx_dma_cfg_dma6_rst,
358 tx_dma_cfg_dma6_stall, tx_dma_cfg_dma6_stop, page0_mask_dma6,
359 page0_value_dma6, page0_reloc_dma6, page0_valid_dma6,
360 page1_mask_dma6, page1_value_dma6, page1_reloc_dma6,
361 page1_valid_dma6, dmc_txc_dma6_page_handle, dmc_txc_dma6_func_num,
362 txc_dmc_dma7_getnxtdesc, txc_dmc_dma7_inc_head,
363 txc_dmc_dma7_reset_done, tx_rng_cfg_dma7_len,
364 tx_rng_cfg_dma7_staddr, tx_rng_tail_dma7, tx_dma_cfg_dma7_rst,
365 tx_dma_cfg_dma7_stall, tx_dma_cfg_dma7_stop, page0_mask_dma7,
366 page0_value_dma7, page0_reloc_dma7, page0_valid_dma7,
367 page1_mask_dma7, page1_value_dma7, page1_reloc_dma7,
368 page1_valid_dma7, dmc_txc_dma7_page_handle, dmc_txc_dma7_func_num,
369 txc_dmc_dma8_getnxtdesc, txc_dmc_dma8_inc_head,
370 txc_dmc_dma8_reset_done, tx_rng_cfg_dma8_len,
371 tx_rng_cfg_dma8_staddr, tx_rng_tail_dma8, tx_dma_cfg_dma8_rst,
372 tx_dma_cfg_dma8_stall, tx_dma_cfg_dma8_stop, page0_mask_dma8,
373 page0_value_dma8, page0_reloc_dma8, page0_valid_dma8,
374 page1_mask_dma8, page1_value_dma8, page1_reloc_dma8,
375 page1_valid_dma8, dmc_txc_dma8_page_handle, dmc_txc_dma8_func_num,
376 txc_dmc_dma9_getnxtdesc, txc_dmc_dma9_inc_head,
377 txc_dmc_dma9_reset_done, tx_rng_cfg_dma9_len,
378 tx_rng_cfg_dma9_staddr, tx_rng_tail_dma9, tx_dma_cfg_dma9_rst,
379 tx_dma_cfg_dma9_stall, tx_dma_cfg_dma9_stop, page0_mask_dma9,
380 page0_value_dma9, page0_reloc_dma9, page0_valid_dma9,
381 page1_mask_dma9, page1_value_dma9, page1_reloc_dma9,
382 page1_valid_dma9, dmc_txc_dma9_page_handle, dmc_txc_dma9_func_num,
383 txc_dmc_dma10_getnxtdesc, txc_dmc_dma10_inc_head,
384 txc_dmc_dma10_reset_done, tx_rng_cfg_dma10_len,
385 tx_rng_cfg_dma10_staddr, tx_rng_tail_dma10, tx_dma_cfg_dma10_rst,
386 tx_dma_cfg_dma10_stall, tx_dma_cfg_dma10_stop, page0_mask_dma10,
387 page0_value_dma10, page0_reloc_dma10, page0_valid_dma10,
388 page1_mask_dma10, page1_value_dma10, page1_reloc_dma10,
389 page1_valid_dma10, dmc_txc_dma10_page_handle,
390 dmc_txc_dma10_func_num, txc_dmc_dma11_getnxtdesc,
391 txc_dmc_dma11_inc_head, txc_dmc_dma11_reset_done,
392 tx_rng_cfg_dma11_len, tx_rng_cfg_dma11_staddr, tx_rng_tail_dma11,
393 tx_dma_cfg_dma11_rst, tx_dma_cfg_dma11_stall,
394 tx_dma_cfg_dma11_stop, page0_mask_dma11, page0_value_dma11,
395 page0_reloc_dma11, page0_valid_dma11, page1_mask_dma11,
396 page1_value_dma11, page1_reloc_dma11, page1_valid_dma11,
397 dmc_txc_dma11_page_handle, dmc_txc_dma11_func_num,
398 txc_dmc_dma12_getnxtdesc, txc_dmc_dma12_inc_head,
399 txc_dmc_dma12_reset_done, tx_rng_cfg_dma12_len,
400 tx_rng_cfg_dma12_staddr, tx_rng_tail_dma12, tx_dma_cfg_dma12_rst,
401 tx_dma_cfg_dma12_stall, tx_dma_cfg_dma12_stop, page0_mask_dma12,
402 page0_value_dma12, page0_reloc_dma12, page0_valid_dma12,
403 page1_mask_dma12, page1_value_dma12, page1_reloc_dma12,
404 page1_valid_dma12, dmc_txc_dma12_page_handle,
405 dmc_txc_dma12_func_num, txc_dmc_dma13_getnxtdesc,
406 txc_dmc_dma13_inc_head, txc_dmc_dma13_reset_done,
407 tx_rng_cfg_dma13_len, tx_rng_cfg_dma13_staddr, tx_rng_tail_dma13,
408 tx_dma_cfg_dma13_rst, tx_dma_cfg_dma13_stall,
409 tx_dma_cfg_dma13_stop, page0_mask_dma13, page0_value_dma13,
410 page0_reloc_dma13, page0_valid_dma13, page1_mask_dma13,
411 page1_value_dma13, page1_reloc_dma13, page1_valid_dma13,
412 dmc_txc_dma13_page_handle, dmc_txc_dma13_func_num,
413 txc_dmc_dma14_getnxtdesc, txc_dmc_dma14_inc_head,
414 txc_dmc_dma14_reset_done, tx_rng_cfg_dma14_len,
415 tx_rng_cfg_dma14_staddr, tx_rng_tail_dma14, tx_dma_cfg_dma14_rst,
416 tx_dma_cfg_dma14_stall, tx_dma_cfg_dma14_stop, page0_mask_dma14,
417 page0_value_dma14, page0_reloc_dma14, page0_valid_dma14,
418 page1_mask_dma14, page1_value_dma14, page1_reloc_dma14,
419 page1_valid_dma14, dmc_txc_dma14_page_handle,
420 dmc_txc_dma14_func_num, txc_dmc_dma15_getnxtdesc,
421 txc_dmc_dma15_inc_head, txc_dmc_dma15_reset_done,
422 tx_rng_cfg_dma15_len, tx_rng_cfg_dma15_staddr, tx_rng_tail_dma15,
423 tx_dma_cfg_dma15_rst, tx_dma_cfg_dma15_stall,
424 tx_dma_cfg_dma15_stop, page0_mask_dma15, page0_value_dma15,
425 page0_reloc_dma15, page0_valid_dma15, page1_mask_dma15,
426 page1_value_dma15, page1_reloc_dma15, page1_valid_dma15,
427 dmc_txc_dma15_page_handle, dmc_txc_dma15_func_num,
428
429`ifdef NEPTUNE
430
431 txc_dmc_dma16_getnxtdesc, txc_dmc_dma16_inc_head,
432 txc_dmc_dma16_reset_done, tx_rng_cfg_dma16_len,
433 tx_rng_cfg_dma16_staddr, tx_rng_tail_dma16, tx_dma_cfg_dma16_rst,
434 tx_dma_cfg_dma16_stall, tx_dma_cfg_dma16_stop, page0_mask_dma16,
435 page0_value_dma16, page0_reloc_dma16, page0_valid_dma16,
436 page1_mask_dma16, page1_value_dma16, page1_reloc_dma16,
437 page1_valid_dma16, dmc_txc_dma16_page_handle,
438 dmc_txc_dma16_func_num, txc_dmc_dma17_getnxtdesc,
439 txc_dmc_dma17_inc_head, txc_dmc_dma17_reset_done,
440 tx_rng_cfg_dma17_len, tx_rng_cfg_dma17_staddr, tx_rng_tail_dma17,
441 tx_dma_cfg_dma17_rst, tx_dma_cfg_dma17_stall,
442 tx_dma_cfg_dma17_stop, page0_mask_dma17, page0_value_dma17,
443 page0_reloc_dma17, page0_valid_dma17, page1_mask_dma17,
444 page1_value_dma17, page1_reloc_dma17, page1_valid_dma17,
445 dmc_txc_dma17_page_handle, dmc_txc_dma17_func_num,
446 txc_dmc_dma18_getnxtdesc, txc_dmc_dma18_inc_head,
447 txc_dmc_dma18_reset_done, tx_rng_cfg_dma18_len,
448 tx_rng_cfg_dma18_staddr, tx_rng_tail_dma18, tx_dma_cfg_dma18_rst,
449 tx_dma_cfg_dma18_stall, tx_dma_cfg_dma18_stop, page0_mask_dma18,
450 page0_value_dma18, page0_reloc_dma18, page0_valid_dma18,
451 page1_mask_dma18, page1_value_dma18, page1_reloc_dma18,
452 page1_valid_dma18, dmc_txc_dma18_page_handle,
453 dmc_txc_dma18_func_num, txc_dmc_dma19_getnxtdesc,
454 txc_dmc_dma19_inc_head, txc_dmc_dma19_reset_done,
455 tx_rng_cfg_dma19_len, tx_rng_cfg_dma19_staddr, tx_rng_tail_dma19,
456 tx_dma_cfg_dma19_rst, tx_dma_cfg_dma19_stall,
457 tx_dma_cfg_dma19_stop, page0_mask_dma19, page0_value_dma19,
458 page0_reloc_dma19, page0_valid_dma19, page1_mask_dma19,
459 page1_value_dma19, page1_reloc_dma19, page1_valid_dma19,
460 dmc_txc_dma19_page_handle, dmc_txc_dma19_func_num,
461 txc_dmc_dma20_getnxtdesc, txc_dmc_dma20_inc_head,
462 txc_dmc_dma20_reset_done, tx_rng_cfg_dma20_len,
463 tx_rng_cfg_dma20_staddr, tx_rng_tail_dma20, tx_dma_cfg_dma20_rst,
464 tx_dma_cfg_dma20_stall, tx_dma_cfg_dma20_stop, page0_mask_dma20,
465 page0_value_dma20, page0_reloc_dma20, page0_valid_dma20,
466 page1_mask_dma20, page1_value_dma20, page1_reloc_dma20,
467 page1_valid_dma20, dmc_txc_dma20_page_handle,
468 dmc_txc_dma20_func_num, txc_dmc_dma21_getnxtdesc,
469 txc_dmc_dma21_inc_head, txc_dmc_dma21_reset_done,
470 tx_rng_cfg_dma21_len, tx_rng_cfg_dma21_staddr, tx_rng_tail_dma21,
471 tx_dma_cfg_dma21_rst, tx_dma_cfg_dma21_stall,
472 tx_dma_cfg_dma21_stop, page0_mask_dma21, page0_value_dma21,
473 page0_reloc_dma21, page0_valid_dma21, page1_mask_dma21,
474 page1_value_dma21, page1_reloc_dma21, page1_valid_dma21,
475 dmc_txc_dma21_page_handle, dmc_txc_dma21_func_num,
476 txc_dmc_dma22_getnxtdesc, txc_dmc_dma22_inc_head,
477 txc_dmc_dma22_reset_done, tx_rng_cfg_dma22_len,
478 tx_rng_cfg_dma22_staddr, tx_rng_tail_dma22, tx_dma_cfg_dma22_rst,
479 tx_dma_cfg_dma22_stall, tx_dma_cfg_dma22_stop, page0_mask_dma22,
480 page0_value_dma22, page0_reloc_dma22, page0_valid_dma22,
481 page1_mask_dma22, page1_value_dma22, page1_reloc_dma22,
482 page1_valid_dma22, dmc_txc_dma22_page_handle,
483 dmc_txc_dma22_func_num, txc_dmc_dma23_getnxtdesc,
484 txc_dmc_dma23_inc_head, txc_dmc_dma23_reset_done,
485 tx_rng_cfg_dma23_len, tx_rng_cfg_dma23_staddr, tx_rng_tail_dma23,
486 tx_dma_cfg_dma23_rst, tx_dma_cfg_dma23_stall,
487 tx_dma_cfg_dma23_stop, page0_mask_dma23, page0_value_dma23,
488 page0_reloc_dma23, page0_valid_dma23, page1_mask_dma23,
489 page1_value_dma23, page1_reloc_dma23, page1_valid_dma23,
490 dmc_txc_dma23_page_handle, dmc_txc_dma23_func_num,
491`endif // ifdef NEPTUNE
492
493 // clocks etc
494 //
495 SysClk, Reset_L
496 );
497
498
499 // Global Signals
500 input SysClk;
501 input Reset_L;
502
503
504`ifdef NEPTUNE
505`else
506 // mbist if
507 input tcu_aclk;
508 input tcu_bclk;
509 input tcu_se_scancollar_in;
510 input tcu_se_scancollar_out;
511 input tcu_array_wr_inhibit;
512 input tcu_scan_en;
513 input tcu_mbist_user_mode;
514
515 input tds_tdmc_mbist_scan_in;
516 output tds_tdmc_mbist_scan_out;
517
518
519 input tcu_tds_tdmc_mbist_start;
520 input tcu_mbist_bisi_en;
521 output tds_tdmc_tcu_mbist_fail;
522 output tds_tdmc_tcu_mbist_done;
523
524 input l2clk_2x;
525 input iol2clk;
526
527 input [6:0] hdr_sram_rvalue_tdmc;
528 input [1:0] hdr_sram_rid_tdmc;
529 input hdr_sram_wr_en_tdmc;
530 input hdr_sram_red_clr_tdmc;
531 output [6:0] sram_hdr_read_data_tdmc;
532 output [39:0] tds_tcu_dmo_data_out;
533 input sram_reset;
534
535`endif // !ifdef NEPTUNE
536
537// debug output
538 output [3:0] TxCacheFetchState;
539
540 // Tx DMA Request Interface
541 input SMX_DMC_TxCache_Req_Ack;
542 output DMC_TxCache_SMX_Req;
543 output [1:0] DMC_TxCache_SMX_Req_Port_Num;
544 output [4:0] DMC_TxCache_SMX_Req_DMA_Num;
545 output [7:0] DMC_TxCache_SMX_Req_Cmd;
546 output [13:0] DMC_TxCache_SMX_Req_Length;
547 output [63:0] DMC_TxCache_SMX_Req_Address;
548 output [1:0] tdmc_arb1_req_func_num;
549
550
551 // Tx DMA Response Interface
552 input SMX_DMC_TxCache_Resp_Rdy;
553 input SMX_DMC_TxCache_Resp_Complete;
554 input SMX_DMC_TxCache_Trans_Complete;
555 input SMX_DMC_TxCache_Resp_Data_Valid;
556 input [4:0] SMX_DMC_TxCache_Resp_DMA_Num;
557 input [15:0] SMX_DMC_TxCache_Resp_ByteEnables;
558 input [13:0] SMX_DMC_TxCache_Resp_Data_Length;
559 input [63:0] SMX_DMC_TxCache_Resp_Address;
560 input [127:0] SMX_DMC_TxCache_Resp_Data;
561 output DMC_TxCache_SMX_Resp_Accept;
562 input [7:0] meta_dmc_resp_cmd;
563
564 input [3:0] meta_dmc_resp_cmd_status;
565 input [3:0] meta_dmc_data_status;
566
567 // Tx DMA Cache
568
569 // Signals for corrupting the parity of cache
570 input [31:0] parity_corrupt_config;
571 input dmc_txc_tx_addr_md;
572 output [`NO_OF_DMAS - 1 :0] txpref_dma_nack_resp;
573 output txpref_nack_resp ;
574 output [43:0] txpref_nack_rd_addr;
575
576
577 // DMA0 TXC Interface
578 output dmc_txc_dma0_active;
579 output dmc_txc_dma0_eoflist;
580 output dmc_txc_dma0_gotnxtdesc;
581 output [63:0] dmc_txc_dma0_descriptor;
582 output dmc_txc_dma0_cacheready;
583 output dmc_txc_dma0_partial;
584 output dmc_txc_dma0_reset_scheduled;
585 input txc_dmc_dma0_getnxtdesc;
586 input txc_dmc_dma0_inc_head;
587 input txc_dmc_dma0_reset_done;
588
589// DMA0 - PIO Interface
590
591 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma0_len;
592 input [37:0] tx_rng_cfg_dma0_staddr;
593 input [`PTR_WIDTH:0] tx_rng_tail_dma0 ;
594 input tx_dma_cfg_dma0_rst;
595 input tx_dma_cfg_dma0_stall;
596 output [`PTR_WIDTH:0] tx_rng_head_dma0 ;
597 output dma0_clear_reset;
598 output tx_dma_cfg_dma0_stop_state;
599 input tx_dma_cfg_dma0_stop;
600 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA0;
601
602
603 // DMA0 -FZC signals
604 input [31:0] page0_mask_dma0;
605 input [31:0] page0_value_dma0;
606 input [31:0] page0_reloc_dma0;
607 input page0_valid_dma0;
608 input [31:0] page1_mask_dma0;
609 input [31:0] page1_value_dma0;
610 input [31:0] page1_reloc_dma0;
611 input page1_valid_dma0;
612 input [19:0] dmc_txc_dma0_page_handle;
613 input [1:0] dmc_txc_dma0_func_num;
614
615
616
617
618// DMA0 ERROR related signals to PIO block
619
620 output set_pref_buf_par_err_dma0;
621 output set_pkt_part_err_dma0;
622 output [43:0] pkt_part_error_address_dma0;
623 output set_conf_part_error_dma0;
624 output set_tx_ring_oflow_dma0;
625
626
627
628 // DMA1 TXC Interface
629 output dmc_txc_dma1_active;
630 output dmc_txc_dma1_eoflist;
631 output dmc_txc_dma1_gotnxtdesc;
632 output [63:0] dmc_txc_dma1_descriptor;
633 output dmc_txc_dma1_cacheready;
634 output dmc_txc_dma1_partial;
635 output dmc_txc_dma1_reset_scheduled;
636 input txc_dmc_dma1_getnxtdesc;
637 input txc_dmc_dma1_inc_head;
638 input txc_dmc_dma1_reset_done;
639
640// DMA1 - PIO Interface
641
642 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma1_len;
643 input [37:0] tx_rng_cfg_dma1_staddr;
644 input [`PTR_WIDTH:0] tx_rng_tail_dma1 ;
645 input tx_dma_cfg_dma1_rst;
646 input tx_dma_cfg_dma1_stall;
647 output [`PTR_WIDTH:0] tx_rng_head_dma1 ;
648 output dma1_clear_reset;
649 output tx_dma_cfg_dma1_stop_state;
650 input tx_dma_cfg_dma1_stop;
651 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA1;
652
653
654 // DMA1 -FZC signals
655 input [31:0] page0_mask_dma1;
656 input [31:0] page0_value_dma1;
657 input [31:0] page0_reloc_dma1;
658 input page0_valid_dma1;
659 input [31:0] page1_mask_dma1;
660 input [31:0] page1_value_dma1;
661 input [31:0] page1_reloc_dma1;
662 input page1_valid_dma1;
663 input [19:0] dmc_txc_dma1_page_handle;
664 input [1:0] dmc_txc_dma1_func_num;
665
666
667
668
669// DMA1 ERROR related signals to PIO block
670
671 output set_pref_buf_par_err_dma1;
672 output set_pkt_part_err_dma1;
673 output [43:0] pkt_part_error_address_dma1;
674 output set_conf_part_error_dma1;
675 output set_tx_ring_oflow_dma1;
676
677
678 // DMA2 TXC Interface
679 output dmc_txc_dma2_active;
680 output dmc_txc_dma2_eoflist;
681 output dmc_txc_dma2_gotnxtdesc;
682 output [63:0] dmc_txc_dma2_descriptor;
683 output dmc_txc_dma2_cacheready;
684 output dmc_txc_dma2_partial;
685 output dmc_txc_dma2_reset_scheduled;
686 input txc_dmc_dma2_getnxtdesc;
687 input txc_dmc_dma2_inc_head;
688 input txc_dmc_dma2_reset_done;
689
690// DMA2 - PIO Interface
691
692 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma2_len;
693 input [37:0] tx_rng_cfg_dma2_staddr;
694 input [`PTR_WIDTH:0] tx_rng_tail_dma2 ;
695 input tx_dma_cfg_dma2_rst;
696 input tx_dma_cfg_dma2_stall;
697 output [`PTR_WIDTH:0] tx_rng_head_dma2 ;
698 output dma2_clear_reset;
699 output tx_dma_cfg_dma2_stop_state;
700 input tx_dma_cfg_dma2_stop;
701 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA2;
702
703
704 // DMA2 -FZC signals
705 input [31:0] page0_mask_dma2;
706 input [31:0] page0_value_dma2;
707 input [31:0] page0_reloc_dma2;
708 input page0_valid_dma2;
709 input [31:0] page1_mask_dma2;
710 input [31:0] page1_value_dma2;
711 input [31:0] page1_reloc_dma2;
712 input page1_valid_dma2;
713 input [19:0] dmc_txc_dma2_page_handle;
714 input [1:0] dmc_txc_dma2_func_num;
715
716
717
718
719// DMA2 ERROR related signals to PIO block
720
721 output set_pref_buf_par_err_dma2;
722 output set_pkt_part_err_dma2;
723 output [43:0] pkt_part_error_address_dma2;
724 output set_conf_part_error_dma2;
725 output set_tx_ring_oflow_dma2;
726
727
728 // DMA3 TXC Interface
729 output dmc_txc_dma3_active;
730 output dmc_txc_dma3_eoflist;
731 output dmc_txc_dma3_gotnxtdesc;
732 output [63:0] dmc_txc_dma3_descriptor;
733 output dmc_txc_dma3_cacheready;
734 output dmc_txc_dma3_partial;
735 output dmc_txc_dma3_reset_scheduled;
736 input txc_dmc_dma3_getnxtdesc;
737 input txc_dmc_dma3_inc_head;
738 input txc_dmc_dma3_reset_done;
739
740// DMA3 - PIO Interface
741
742 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma3_len;
743 input [37:0] tx_rng_cfg_dma3_staddr;
744 input [`PTR_WIDTH:0] tx_rng_tail_dma3 ;
745 input tx_dma_cfg_dma3_rst;
746 input tx_dma_cfg_dma3_stall;
747 output [`PTR_WIDTH:0] tx_rng_head_dma3 ;
748 output dma3_clear_reset;
749 output tx_dma_cfg_dma3_stop_state;
750 input tx_dma_cfg_dma3_stop;
751 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA3;
752
753
754 // DMA3 -FZC signals
755 input [31:0] page0_mask_dma3;
756 input [31:0] page0_value_dma3;
757 input [31:0] page0_reloc_dma3;
758 input page0_valid_dma3;
759 input [31:0] page1_mask_dma3;
760 input [31:0] page1_value_dma3;
761 input [31:0] page1_reloc_dma3;
762 input page1_valid_dma3;
763 input [19:0] dmc_txc_dma3_page_handle;
764 input [1:0] dmc_txc_dma3_func_num;
765
766
767
768
769// DMA3 ERROR related signals to PIO block
770
771 output set_pref_buf_par_err_dma3;
772 output set_pkt_part_err_dma3;
773 output [43:0] pkt_part_error_address_dma3;
774 output set_conf_part_error_dma3;
775 output set_tx_ring_oflow_dma3;
776
777
778 // DMA4 TXC Interface
779 output dmc_txc_dma4_active;
780 output dmc_txc_dma4_eoflist;
781 output dmc_txc_dma4_gotnxtdesc;
782 output [63:0] dmc_txc_dma4_descriptor;
783 output dmc_txc_dma4_cacheready;
784 output dmc_txc_dma4_partial;
785 output dmc_txc_dma4_reset_scheduled;
786 input txc_dmc_dma4_getnxtdesc;
787 input txc_dmc_dma4_inc_head;
788 input txc_dmc_dma4_reset_done;
789
790// DMA4 - PIO Interface
791
792 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma4_len;
793 input [37:0] tx_rng_cfg_dma4_staddr;
794 input [`PTR_WIDTH:0] tx_rng_tail_dma4 ;
795 input tx_dma_cfg_dma4_rst;
796 input tx_dma_cfg_dma4_stall;
797 output [`PTR_WIDTH:0] tx_rng_head_dma4 ;
798 output dma4_clear_reset;
799 output tx_dma_cfg_dma4_stop_state;
800 input tx_dma_cfg_dma4_stop;
801 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA4;
802
803
804 // DMA4 -FZC signals
805 input [31:0] page0_mask_dma4;
806 input [31:0] page0_value_dma4;
807 input [31:0] page0_reloc_dma4;
808 input page0_valid_dma4;
809 input [31:0] page1_mask_dma4;
810 input [31:0] page1_value_dma4;
811 input [31:0] page1_reloc_dma4;
812 input page1_valid_dma4;
813 input [19:0] dmc_txc_dma4_page_handle;
814 input [1:0] dmc_txc_dma4_func_num;
815
816
817
818
819// DMA4 ERROR related signals to PIO block
820
821 output set_pref_buf_par_err_dma4;
822 output set_pkt_part_err_dma4;
823 output [43:0] pkt_part_error_address_dma4;
824 output set_conf_part_error_dma4;
825 output set_tx_ring_oflow_dma4;
826
827
828 // DMA5 TXC Interface
829 output dmc_txc_dma5_active;
830 output dmc_txc_dma5_eoflist;
831 output dmc_txc_dma5_gotnxtdesc;
832 output [63:0] dmc_txc_dma5_descriptor;
833 output dmc_txc_dma5_cacheready;
834 output dmc_txc_dma5_partial;
835 output dmc_txc_dma5_reset_scheduled;
836 input txc_dmc_dma5_getnxtdesc;
837 input txc_dmc_dma5_inc_head;
838 input txc_dmc_dma5_reset_done;
839
840// DMA5 - PIO Interface
841
842 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma5_len;
843 input [37:0] tx_rng_cfg_dma5_staddr;
844 input [`PTR_WIDTH:0] tx_rng_tail_dma5 ;
845 input tx_dma_cfg_dma5_rst;
846 input tx_dma_cfg_dma5_stall;
847 output [`PTR_WIDTH:0] tx_rng_head_dma5 ;
848 output dma5_clear_reset;
849 output tx_dma_cfg_dma5_stop_state;
850 input tx_dma_cfg_dma5_stop;
851 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA5;
852
853
854 // DMA5 -FZC signals
855 input [31:0] page0_mask_dma5;
856 input [31:0] page0_value_dma5;
857 input [31:0] page0_reloc_dma5;
858 input page0_valid_dma5;
859 input [31:0] page1_mask_dma5;
860 input [31:0] page1_value_dma5;
861 input [31:0] page1_reloc_dma5;
862 input page1_valid_dma5;
863 input [19:0] dmc_txc_dma5_page_handle;
864 input [1:0] dmc_txc_dma5_func_num;
865
866
867
868
869// DMA5 ERROR related signals to PIO block
870
871 output set_pref_buf_par_err_dma5;
872 output set_pkt_part_err_dma5;
873 output [43:0] pkt_part_error_address_dma5;
874 output set_conf_part_error_dma5;
875 output set_tx_ring_oflow_dma5;
876
877
878 // DMA6 TXC Interface
879 output dmc_txc_dma6_active;
880 output dmc_txc_dma6_eoflist;
881 output dmc_txc_dma6_gotnxtdesc;
882 output [63:0] dmc_txc_dma6_descriptor;
883 output dmc_txc_dma6_cacheready;
884 output dmc_txc_dma6_partial;
885 output dmc_txc_dma6_reset_scheduled;
886 input txc_dmc_dma6_getnxtdesc;
887 input txc_dmc_dma6_inc_head;
888 input txc_dmc_dma6_reset_done;
889
890// DMA6 - PIO Interface
891
892 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma6_len;
893 input [37:0] tx_rng_cfg_dma6_staddr;
894 input [`PTR_WIDTH:0] tx_rng_tail_dma6 ;
895 input tx_dma_cfg_dma6_rst;
896 input tx_dma_cfg_dma6_stall;
897 output [`PTR_WIDTH:0] tx_rng_head_dma6 ;
898 output dma6_clear_reset;
899 output tx_dma_cfg_dma6_stop_state;
900 input tx_dma_cfg_dma6_stop;
901 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA6;
902
903
904 // DMA6 -FZC signals
905 input [31:0] page0_mask_dma6;
906 input [31:0] page0_value_dma6;
907 input [31:0] page0_reloc_dma6;
908 input page0_valid_dma6;
909 input [31:0] page1_mask_dma6;
910 input [31:0] page1_value_dma6;
911 input [31:0] page1_reloc_dma6;
912 input page1_valid_dma6;
913 input [19:0] dmc_txc_dma6_page_handle;
914 input [1:0] dmc_txc_dma6_func_num;
915
916
917
918
919// DMA6 ERROR related signals to PIO block
920
921 output set_pref_buf_par_err_dma6;
922 output set_pkt_part_err_dma6;
923 output [43:0] pkt_part_error_address_dma6;
924 output set_conf_part_error_dma6;
925 output set_tx_ring_oflow_dma6;
926
927
928 // DMA7 TXC Interface
929 output dmc_txc_dma7_active;
930 output dmc_txc_dma7_eoflist;
931 output dmc_txc_dma7_gotnxtdesc;
932 output [63:0] dmc_txc_dma7_descriptor;
933 output dmc_txc_dma7_cacheready;
934 output dmc_txc_dma7_partial;
935 output dmc_txc_dma7_reset_scheduled;
936 input txc_dmc_dma7_getnxtdesc;
937 input txc_dmc_dma7_inc_head;
938 input txc_dmc_dma7_reset_done;
939
940// DMA7 - PIO Interface
941
942 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma7_len;
943 input [37:0] tx_rng_cfg_dma7_staddr;
944 input [`PTR_WIDTH:0] tx_rng_tail_dma7 ;
945 input tx_dma_cfg_dma7_rst;
946 input tx_dma_cfg_dma7_stall;
947 output [`PTR_WIDTH:0] tx_rng_head_dma7 ;
948 output dma7_clear_reset;
949 output tx_dma_cfg_dma7_stop_state;
950 input tx_dma_cfg_dma7_stop;
951 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA7;
952
953
954 // DMA7 -FZC signals
955 input [31:0] page0_mask_dma7;
956 input [31:0] page0_value_dma7;
957 input [31:0] page0_reloc_dma7;
958 input page0_valid_dma7;
959 input [31:0] page1_mask_dma7;
960 input [31:0] page1_value_dma7;
961 input [31:0] page1_reloc_dma7;
962 input page1_valid_dma7;
963 input [19:0] dmc_txc_dma7_page_handle;
964 input [1:0] dmc_txc_dma7_func_num;
965
966
967
968
969// DMA7 ERROR related signals to PIO block
970
971 output set_pref_buf_par_err_dma7;
972 output set_pkt_part_err_dma7;
973 output [43:0] pkt_part_error_address_dma7;
974 output set_conf_part_error_dma7;
975 output set_tx_ring_oflow_dma7;
976
977
978 // DMA8 TXC Interface
979 output dmc_txc_dma8_active;
980 output dmc_txc_dma8_eoflist;
981 output dmc_txc_dma8_gotnxtdesc;
982 output [63:0] dmc_txc_dma8_descriptor;
983 output dmc_txc_dma8_cacheready;
984 output dmc_txc_dma8_partial;
985 output dmc_txc_dma8_reset_scheduled;
986 input txc_dmc_dma8_getnxtdesc;
987 input txc_dmc_dma8_inc_head;
988 input txc_dmc_dma8_reset_done;
989
990// DMA8 - PIO Interface
991
992 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma8_len;
993 input [37:0] tx_rng_cfg_dma8_staddr;
994 input [`PTR_WIDTH:0] tx_rng_tail_dma8 ;
995 input tx_dma_cfg_dma8_rst;
996 input tx_dma_cfg_dma8_stall;
997 output [`PTR_WIDTH:0] tx_rng_head_dma8 ;
998 output dma8_clear_reset;
999 output tx_dma_cfg_dma8_stop_state;
1000 input tx_dma_cfg_dma8_stop;
1001 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA8;
1002
1003
1004 // DMA8 -FZC signals
1005 input [31:0] page0_mask_dma8;
1006 input [31:0] page0_value_dma8;
1007 input [31:0] page0_reloc_dma8;
1008 input page0_valid_dma8;
1009 input [31:0] page1_mask_dma8;
1010 input [31:0] page1_value_dma8;
1011 input [31:0] page1_reloc_dma8;
1012 input page1_valid_dma8;
1013 input [19:0] dmc_txc_dma8_page_handle;
1014 input [1:0] dmc_txc_dma8_func_num;
1015
1016
1017
1018
1019// DMA8 ERROR related signals to PIO block
1020
1021 output set_pref_buf_par_err_dma8;
1022 output set_pkt_part_err_dma8;
1023 output [43:0] pkt_part_error_address_dma8;
1024 output set_conf_part_error_dma8;
1025 output set_tx_ring_oflow_dma8;
1026
1027
1028 // DMA9 TXC Interface
1029 output dmc_txc_dma9_active;
1030 output dmc_txc_dma9_eoflist;
1031 output dmc_txc_dma9_gotnxtdesc;
1032 output [63:0] dmc_txc_dma9_descriptor;
1033 output dmc_txc_dma9_cacheready;
1034 output dmc_txc_dma9_partial;
1035 output dmc_txc_dma9_reset_scheduled;
1036 input txc_dmc_dma9_getnxtdesc;
1037 input txc_dmc_dma9_inc_head;
1038 input txc_dmc_dma9_reset_done;
1039
1040// DMA9 - PIO Interface
1041
1042 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma9_len;
1043 input [37:0] tx_rng_cfg_dma9_staddr;
1044 input [`PTR_WIDTH:0] tx_rng_tail_dma9 ;
1045 input tx_dma_cfg_dma9_rst;
1046 input tx_dma_cfg_dma9_stall;
1047 output [`PTR_WIDTH:0] tx_rng_head_dma9 ;
1048 output dma9_clear_reset;
1049 output tx_dma_cfg_dma9_stop_state;
1050 input tx_dma_cfg_dma9_stop;
1051 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA9;
1052
1053
1054 // DMA9 -FZC signals
1055 input [31:0] page0_mask_dma9;
1056 input [31:0] page0_value_dma9;
1057 input [31:0] page0_reloc_dma9;
1058 input page0_valid_dma9;
1059 input [31:0] page1_mask_dma9;
1060 input [31:0] page1_value_dma9;
1061 input [31:0] page1_reloc_dma9;
1062 input page1_valid_dma9;
1063 input [19:0] dmc_txc_dma9_page_handle;
1064 input [1:0] dmc_txc_dma9_func_num;
1065
1066
1067
1068
1069// DMA9 ERROR related signals to PIO block
1070
1071 output set_pref_buf_par_err_dma9;
1072 output set_pkt_part_err_dma9;
1073 output [43:0] pkt_part_error_address_dma9;
1074 output set_conf_part_error_dma9;
1075 output set_tx_ring_oflow_dma9;
1076
1077
1078 // DMA10 TXC Interface
1079 output dmc_txc_dma10_active;
1080 output dmc_txc_dma10_eoflist;
1081 output dmc_txc_dma10_gotnxtdesc;
1082 output [63:0] dmc_txc_dma10_descriptor;
1083 output dmc_txc_dma10_cacheready;
1084 output dmc_txc_dma10_partial;
1085 output dmc_txc_dma10_reset_scheduled;
1086 input txc_dmc_dma10_getnxtdesc;
1087 input txc_dmc_dma10_inc_head;
1088 input txc_dmc_dma10_reset_done;
1089
1090// DMA10 - PIO Interface
1091
1092 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma10_len;
1093 input [37:0] tx_rng_cfg_dma10_staddr;
1094 input [`PTR_WIDTH:0] tx_rng_tail_dma10 ;
1095 input tx_dma_cfg_dma10_rst;
1096 input tx_dma_cfg_dma10_stall;
1097 output [`PTR_WIDTH:0] tx_rng_head_dma10 ;
1098 output dma10_clear_reset;
1099 output tx_dma_cfg_dma10_stop_state;
1100 input tx_dma_cfg_dma10_stop;
1101 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA10;
1102
1103
1104 // DMA10 -FZC signals
1105 input [31:0] page0_mask_dma10;
1106 input [31:0] page0_value_dma10;
1107 input [31:0] page0_reloc_dma10;
1108 input page0_valid_dma10;
1109 input [31:0] page1_mask_dma10;
1110 input [31:0] page1_value_dma10;
1111 input [31:0] page1_reloc_dma10;
1112 input page1_valid_dma10;
1113 input [19:0] dmc_txc_dma10_page_handle;
1114 input [1:0] dmc_txc_dma10_func_num;
1115
1116
1117
1118
1119// DMA10 ERROR related signals to PIO block
1120
1121 output set_pref_buf_par_err_dma10;
1122 output set_pkt_part_err_dma10;
1123 output [43:0] pkt_part_error_address_dma10;
1124 output set_conf_part_error_dma10;
1125 output set_tx_ring_oflow_dma10;
1126
1127
1128 // DMA11 TXC Interface
1129 output dmc_txc_dma11_active;
1130 output dmc_txc_dma11_eoflist;
1131 output dmc_txc_dma11_gotnxtdesc;
1132 output [63:0] dmc_txc_dma11_descriptor;
1133 output dmc_txc_dma11_cacheready;
1134 output dmc_txc_dma11_partial;
1135 output dmc_txc_dma11_reset_scheduled;
1136 input txc_dmc_dma11_getnxtdesc;
1137 input txc_dmc_dma11_inc_head;
1138 input txc_dmc_dma11_reset_done;
1139
1140// DMA11 - PIO Interface
1141
1142 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma11_len;
1143 input [37:0] tx_rng_cfg_dma11_staddr;
1144 input [`PTR_WIDTH:0] tx_rng_tail_dma11 ;
1145 input tx_dma_cfg_dma11_rst;
1146 input tx_dma_cfg_dma11_stall;
1147 output [`PTR_WIDTH:0] tx_rng_head_dma11 ;
1148 output dma11_clear_reset;
1149 output tx_dma_cfg_dma11_stop_state;
1150 input tx_dma_cfg_dma11_stop;
1151 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA11;
1152
1153
1154 // DMA11 -FZC signals
1155 input [31:0] page0_mask_dma11;
1156 input [31:0] page0_value_dma11;
1157 input [31:0] page0_reloc_dma11;
1158 input page0_valid_dma11;
1159 input [31:0] page1_mask_dma11;
1160 input [31:0] page1_value_dma11;
1161 input [31:0] page1_reloc_dma11;
1162 input page1_valid_dma11;
1163 input [19:0] dmc_txc_dma11_page_handle;
1164 input [1:0] dmc_txc_dma11_func_num;
1165
1166
1167
1168
1169// DMA11 ERROR related signals to PIO block
1170
1171 output set_pref_buf_par_err_dma11;
1172 output set_pkt_part_err_dma11;
1173 output [43:0] pkt_part_error_address_dma11;
1174 output set_conf_part_error_dma11;
1175 output set_tx_ring_oflow_dma11;
1176
1177
1178 // DMA12 TXC Interface
1179 output dmc_txc_dma12_active;
1180 output dmc_txc_dma12_eoflist;
1181 output dmc_txc_dma12_gotnxtdesc;
1182 output [63:0] dmc_txc_dma12_descriptor;
1183 output dmc_txc_dma12_cacheready;
1184 output dmc_txc_dma12_partial;
1185 output dmc_txc_dma12_reset_scheduled;
1186 input txc_dmc_dma12_getnxtdesc;
1187 input txc_dmc_dma12_inc_head;
1188 input txc_dmc_dma12_reset_done;
1189
1190// DMA12 - PIO Interface
1191
1192 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma12_len;
1193 input [37:0] tx_rng_cfg_dma12_staddr;
1194 input [`PTR_WIDTH:0] tx_rng_tail_dma12 ;
1195 input tx_dma_cfg_dma12_rst;
1196 input tx_dma_cfg_dma12_stall;
1197 output [`PTR_WIDTH:0] tx_rng_head_dma12 ;
1198 output dma12_clear_reset;
1199 output tx_dma_cfg_dma12_stop_state;
1200 input tx_dma_cfg_dma12_stop;
1201 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA12;
1202
1203
1204 // DMA12 -FZC signals
1205 input [31:0] page0_mask_dma12;
1206 input [31:0] page0_value_dma12;
1207 input [31:0] page0_reloc_dma12;
1208 input page0_valid_dma12;
1209 input [31:0] page1_mask_dma12;
1210 input [31:0] page1_value_dma12;
1211 input [31:0] page1_reloc_dma12;
1212 input page1_valid_dma12;
1213 input [19:0] dmc_txc_dma12_page_handle;
1214 input [1:0] dmc_txc_dma12_func_num;
1215
1216
1217
1218
1219// DMA12 ERROR related signals to PIO block
1220
1221 output set_pref_buf_par_err_dma12;
1222 output set_pkt_part_err_dma12;
1223 output [43:0] pkt_part_error_address_dma12;
1224 output set_conf_part_error_dma12;
1225 output set_tx_ring_oflow_dma12;
1226
1227
1228 // DMA13 TXC Interface
1229 output dmc_txc_dma13_active;
1230 output dmc_txc_dma13_eoflist;
1231 output dmc_txc_dma13_gotnxtdesc;
1232 output [63:0] dmc_txc_dma13_descriptor;
1233 output dmc_txc_dma13_cacheready;
1234 output dmc_txc_dma13_partial;
1235 output dmc_txc_dma13_reset_scheduled;
1236 input txc_dmc_dma13_getnxtdesc;
1237 input txc_dmc_dma13_inc_head;
1238 input txc_dmc_dma13_reset_done;
1239
1240// DMA13 - PIO Interface
1241
1242 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma13_len;
1243 input [37:0] tx_rng_cfg_dma13_staddr;
1244 input [`PTR_WIDTH:0] tx_rng_tail_dma13 ;
1245 input tx_dma_cfg_dma13_rst;
1246 input tx_dma_cfg_dma13_stall;
1247 output [`PTR_WIDTH:0] tx_rng_head_dma13 ;
1248 output dma13_clear_reset;
1249 output tx_dma_cfg_dma13_stop_state;
1250 input tx_dma_cfg_dma13_stop;
1251 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA13;
1252
1253
1254 // DMA13 -FZC signals
1255 input [31:0] page0_mask_dma13;
1256 input [31:0] page0_value_dma13;
1257 input [31:0] page0_reloc_dma13;
1258 input page0_valid_dma13;
1259 input [31:0] page1_mask_dma13;
1260 input [31:0] page1_value_dma13;
1261 input [31:0] page1_reloc_dma13;
1262 input page1_valid_dma13;
1263 input [19:0] dmc_txc_dma13_page_handle;
1264 input [1:0] dmc_txc_dma13_func_num;
1265
1266
1267
1268
1269// DMA13 ERROR related signals to PIO block
1270
1271 output set_pref_buf_par_err_dma13;
1272 output set_pkt_part_err_dma13;
1273 output [43:0] pkt_part_error_address_dma13;
1274 output set_conf_part_error_dma13;
1275 output set_tx_ring_oflow_dma13;
1276
1277
1278 // DMA14 TXC Interface
1279 output dmc_txc_dma14_active;
1280 output dmc_txc_dma14_eoflist;
1281 output dmc_txc_dma14_gotnxtdesc;
1282 output [63:0] dmc_txc_dma14_descriptor;
1283 output dmc_txc_dma14_cacheready;
1284 output dmc_txc_dma14_partial;
1285 output dmc_txc_dma14_reset_scheduled;
1286 input txc_dmc_dma14_getnxtdesc;
1287 input txc_dmc_dma14_inc_head;
1288 input txc_dmc_dma14_reset_done;
1289
1290// DMA14 - PIO Interface
1291
1292 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma14_len;
1293 input [37:0] tx_rng_cfg_dma14_staddr;
1294 input [`PTR_WIDTH:0] tx_rng_tail_dma14 ;
1295 input tx_dma_cfg_dma14_rst;
1296 input tx_dma_cfg_dma14_stall;
1297 output [`PTR_WIDTH:0] tx_rng_head_dma14 ;
1298 output dma14_clear_reset;
1299 output tx_dma_cfg_dma14_stop_state;
1300 input tx_dma_cfg_dma14_stop;
1301 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA14;
1302
1303
1304 // DMA14 -FZC signals
1305 input [31:0] page0_mask_dma14;
1306 input [31:0] page0_value_dma14;
1307 input [31:0] page0_reloc_dma14;
1308 input page0_valid_dma14;
1309 input [31:0] page1_mask_dma14;
1310 input [31:0] page1_value_dma14;
1311 input [31:0] page1_reloc_dma14;
1312 input page1_valid_dma14;
1313 input [19:0] dmc_txc_dma14_page_handle;
1314 input [1:0] dmc_txc_dma14_func_num;
1315
1316
1317
1318
1319// DMA14 ERROR related signals to PIO block
1320
1321 output set_pref_buf_par_err_dma14;
1322 output set_pkt_part_err_dma14;
1323 output [43:0] pkt_part_error_address_dma14;
1324 output set_conf_part_error_dma14;
1325 output set_tx_ring_oflow_dma14;
1326
1327
1328 // DMA15 TXC Interface
1329 output dmc_txc_dma15_active;
1330 output dmc_txc_dma15_eoflist;
1331 output dmc_txc_dma15_gotnxtdesc;
1332 output [63:0] dmc_txc_dma15_descriptor;
1333 output dmc_txc_dma15_cacheready;
1334 output dmc_txc_dma15_partial;
1335 output dmc_txc_dma15_reset_scheduled;
1336 input txc_dmc_dma15_getnxtdesc;
1337 input txc_dmc_dma15_inc_head;
1338 input txc_dmc_dma15_reset_done;
1339
1340// DMA15 - PIO Interface
1341
1342 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma15_len;
1343 input [37:0] tx_rng_cfg_dma15_staddr;
1344 input [`PTR_WIDTH:0] tx_rng_tail_dma15 ;
1345 input tx_dma_cfg_dma15_rst;
1346 input tx_dma_cfg_dma15_stall;
1347 output [`PTR_WIDTH:0] tx_rng_head_dma15 ;
1348 output dma15_clear_reset;
1349 output tx_dma_cfg_dma15_stop_state;
1350 input tx_dma_cfg_dma15_stop;
1351 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA15;
1352
1353
1354 // DMA15 -FZC signals
1355 input [31:0] page0_mask_dma15;
1356 input [31:0] page0_value_dma15;
1357 input [31:0] page0_reloc_dma15;
1358 input page0_valid_dma15;
1359 input [31:0] page1_mask_dma15;
1360 input [31:0] page1_value_dma15;
1361 input [31:0] page1_reloc_dma15;
1362 input page1_valid_dma15;
1363 input [19:0] dmc_txc_dma15_page_handle;
1364 input [1:0] dmc_txc_dma15_func_num;
1365
1366
1367
1368
1369// DMA15 ERROR related signals to PIO block
1370
1371 output set_pref_buf_par_err_dma15;
1372 output set_pkt_part_err_dma15;
1373 output [43:0] pkt_part_error_address_dma15;
1374 output set_conf_part_error_dma15;
1375 output set_tx_ring_oflow_dma15;
1376
1377
1378`ifdef NEPTUNE
1379 // DMA16 TXC Interface
1380 output dmc_txc_dma16_active;
1381 output dmc_txc_dma16_eoflist;
1382 output dmc_txc_dma16_gotnxtdesc;
1383 output [63:0] dmc_txc_dma16_descriptor;
1384 output dmc_txc_dma16_cacheready;
1385 output dmc_txc_dma16_partial;
1386 output dmc_txc_dma16_reset_scheduled;
1387 input txc_dmc_dma16_getnxtdesc;
1388 input txc_dmc_dma16_inc_head;
1389 input txc_dmc_dma16_reset_done;
1390
1391// DMA16 - PIO Interface
1392
1393 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma16_len;
1394 input [37:0] tx_rng_cfg_dma16_staddr;
1395 input [`PTR_WIDTH:0] tx_rng_tail_dma16 ;
1396 input tx_dma_cfg_dma16_rst;
1397 input tx_dma_cfg_dma16_stall;
1398 output [`PTR_WIDTH:0] tx_rng_head_dma16 ;
1399 output dma16_clear_reset;
1400 output tx_dma_cfg_dma16_stop_state;
1401 input tx_dma_cfg_dma16_stop;
1402 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA16;
1403
1404
1405 // DMA16 -FZC signals
1406 input [31:0] page0_mask_dma16;
1407 input [31:0] page0_value_dma16;
1408 input [31:0] page0_reloc_dma16;
1409 input page0_valid_dma16;
1410 input [31:0] page1_mask_dma16;
1411 input [31:0] page1_value_dma16;
1412 input [31:0] page1_reloc_dma16;
1413 input page1_valid_dma16;
1414 input [19:0] dmc_txc_dma16_page_handle;
1415 input [1:0] dmc_txc_dma16_func_num;
1416
1417
1418
1419
1420// DMA16 ERROR related signals to PIO block
1421
1422 output set_pref_buf_par_err_dma16;
1423 output set_pkt_part_err_dma16;
1424 output [43:0] pkt_part_error_address_dma16;
1425 output set_conf_part_error_dma16;
1426 output set_tx_ring_oflow_dma16;
1427
1428
1429 // DMA17 TXC Interface
1430 output dmc_txc_dma17_active;
1431 output dmc_txc_dma17_eoflist;
1432 output dmc_txc_dma17_gotnxtdesc;
1433 output [63:0] dmc_txc_dma17_descriptor;
1434 output dmc_txc_dma17_cacheready;
1435 output dmc_txc_dma17_partial;
1436 output dmc_txc_dma17_reset_scheduled;
1437 input txc_dmc_dma17_getnxtdesc;
1438 input txc_dmc_dma17_inc_head;
1439 input txc_dmc_dma17_reset_done;
1440
1441// DMA17 - PIO Interface
1442
1443 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma17_len;
1444 input [37:0] tx_rng_cfg_dma17_staddr;
1445 input [`PTR_WIDTH:0] tx_rng_tail_dma17 ;
1446 input tx_dma_cfg_dma17_rst;
1447 input tx_dma_cfg_dma17_stall;
1448 output [`PTR_WIDTH:0] tx_rng_head_dma17 ;
1449 output dma17_clear_reset;
1450 output tx_dma_cfg_dma17_stop_state;
1451 input tx_dma_cfg_dma17_stop;
1452 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA17;
1453
1454
1455 // DMA17 -FZC signals
1456 input [31:0] page0_mask_dma17;
1457 input [31:0] page0_value_dma17;
1458 input [31:0] page0_reloc_dma17;
1459 input page0_valid_dma17;
1460 input [31:0] page1_mask_dma17;
1461 input [31:0] page1_value_dma17;
1462 input [31:0] page1_reloc_dma17;
1463 input page1_valid_dma17;
1464 input [19:0] dmc_txc_dma17_page_handle;
1465 input [1:0] dmc_txc_dma17_func_num;
1466
1467
1468
1469
1470// DMA17 ERROR related signals to PIO block
1471
1472 output set_pref_buf_par_err_dma17;
1473 output set_pkt_part_err_dma17;
1474 output [43:0] pkt_part_error_address_dma17;
1475 output set_conf_part_error_dma17;
1476 output set_tx_ring_oflow_dma17;
1477
1478
1479 // DMA18 TXC Interface
1480 output dmc_txc_dma18_active;
1481 output dmc_txc_dma18_eoflist;
1482 output dmc_txc_dma18_gotnxtdesc;
1483 output [63:0] dmc_txc_dma18_descriptor;
1484 output dmc_txc_dma18_cacheready;
1485 output dmc_txc_dma18_partial;
1486 output dmc_txc_dma18_reset_scheduled;
1487 input txc_dmc_dma18_getnxtdesc;
1488 input txc_dmc_dma18_inc_head;
1489 input txc_dmc_dma18_reset_done;
1490
1491// DMA18 - PIO Interface
1492
1493 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma18_len;
1494 input [37:0] tx_rng_cfg_dma18_staddr;
1495 input [`PTR_WIDTH:0] tx_rng_tail_dma18 ;
1496 input tx_dma_cfg_dma18_rst;
1497 input tx_dma_cfg_dma18_stall;
1498 output [`PTR_WIDTH:0] tx_rng_head_dma18 ;
1499 output dma18_clear_reset;
1500 output tx_dma_cfg_dma18_stop_state;
1501 input tx_dma_cfg_dma18_stop;
1502 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA18;
1503
1504
1505 // DMA18 -FZC signals
1506 input [31:0] page0_mask_dma18;
1507 input [31:0] page0_value_dma18;
1508 input [31:0] page0_reloc_dma18;
1509 input page0_valid_dma18;
1510 input [31:0] page1_mask_dma18;
1511 input [31:0] page1_value_dma18;
1512 input [31:0] page1_reloc_dma18;
1513 input page1_valid_dma18;
1514 input [19:0] dmc_txc_dma18_page_handle;
1515 input [1:0] dmc_txc_dma18_func_num;
1516
1517
1518
1519
1520// DMA18 ERROR related signals to PIO block
1521
1522 output set_pref_buf_par_err_dma18;
1523 output set_pkt_part_err_dma18;
1524 output [43:0] pkt_part_error_address_dma18;
1525 output set_conf_part_error_dma18;
1526 output set_tx_ring_oflow_dma18;
1527
1528
1529 // DMA19 TXC Interface
1530 output dmc_txc_dma19_active;
1531 output dmc_txc_dma19_eoflist;
1532 output dmc_txc_dma19_gotnxtdesc;
1533 output [63:0] dmc_txc_dma19_descriptor;
1534 output dmc_txc_dma19_cacheready;
1535 output dmc_txc_dma19_partial;
1536 output dmc_txc_dma19_reset_scheduled;
1537 input txc_dmc_dma19_getnxtdesc;
1538 input txc_dmc_dma19_inc_head;
1539 input txc_dmc_dma19_reset_done;
1540
1541// DMA19 - PIO Interface
1542
1543 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma19_len;
1544 input [37:0] tx_rng_cfg_dma19_staddr;
1545 input [`PTR_WIDTH:0] tx_rng_tail_dma19 ;
1546 input tx_dma_cfg_dma19_rst;
1547 input tx_dma_cfg_dma19_stall;
1548 output [`PTR_WIDTH:0] tx_rng_head_dma19 ;
1549 output dma19_clear_reset;
1550 output tx_dma_cfg_dma19_stop_state;
1551 input tx_dma_cfg_dma19_stop;
1552 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA19;
1553
1554
1555 // DMA19 -FZC signals
1556 input [31:0] page0_mask_dma19;
1557 input [31:0] page0_value_dma19;
1558 input [31:0] page0_reloc_dma19;
1559 input page0_valid_dma19;
1560 input [31:0] page1_mask_dma19;
1561 input [31:0] page1_value_dma19;
1562 input [31:0] page1_reloc_dma19;
1563 input page1_valid_dma19;
1564 input [19:0] dmc_txc_dma19_page_handle;
1565 input [1:0] dmc_txc_dma19_func_num;
1566
1567
1568
1569
1570// DMA19 ERROR related signals to PIO block
1571
1572 output set_pref_buf_par_err_dma19;
1573 output set_pkt_part_err_dma19;
1574 output [43:0] pkt_part_error_address_dma19;
1575 output set_conf_part_error_dma19;
1576 output set_tx_ring_oflow_dma19;
1577
1578
1579 // DMA20 TXC Interface
1580 output dmc_txc_dma20_active;
1581 output dmc_txc_dma20_eoflist;
1582 output dmc_txc_dma20_gotnxtdesc;
1583 output [63:0] dmc_txc_dma20_descriptor;
1584 output dmc_txc_dma20_cacheready;
1585 output dmc_txc_dma20_partial;
1586 output dmc_txc_dma20_reset_scheduled;
1587 input txc_dmc_dma20_getnxtdesc;
1588 input txc_dmc_dma20_inc_head;
1589 input txc_dmc_dma20_reset_done;
1590
1591// DMA20 - PIO Interface
1592
1593 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma20_len;
1594 input [37:0] tx_rng_cfg_dma20_staddr;
1595 input [`PTR_WIDTH:0] tx_rng_tail_dma20 ;
1596 input tx_dma_cfg_dma20_rst;
1597 input tx_dma_cfg_dma20_stall;
1598 output [`PTR_WIDTH:0] tx_rng_head_dma20 ;
1599 output dma20_clear_reset;
1600 output tx_dma_cfg_dma20_stop_state;
1601 input tx_dma_cfg_dma20_stop;
1602 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA20;
1603
1604
1605 // DMA20 -FZC signals
1606 input [31:0] page0_mask_dma20;
1607 input [31:0] page0_value_dma20;
1608 input [31:0] page0_reloc_dma20;
1609 input page0_valid_dma20;
1610 input [31:0] page1_mask_dma20;
1611 input [31:0] page1_value_dma20;
1612 input [31:0] page1_reloc_dma20;
1613 input page1_valid_dma20;
1614 input [19:0] dmc_txc_dma20_page_handle;
1615 input [1:0] dmc_txc_dma20_func_num;
1616
1617
1618
1619
1620// DMA20 ERROR related signals to PIO block
1621
1622 output set_pref_buf_par_err_dma20;
1623 output set_pkt_part_err_dma20;
1624 output [43:0] pkt_part_error_address_dma20;
1625 output set_conf_part_error_dma20;
1626 output set_tx_ring_oflow_dma20;
1627
1628
1629 // DMA21 TXC Interface
1630 output dmc_txc_dma21_active;
1631 output dmc_txc_dma21_eoflist;
1632 output dmc_txc_dma21_gotnxtdesc;
1633 output [63:0] dmc_txc_dma21_descriptor;
1634 output dmc_txc_dma21_cacheready;
1635 output dmc_txc_dma21_partial;
1636 output dmc_txc_dma21_reset_scheduled;
1637 input txc_dmc_dma21_getnxtdesc;
1638 input txc_dmc_dma21_inc_head;
1639 input txc_dmc_dma21_reset_done;
1640
1641// DMA21 - PIO Interface
1642
1643 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma21_len;
1644 input [37:0] tx_rng_cfg_dma21_staddr;
1645 input [`PTR_WIDTH:0] tx_rng_tail_dma21 ;
1646 input tx_dma_cfg_dma21_rst;
1647 input tx_dma_cfg_dma21_stall;
1648 output [`PTR_WIDTH:0] tx_rng_head_dma21 ;
1649 output dma21_clear_reset;
1650 output tx_dma_cfg_dma21_stop_state;
1651 input tx_dma_cfg_dma21_stop;
1652 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA21;
1653
1654
1655 // DMA21 -FZC signals
1656 input [31:0] page0_mask_dma21;
1657 input [31:0] page0_value_dma21;
1658 input [31:0] page0_reloc_dma21;
1659 input page0_valid_dma21;
1660 input [31:0] page1_mask_dma21;
1661 input [31:0] page1_value_dma21;
1662 input [31:0] page1_reloc_dma21;
1663 input page1_valid_dma21;
1664 input [19:0] dmc_txc_dma21_page_handle;
1665 input [1:0] dmc_txc_dma21_func_num;
1666
1667
1668
1669
1670// DMA21 ERROR related signals to PIO block
1671
1672 output set_pref_buf_par_err_dma21;
1673 output set_pkt_part_err_dma21;
1674 output [43:0] pkt_part_error_address_dma21;
1675 output set_conf_part_error_dma21;
1676 output set_tx_ring_oflow_dma21;
1677
1678
1679 // DMA22 TXC Interface
1680 output dmc_txc_dma22_active;
1681 output dmc_txc_dma22_eoflist;
1682 output dmc_txc_dma22_gotnxtdesc;
1683 output [63:0] dmc_txc_dma22_descriptor;
1684 output dmc_txc_dma22_cacheready;
1685 output dmc_txc_dma22_partial;
1686 output dmc_txc_dma22_reset_scheduled;
1687 input txc_dmc_dma22_getnxtdesc;
1688 input txc_dmc_dma22_inc_head;
1689 input txc_dmc_dma22_reset_done;
1690
1691// DMA22 - PIO Interface
1692
1693 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma22_len;
1694 input [37:0] tx_rng_cfg_dma22_staddr;
1695 input [`PTR_WIDTH:0] tx_rng_tail_dma22 ;
1696 input tx_dma_cfg_dma22_rst;
1697 input tx_dma_cfg_dma22_stall;
1698 output [`PTR_WIDTH:0] tx_rng_head_dma22 ;
1699 output dma22_clear_reset;
1700 output tx_dma_cfg_dma22_stop_state;
1701 input tx_dma_cfg_dma22_stop;
1702 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA22;
1703
1704
1705 // DMA22 -FZC signals
1706 input [31:0] page0_mask_dma22;
1707 input [31:0] page0_value_dma22;
1708 input [31:0] page0_reloc_dma22;
1709 input page0_valid_dma22;
1710 input [31:0] page1_mask_dma22;
1711 input [31:0] page1_value_dma22;
1712 input [31:0] page1_reloc_dma22;
1713 input page1_valid_dma22;
1714 input [19:0] dmc_txc_dma22_page_handle;
1715 input [1:0] dmc_txc_dma22_func_num;
1716
1717
1718
1719
1720// DMA22 ERROR related signals to PIO block
1721
1722 output set_pref_buf_par_err_dma22;
1723 output set_pkt_part_err_dma22;
1724 output [43:0] pkt_part_error_address_dma22;
1725 output set_conf_part_error_dma22;
1726 output set_tx_ring_oflow_dma22;
1727
1728
1729 // DMA23 TXC Interface
1730 output dmc_txc_dma23_active;
1731 output dmc_txc_dma23_eoflist;
1732 output dmc_txc_dma23_gotnxtdesc;
1733 output [63:0] dmc_txc_dma23_descriptor;
1734 output dmc_txc_dma23_cacheready;
1735 output dmc_txc_dma23_partial;
1736 output dmc_txc_dma23_reset_scheduled;
1737 input txc_dmc_dma23_getnxtdesc;
1738 input txc_dmc_dma23_inc_head;
1739 input txc_dmc_dma23_reset_done;
1740
1741// DMA23 - PIO Interface
1742
1743 input [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma23_len;
1744 input [37:0] tx_rng_cfg_dma23_staddr;
1745 input [`PTR_WIDTH:0] tx_rng_tail_dma23 ;
1746 input tx_dma_cfg_dma23_rst;
1747 input tx_dma_cfg_dma23_stall;
1748 output [`PTR_WIDTH:0] tx_rng_head_dma23 ;
1749 output dma23_clear_reset;
1750 output tx_dma_cfg_dma23_stop_state;
1751 input tx_dma_cfg_dma23_stop;
1752 output [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA23;
1753
1754
1755 // DMA23 -FZC signals
1756 input [31:0] page0_mask_dma23;
1757 input [31:0] page0_value_dma23;
1758 input [31:0] page0_reloc_dma23;
1759 input page0_valid_dma23;
1760 input [31:0] page1_mask_dma23;
1761 input [31:0] page1_value_dma23;
1762 input [31:0] page1_reloc_dma23;
1763 input page1_valid_dma23;
1764 input [19:0] dmc_txc_dma23_page_handle;
1765 input [1:0] dmc_txc_dma23_func_num;
1766
1767
1768
1769
1770// DMA23 ERROR related signals to PIO block
1771
1772 output set_pref_buf_par_err_dma23;
1773 output set_pkt_part_err_dma23;
1774 output [43:0] pkt_part_error_address_dma23;
1775 output set_conf_part_error_dma23;
1776 output set_tx_ring_oflow_dma23;
1777
1778`endif // ifdef NEPTUNE
1779
1780
1781/*debug port*/
1782 output[31:0] dma0_debug_port;
1783 output[31:0] dma1_debug_port;
1784 output[31:0] dma2_debug_port;
1785 output[31:0] dma3_debug_port;
1786 output[31:0] dma4_debug_port;
1787 output[31:0] dma5_debug_port;
1788 output[31:0] dma6_debug_port;
1789 output[31:0] dma7_debug_port;
1790 output[31:0] dma8_debug_port;
1791 output[31:0] dma9_debug_port;
1792 output[31:0] dma10_debug_port;
1793 output[31:0] dma11_debug_port;
1794 output[31:0] dma12_debug_port;
1795 output[31:0] dma13_debug_port;
1796 output[31:0] dma14_debug_port;
1797 output[31:0] dma15_debug_port;
1798
1799`ifdef NEPTUNE
1800 output[31:0] dma16_debug_port;
1801 output[31:0] dma17_debug_port;
1802 output[31:0] dma18_debug_port;
1803 output[31:0] dma19_debug_port;
1804 output[31:0] dma20_debug_port;
1805 output[31:0] dma21_debug_port;
1806 output[31:0] dma22_debug_port;
1807 output[31:0] dma23_debug_port;
1808`else
1809`endif
1810
1811
1812
1813
1814
1815
1816 wire DMC_TxCache_SMX_Resp_Accept;
1817 wire [1:0] tdmc_arb1_req_func_num;
1818
1819 // TMP Wires
1820
1821 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma1_len;
1822 wire [37:0] tx_rng_cfg_dma1_staddr;
1823 wire [`PTR_WIDTH:0] tx_rng_tail_dma1 ;
1824 wire tx_dma_cfg_dma1_rst;
1825 wire tx_dma_cfg_dma1_stall;
1826 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma2_len;
1827 wire [37:0] tx_rng_cfg_dma2_staddr;
1828 wire [`PTR_WIDTH:0] tx_rng_tail_dma2 ;
1829 wire tx_dma_cfg_dma2_rst;
1830 wire tx_dma_cfg_dma2_stall;
1831 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma3_len;
1832 wire [37:0] tx_rng_cfg_dma3_staddr;
1833 wire [`PTR_WIDTH:0] tx_rng_tail_dma3 ;
1834 wire tx_dma_cfg_dma3_rst;
1835 wire tx_dma_cfg_dma3_stall;
1836 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma4_len;
1837 wire [37:0] tx_rng_cfg_dma4_staddr;
1838 wire [`PTR_WIDTH:0] tx_rng_tail_dma4 ;
1839 wire tx_dma_cfg_dma4_rst;
1840 wire tx_dma_cfg_dma4_stall;
1841 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma5_len;
1842 wire [37:0] tx_rng_cfg_dma5_staddr;
1843 wire [`PTR_WIDTH:0] tx_rng_tail_dma5 ;
1844 wire tx_dma_cfg_dma5_rst;
1845 wire tx_dma_cfg_dma5_stall;
1846 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma6_len;
1847 wire [37:0] tx_rng_cfg_dma6_staddr;
1848 wire [`PTR_WIDTH:0] tx_rng_tail_dma6 ;
1849 wire tx_dma_cfg_dma6_rst;
1850 wire tx_dma_cfg_dma6_stall;
1851 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma7_len;
1852 wire [37:0] tx_rng_cfg_dma7_staddr;
1853 wire [`PTR_WIDTH:0] tx_rng_tail_dma7 ;
1854 wire tx_dma_cfg_dma7_rst;
1855 wire tx_dma_cfg_dma7_stall;
1856 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma8_len;
1857 wire [37:0] tx_rng_cfg_dma8_staddr;
1858 wire [`PTR_WIDTH:0] tx_rng_tail_dma8 ;
1859 wire tx_dma_cfg_dma8_rst;
1860 wire tx_dma_cfg_dma8_stall;
1861 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma9_len;
1862 wire [37:0] tx_rng_cfg_dma9_staddr;
1863 wire [`PTR_WIDTH:0] tx_rng_tail_dma9 ;
1864 wire tx_dma_cfg_dma9_rst;
1865 wire tx_dma_cfg_dma9_stall;
1866 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma10_len;
1867 wire [37:0] tx_rng_cfg_dma10_staddr;
1868 wire [`PTR_WIDTH:0] tx_rng_tail_dma10 ;
1869 wire tx_dma_cfg_dma10_rst;
1870 wire tx_dma_cfg_dma10_stall;
1871 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma11_len;
1872 wire [37:0] tx_rng_cfg_dma11_staddr;
1873 wire [`PTR_WIDTH:0] tx_rng_tail_dma11 ;
1874 wire tx_dma_cfg_dma11_rst;
1875 wire tx_dma_cfg_dma11_stall;
1876 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma12_len;
1877 wire [37:0] tx_rng_cfg_dma12_staddr;
1878 wire [`PTR_WIDTH:0] tx_rng_tail_dma12 ;
1879 wire tx_dma_cfg_dma12_rst;
1880 wire tx_dma_cfg_dma12_stall;
1881 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma13_len;
1882 wire [37:0] tx_rng_cfg_dma13_staddr;
1883 wire [`PTR_WIDTH:0] tx_rng_tail_dma13 ;
1884 wire tx_dma_cfg_dma13_rst;
1885 wire tx_dma_cfg_dma13_stall;
1886 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma14_len;
1887 wire [37:0] tx_rng_cfg_dma14_staddr;
1888 wire [`PTR_WIDTH:0] tx_rng_tail_dma14 ;
1889 wire tx_dma_cfg_dma14_rst;
1890 wire tx_dma_cfg_dma14_stall;
1891 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma15_len;
1892 wire [37:0] tx_rng_cfg_dma15_staddr;
1893 wire [`PTR_WIDTH:0] tx_rng_tail_dma15 ;
1894 wire tx_dma_cfg_dma15_rst;
1895 wire tx_dma_cfg_dma15_stall;
1896`ifdef NEPTUNE
1897
1898 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma16_len;
1899 wire [37:0] tx_rng_cfg_dma16_staddr;
1900 wire [`PTR_WIDTH:0] tx_rng_tail_dma16 ;
1901 wire tx_dma_cfg_dma16_rst;
1902 wire tx_dma_cfg_dma16_stall;
1903 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma17_len;
1904 wire [37:0] tx_rng_cfg_dma17_staddr;
1905 wire [`PTR_WIDTH:0] tx_rng_tail_dma17 ;
1906 wire tx_dma_cfg_dma17_rst;
1907 wire tx_dma_cfg_dma17_stall;
1908 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma18_len;
1909 wire [37:0] tx_rng_cfg_dma18_staddr;
1910 wire [`PTR_WIDTH:0] tx_rng_tail_dma18 ;
1911 wire tx_dma_cfg_dma18_rst;
1912 wire tx_dma_cfg_dma18_stall;
1913 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma19_len;
1914 wire [37:0] tx_rng_cfg_dma19_staddr;
1915 wire [`PTR_WIDTH:0] tx_rng_tail_dma19 ;
1916 wire tx_dma_cfg_dma19_rst;
1917 wire tx_dma_cfg_dma19_stall;
1918 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma20_len;
1919 wire [37:0] tx_rng_cfg_dma20_staddr;
1920 wire [`PTR_WIDTH:0] tx_rng_tail_dma20 ;
1921 wire tx_dma_cfg_dma20_rst;
1922 wire tx_dma_cfg_dma20_stall;
1923 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma21_len;
1924 wire [37:0] tx_rng_cfg_dma21_staddr;
1925 wire [`PTR_WIDTH:0] tx_rng_tail_dma21 ;
1926 wire tx_dma_cfg_dma21_rst;
1927 wire tx_dma_cfg_dma21_stall;
1928 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma22_len;
1929 wire [37:0] tx_rng_cfg_dma22_staddr;
1930 wire [`PTR_WIDTH:0] tx_rng_tail_dma22 ;
1931 wire tx_dma_cfg_dma22_rst;
1932 wire tx_dma_cfg_dma22_stall;
1933 wire [`RNG_LENGTH_WIDTH -1 :0] tx_rng_cfg_dma23_len;
1934 wire [37:0] tx_rng_cfg_dma23_staddr;
1935 wire [`PTR_WIDTH:0] tx_rng_tail_dma23 ;
1936 wire tx_dma_cfg_dma23_rst;
1937 wire tx_dma_cfg_dma23_stall;
1938`endif // ifdef NEPTUNE
1939
1940 wire[31:0] dma0_debug_port;
1941 wire[31:0] dma1_debug_port;
1942 wire[31:0] dma2_debug_port;
1943 wire[31:0] dma3_debug_port;
1944 wire[31:0] dma4_debug_port;
1945 wire[31:0] dma5_debug_port;
1946 wire[31:0] dma6_debug_port;
1947 wire[31:0] dma7_debug_port;
1948 wire[31:0] dma8_debug_port;
1949 wire[31:0] dma9_debug_port;
1950 wire[31:0] dma10_debug_port;
1951 wire[31:0] dma11_debug_port;
1952 wire[31:0] dma12_debug_port;
1953 wire[31:0] dma13_debug_port;
1954 wire[31:0] dma14_debug_port;
1955 wire[31:0] dma15_debug_port;
1956
1957`ifdef NEPTUNE
1958 wire[31:0] dma16_debug_port;
1959 wire[31:0] dma17_debug_port;
1960 wire[31:0] dma18_debug_port;
1961 wire[31:0] dma19_debug_port;
1962 wire[31:0] dma20_debug_port;
1963 wire[31:0] dma21_debug_port;
1964 wire[31:0] dma22_debug_port;
1965 wire[31:0] dma23_debug_port;
1966`else
1967`endif
1968
1969
1970
1971
1972
1973
1974 /*--------------------------------------------------------------*/
1975 // Wires & Registers
1976 /*--------------------------------------------------------------*/
1977
1978 wire [31:0] DMAs_AvailableFor_Fetch;
1979
1980
1981
1982 wire [3:0] TxCacheFetchState;
1983
1984 wire [4:0] meta_resp_dma_num;
1985 wire [4:0] DMANumToReq;
1986 wire [4:0] DMANumToReqArbOut;
1987
1988 wire [`NO_OF_DMAS - 1 :0] updateCacheWritePtrs;
1989 wire [`NO_OF_DMAS - 1 :0] receivedErrorResp;
1990
1991 wire [3:0] NoOfCacheWritesDispatched; // Max of 2 CacheLines- - 8 entries in the local cache
1992
1993 wire ArbDone;
1994 wire choose_available_dmas;
1995 wire [`NO_OF_DMAS - 1 :0] updateCacheContext;
1996
1997 wire DMC_TxCache_SMX_Req;
1998 wire [63:0] DMC_TxCache_SMX_Req_Address;
1999 wire [7:0] DMC_TxCache_SMX_Req_Cmd;
2000 wire [4:0] DMC_TxCache_SMX_Req_DMA_Num;
2001 wire [13:0] DMC_TxCache_SMX_Req_Length;
2002 wire [1:0] DMC_TxCache_SMX_Req_Port_Num;
2003
2004
2005
2006 wire [63:0] dmc_txc_dma0_descriptor;
2007 wire [63:0] dmc_txc_dma1_descriptor;
2008 wire [63:0] dmc_txc_dma2_descriptor;
2009 wire [63:0] dmc_txc_dma3_descriptor;
2010 wire [63:0] dmc_txc_dma4_descriptor;
2011 wire [63:0] dmc_txc_dma5_descriptor;
2012 wire [63:0] dmc_txc_dma6_descriptor;
2013 wire [63:0] dmc_txc_dma7_descriptor;
2014 wire [63:0] dmc_txc_dma8_descriptor;
2015 wire [63:0] dmc_txc_dma9_descriptor;
2016 wire [63:0] dmc_txc_dma10_descriptor;
2017 wire [63:0] dmc_txc_dma11_descriptor;
2018 wire [63:0] dmc_txc_dma12_descriptor;
2019 wire [63:0] dmc_txc_dma13_descriptor;
2020 wire [63:0] dmc_txc_dma14_descriptor;
2021 wire [63:0] dmc_txc_dma15_descriptor;
2022`ifdef NEPTUNE
2023
2024 wire [63:0] dmc_txc_dma16_descriptor;
2025 wire [63:0] dmc_txc_dma17_descriptor;
2026 wire [63:0] dmc_txc_dma18_descriptor;
2027 wire [63:0] dmc_txc_dma19_descriptor;
2028 wire [63:0] dmc_txc_dma20_descriptor;
2029 wire [63:0] dmc_txc_dma21_descriptor;
2030 wire [63:0] dmc_txc_dma22_descriptor;
2031 wire [63:0] dmc_txc_dma23_descriptor;
2032`endif // ifdef NEPTUNE
2033
2034
2035
2036
2037
2038
2039
2040
2041 // Check the exact size of the cache
2042 wire [7:0] DMA_TxCacheReadPtr;
2043 wire [7:0] DMA_TxCacheWritePtr;
2044 wire DMA_TxCacheWrite;
2045 wire DMA_TxCacheRead;
2046 wire [4:0] NoOfValidEntries ; // No Of valid descriptors written into the cache - a max of 16
2047 wire [127:0] DMA_TxCacheWriteData;// ???
2048 wire [127:0] DMA_TxCacheReadData;// ???
2049 wire [3:0] DMA_TxCacheTags;// ???
2050 wire [3:0] DMA_TxCacheWriteEntriesValid;
2051
2052
2053
2054 wire LatchDMAPtrs;
2055
2056
2057
2058 wire [4:0] NoOfFreeSpaceInCache;
2059 wire ShadowRingWrap;
2060
2061 // new regs for REORDER
2062 wire [3:0] meta_resp_address;
2063
2064
2065
2066 /*--------------------------------------------------------------*/
2067 // Parameters and Defines
2068 /*--------------------------------------------------------------*/
2069
2070
2071 wire [63:0] DMA_AddressToReq_ff ;
2072
2073 // DMA0
2074 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA0;
2075 wire [63:0] DMA0_Address;
2076 wire DMA0_Ring_Wrapped;
2077 wire [`PTR_WIDTH - 1 :0] DMA0_RingLength;
2078 wire DMA0CacheEntryValid;
2079 wire dmc_txc_dma0_active;
2080 wire dmc_txc_dma0_eoflist;
2081 wire [3:0] DMA0_EmptySpace ;
2082 wire [`PTR_WIDTH:0] tx_rng_head_dma0;
2083 wire DMA0_AvailableFor_Fetch;
2084 wire DMA0_ReqPending;
2085 wire [4:0] DMA0_EntriesValid;
2086 wire DMA0_CacheEmpty;
2087 wire [3:0] DMA0_CacheReadPtr;
2088 wire [3:0] DMA0_CacheWritePtrReOrder;
2089 wire IncrDMA0RdPtr;
2090 wire inc_DMA0HeadShadow;
2091 wire ResetDMA0RdPtr;
2092 wire DMA0_CacheReadReq;
2093 wire DMA0_CacheReadGnt;
2094
2095
2096 // DMA1
2097 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA1;
2098 wire [63:0] DMA1_Address;
2099 wire DMA1_Ring_Wrapped;
2100 wire [`PTR_WIDTH - 1 :0] DMA1_RingLength;
2101 wire DMA1CacheEntryValid;
2102 wire dmc_txc_dma1_active;
2103 wire dmc_txc_dma1_eoflist;
2104 wire [3:0] DMA1_EmptySpace ;
2105 wire [`PTR_WIDTH:0] tx_rng_head_dma1;
2106 wire DMA1_AvailableFor_Fetch;
2107 wire DMA1_ReqPending;
2108 wire [4:0] DMA1_EntriesValid;
2109 wire DMA1_CacheEmpty;
2110 wire [3:0] DMA1_CacheReadPtr;
2111 wire [3:0] DMA1_CacheWritePtrReOrder;
2112 wire IncrDMA1RdPtr;
2113 wire inc_DMA1HeadShadow;
2114 wire ResetDMA1RdPtr;
2115 wire DMA1_CacheReadReq;
2116 wire DMA1_CacheReadGnt;
2117
2118
2119 // DMA2
2120 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA2;
2121 wire [63:0] DMA2_Address;
2122 wire DMA2_Ring_Wrapped;
2123 wire [`PTR_WIDTH - 1 :0] DMA2_RingLength;
2124 wire DMA2CacheEntryValid;
2125 wire dmc_txc_dma2_active;
2126 wire dmc_txc_dma2_eoflist;
2127 wire [3:0] DMA2_EmptySpace ;
2128 wire [`PTR_WIDTH:0] tx_rng_head_dma2;
2129 wire DMA2_AvailableFor_Fetch;
2130 wire DMA2_ReqPending;
2131 wire [4:0] DMA2_EntriesValid;
2132 wire DMA2_CacheEmpty;
2133 wire [3:0] DMA2_CacheReadPtr;
2134 wire [3:0] DMA2_CacheWritePtrReOrder;
2135 wire IncrDMA2RdPtr;
2136 wire inc_DMA2HeadShadow;
2137 wire ResetDMA2RdPtr;
2138 wire DMA2_CacheReadReq;
2139 wire DMA2_CacheReadGnt;
2140
2141
2142 // DMA3
2143 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA3;
2144 wire [63:0] DMA3_Address;
2145 wire DMA3_Ring_Wrapped;
2146 wire [`PTR_WIDTH - 1 :0] DMA3_RingLength;
2147 wire DMA3CacheEntryValid;
2148 wire dmc_txc_dma3_active;
2149 wire dmc_txc_dma3_eoflist;
2150 wire [3:0] DMA3_EmptySpace ;
2151 wire [`PTR_WIDTH:0] tx_rng_head_dma3;
2152 wire DMA3_AvailableFor_Fetch;
2153 wire DMA3_ReqPending;
2154 wire [4:0] DMA3_EntriesValid;
2155 wire DMA3_CacheEmpty;
2156 wire [3:0] DMA3_CacheReadPtr;
2157 wire [3:0] DMA3_CacheWritePtrReOrder;
2158 wire IncrDMA3RdPtr;
2159 wire inc_DMA3HeadShadow;
2160 wire ResetDMA3RdPtr;
2161 wire DMA3_CacheReadReq;
2162 wire DMA3_CacheReadGnt;
2163
2164
2165 // DMA4
2166 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA4;
2167 wire [63:0] DMA4_Address;
2168 wire DMA4_Ring_Wrapped;
2169 wire [`PTR_WIDTH - 1 :0] DMA4_RingLength;
2170 wire DMA4CacheEntryValid;
2171 wire dmc_txc_dma4_active;
2172 wire dmc_txc_dma4_eoflist;
2173 wire [3:0] DMA4_EmptySpace ;
2174 wire [`PTR_WIDTH:0] tx_rng_head_dma4;
2175 wire DMA4_AvailableFor_Fetch;
2176 wire DMA4_ReqPending;
2177 wire [4:0] DMA4_EntriesValid;
2178 wire DMA4_CacheEmpty;
2179 wire [3:0] DMA4_CacheReadPtr;
2180 wire [3:0] DMA4_CacheWritePtrReOrder;
2181 wire IncrDMA4RdPtr;
2182 wire inc_DMA4HeadShadow;
2183 wire ResetDMA4RdPtr;
2184 wire DMA4_CacheReadReq;
2185 wire DMA4_CacheReadGnt;
2186
2187
2188 // DMA5
2189 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA5;
2190 wire [63:0] DMA5_Address;
2191 wire DMA5_Ring_Wrapped;
2192 wire [`PTR_WIDTH - 1 :0] DMA5_RingLength;
2193 wire DMA5CacheEntryValid;
2194 wire dmc_txc_dma5_active;
2195 wire dmc_txc_dma5_eoflist;
2196 wire [3:0] DMA5_EmptySpace ;
2197 wire [`PTR_WIDTH:0] tx_rng_head_dma5;
2198 wire DMA5_AvailableFor_Fetch;
2199 wire DMA5_ReqPending;
2200 wire [4:0] DMA5_EntriesValid;
2201 wire DMA5_CacheEmpty;
2202 wire [3:0] DMA5_CacheReadPtr;
2203 wire [3:0] DMA5_CacheWritePtrReOrder;
2204 wire IncrDMA5RdPtr;
2205 wire inc_DMA5HeadShadow;
2206 wire ResetDMA5RdPtr;
2207 wire DMA5_CacheReadReq;
2208 wire DMA5_CacheReadGnt;
2209
2210
2211 // DMA6
2212 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA6;
2213 wire [63:0] DMA6_Address;
2214 wire DMA6_Ring_Wrapped;
2215 wire [`PTR_WIDTH - 1 :0] DMA6_RingLength;
2216 wire DMA6CacheEntryValid;
2217 wire dmc_txc_dma6_active;
2218 wire dmc_txc_dma6_eoflist;
2219 wire [3:0] DMA6_EmptySpace ;
2220 wire [`PTR_WIDTH:0] tx_rng_head_dma6;
2221 wire DMA6_AvailableFor_Fetch;
2222 wire DMA6_ReqPending;
2223 wire [4:0] DMA6_EntriesValid;
2224 wire DMA6_CacheEmpty;
2225 wire [3:0] DMA6_CacheReadPtr;
2226 wire [3:0] DMA6_CacheWritePtrReOrder;
2227 wire IncrDMA6RdPtr;
2228 wire inc_DMA6HeadShadow;
2229 wire ResetDMA6RdPtr;
2230 wire DMA6_CacheReadReq;
2231 wire DMA6_CacheReadGnt;
2232
2233
2234 // DMA7
2235 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA7;
2236 wire [63:0] DMA7_Address;
2237 wire DMA7_Ring_Wrapped;
2238 wire [`PTR_WIDTH - 1 :0] DMA7_RingLength;
2239 wire DMA7CacheEntryValid;
2240 wire dmc_txc_dma7_active;
2241 wire dmc_txc_dma7_eoflist;
2242 wire [3:0] DMA7_EmptySpace ;
2243 wire [`PTR_WIDTH:0] tx_rng_head_dma7;
2244 wire DMA7_AvailableFor_Fetch;
2245 wire DMA7_ReqPending;
2246 wire [4:0] DMA7_EntriesValid;
2247 wire DMA7_CacheEmpty;
2248 wire [3:0] DMA7_CacheReadPtr;
2249 wire [3:0] DMA7_CacheWritePtrReOrder;
2250 wire IncrDMA7RdPtr;
2251 wire inc_DMA7HeadShadow;
2252 wire ResetDMA7RdPtr;
2253 wire DMA7_CacheReadReq;
2254 wire DMA7_CacheReadGnt;
2255
2256
2257 // DMA8
2258 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA8;
2259 wire [63:0] DMA8_Address;
2260 wire DMA8_Ring_Wrapped;
2261 wire [`PTR_WIDTH - 1 :0] DMA8_RingLength;
2262 wire DMA8CacheEntryValid;
2263 wire dmc_txc_dma8_active;
2264 wire dmc_txc_dma8_eoflist;
2265 wire [3:0] DMA8_EmptySpace ;
2266 wire [`PTR_WIDTH:0] tx_rng_head_dma8;
2267 wire DMA8_AvailableFor_Fetch;
2268 wire DMA8_ReqPending;
2269 wire [4:0] DMA8_EntriesValid;
2270 wire DMA8_CacheEmpty;
2271 wire [3:0] DMA8_CacheReadPtr;
2272 wire [3:0] DMA8_CacheWritePtrReOrder;
2273 wire IncrDMA8RdPtr;
2274 wire inc_DMA8HeadShadow;
2275 wire ResetDMA8RdPtr;
2276 wire DMA8_CacheReadReq;
2277 wire DMA8_CacheReadGnt;
2278
2279
2280 // DMA9
2281 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA9;
2282 wire [63:0] DMA9_Address;
2283 wire DMA9_Ring_Wrapped;
2284 wire [`PTR_WIDTH - 1 :0] DMA9_RingLength;
2285 wire DMA9CacheEntryValid;
2286 wire dmc_txc_dma9_active;
2287 wire dmc_txc_dma9_eoflist;
2288 wire [3:0] DMA9_EmptySpace ;
2289 wire [`PTR_WIDTH:0] tx_rng_head_dma9;
2290 wire DMA9_AvailableFor_Fetch;
2291 wire DMA9_ReqPending;
2292 wire [4:0] DMA9_EntriesValid;
2293 wire DMA9_CacheEmpty;
2294 wire [3:0] DMA9_CacheReadPtr;
2295 wire [3:0] DMA9_CacheWritePtrReOrder;
2296 wire IncrDMA9RdPtr;
2297 wire inc_DMA9HeadShadow;
2298 wire ResetDMA9RdPtr;
2299 wire DMA9_CacheReadReq;
2300 wire DMA9_CacheReadGnt;
2301
2302
2303 // DMA10
2304 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA10;
2305 wire [63:0] DMA10_Address;
2306 wire DMA10_Ring_Wrapped;
2307 wire [`PTR_WIDTH - 1 :0] DMA10_RingLength;
2308 wire DMA10CacheEntryValid;
2309 wire dmc_txc_dma10_active;
2310 wire dmc_txc_dma10_eoflist;
2311 wire [3:0] DMA10_EmptySpace ;
2312 wire [`PTR_WIDTH:0] tx_rng_head_dma10;
2313 wire DMA10_AvailableFor_Fetch;
2314 wire DMA10_ReqPending;
2315 wire [4:0] DMA10_EntriesValid;
2316 wire DMA10_CacheEmpty;
2317 wire [3:0] DMA10_CacheReadPtr;
2318 wire [3:0] DMA10_CacheWritePtrReOrder;
2319 wire IncrDMA10RdPtr;
2320 wire inc_DMA10HeadShadow;
2321 wire ResetDMA10RdPtr;
2322 wire DMA10_CacheReadReq;
2323 wire DMA10_CacheReadGnt;
2324
2325
2326 // DMA11
2327 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA11;
2328 wire [63:0] DMA11_Address;
2329 wire DMA11_Ring_Wrapped;
2330 wire [`PTR_WIDTH - 1 :0] DMA11_RingLength;
2331 wire DMA11CacheEntryValid;
2332 wire dmc_txc_dma11_active;
2333 wire dmc_txc_dma11_eoflist;
2334 wire [3:0] DMA11_EmptySpace ;
2335 wire [`PTR_WIDTH:0] tx_rng_head_dma11;
2336 wire DMA11_AvailableFor_Fetch;
2337 wire DMA11_ReqPending;
2338 wire [4:0] DMA11_EntriesValid;
2339 wire DMA11_CacheEmpty;
2340 wire [3:0] DMA11_CacheReadPtr;
2341 wire [3:0] DMA11_CacheWritePtrReOrder;
2342 wire IncrDMA11RdPtr;
2343 wire inc_DMA11HeadShadow;
2344 wire ResetDMA11RdPtr;
2345 wire DMA11_CacheReadReq;
2346 wire DMA11_CacheReadGnt;
2347
2348
2349 // DMA12
2350 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA12;
2351 wire [63:0] DMA12_Address;
2352 wire DMA12_Ring_Wrapped;
2353 wire [`PTR_WIDTH - 1 :0] DMA12_RingLength;
2354 wire DMA12CacheEntryValid;
2355 wire dmc_txc_dma12_active;
2356 wire dmc_txc_dma12_eoflist;
2357 wire [3:0] DMA12_EmptySpace ;
2358 wire [`PTR_WIDTH:0] tx_rng_head_dma12;
2359 wire DMA12_AvailableFor_Fetch;
2360 wire DMA12_ReqPending;
2361 wire [4:0] DMA12_EntriesValid;
2362 wire DMA12_CacheEmpty;
2363 wire [3:0] DMA12_CacheReadPtr;
2364 wire [3:0] DMA12_CacheWritePtrReOrder;
2365 wire IncrDMA12RdPtr;
2366 wire inc_DMA12HeadShadow;
2367 wire ResetDMA12RdPtr;
2368 wire DMA12_CacheReadReq;
2369 wire DMA12_CacheReadGnt;
2370
2371
2372 // DMA13
2373 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA13;
2374 wire [63:0] DMA13_Address;
2375 wire DMA13_Ring_Wrapped;
2376 wire [`PTR_WIDTH - 1 :0] DMA13_RingLength;
2377 wire DMA13CacheEntryValid;
2378 wire dmc_txc_dma13_active;
2379 wire dmc_txc_dma13_eoflist;
2380 wire [3:0] DMA13_EmptySpace ;
2381 wire [`PTR_WIDTH:0] tx_rng_head_dma13;
2382 wire DMA13_AvailableFor_Fetch;
2383 wire DMA13_ReqPending;
2384 wire [4:0] DMA13_EntriesValid;
2385 wire DMA13_CacheEmpty;
2386 wire [3:0] DMA13_CacheReadPtr;
2387 wire [3:0] DMA13_CacheWritePtrReOrder;
2388 wire IncrDMA13RdPtr;
2389 wire inc_DMA13HeadShadow;
2390 wire ResetDMA13RdPtr;
2391 wire DMA13_CacheReadReq;
2392 wire DMA13_CacheReadGnt;
2393
2394
2395 // DMA14
2396 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA14;
2397 wire [63:0] DMA14_Address;
2398 wire DMA14_Ring_Wrapped;
2399 wire [`PTR_WIDTH - 1 :0] DMA14_RingLength;
2400 wire DMA14CacheEntryValid;
2401 wire dmc_txc_dma14_active;
2402 wire dmc_txc_dma14_eoflist;
2403 wire [3:0] DMA14_EmptySpace ;
2404 wire [`PTR_WIDTH:0] tx_rng_head_dma14;
2405 wire DMA14_AvailableFor_Fetch;
2406 wire DMA14_ReqPending;
2407 wire [4:0] DMA14_EntriesValid;
2408 wire DMA14_CacheEmpty;
2409 wire [3:0] DMA14_CacheReadPtr;
2410 wire [3:0] DMA14_CacheWritePtrReOrder;
2411 wire IncrDMA14RdPtr;
2412 wire inc_DMA14HeadShadow;
2413 wire ResetDMA14RdPtr;
2414 wire DMA14_CacheReadReq;
2415 wire DMA14_CacheReadGnt;
2416
2417
2418 // DMA15
2419 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA15;
2420 wire [63:0] DMA15_Address;
2421 wire DMA15_Ring_Wrapped;
2422 wire [`PTR_WIDTH - 1 :0] DMA15_RingLength;
2423 wire DMA15CacheEntryValid;
2424 wire dmc_txc_dma15_active;
2425 wire dmc_txc_dma15_eoflist;
2426 wire [3:0] DMA15_EmptySpace ;
2427 wire [`PTR_WIDTH:0] tx_rng_head_dma15;
2428 wire DMA15_AvailableFor_Fetch;
2429 wire DMA15_ReqPending;
2430 wire [4:0] DMA15_EntriesValid;
2431 wire DMA15_CacheEmpty;
2432 wire [3:0] DMA15_CacheReadPtr;
2433 wire [3:0] DMA15_CacheWritePtrReOrder;
2434 wire IncrDMA15RdPtr;
2435 wire inc_DMA15HeadShadow;
2436 wire ResetDMA15RdPtr;
2437 wire DMA15_CacheReadReq;
2438 wire DMA15_CacheReadGnt;
2439
2440
2441`ifdef NEPTUNE
2442
2443 // DMA16
2444 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA16;
2445 wire [63:0] DMA16_Address;
2446 wire DMA16_Ring_Wrapped;
2447 wire [`PTR_WIDTH - 1 :0] DMA16_RingLength;
2448 wire DMA16CacheEntryValid;
2449 wire dmc_txc_dma16_active;
2450 wire dmc_txc_dma16_eoflist;
2451 wire [3:0] DMA16_EmptySpace ;
2452 wire [`PTR_WIDTH:0] tx_rng_head_dma16;
2453 wire DMA16_AvailableFor_Fetch;
2454 wire DMA16_ReqPending;
2455 wire [4:0] DMA16_EntriesValid;
2456 wire DMA16_CacheEmpty;
2457 wire [3:0] DMA16_CacheReadPtr;
2458 wire [3:0] DMA16_CacheWritePtrReOrder;
2459 wire IncrDMA16RdPtr;
2460 wire inc_DMA16HeadShadow;
2461 wire ResetDMA16RdPtr;
2462 wire DMA16_CacheReadReq;
2463 wire DMA16_CacheReadGnt;
2464
2465
2466 // DMA17
2467 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA17;
2468 wire [63:0] DMA17_Address;
2469 wire DMA17_Ring_Wrapped;
2470 wire [`PTR_WIDTH - 1 :0] DMA17_RingLength;
2471 wire DMA17CacheEntryValid;
2472 wire dmc_txc_dma17_active;
2473 wire dmc_txc_dma17_eoflist;
2474 wire [3:0] DMA17_EmptySpace ;
2475 wire [`PTR_WIDTH:0] tx_rng_head_dma17;
2476 wire DMA17_AvailableFor_Fetch;
2477 wire DMA17_ReqPending;
2478 wire [4:0] DMA17_EntriesValid;
2479 wire DMA17_CacheEmpty;
2480 wire [3:0] DMA17_CacheReadPtr;
2481 wire [3:0] DMA17_CacheWritePtrReOrder;
2482 wire IncrDMA17RdPtr;
2483 wire inc_DMA17HeadShadow;
2484 wire ResetDMA17RdPtr;
2485 wire DMA17_CacheReadReq;
2486 wire DMA17_CacheReadGnt;
2487
2488
2489 // DMA18
2490 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA18;
2491 wire [63:0] DMA18_Address;
2492 wire DMA18_Ring_Wrapped;
2493 wire [`PTR_WIDTH - 1 :0] DMA18_RingLength;
2494 wire DMA18CacheEntryValid;
2495 wire dmc_txc_dma18_active;
2496 wire dmc_txc_dma18_eoflist;
2497 wire [3:0] DMA18_EmptySpace ;
2498 wire [`PTR_WIDTH:0] tx_rng_head_dma18;
2499 wire DMA18_AvailableFor_Fetch;
2500 wire DMA18_ReqPending;
2501 wire [4:0] DMA18_EntriesValid;
2502 wire DMA18_CacheEmpty;
2503 wire [3:0] DMA18_CacheReadPtr;
2504 wire [3:0] DMA18_CacheWritePtrReOrder;
2505 wire IncrDMA18RdPtr;
2506 wire inc_DMA18HeadShadow;
2507 wire ResetDMA18RdPtr;
2508 wire DMA18_CacheReadReq;
2509 wire DMA18_CacheReadGnt;
2510
2511
2512 // DMA19
2513 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA19;
2514 wire [63:0] DMA19_Address;
2515 wire DMA19_Ring_Wrapped;
2516 wire [`PTR_WIDTH - 1 :0] DMA19_RingLength;
2517 wire DMA19CacheEntryValid;
2518 wire dmc_txc_dma19_active;
2519 wire dmc_txc_dma19_eoflist;
2520 wire [3:0] DMA19_EmptySpace ;
2521 wire [`PTR_WIDTH:0] tx_rng_head_dma19;
2522 wire DMA19_AvailableFor_Fetch;
2523 wire DMA19_ReqPending;
2524 wire [4:0] DMA19_EntriesValid;
2525 wire DMA19_CacheEmpty;
2526 wire [3:0] DMA19_CacheReadPtr;
2527 wire [3:0] DMA19_CacheWritePtrReOrder;
2528 wire IncrDMA19RdPtr;
2529 wire inc_DMA19HeadShadow;
2530 wire ResetDMA19RdPtr;
2531 wire DMA19_CacheReadReq;
2532 wire DMA19_CacheReadGnt;
2533
2534
2535 // DMA20
2536 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA20;
2537 wire [63:0] DMA20_Address;
2538 wire DMA20_Ring_Wrapped;
2539 wire [`PTR_WIDTH - 1 :0] DMA20_RingLength;
2540 wire DMA20CacheEntryValid;
2541 wire dmc_txc_dma20_active;
2542 wire dmc_txc_dma20_eoflist;
2543 wire [3:0] DMA20_EmptySpace ;
2544 wire [`PTR_WIDTH:0] tx_rng_head_dma20;
2545 wire DMA20_AvailableFor_Fetch;
2546 wire DMA20_ReqPending;
2547 wire [4:0] DMA20_EntriesValid;
2548 wire DMA20_CacheEmpty;
2549 wire [3:0] DMA20_CacheReadPtr;
2550 wire [3:0] DMA20_CacheWritePtrReOrder;
2551 wire IncrDMA20RdPtr;
2552 wire inc_DMA20HeadShadow;
2553 wire ResetDMA20RdPtr;
2554 wire DMA20_CacheReadReq;
2555 wire DMA20_CacheReadGnt;
2556
2557
2558 // DMA21
2559 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA21;
2560 wire [63:0] DMA21_Address;
2561 wire DMA21_Ring_Wrapped;
2562 wire [`PTR_WIDTH - 1 :0] DMA21_RingLength;
2563 wire DMA21CacheEntryValid;
2564 wire dmc_txc_dma21_active;
2565 wire dmc_txc_dma21_eoflist;
2566 wire [3:0] DMA21_EmptySpace ;
2567 wire [`PTR_WIDTH:0] tx_rng_head_dma21;
2568 wire DMA21_AvailableFor_Fetch;
2569 wire DMA21_ReqPending;
2570 wire [4:0] DMA21_EntriesValid;
2571 wire DMA21_CacheEmpty;
2572 wire [3:0] DMA21_CacheReadPtr;
2573 wire [3:0] DMA21_CacheWritePtrReOrder;
2574 wire IncrDMA21RdPtr;
2575 wire inc_DMA21HeadShadow;
2576 wire ResetDMA21RdPtr;
2577 wire DMA21_CacheReadReq;
2578 wire DMA21_CacheReadGnt;
2579
2580
2581 // DMA22
2582 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA22;
2583 wire [63:0] DMA22_Address;
2584 wire DMA22_Ring_Wrapped;
2585 wire [`PTR_WIDTH - 1 :0] DMA22_RingLength;
2586 wire DMA22CacheEntryValid;
2587 wire dmc_txc_dma22_active;
2588 wire dmc_txc_dma22_eoflist;
2589 wire [3:0] DMA22_EmptySpace ;
2590 wire [`PTR_WIDTH:0] tx_rng_head_dma22;
2591 wire DMA22_AvailableFor_Fetch;
2592 wire DMA22_ReqPending;
2593 wire [4:0] DMA22_EntriesValid;
2594 wire DMA22_CacheEmpty;
2595 wire [3:0] DMA22_CacheReadPtr;
2596 wire [3:0] DMA22_CacheWritePtrReOrder;
2597 wire IncrDMA22RdPtr;
2598 wire inc_DMA22HeadShadow;
2599 wire ResetDMA22RdPtr;
2600 wire DMA22_CacheReadReq;
2601 wire DMA22_CacheReadGnt;
2602
2603
2604 // DMA23
2605 wire [`PTR_WIDTH - 1 :0] ShadowRingCurrentPtr_DMA23;
2606 wire [63:0] DMA23_Address;
2607 wire DMA23_Ring_Wrapped;
2608 wire [`PTR_WIDTH - 1 :0] DMA23_RingLength;
2609 wire DMA23CacheEntryValid;
2610 wire dmc_txc_dma23_active;
2611 wire dmc_txc_dma23_eoflist;
2612 wire [3:0] DMA23_EmptySpace ;
2613 wire [`PTR_WIDTH:0] tx_rng_head_dma23;
2614 wire DMA23_AvailableFor_Fetch;
2615 wire DMA23_ReqPending;
2616 wire [4:0] DMA23_EntriesValid;
2617 wire DMA23_CacheEmpty;
2618 wire [3:0] DMA23_CacheReadPtr;
2619 wire [3:0] DMA23_CacheWritePtrReOrder;
2620 wire IncrDMA23RdPtr;
2621 wire inc_DMA23HeadShadow;
2622 wire ResetDMA23RdPtr;
2623 wire DMA23_CacheReadReq;
2624 wire DMA23_CacheReadGnt;
2625
2626`endif // ifdef NEPTUNE
2627
2628
2629
2630
2631 wire [31:0] DMANumToUpdate;
2632
2633 wire [43:0] DMA_UpdateAddress;
2634 wire ParityStatus;
2635
2636
2637 // Error related wires
2638
2639
2640
2641 wire set_pref_buf_par_err_dma0;
2642 wire set_pkt_part_err_dma0;
2643 wire [43:0] pkt_part_error_address_dma0;
2644 wire set_conf_part_error_dma0;
2645
2646 wire set_pref_buf_par_err_dma1;
2647 wire set_pkt_part_err_dma1;
2648 wire [43:0] pkt_part_error_address_dma1;
2649 wire set_conf_part_error_dma1;
2650
2651 wire set_pref_buf_par_err_dma2;
2652 wire set_pkt_part_err_dma2;
2653 wire [43:0] pkt_part_error_address_dma2;
2654 wire set_conf_part_error_dma2;
2655
2656 wire set_pref_buf_par_err_dma3;
2657 wire set_pkt_part_err_dma3;
2658 wire [43:0] pkt_part_error_address_dma3;
2659 wire set_conf_part_error_dma3;
2660
2661 wire set_pref_buf_par_err_dma4;
2662 wire set_pkt_part_err_dma4;
2663 wire [43:0] pkt_part_error_address_dma4;
2664 wire set_conf_part_error_dma4;
2665
2666 wire set_pref_buf_par_err_dma5;
2667 wire set_pkt_part_err_dma5;
2668 wire [43:0] pkt_part_error_address_dma5;
2669 wire set_conf_part_error_dma5;
2670
2671 wire set_pref_buf_par_err_dma6;
2672 wire set_pkt_part_err_dma6;
2673 wire [43:0] pkt_part_error_address_dma6;
2674 wire set_conf_part_error_dma6;
2675
2676 wire set_pref_buf_par_err_dma7;
2677 wire set_pkt_part_err_dma7;
2678 wire [43:0] pkt_part_error_address_dma7;
2679 wire set_conf_part_error_dma7;
2680
2681 wire set_pref_buf_par_err_dma8;
2682 wire set_pkt_part_err_dma8;
2683 wire [43:0] pkt_part_error_address_dma8;
2684 wire set_conf_part_error_dma8;
2685
2686 wire set_pref_buf_par_err_dma9;
2687 wire set_pkt_part_err_dma9;
2688 wire [43:0] pkt_part_error_address_dma9;
2689 wire set_conf_part_error_dma9;
2690
2691 wire set_pref_buf_par_err_dma10;
2692 wire set_pkt_part_err_dma10;
2693 wire [43:0] pkt_part_error_address_dma10;
2694 wire set_conf_part_error_dma10;
2695
2696 wire set_pref_buf_par_err_dma11;
2697 wire set_pkt_part_err_dma11;
2698 wire [43:0] pkt_part_error_address_dma11;
2699 wire set_conf_part_error_dma11;
2700
2701 wire set_pref_buf_par_err_dma12;
2702 wire set_pkt_part_err_dma12;
2703 wire [43:0] pkt_part_error_address_dma12;
2704 wire set_conf_part_error_dma12;
2705
2706 wire set_pref_buf_par_err_dma13;
2707 wire set_pkt_part_err_dma13;
2708 wire [43:0] pkt_part_error_address_dma13;
2709 wire set_conf_part_error_dma13;
2710
2711 wire set_pref_buf_par_err_dma14;
2712 wire set_pkt_part_err_dma14;
2713 wire [43:0] pkt_part_error_address_dma14;
2714 wire set_conf_part_error_dma14;
2715
2716 wire set_pref_buf_par_err_dma15;
2717 wire set_pkt_part_err_dma15;
2718 wire [43:0] pkt_part_error_address_dma15;
2719 wire set_conf_part_error_dma15;
2720
2721`ifdef NEPTUNE
2722
2723 wire set_pref_buf_par_err_dma16;
2724 wire set_pkt_part_err_dma16;
2725 wire [43:0] pkt_part_error_address_dma16;
2726 wire set_conf_part_error_dma16;
2727
2728 wire set_pref_buf_par_err_dma17;
2729 wire set_pkt_part_err_dma17;
2730 wire [43:0] pkt_part_error_address_dma17;
2731 wire set_conf_part_error_dma17;
2732
2733 wire set_pref_buf_par_err_dma18;
2734 wire set_pkt_part_err_dma18;
2735 wire [43:0] pkt_part_error_address_dma18;
2736 wire set_conf_part_error_dma18;
2737
2738 wire set_pref_buf_par_err_dma19;
2739 wire set_pkt_part_err_dma19;
2740 wire [43:0] pkt_part_error_address_dma19;
2741 wire set_conf_part_error_dma19;
2742
2743 wire set_pref_buf_par_err_dma20;
2744 wire set_pkt_part_err_dma20;
2745 wire [43:0] pkt_part_error_address_dma20;
2746 wire set_conf_part_error_dma20;
2747
2748 wire set_pref_buf_par_err_dma21;
2749 wire set_pkt_part_err_dma21;
2750 wire [43:0] pkt_part_error_address_dma21;
2751 wire set_conf_part_error_dma21;
2752
2753 wire set_pref_buf_par_err_dma22;
2754 wire set_pkt_part_err_dma22;
2755 wire [43:0] pkt_part_error_address_dma22;
2756 wire set_conf_part_error_dma22;
2757
2758 wire set_pref_buf_par_err_dma23;
2759 wire set_pkt_part_err_dma23;
2760 wire [43:0] pkt_part_error_address_dma23;
2761 wire set_conf_part_error_dma23;
2762
2763`endif // ifdef NEPTUNE
2764
2765
2766
2767 wire [`NO_OF_DMAS - 1 :0] txpref_dma_nack_resp;
2768 wire txpref_nack_resp ;
2769 wire [43:0] txpref_nack_rd_addr;
2770
2771
2772wire [4:0] meta_entries_requested_dma0;
2773wire [4:0] meta_entries_requested_dma1;
2774wire [4:0] meta_entries_requested_dma2;
2775wire [4:0] meta_entries_requested_dma3;
2776wire [4:0] meta_entries_requested_dma4;
2777wire [4:0] meta_entries_requested_dma5;
2778wire [4:0] meta_entries_requested_dma6;
2779wire [4:0] meta_entries_requested_dma7;
2780wire [4:0] meta_entries_requested_dma8;
2781wire [4:0] meta_entries_requested_dma9;
2782wire [4:0] meta_entries_requested_dma10;
2783wire [4:0] meta_entries_requested_dma11;
2784wire [4:0] meta_entries_requested_dma12;
2785wire [4:0] meta_entries_requested_dma13;
2786wire [4:0] meta_entries_requested_dma14;
2787wire [4:0] meta_entries_requested_dma15;
2788`ifdef NEPTUNE
2789
2790wire [4:0] meta_entries_requested_dma16;
2791wire [4:0] meta_entries_requested_dma17;
2792wire [4:0] meta_entries_requested_dma18;
2793wire [4:0] meta_entries_requested_dma19;
2794wire [4:0] meta_entries_requested_dma20;
2795wire [4:0] meta_entries_requested_dma21;
2796wire [4:0] meta_entries_requested_dma22;
2797wire [4:0] meta_entries_requested_dma23;
2798`endif // ifdef NEPTUNE
2799
2800
2801// dma0 wires
2802wire dma0_reset_scheduled;
2803wire dma0_reset_done_hold;
2804// dma1 wires
2805wire dma1_reset_scheduled;
2806wire dma1_reset_done_hold;
2807// dma2 wires
2808wire dma2_reset_scheduled;
2809wire dma2_reset_done_hold;
2810// dma3 wires
2811wire dma3_reset_scheduled;
2812wire dma3_reset_done_hold;
2813// dma4 wires
2814wire dma4_reset_scheduled;
2815wire dma4_reset_done_hold;
2816// dma5 wires
2817wire dma5_reset_scheduled;
2818wire dma5_reset_done_hold;
2819// dma6 wires
2820wire dma6_reset_scheduled;
2821wire dma6_reset_done_hold;
2822// dma7 wires
2823wire dma7_reset_scheduled;
2824wire dma7_reset_done_hold;
2825// dma8 wires
2826wire dma8_reset_scheduled;
2827wire dma8_reset_done_hold;
2828// dma9 wires
2829wire dma9_reset_scheduled;
2830wire dma9_reset_done_hold;
2831// dma10 wires
2832wire dma10_reset_scheduled;
2833wire dma10_reset_done_hold;
2834// dma11 wires
2835wire dma11_reset_scheduled;
2836wire dma11_reset_done_hold;
2837// dma12 wires
2838wire dma12_reset_scheduled;
2839wire dma12_reset_done_hold;
2840// dma13 wires
2841wire dma13_reset_scheduled;
2842wire dma13_reset_done_hold;
2843// dma14 wires
2844wire dma14_reset_scheduled;
2845wire dma14_reset_done_hold;
2846// dma15 wires
2847wire dma15_reset_scheduled;
2848wire dma15_reset_done_hold;
2849`ifdef NEPTUNE
2850
2851// dma16 wires
2852wire dma16_reset_scheduled;
2853wire dma16_reset_done_hold;
2854// dma17 wires
2855wire dma17_reset_scheduled;
2856wire dma17_reset_done_hold;
2857// dma18 wires
2858wire dma18_reset_scheduled;
2859wire dma18_reset_done_hold;
2860// dma19 wires
2861wire dma19_reset_scheduled;
2862wire dma19_reset_done_hold;
2863// dma20 wires
2864wire dma20_reset_scheduled;
2865wire dma20_reset_done_hold;
2866// dma21 wires
2867wire dma21_reset_scheduled;
2868wire dma21_reset_done_hold;
2869// dma22 wires
2870wire dma22_reset_scheduled;
2871wire dma22_reset_done_hold;
2872// dma23 wires
2873wire dma23_reset_scheduled;
2874wire dma23_reset_done_hold;
2875
2876`endif // ifdef NEPTUNE
2877
2878
2879
2880 wire [`NO_OF_DMAS - 1:0] parity_corrupt_dma_match;
2881 wire [`PTR_WIDTH - 1 :0] NoOfDescInMem;
2882 wire [`PTR_WIDTH - 1 :0] NoOfDescLeft;
2883
2884`ifdef NEPTUNE
2885`else
2886 wire [6:0] sram_hdr_read_data_tdmc;
2887`endif // ifdef NEPTUNE
2888
2889
2890
2891
2892// DMA0
2893niu_tdmc_dmacontext niu_tdmc_dmacontext_0 (/*AUTOJUNK*/
2894 // Outputs
2895 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA0[`PTR_WIDTH - 1 :0]),
2896 .DMA_Address(DMA0_Address[63:0]),
2897 .DMA_Ring_Wrapped(DMA0_Ring_Wrapped),
2898 .DMA_RingLength(DMA0_RingLength[`PTR_WIDTH - 1 :0]),
2899 .DMACacheEntryValid(DMA0CacheEntryValid),
2900 .dmc_txc_dma_active(dmc_txc_dma0_active),
2901 .dmc_txc_dma_eoflist(dmc_txc_dma0_eoflist),
2902 .DMA_EmptySpace(DMA0_EmptySpace[3:0]),
2903 .tx_rng_head_dma(tx_rng_head_dma0[`PTR_WIDTH:0]),
2904 .DMA_AvailableFor_Fetch(DMA0_AvailableFor_Fetch),
2905 .DMA_ReqPending(DMA0_ReqPending),
2906 .DMA_EntriesValid(DMA0_EntriesValid[4:0]),
2907 .DMA_CacheEmpty(DMA0_CacheEmpty),
2908 .DMA_CacheReadPtr(DMA0_CacheReadPtr[3:0]),
2909 .DMA_CacheWritePtrReOrder(DMA0_CacheWritePtrReOrder[3:0]),
2910 .dma_reset_scheduled ( dma0_reset_scheduled ),
2911 .dma_clear_reset ( dma0_clear_reset ),
2912 .set_conf_part_error_dma(set_conf_part_error_dma0),
2913 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma0),
2914 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma0_stop_state),
2915 .meta_entries_requested_dma(meta_entries_requested_dma0),
2916 .dma_debug_port (dma0_debug_port),
2917 // Inputs
2918 .page0_mask_dma ( page0_mask_dma0 ),
2919 .page0_value_dma( page0_value_dma0 ),
2920 .page0_reloc_dma( page0_reloc_dma0 ),
2921 .page0_valid_dma( page0_valid_dma0 ),
2922 .page1_mask_dma ( page1_mask_dma0 ),
2923 .page1_value_dma( page1_value_dma0 ),
2924 .page1_reloc_dma( page1_reloc_dma0 ),
2925 .page1_valid_dma( page1_valid_dma0 ),
2926 .dmc_txc_dma_page_handle( dmc_txc_dma0_page_handle ),
2927 .txc_dmc_dma_inc_head(txc_dmc_dma0_inc_head),
2928 .dmc_txc_dma_partial ( dmc_txc_dma0_partial ),
2929 .NoOfValidEntries ( NoOfValidEntries),
2930 .inc_DMAHeadShadow(inc_DMA0HeadShadow),
2931 .updateCacheWritePtrs(updateCacheWritePtrs[0] ),
2932 .receivedErrorResp(receivedErrorResp[0]),
2933 .ResetDMARdPtr(ResetDMA0RdPtr),
2934 .meta_resp_address(meta_resp_address[2:0]),
2935 .updateCacheContext(updateCacheContext[0]),
2936 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma0_staddr[37:0]),
2937 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
2938 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
2939 .DMA_UpdateAddress ( DMA_UpdateAddress ),
2940 .tx_rng_cfg_dma_len(tx_rng_cfg_dma0_len[`RNG_LENGTH_WIDTH -1 :0]),
2941 .tx_rng_tail_dma(tx_rng_tail_dma0[`PTR_WIDTH:0]),
2942 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma0_stall),
2943 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma0_rst ),
2944 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma0_stop),
2945 .dma_reset_done_hold (dma0_reset_done_hold),
2946 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
2947 .DMANumToReq(DMANumToReq[4:0]),
2948 .dmc_txc_dma_cacheready(dmc_txc_dma0_cacheready),
2949 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
2950 .IncrDMARdPtr(IncrDMA0RdPtr),
2951 .SysClk(SysClk),
2952 .Reset_L(Reset_L));
2953
2954// DMA1
2955niu_tdmc_dmacontext niu_tdmc_dmacontext_1 (/*AUTOJUNK*/
2956 // Outputs
2957 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA1[`PTR_WIDTH - 1 :0]),
2958 .DMA_Address(DMA1_Address[63:0]),
2959 .DMA_Ring_Wrapped(DMA1_Ring_Wrapped),
2960 .DMA_RingLength(DMA1_RingLength[`PTR_WIDTH - 1 :0]),
2961 .DMACacheEntryValid(DMA1CacheEntryValid),
2962 .dmc_txc_dma_active(dmc_txc_dma1_active),
2963 .dmc_txc_dma_eoflist(dmc_txc_dma1_eoflist),
2964 .DMA_EmptySpace(DMA1_EmptySpace[3:0]),
2965 .tx_rng_head_dma(tx_rng_head_dma1[`PTR_WIDTH:0]),
2966 .DMA_AvailableFor_Fetch(DMA1_AvailableFor_Fetch),
2967 .DMA_ReqPending(DMA1_ReqPending),
2968 .DMA_EntriesValid(DMA1_EntriesValid[4:0]),
2969 .DMA_CacheEmpty(DMA1_CacheEmpty),
2970 .DMA_CacheReadPtr(DMA1_CacheReadPtr[3:0]),
2971 .DMA_CacheWritePtrReOrder(DMA1_CacheWritePtrReOrder[3:0]),
2972 .dma_reset_scheduled ( dma1_reset_scheduled ),
2973 .dma_clear_reset ( dma1_clear_reset ),
2974 .set_conf_part_error_dma(set_conf_part_error_dma1),
2975 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma1),
2976 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma1_stop_state),
2977 .meta_entries_requested_dma(meta_entries_requested_dma1),
2978 .dma_debug_port (dma1_debug_port),
2979
2980 // Inputs
2981 .page0_mask_dma ( page0_mask_dma1 ),
2982 .page0_value_dma( page0_value_dma1 ),
2983 .page0_reloc_dma( page0_reloc_dma1 ),
2984 .page0_valid_dma( page0_valid_dma1 ),
2985 .page1_mask_dma ( page1_mask_dma1 ),
2986 .page1_value_dma( page1_value_dma1 ),
2987 .page1_reloc_dma( page1_reloc_dma1 ),
2988 .page1_valid_dma( page1_valid_dma1 ),
2989 .dmc_txc_dma_page_handle( dmc_txc_dma1_page_handle ),
2990 .txc_dmc_dma_inc_head(txc_dmc_dma1_inc_head),
2991 .dmc_txc_dma_partial ( dmc_txc_dma1_partial ),
2992 .NoOfValidEntries ( NoOfValidEntries),
2993 .inc_DMAHeadShadow(inc_DMA1HeadShadow),
2994 .updateCacheWritePtrs(updateCacheWritePtrs[1] ),
2995 .receivedErrorResp(receivedErrorResp[1]),
2996 .ResetDMARdPtr(ResetDMA1RdPtr),
2997 .meta_resp_address(meta_resp_address[2:0]),
2998 .updateCacheContext(updateCacheContext[1]),
2999 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma1_staddr[37:0]),
3000 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3001 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3002 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3003 .tx_rng_cfg_dma_len(tx_rng_cfg_dma1_len[`RNG_LENGTH_WIDTH -1 :0]),
3004 .tx_rng_tail_dma(tx_rng_tail_dma1[`PTR_WIDTH:0]),
3005 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma1_stall),
3006 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma1_rst ),
3007 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma1_stop),
3008 .dma_reset_done_hold (dma1_reset_done_hold),
3009 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3010 .DMANumToReq(DMANumToReq[4:0]),
3011 .dmc_txc_dma_cacheready(dmc_txc_dma1_cacheready),
3012 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3013 .IncrDMARdPtr(IncrDMA1RdPtr),
3014 .SysClk(SysClk),
3015 .Reset_L(Reset_L));
3016
3017// DMA2
3018niu_tdmc_dmacontext niu_tdmc_dmacontext_2 (/*AUTOJUNK*/
3019 // Outputs
3020 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA2[`PTR_WIDTH - 1 :0]),
3021 .DMA_Address(DMA2_Address[63:0]),
3022 .DMA_Ring_Wrapped(DMA2_Ring_Wrapped),
3023 .DMA_RingLength(DMA2_RingLength[`PTR_WIDTH - 1 :0]),
3024 .DMACacheEntryValid(DMA2CacheEntryValid),
3025 .dmc_txc_dma_active(dmc_txc_dma2_active),
3026 .dmc_txc_dma_eoflist(dmc_txc_dma2_eoflist),
3027 .DMA_EmptySpace(DMA2_EmptySpace[3:0]),
3028 .tx_rng_head_dma(tx_rng_head_dma2[`PTR_WIDTH:0]),
3029 .DMA_AvailableFor_Fetch(DMA2_AvailableFor_Fetch),
3030 .DMA_ReqPending(DMA2_ReqPending),
3031 .DMA_EntriesValid(DMA2_EntriesValid[4:0]),
3032 .DMA_CacheEmpty(DMA2_CacheEmpty),
3033 .DMA_CacheReadPtr(DMA2_CacheReadPtr[3:0]),
3034 .DMA_CacheWritePtrReOrder(DMA2_CacheWritePtrReOrder[3:0]),
3035 .dma_reset_scheduled ( dma2_reset_scheduled ),
3036 .dma_clear_reset ( dma2_clear_reset ),
3037 .set_conf_part_error_dma(set_conf_part_error_dma2),
3038 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma2),
3039 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma2_stop_state),
3040 .meta_entries_requested_dma(meta_entries_requested_dma2),
3041 .dma_debug_port (dma2_debug_port),
3042
3043 // Inputs
3044 .page0_mask_dma ( page0_mask_dma2 ),
3045 .page0_value_dma( page0_value_dma2 ),
3046 .page0_reloc_dma( page0_reloc_dma2 ),
3047 .page0_valid_dma( page0_valid_dma2 ),
3048 .page1_mask_dma ( page1_mask_dma2 ),
3049 .page1_value_dma( page1_value_dma2 ),
3050 .page1_reloc_dma( page1_reloc_dma2 ),
3051 .page1_valid_dma( page1_valid_dma2 ),
3052 .dmc_txc_dma_page_handle( dmc_txc_dma2_page_handle ),
3053 .txc_dmc_dma_inc_head(txc_dmc_dma2_inc_head),
3054 .dmc_txc_dma_partial ( dmc_txc_dma2_partial ),
3055 .NoOfValidEntries ( NoOfValidEntries),
3056 .inc_DMAHeadShadow(inc_DMA2HeadShadow),
3057 .updateCacheWritePtrs(updateCacheWritePtrs[2] ),
3058 .receivedErrorResp(receivedErrorResp[2]),
3059 .ResetDMARdPtr(ResetDMA2RdPtr),
3060 .meta_resp_address(meta_resp_address[2:0]),
3061 .updateCacheContext(updateCacheContext[2]),
3062 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma2_staddr[37:0]),
3063 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3064 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3065 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3066 .tx_rng_cfg_dma_len(tx_rng_cfg_dma2_len[`RNG_LENGTH_WIDTH -1 :0]),
3067 .tx_rng_tail_dma(tx_rng_tail_dma2[`PTR_WIDTH:0]),
3068 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma2_stall),
3069 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma2_rst ),
3070 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma2_stop),
3071 .dma_reset_done_hold (dma2_reset_done_hold),
3072 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3073 .DMANumToReq(DMANumToReq[4:0]),
3074 .dmc_txc_dma_cacheready(dmc_txc_dma2_cacheready),
3075 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3076 .IncrDMARdPtr(IncrDMA2RdPtr),
3077 .SysClk(SysClk),
3078 .Reset_L(Reset_L));
3079
3080// DMA3
3081niu_tdmc_dmacontext niu_tdmc_dmacontext_3 (/*AUTOJUNK*/
3082 // Outputs
3083 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA3[`PTR_WIDTH - 1 :0]),
3084 .DMA_Address(DMA3_Address[63:0]),
3085 .DMA_Ring_Wrapped(DMA3_Ring_Wrapped),
3086 .DMA_RingLength(DMA3_RingLength[`PTR_WIDTH - 1 :0]),
3087 .DMACacheEntryValid(DMA3CacheEntryValid),
3088 .dmc_txc_dma_active(dmc_txc_dma3_active),
3089 .dmc_txc_dma_eoflist(dmc_txc_dma3_eoflist),
3090 .DMA_EmptySpace(DMA3_EmptySpace[3:0]),
3091 .tx_rng_head_dma(tx_rng_head_dma3[`PTR_WIDTH:0]),
3092 .DMA_AvailableFor_Fetch(DMA3_AvailableFor_Fetch),
3093 .DMA_ReqPending(DMA3_ReqPending),
3094 .DMA_EntriesValid(DMA3_EntriesValid[4:0]),
3095 .DMA_CacheEmpty(DMA3_CacheEmpty),
3096 .DMA_CacheReadPtr(DMA3_CacheReadPtr[3:0]),
3097 .DMA_CacheWritePtrReOrder(DMA3_CacheWritePtrReOrder[3:0]),
3098 .dma_reset_scheduled ( dma3_reset_scheduled ),
3099 .dma_clear_reset ( dma3_clear_reset ),
3100 .set_conf_part_error_dma(set_conf_part_error_dma3),
3101 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma3),
3102 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma3_stop_state),
3103 .meta_entries_requested_dma(meta_entries_requested_dma3),
3104 .dma_debug_port (dma3_debug_port),
3105
3106 // Inputs
3107 .page0_mask_dma ( page0_mask_dma3 ),
3108 .page0_value_dma( page0_value_dma3 ),
3109 .page0_reloc_dma( page0_reloc_dma3 ),
3110 .page0_valid_dma( page0_valid_dma3 ),
3111 .page1_mask_dma ( page1_mask_dma3 ),
3112 .page1_value_dma( page1_value_dma3 ),
3113 .page1_reloc_dma( page1_reloc_dma3 ),
3114 .page1_valid_dma( page1_valid_dma3 ),
3115 .dmc_txc_dma_page_handle( dmc_txc_dma3_page_handle ),
3116 .txc_dmc_dma_inc_head(txc_dmc_dma3_inc_head),
3117 .dmc_txc_dma_partial ( dmc_txc_dma3_partial ),
3118 .NoOfValidEntries ( NoOfValidEntries),
3119 .inc_DMAHeadShadow(inc_DMA3HeadShadow),
3120 .updateCacheWritePtrs(updateCacheWritePtrs[3] ),
3121 .receivedErrorResp(receivedErrorResp[3]),
3122 .ResetDMARdPtr(ResetDMA3RdPtr),
3123 .meta_resp_address(meta_resp_address[2:0]),
3124 .updateCacheContext(updateCacheContext[3]),
3125 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma3_staddr[37:0]),
3126 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3127 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3128 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3129 .tx_rng_cfg_dma_len(tx_rng_cfg_dma3_len[`RNG_LENGTH_WIDTH -1 :0]),
3130 .tx_rng_tail_dma(tx_rng_tail_dma3[`PTR_WIDTH:0]),
3131 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma3_stall),
3132 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma3_rst ),
3133 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma3_stop),
3134 .dma_reset_done_hold (dma3_reset_done_hold),
3135 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3136 .DMANumToReq(DMANumToReq[4:0]),
3137 .dmc_txc_dma_cacheready(dmc_txc_dma3_cacheready),
3138 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3139 .IncrDMARdPtr(IncrDMA3RdPtr),
3140 .SysClk(SysClk),
3141 .Reset_L(Reset_L));
3142
3143// DMA4
3144niu_tdmc_dmacontext niu_tdmc_dmacontext_4 (/*AUTOJUNK*/
3145 // Outputs
3146 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA4[`PTR_WIDTH - 1 :0]),
3147 .DMA_Address(DMA4_Address[63:0]),
3148 .DMA_Ring_Wrapped(DMA4_Ring_Wrapped),
3149 .DMA_RingLength(DMA4_RingLength[`PTR_WIDTH - 1 :0]),
3150 .DMACacheEntryValid(DMA4CacheEntryValid),
3151 .dmc_txc_dma_active(dmc_txc_dma4_active),
3152 .dmc_txc_dma_eoflist(dmc_txc_dma4_eoflist),
3153 .DMA_EmptySpace(DMA4_EmptySpace[3:0]),
3154 .tx_rng_head_dma(tx_rng_head_dma4[`PTR_WIDTH:0]),
3155 .DMA_AvailableFor_Fetch(DMA4_AvailableFor_Fetch),
3156 .DMA_ReqPending(DMA4_ReqPending),
3157 .DMA_EntriesValid(DMA4_EntriesValid[4:0]),
3158 .DMA_CacheEmpty(DMA4_CacheEmpty),
3159 .DMA_CacheReadPtr(DMA4_CacheReadPtr[3:0]),
3160 .DMA_CacheWritePtrReOrder(DMA4_CacheWritePtrReOrder[3:0]),
3161 .dma_reset_scheduled ( dma4_reset_scheduled ),
3162 .dma_clear_reset ( dma4_clear_reset ),
3163 .set_conf_part_error_dma(set_conf_part_error_dma4),
3164 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma4),
3165 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma4_stop_state),
3166 .meta_entries_requested_dma(meta_entries_requested_dma4),
3167 .dma_debug_port (dma4_debug_port),
3168
3169 // Inputs
3170 .page0_mask_dma ( page0_mask_dma4 ),
3171 .page0_value_dma( page0_value_dma4 ),
3172 .page0_reloc_dma( page0_reloc_dma4 ),
3173 .page0_valid_dma( page0_valid_dma4 ),
3174 .page1_mask_dma ( page1_mask_dma4 ),
3175 .page1_value_dma( page1_value_dma4 ),
3176 .page1_reloc_dma( page1_reloc_dma4 ),
3177 .page1_valid_dma( page1_valid_dma4 ),
3178 .dmc_txc_dma_page_handle( dmc_txc_dma4_page_handle ),
3179 .txc_dmc_dma_inc_head(txc_dmc_dma4_inc_head),
3180 .dmc_txc_dma_partial ( dmc_txc_dma4_partial ),
3181 .NoOfValidEntries ( NoOfValidEntries),
3182 .inc_DMAHeadShadow(inc_DMA4HeadShadow),
3183 .updateCacheWritePtrs(updateCacheWritePtrs[4] ),
3184 .receivedErrorResp(receivedErrorResp[4]),
3185 .ResetDMARdPtr(ResetDMA4RdPtr),
3186 .meta_resp_address(meta_resp_address[2:0]),
3187 .updateCacheContext(updateCacheContext[4]),
3188 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma4_staddr[37:0]),
3189 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3190 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3191 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3192 .tx_rng_cfg_dma_len(tx_rng_cfg_dma4_len[`RNG_LENGTH_WIDTH -1 :0]),
3193 .tx_rng_tail_dma(tx_rng_tail_dma4[`PTR_WIDTH:0]),
3194 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma4_stall),
3195 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma4_rst ),
3196 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma4_stop),
3197 .dma_reset_done_hold (dma4_reset_done_hold),
3198 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3199 .DMANumToReq(DMANumToReq[4:0]),
3200 .dmc_txc_dma_cacheready(dmc_txc_dma4_cacheready),
3201 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3202 .IncrDMARdPtr(IncrDMA4RdPtr),
3203 .SysClk(SysClk),
3204 .Reset_L(Reset_L));
3205
3206// DMA5
3207niu_tdmc_dmacontext niu_tdmc_dmacontext_5 (/*AUTOJUNK*/
3208 // Outputs
3209 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA5[`PTR_WIDTH - 1 :0]),
3210 .DMA_Address(DMA5_Address[63:0]),
3211 .DMA_Ring_Wrapped(DMA5_Ring_Wrapped),
3212 .DMA_RingLength(DMA5_RingLength[`PTR_WIDTH - 1 :0]),
3213 .DMACacheEntryValid(DMA5CacheEntryValid),
3214 .dmc_txc_dma_active(dmc_txc_dma5_active),
3215 .dmc_txc_dma_eoflist(dmc_txc_dma5_eoflist),
3216 .DMA_EmptySpace(DMA5_EmptySpace[3:0]),
3217 .tx_rng_head_dma(tx_rng_head_dma5[`PTR_WIDTH:0]),
3218 .DMA_AvailableFor_Fetch(DMA5_AvailableFor_Fetch),
3219 .DMA_ReqPending(DMA5_ReqPending),
3220 .DMA_EntriesValid(DMA5_EntriesValid[4:0]),
3221 .DMA_CacheEmpty(DMA5_CacheEmpty),
3222 .DMA_CacheReadPtr(DMA5_CacheReadPtr[3:0]),
3223 .DMA_CacheWritePtrReOrder(DMA5_CacheWritePtrReOrder[3:0]),
3224 .dma_reset_scheduled ( dma5_reset_scheduled ),
3225 .dma_clear_reset ( dma5_clear_reset ),
3226 .set_conf_part_error_dma(set_conf_part_error_dma5),
3227 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma5),
3228 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma5_stop_state),
3229 .meta_entries_requested_dma(meta_entries_requested_dma5),
3230 .dma_debug_port (dma5_debug_port),
3231
3232 // Inputs
3233 .page0_mask_dma ( page0_mask_dma5 ),
3234 .page0_value_dma( page0_value_dma5 ),
3235 .page0_reloc_dma( page0_reloc_dma5 ),
3236 .page0_valid_dma( page0_valid_dma5 ),
3237 .page1_mask_dma ( page1_mask_dma5 ),
3238 .page1_value_dma( page1_value_dma5 ),
3239 .page1_reloc_dma( page1_reloc_dma5 ),
3240 .page1_valid_dma( page1_valid_dma5 ),
3241 .dmc_txc_dma_page_handle( dmc_txc_dma5_page_handle ),
3242 .txc_dmc_dma_inc_head(txc_dmc_dma5_inc_head),
3243 .dmc_txc_dma_partial ( dmc_txc_dma5_partial ),
3244 .NoOfValidEntries ( NoOfValidEntries),
3245 .inc_DMAHeadShadow(inc_DMA5HeadShadow),
3246 .updateCacheWritePtrs(updateCacheWritePtrs[5] ),
3247 .receivedErrorResp(receivedErrorResp[5]),
3248 .ResetDMARdPtr(ResetDMA5RdPtr),
3249 .meta_resp_address(meta_resp_address[2:0]),
3250 .updateCacheContext(updateCacheContext[5]),
3251 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma5_staddr[37:0]),
3252 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3253 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3254 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3255 .tx_rng_cfg_dma_len(tx_rng_cfg_dma5_len[`RNG_LENGTH_WIDTH -1 :0]),
3256 .tx_rng_tail_dma(tx_rng_tail_dma5[`PTR_WIDTH:0]),
3257 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma5_stall),
3258 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma5_rst ),
3259 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma5_stop),
3260 .dma_reset_done_hold (dma5_reset_done_hold),
3261 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3262 .DMANumToReq(DMANumToReq[4:0]),
3263 .dmc_txc_dma_cacheready(dmc_txc_dma5_cacheready),
3264 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3265 .IncrDMARdPtr(IncrDMA5RdPtr),
3266 .SysClk(SysClk),
3267 .Reset_L(Reset_L));
3268
3269// DMA6
3270niu_tdmc_dmacontext niu_tdmc_dmacontext_6 (/*AUTOJUNK*/
3271 // Outputs
3272 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA6[`PTR_WIDTH - 1 :0]),
3273 .DMA_Address(DMA6_Address[63:0]),
3274 .DMA_Ring_Wrapped(DMA6_Ring_Wrapped),
3275 .DMA_RingLength(DMA6_RingLength[`PTR_WIDTH - 1 :0]),
3276 .DMACacheEntryValid(DMA6CacheEntryValid),
3277 .dmc_txc_dma_active(dmc_txc_dma6_active),
3278 .dmc_txc_dma_eoflist(dmc_txc_dma6_eoflist),
3279 .DMA_EmptySpace(DMA6_EmptySpace[3:0]),
3280 .tx_rng_head_dma(tx_rng_head_dma6[`PTR_WIDTH:0]),
3281 .DMA_AvailableFor_Fetch(DMA6_AvailableFor_Fetch),
3282 .DMA_ReqPending(DMA6_ReqPending),
3283 .DMA_EntriesValid(DMA6_EntriesValid[4:0]),
3284 .DMA_CacheEmpty(DMA6_CacheEmpty),
3285 .DMA_CacheReadPtr(DMA6_CacheReadPtr[3:0]),
3286 .DMA_CacheWritePtrReOrder(DMA6_CacheWritePtrReOrder[3:0]),
3287 .dma_reset_scheduled ( dma6_reset_scheduled ),
3288 .dma_clear_reset ( dma6_clear_reset ),
3289 .set_conf_part_error_dma(set_conf_part_error_dma6),
3290 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma6),
3291 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma6_stop_state),
3292 .meta_entries_requested_dma(meta_entries_requested_dma6),
3293 .dma_debug_port (dma6_debug_port),
3294
3295 // Inputs
3296 .page0_mask_dma ( page0_mask_dma6 ),
3297 .page0_value_dma( page0_value_dma6 ),
3298 .page0_reloc_dma( page0_reloc_dma6 ),
3299 .page0_valid_dma( page0_valid_dma6 ),
3300 .page1_mask_dma ( page1_mask_dma6 ),
3301 .page1_value_dma( page1_value_dma6 ),
3302 .page1_reloc_dma( page1_reloc_dma6 ),
3303 .page1_valid_dma( page1_valid_dma6 ),
3304 .dmc_txc_dma_page_handle( dmc_txc_dma6_page_handle ),
3305 .txc_dmc_dma_inc_head(txc_dmc_dma6_inc_head),
3306 .dmc_txc_dma_partial ( dmc_txc_dma6_partial ),
3307 .NoOfValidEntries ( NoOfValidEntries),
3308 .inc_DMAHeadShadow(inc_DMA6HeadShadow),
3309 .updateCacheWritePtrs(updateCacheWritePtrs[6] ),
3310 .receivedErrorResp(receivedErrorResp[6]),
3311 .ResetDMARdPtr(ResetDMA6RdPtr),
3312 .meta_resp_address(meta_resp_address[2:0]),
3313 .updateCacheContext(updateCacheContext[6]),
3314 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma6_staddr[37:0]),
3315 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3316 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3317 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3318 .tx_rng_cfg_dma_len(tx_rng_cfg_dma6_len[`RNG_LENGTH_WIDTH -1 :0]),
3319 .tx_rng_tail_dma(tx_rng_tail_dma6[`PTR_WIDTH:0]),
3320 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma6_stall),
3321 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma6_rst ),
3322 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma6_stop),
3323 .dma_reset_done_hold (dma6_reset_done_hold),
3324 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3325 .DMANumToReq(DMANumToReq[4:0]),
3326 .dmc_txc_dma_cacheready(dmc_txc_dma6_cacheready),
3327 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3328 .IncrDMARdPtr(IncrDMA6RdPtr),
3329 .SysClk(SysClk),
3330 .Reset_L(Reset_L));
3331
3332// DMA7
3333niu_tdmc_dmacontext niu_tdmc_dmacontext_7 (/*AUTOJUNK*/
3334 // Outputs
3335 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA7[`PTR_WIDTH - 1 :0]),
3336 .DMA_Address(DMA7_Address[63:0]),
3337 .DMA_Ring_Wrapped(DMA7_Ring_Wrapped),
3338 .DMA_RingLength(DMA7_RingLength[`PTR_WIDTH - 1 :0]),
3339 .DMACacheEntryValid(DMA7CacheEntryValid),
3340 .dmc_txc_dma_active(dmc_txc_dma7_active),
3341 .dmc_txc_dma_eoflist(dmc_txc_dma7_eoflist),
3342 .DMA_EmptySpace(DMA7_EmptySpace[3:0]),
3343 .tx_rng_head_dma(tx_rng_head_dma7[`PTR_WIDTH:0]),
3344 .DMA_AvailableFor_Fetch(DMA7_AvailableFor_Fetch),
3345 .DMA_ReqPending(DMA7_ReqPending),
3346 .DMA_EntriesValid(DMA7_EntriesValid[4:0]),
3347 .DMA_CacheEmpty(DMA7_CacheEmpty),
3348 .DMA_CacheReadPtr(DMA7_CacheReadPtr[3:0]),
3349 .DMA_CacheWritePtrReOrder(DMA7_CacheWritePtrReOrder[3:0]),
3350 .dma_reset_scheduled ( dma7_reset_scheduled ),
3351 .dma_clear_reset ( dma7_clear_reset ),
3352 .set_conf_part_error_dma(set_conf_part_error_dma7),
3353 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma7),
3354 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma7_stop_state),
3355 .meta_entries_requested_dma(meta_entries_requested_dma7),
3356 .dma_debug_port (dma7_debug_port),
3357
3358 // Inputs
3359 .page0_mask_dma ( page0_mask_dma7 ),
3360 .page0_value_dma( page0_value_dma7 ),
3361 .page0_reloc_dma( page0_reloc_dma7 ),
3362 .page0_valid_dma( page0_valid_dma7 ),
3363 .page1_mask_dma ( page1_mask_dma7 ),
3364 .page1_value_dma( page1_value_dma7 ),
3365 .page1_reloc_dma( page1_reloc_dma7 ),
3366 .page1_valid_dma( page1_valid_dma7 ),
3367 .dmc_txc_dma_page_handle( dmc_txc_dma7_page_handle ),
3368 .txc_dmc_dma_inc_head(txc_dmc_dma7_inc_head),
3369 .dmc_txc_dma_partial ( dmc_txc_dma7_partial ),
3370 .NoOfValidEntries ( NoOfValidEntries),
3371 .inc_DMAHeadShadow(inc_DMA7HeadShadow),
3372 .updateCacheWritePtrs(updateCacheWritePtrs[7] ),
3373 .receivedErrorResp(receivedErrorResp[7]),
3374 .ResetDMARdPtr(ResetDMA7RdPtr),
3375 .meta_resp_address(meta_resp_address[2:0]),
3376 .updateCacheContext(updateCacheContext[7]),
3377 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma7_staddr[37:0]),
3378 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3379 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3380 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3381 .tx_rng_cfg_dma_len(tx_rng_cfg_dma7_len[`RNG_LENGTH_WIDTH -1 :0]),
3382 .tx_rng_tail_dma(tx_rng_tail_dma7[`PTR_WIDTH:0]),
3383 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma7_stall),
3384 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma7_rst ),
3385 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma7_stop),
3386 .dma_reset_done_hold (dma7_reset_done_hold),
3387 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3388 .DMANumToReq(DMANumToReq[4:0]),
3389 .dmc_txc_dma_cacheready(dmc_txc_dma7_cacheready),
3390 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3391 .IncrDMARdPtr(IncrDMA7RdPtr),
3392 .SysClk(SysClk),
3393 .Reset_L(Reset_L));
3394
3395// DMA8
3396niu_tdmc_dmacontext niu_tdmc_dmacontext_8 (/*AUTOJUNK*/
3397 // Outputs
3398 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA8[`PTR_WIDTH - 1 :0]),
3399 .DMA_Address(DMA8_Address[63:0]),
3400 .DMA_Ring_Wrapped(DMA8_Ring_Wrapped),
3401 .DMA_RingLength(DMA8_RingLength[`PTR_WIDTH - 1 :0]),
3402 .DMACacheEntryValid(DMA8CacheEntryValid),
3403 .dmc_txc_dma_active(dmc_txc_dma8_active),
3404 .dmc_txc_dma_eoflist(dmc_txc_dma8_eoflist),
3405 .DMA_EmptySpace(DMA8_EmptySpace[3:0]),
3406 .tx_rng_head_dma(tx_rng_head_dma8[`PTR_WIDTH:0]),
3407 .DMA_AvailableFor_Fetch(DMA8_AvailableFor_Fetch),
3408 .DMA_ReqPending(DMA8_ReqPending),
3409 .DMA_EntriesValid(DMA8_EntriesValid[4:0]),
3410 .DMA_CacheEmpty(DMA8_CacheEmpty),
3411 .DMA_CacheReadPtr(DMA8_CacheReadPtr[3:0]),
3412 .DMA_CacheWritePtrReOrder(DMA8_CacheWritePtrReOrder[3:0]),
3413 .dma_reset_scheduled ( dma8_reset_scheduled ),
3414 .dma_clear_reset ( dma8_clear_reset ),
3415 .set_conf_part_error_dma(set_conf_part_error_dma8),
3416 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma8),
3417 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma8_stop_state),
3418 .meta_entries_requested_dma(meta_entries_requested_dma8),
3419 .dma_debug_port (dma8_debug_port),
3420
3421 // Inputs
3422 .page0_mask_dma ( page0_mask_dma8 ),
3423 .page0_value_dma( page0_value_dma8 ),
3424 .page0_reloc_dma( page0_reloc_dma8 ),
3425 .page0_valid_dma( page0_valid_dma8 ),
3426 .page1_mask_dma ( page1_mask_dma8 ),
3427 .page1_value_dma( page1_value_dma8 ),
3428 .page1_reloc_dma( page1_reloc_dma8 ),
3429 .page1_valid_dma( page1_valid_dma8 ),
3430 .dmc_txc_dma_page_handle( dmc_txc_dma8_page_handle ),
3431 .txc_dmc_dma_inc_head(txc_dmc_dma8_inc_head),
3432 .dmc_txc_dma_partial ( dmc_txc_dma8_partial ),
3433 .NoOfValidEntries ( NoOfValidEntries),
3434 .inc_DMAHeadShadow(inc_DMA8HeadShadow),
3435 .updateCacheWritePtrs(updateCacheWritePtrs[8] ),
3436 .receivedErrorResp(receivedErrorResp[8]),
3437 .ResetDMARdPtr(ResetDMA8RdPtr),
3438 .meta_resp_address(meta_resp_address[2:0]),
3439 .updateCacheContext(updateCacheContext[8]),
3440 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma8_staddr[37:0]),
3441 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3442 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3443 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3444 .tx_rng_cfg_dma_len(tx_rng_cfg_dma8_len[`RNG_LENGTH_WIDTH -1 :0]),
3445 .tx_rng_tail_dma(tx_rng_tail_dma8[`PTR_WIDTH:0]),
3446 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma8_stall),
3447 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma8_rst ),
3448 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma8_stop),
3449 .dma_reset_done_hold (dma8_reset_done_hold),
3450 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3451 .DMANumToReq(DMANumToReq[4:0]),
3452 .dmc_txc_dma_cacheready(dmc_txc_dma8_cacheready),
3453 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3454 .IncrDMARdPtr(IncrDMA8RdPtr),
3455 .SysClk(SysClk),
3456 .Reset_L(Reset_L));
3457
3458// DMA9
3459niu_tdmc_dmacontext niu_tdmc_dmacontext_9 (/*AUTOJUNK*/
3460 // Outputs
3461 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA9[`PTR_WIDTH - 1 :0]),
3462 .DMA_Address(DMA9_Address[63:0]),
3463 .DMA_Ring_Wrapped(DMA9_Ring_Wrapped),
3464 .DMA_RingLength(DMA9_RingLength[`PTR_WIDTH - 1 :0]),
3465 .DMACacheEntryValid(DMA9CacheEntryValid),
3466 .dmc_txc_dma_active(dmc_txc_dma9_active),
3467 .dmc_txc_dma_eoflist(dmc_txc_dma9_eoflist),
3468 .DMA_EmptySpace(DMA9_EmptySpace[3:0]),
3469 .tx_rng_head_dma(tx_rng_head_dma9[`PTR_WIDTH:0]),
3470 .DMA_AvailableFor_Fetch(DMA9_AvailableFor_Fetch),
3471 .DMA_ReqPending(DMA9_ReqPending),
3472 .DMA_EntriesValid(DMA9_EntriesValid[4:0]),
3473 .DMA_CacheEmpty(DMA9_CacheEmpty),
3474 .DMA_CacheReadPtr(DMA9_CacheReadPtr[3:0]),
3475 .DMA_CacheWritePtrReOrder(DMA9_CacheWritePtrReOrder[3:0]),
3476 .dma_reset_scheduled ( dma9_reset_scheduled ),
3477 .dma_clear_reset ( dma9_clear_reset ),
3478 .set_conf_part_error_dma(set_conf_part_error_dma9),
3479 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma9),
3480 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma9_stop_state),
3481 .meta_entries_requested_dma(meta_entries_requested_dma9),
3482 .dma_debug_port (dma9_debug_port),
3483
3484 // Inputs
3485 .page0_mask_dma ( page0_mask_dma9 ),
3486 .page0_value_dma( page0_value_dma9 ),
3487 .page0_reloc_dma( page0_reloc_dma9 ),
3488 .page0_valid_dma( page0_valid_dma9 ),
3489 .page1_mask_dma ( page1_mask_dma9 ),
3490 .page1_value_dma( page1_value_dma9 ),
3491 .page1_reloc_dma( page1_reloc_dma9 ),
3492 .page1_valid_dma( page1_valid_dma9 ),
3493 .dmc_txc_dma_page_handle( dmc_txc_dma9_page_handle ),
3494 .txc_dmc_dma_inc_head(txc_dmc_dma9_inc_head),
3495 .dmc_txc_dma_partial ( dmc_txc_dma9_partial ),
3496 .NoOfValidEntries ( NoOfValidEntries),
3497 .inc_DMAHeadShadow(inc_DMA9HeadShadow),
3498 .updateCacheWritePtrs(updateCacheWritePtrs[9] ),
3499 .receivedErrorResp(receivedErrorResp[9]),
3500 .ResetDMARdPtr(ResetDMA9RdPtr),
3501 .meta_resp_address(meta_resp_address[2:0]),
3502 .updateCacheContext(updateCacheContext[9]),
3503 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma9_staddr[37:0]),
3504 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3505 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3506 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3507 .tx_rng_cfg_dma_len(tx_rng_cfg_dma9_len[`RNG_LENGTH_WIDTH -1 :0]),
3508 .tx_rng_tail_dma(tx_rng_tail_dma9[`PTR_WIDTH:0]),
3509 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma9_stall),
3510 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma9_rst ),
3511 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma9_stop),
3512 .dma_reset_done_hold (dma9_reset_done_hold),
3513 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3514 .DMANumToReq(DMANumToReq[4:0]),
3515 .dmc_txc_dma_cacheready(dmc_txc_dma9_cacheready),
3516 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3517 .IncrDMARdPtr(IncrDMA9RdPtr),
3518 .SysClk(SysClk),
3519 .Reset_L(Reset_L));
3520
3521// DMA10
3522niu_tdmc_dmacontext niu_tdmc_dmacontext_10 (/*AUTOJUNK*/
3523 // Outputs
3524 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA10[`PTR_WIDTH - 1 :0]),
3525 .DMA_Address(DMA10_Address[63:0]),
3526 .DMA_Ring_Wrapped(DMA10_Ring_Wrapped),
3527 .DMA_RingLength(DMA10_RingLength[`PTR_WIDTH - 1 :0]),
3528 .DMACacheEntryValid(DMA10CacheEntryValid),
3529 .dmc_txc_dma_active(dmc_txc_dma10_active),
3530 .dmc_txc_dma_eoflist(dmc_txc_dma10_eoflist),
3531 .DMA_EmptySpace(DMA10_EmptySpace[3:0]),
3532 .tx_rng_head_dma(tx_rng_head_dma10[`PTR_WIDTH:0]),
3533 .DMA_AvailableFor_Fetch(DMA10_AvailableFor_Fetch),
3534 .DMA_ReqPending(DMA10_ReqPending),
3535 .DMA_EntriesValid(DMA10_EntriesValid[4:0]),
3536 .DMA_CacheEmpty(DMA10_CacheEmpty),
3537 .DMA_CacheReadPtr(DMA10_CacheReadPtr[3:0]),
3538 .DMA_CacheWritePtrReOrder(DMA10_CacheWritePtrReOrder[3:0]),
3539 .dma_reset_scheduled ( dma10_reset_scheduled ),
3540 .dma_clear_reset ( dma10_clear_reset ),
3541 .set_conf_part_error_dma(set_conf_part_error_dma10),
3542 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma10),
3543 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma10_stop_state),
3544 .meta_entries_requested_dma(meta_entries_requested_dma10),
3545 .dma_debug_port (dma10_debug_port),
3546
3547 // Inputs
3548 .page0_mask_dma ( page0_mask_dma10 ),
3549 .page0_value_dma( page0_value_dma10 ),
3550 .page0_reloc_dma( page0_reloc_dma10 ),
3551 .page0_valid_dma( page0_valid_dma10 ),
3552 .page1_mask_dma ( page1_mask_dma10 ),
3553 .page1_value_dma( page1_value_dma10 ),
3554 .page1_reloc_dma( page1_reloc_dma10 ),
3555 .page1_valid_dma( page1_valid_dma10 ),
3556 .dmc_txc_dma_page_handle( dmc_txc_dma10_page_handle ),
3557 .txc_dmc_dma_inc_head(txc_dmc_dma10_inc_head),
3558 .dmc_txc_dma_partial ( dmc_txc_dma10_partial ),
3559 .NoOfValidEntries ( NoOfValidEntries),
3560 .inc_DMAHeadShadow(inc_DMA10HeadShadow),
3561 .updateCacheWritePtrs(updateCacheWritePtrs[10] ),
3562 .receivedErrorResp(receivedErrorResp[10]),
3563 .ResetDMARdPtr(ResetDMA10RdPtr),
3564 .meta_resp_address(meta_resp_address[2:0]),
3565 .updateCacheContext(updateCacheContext[10]),
3566 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma10_staddr[37:0]),
3567 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3568 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3569 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3570 .tx_rng_cfg_dma_len(tx_rng_cfg_dma10_len[`RNG_LENGTH_WIDTH -1 :0]),
3571 .tx_rng_tail_dma(tx_rng_tail_dma10[`PTR_WIDTH:0]),
3572 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma10_stall),
3573 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma10_rst ),
3574 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma10_stop),
3575 .dma_reset_done_hold (dma10_reset_done_hold),
3576 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3577 .DMANumToReq(DMANumToReq[4:0]),
3578 .dmc_txc_dma_cacheready(dmc_txc_dma10_cacheready),
3579 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3580 .IncrDMARdPtr(IncrDMA10RdPtr),
3581 .SysClk(SysClk),
3582 .Reset_L(Reset_L));
3583
3584// DMA11
3585niu_tdmc_dmacontext niu_tdmc_dmacontext_11 (/*AUTOJUNK*/
3586 // Outputs
3587 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA11[`PTR_WIDTH - 1 :0]),
3588 .DMA_Address(DMA11_Address[63:0]),
3589 .DMA_Ring_Wrapped(DMA11_Ring_Wrapped),
3590 .DMA_RingLength(DMA11_RingLength[`PTR_WIDTH - 1 :0]),
3591 .DMACacheEntryValid(DMA11CacheEntryValid),
3592 .dmc_txc_dma_active(dmc_txc_dma11_active),
3593 .dmc_txc_dma_eoflist(dmc_txc_dma11_eoflist),
3594 .DMA_EmptySpace(DMA11_EmptySpace[3:0]),
3595 .tx_rng_head_dma(tx_rng_head_dma11[`PTR_WIDTH:0]),
3596 .DMA_AvailableFor_Fetch(DMA11_AvailableFor_Fetch),
3597 .DMA_ReqPending(DMA11_ReqPending),
3598 .DMA_EntriesValid(DMA11_EntriesValid[4:0]),
3599 .DMA_CacheEmpty(DMA11_CacheEmpty),
3600 .DMA_CacheReadPtr(DMA11_CacheReadPtr[3:0]),
3601 .DMA_CacheWritePtrReOrder(DMA11_CacheWritePtrReOrder[3:0]),
3602 .dma_reset_scheduled ( dma11_reset_scheduled ),
3603 .dma_clear_reset ( dma11_clear_reset ),
3604 .set_conf_part_error_dma(set_conf_part_error_dma11),
3605 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma11),
3606 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma11_stop_state),
3607 .meta_entries_requested_dma(meta_entries_requested_dma11),
3608 .dma_debug_port (dma11_debug_port),
3609
3610 // Inputs
3611 .page0_mask_dma ( page0_mask_dma11 ),
3612 .page0_value_dma( page0_value_dma11 ),
3613 .page0_reloc_dma( page0_reloc_dma11 ),
3614 .page0_valid_dma( page0_valid_dma11 ),
3615 .page1_mask_dma ( page1_mask_dma11 ),
3616 .page1_value_dma( page1_value_dma11 ),
3617 .page1_reloc_dma( page1_reloc_dma11 ),
3618 .page1_valid_dma( page1_valid_dma11 ),
3619 .dmc_txc_dma_page_handle( dmc_txc_dma11_page_handle ),
3620 .txc_dmc_dma_inc_head(txc_dmc_dma11_inc_head),
3621 .dmc_txc_dma_partial ( dmc_txc_dma11_partial ),
3622 .NoOfValidEntries ( NoOfValidEntries),
3623 .inc_DMAHeadShadow(inc_DMA11HeadShadow),
3624 .updateCacheWritePtrs(updateCacheWritePtrs[11] ),
3625 .receivedErrorResp(receivedErrorResp[11]),
3626 .ResetDMARdPtr(ResetDMA11RdPtr),
3627 .meta_resp_address(meta_resp_address[2:0]),
3628 .updateCacheContext(updateCacheContext[11]),
3629 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma11_staddr[37:0]),
3630 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3631 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3632 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3633 .tx_rng_cfg_dma_len(tx_rng_cfg_dma11_len[`RNG_LENGTH_WIDTH -1 :0]),
3634 .tx_rng_tail_dma(tx_rng_tail_dma11[`PTR_WIDTH:0]),
3635 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma11_stall),
3636 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma11_rst ),
3637 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma11_stop),
3638 .dma_reset_done_hold (dma11_reset_done_hold),
3639 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3640 .DMANumToReq(DMANumToReq[4:0]),
3641 .dmc_txc_dma_cacheready(dmc_txc_dma11_cacheready),
3642 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3643 .IncrDMARdPtr(IncrDMA11RdPtr),
3644 .SysClk(SysClk),
3645 .Reset_L(Reset_L));
3646
3647// DMA12
3648niu_tdmc_dmacontext niu_tdmc_dmacontext_12 (/*AUTOJUNK*/
3649 // Outputs
3650 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA12[`PTR_WIDTH - 1 :0]),
3651 .DMA_Address(DMA12_Address[63:0]),
3652 .DMA_Ring_Wrapped(DMA12_Ring_Wrapped),
3653 .DMA_RingLength(DMA12_RingLength[`PTR_WIDTH - 1 :0]),
3654 .DMACacheEntryValid(DMA12CacheEntryValid),
3655 .dmc_txc_dma_active(dmc_txc_dma12_active),
3656 .dmc_txc_dma_eoflist(dmc_txc_dma12_eoflist),
3657 .DMA_EmptySpace(DMA12_EmptySpace[3:0]),
3658 .tx_rng_head_dma(tx_rng_head_dma12[`PTR_WIDTH:0]),
3659 .DMA_AvailableFor_Fetch(DMA12_AvailableFor_Fetch),
3660 .DMA_ReqPending(DMA12_ReqPending),
3661 .DMA_EntriesValid(DMA12_EntriesValid[4:0]),
3662 .DMA_CacheEmpty(DMA12_CacheEmpty),
3663 .DMA_CacheReadPtr(DMA12_CacheReadPtr[3:0]),
3664 .DMA_CacheWritePtrReOrder(DMA12_CacheWritePtrReOrder[3:0]),
3665 .dma_reset_scheduled ( dma12_reset_scheduled ),
3666 .dma_clear_reset ( dma12_clear_reset ),
3667 .set_conf_part_error_dma(set_conf_part_error_dma12),
3668 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma12),
3669 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma12_stop_state),
3670 .meta_entries_requested_dma(meta_entries_requested_dma12),
3671 .dma_debug_port (dma12_debug_port),
3672
3673 // Inputs
3674 .page0_mask_dma ( page0_mask_dma12 ),
3675 .page0_value_dma( page0_value_dma12 ),
3676 .page0_reloc_dma( page0_reloc_dma12 ),
3677 .page0_valid_dma( page0_valid_dma12 ),
3678 .page1_mask_dma ( page1_mask_dma12 ),
3679 .page1_value_dma( page1_value_dma12 ),
3680 .page1_reloc_dma( page1_reloc_dma12 ),
3681 .page1_valid_dma( page1_valid_dma12 ),
3682 .dmc_txc_dma_page_handle( dmc_txc_dma12_page_handle ),
3683 .txc_dmc_dma_inc_head(txc_dmc_dma12_inc_head),
3684 .dmc_txc_dma_partial ( dmc_txc_dma12_partial ),
3685 .NoOfValidEntries ( NoOfValidEntries),
3686 .inc_DMAHeadShadow(inc_DMA12HeadShadow),
3687 .updateCacheWritePtrs(updateCacheWritePtrs[12] ),
3688 .receivedErrorResp(receivedErrorResp[12]),
3689 .ResetDMARdPtr(ResetDMA12RdPtr),
3690 .meta_resp_address(meta_resp_address[2:0]),
3691 .updateCacheContext(updateCacheContext[12]),
3692 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma12_staddr[37:0]),
3693 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3694 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3695 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3696 .tx_rng_cfg_dma_len(tx_rng_cfg_dma12_len[`RNG_LENGTH_WIDTH -1 :0]),
3697 .tx_rng_tail_dma(tx_rng_tail_dma12[`PTR_WIDTH:0]),
3698 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma12_stall),
3699 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma12_rst ),
3700 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma12_stop),
3701 .dma_reset_done_hold (dma12_reset_done_hold),
3702 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3703 .DMANumToReq(DMANumToReq[4:0]),
3704 .dmc_txc_dma_cacheready(dmc_txc_dma12_cacheready),
3705 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3706 .IncrDMARdPtr(IncrDMA12RdPtr),
3707 .SysClk(SysClk),
3708 .Reset_L(Reset_L));
3709
3710// DMA13
3711niu_tdmc_dmacontext niu_tdmc_dmacontext_13 (/*AUTOJUNK*/
3712 // Outputs
3713 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA13[`PTR_WIDTH - 1 :0]),
3714 .DMA_Address(DMA13_Address[63:0]),
3715 .DMA_Ring_Wrapped(DMA13_Ring_Wrapped),
3716 .DMA_RingLength(DMA13_RingLength[`PTR_WIDTH - 1 :0]),
3717 .DMACacheEntryValid(DMA13CacheEntryValid),
3718 .dmc_txc_dma_active(dmc_txc_dma13_active),
3719 .dmc_txc_dma_eoflist(dmc_txc_dma13_eoflist),
3720 .DMA_EmptySpace(DMA13_EmptySpace[3:0]),
3721 .tx_rng_head_dma(tx_rng_head_dma13[`PTR_WIDTH:0]),
3722 .DMA_AvailableFor_Fetch(DMA13_AvailableFor_Fetch),
3723 .DMA_ReqPending(DMA13_ReqPending),
3724 .DMA_EntriesValid(DMA13_EntriesValid[4:0]),
3725 .DMA_CacheEmpty(DMA13_CacheEmpty),
3726 .DMA_CacheReadPtr(DMA13_CacheReadPtr[3:0]),
3727 .DMA_CacheWritePtrReOrder(DMA13_CacheWritePtrReOrder[3:0]),
3728 .dma_reset_scheduled ( dma13_reset_scheduled ),
3729 .dma_clear_reset ( dma13_clear_reset ),
3730 .set_conf_part_error_dma(set_conf_part_error_dma13),
3731 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma13),
3732 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma13_stop_state),
3733 .meta_entries_requested_dma(meta_entries_requested_dma13),
3734 .dma_debug_port (dma13_debug_port),
3735
3736 // Inputs
3737 .page0_mask_dma ( page0_mask_dma13 ),
3738 .page0_value_dma( page0_value_dma13 ),
3739 .page0_reloc_dma( page0_reloc_dma13 ),
3740 .page0_valid_dma( page0_valid_dma13 ),
3741 .page1_mask_dma ( page1_mask_dma13 ),
3742 .page1_value_dma( page1_value_dma13 ),
3743 .page1_reloc_dma( page1_reloc_dma13 ),
3744 .page1_valid_dma( page1_valid_dma13 ),
3745 .dmc_txc_dma_page_handle( dmc_txc_dma13_page_handle ),
3746 .txc_dmc_dma_inc_head(txc_dmc_dma13_inc_head),
3747 .dmc_txc_dma_partial ( dmc_txc_dma13_partial ),
3748 .NoOfValidEntries ( NoOfValidEntries),
3749 .inc_DMAHeadShadow(inc_DMA13HeadShadow),
3750 .updateCacheWritePtrs(updateCacheWritePtrs[13] ),
3751 .receivedErrorResp(receivedErrorResp[13]),
3752 .ResetDMARdPtr(ResetDMA13RdPtr),
3753 .meta_resp_address(meta_resp_address[2:0]),
3754 .updateCacheContext(updateCacheContext[13]),
3755 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma13_staddr[37:0]),
3756 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3757 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3758 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3759 .tx_rng_cfg_dma_len(tx_rng_cfg_dma13_len[`RNG_LENGTH_WIDTH -1 :0]),
3760 .tx_rng_tail_dma(tx_rng_tail_dma13[`PTR_WIDTH:0]),
3761 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma13_stall),
3762 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma13_rst ),
3763 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma13_stop),
3764 .dma_reset_done_hold (dma13_reset_done_hold),
3765 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3766 .DMANumToReq(DMANumToReq[4:0]),
3767 .dmc_txc_dma_cacheready(dmc_txc_dma13_cacheready),
3768 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3769 .IncrDMARdPtr(IncrDMA13RdPtr),
3770 .SysClk(SysClk),
3771 .Reset_L(Reset_L));
3772
3773// DMA14
3774niu_tdmc_dmacontext niu_tdmc_dmacontext_14 (/*AUTOJUNK*/
3775 // Outputs
3776 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA14[`PTR_WIDTH - 1 :0]),
3777 .DMA_Address(DMA14_Address[63:0]),
3778 .DMA_Ring_Wrapped(DMA14_Ring_Wrapped),
3779 .DMA_RingLength(DMA14_RingLength[`PTR_WIDTH - 1 :0]),
3780 .DMACacheEntryValid(DMA14CacheEntryValid),
3781 .dmc_txc_dma_active(dmc_txc_dma14_active),
3782 .dmc_txc_dma_eoflist(dmc_txc_dma14_eoflist),
3783 .DMA_EmptySpace(DMA14_EmptySpace[3:0]),
3784 .tx_rng_head_dma(tx_rng_head_dma14[`PTR_WIDTH:0]),
3785 .DMA_AvailableFor_Fetch(DMA14_AvailableFor_Fetch),
3786 .DMA_ReqPending(DMA14_ReqPending),
3787 .DMA_EntriesValid(DMA14_EntriesValid[4:0]),
3788 .DMA_CacheEmpty(DMA14_CacheEmpty),
3789 .DMA_CacheReadPtr(DMA14_CacheReadPtr[3:0]),
3790 .DMA_CacheWritePtrReOrder(DMA14_CacheWritePtrReOrder[3:0]),
3791 .dma_reset_scheduled ( dma14_reset_scheduled ),
3792 .dma_clear_reset ( dma14_clear_reset ),
3793 .set_conf_part_error_dma(set_conf_part_error_dma14),
3794 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma14),
3795 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma14_stop_state),
3796 .meta_entries_requested_dma(meta_entries_requested_dma14),
3797 .dma_debug_port (dma14_debug_port),
3798
3799 // Inputs
3800 .page0_mask_dma ( page0_mask_dma14 ),
3801 .page0_value_dma( page0_value_dma14 ),
3802 .page0_reloc_dma( page0_reloc_dma14 ),
3803 .page0_valid_dma( page0_valid_dma14 ),
3804 .page1_mask_dma ( page1_mask_dma14 ),
3805 .page1_value_dma( page1_value_dma14 ),
3806 .page1_reloc_dma( page1_reloc_dma14 ),
3807 .page1_valid_dma( page1_valid_dma14 ),
3808 .dmc_txc_dma_page_handle( dmc_txc_dma14_page_handle ),
3809 .txc_dmc_dma_inc_head(txc_dmc_dma14_inc_head),
3810 .dmc_txc_dma_partial ( dmc_txc_dma14_partial ),
3811 .NoOfValidEntries ( NoOfValidEntries),
3812 .inc_DMAHeadShadow(inc_DMA14HeadShadow),
3813 .updateCacheWritePtrs(updateCacheWritePtrs[14] ),
3814 .receivedErrorResp(receivedErrorResp[14]),
3815 .ResetDMARdPtr(ResetDMA14RdPtr),
3816 .meta_resp_address(meta_resp_address[2:0]),
3817 .updateCacheContext(updateCacheContext[14]),
3818 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma14_staddr[37:0]),
3819 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3820 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3821 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3822 .tx_rng_cfg_dma_len(tx_rng_cfg_dma14_len[`RNG_LENGTH_WIDTH -1 :0]),
3823 .tx_rng_tail_dma(tx_rng_tail_dma14[`PTR_WIDTH:0]),
3824 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma14_stall),
3825 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma14_rst ),
3826 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma14_stop),
3827 .dma_reset_done_hold (dma14_reset_done_hold),
3828 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3829 .DMANumToReq(DMANumToReq[4:0]),
3830 .dmc_txc_dma_cacheready(dmc_txc_dma14_cacheready),
3831 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3832 .IncrDMARdPtr(IncrDMA14RdPtr),
3833 .SysClk(SysClk),
3834 .Reset_L(Reset_L));
3835
3836// DMA15
3837niu_tdmc_dmacontext niu_tdmc_dmacontext_15 (/*AUTOJUNK*/
3838 // Outputs
3839 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA15[`PTR_WIDTH - 1 :0]),
3840 .DMA_Address(DMA15_Address[63:0]),
3841 .DMA_Ring_Wrapped(DMA15_Ring_Wrapped),
3842 .DMA_RingLength(DMA15_RingLength[`PTR_WIDTH - 1 :0]),
3843 .DMACacheEntryValid(DMA15CacheEntryValid),
3844 .dmc_txc_dma_active(dmc_txc_dma15_active),
3845 .dmc_txc_dma_eoflist(dmc_txc_dma15_eoflist),
3846 .DMA_EmptySpace(DMA15_EmptySpace[3:0]),
3847 .tx_rng_head_dma(tx_rng_head_dma15[`PTR_WIDTH:0]),
3848 .DMA_AvailableFor_Fetch(DMA15_AvailableFor_Fetch),
3849 .DMA_ReqPending(DMA15_ReqPending),
3850 .DMA_EntriesValid(DMA15_EntriesValid[4:0]),
3851 .DMA_CacheEmpty(DMA15_CacheEmpty),
3852 .DMA_CacheReadPtr(DMA15_CacheReadPtr[3:0]),
3853 .DMA_CacheWritePtrReOrder(DMA15_CacheWritePtrReOrder[3:0]),
3854 .dma_reset_scheduled ( dma15_reset_scheduled ),
3855 .dma_clear_reset ( dma15_clear_reset ),
3856 .set_conf_part_error_dma(set_conf_part_error_dma15),
3857 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma15),
3858 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma15_stop_state),
3859 .meta_entries_requested_dma(meta_entries_requested_dma15),
3860 .dma_debug_port (dma15_debug_port),
3861
3862 // Inputs
3863 .page0_mask_dma ( page0_mask_dma15 ),
3864 .page0_value_dma( page0_value_dma15 ),
3865 .page0_reloc_dma( page0_reloc_dma15 ),
3866 .page0_valid_dma( page0_valid_dma15 ),
3867 .page1_mask_dma ( page1_mask_dma15 ),
3868 .page1_value_dma( page1_value_dma15 ),
3869 .page1_reloc_dma( page1_reloc_dma15 ),
3870 .page1_valid_dma( page1_valid_dma15 ),
3871 .dmc_txc_dma_page_handle( dmc_txc_dma15_page_handle ),
3872 .txc_dmc_dma_inc_head(txc_dmc_dma15_inc_head),
3873 .dmc_txc_dma_partial ( dmc_txc_dma15_partial ),
3874 .NoOfValidEntries ( NoOfValidEntries),
3875 .inc_DMAHeadShadow(inc_DMA15HeadShadow),
3876 .updateCacheWritePtrs(updateCacheWritePtrs[15] ),
3877 .receivedErrorResp(receivedErrorResp[15]),
3878 .ResetDMARdPtr(ResetDMA15RdPtr),
3879 .meta_resp_address(meta_resp_address[2:0]),
3880 .updateCacheContext(updateCacheContext[15]),
3881 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma15_staddr[37:0]),
3882 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3883 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3884 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3885 .tx_rng_cfg_dma_len(tx_rng_cfg_dma15_len[`RNG_LENGTH_WIDTH -1 :0]),
3886 .tx_rng_tail_dma(tx_rng_tail_dma15[`PTR_WIDTH:0]),
3887 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma15_stall),
3888 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma15_rst ),
3889 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma15_stop),
3890 .dma_reset_done_hold (dma15_reset_done_hold),
3891 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3892 .DMANumToReq(DMANumToReq[4:0]),
3893 .dmc_txc_dma_cacheready(dmc_txc_dma15_cacheready),
3894 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3895 .IncrDMARdPtr(IncrDMA15RdPtr),
3896 .SysClk(SysClk),
3897 .Reset_L(Reset_L));
3898
3899`ifdef NEPTUNE
3900
3901// DMA16
3902niu_tdmc_dmacontext niu_tdmc_dmacontext_16 (/*AUTOJUNK*/
3903 // Outputs
3904 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA16[`PTR_WIDTH - 1 :0]),
3905 .DMA_Address(DMA16_Address[63:0]),
3906 .DMA_Ring_Wrapped(DMA16_Ring_Wrapped),
3907 .DMA_RingLength(DMA16_RingLength[`PTR_WIDTH - 1 :0]),
3908 .DMACacheEntryValid(DMA16CacheEntryValid),
3909 .dmc_txc_dma_active(dmc_txc_dma16_active),
3910 .dmc_txc_dma_eoflist(dmc_txc_dma16_eoflist),
3911 .DMA_EmptySpace(DMA16_EmptySpace[3:0]),
3912 .tx_rng_head_dma(tx_rng_head_dma16[`PTR_WIDTH:0]),
3913 .DMA_AvailableFor_Fetch(DMA16_AvailableFor_Fetch),
3914 .DMA_ReqPending(DMA16_ReqPending),
3915 .DMA_EntriesValid(DMA16_EntriesValid[4:0]),
3916 .DMA_CacheEmpty(DMA16_CacheEmpty),
3917 .DMA_CacheReadPtr(DMA16_CacheReadPtr[3:0]),
3918 .DMA_CacheWritePtrReOrder(DMA16_CacheWritePtrReOrder[3:0]),
3919 .dma_reset_scheduled ( dma16_reset_scheduled ),
3920 .dma_clear_reset ( dma16_clear_reset ),
3921 .set_conf_part_error_dma(set_conf_part_error_dma16),
3922 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma16),
3923 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma16_stop_state),
3924 .meta_entries_requested_dma(meta_entries_requested_dma16),
3925 .dma_debug_port (dma16_debug_port),
3926
3927 // Inputs
3928 .page0_mask_dma ( page0_mask_dma16 ),
3929 .page0_value_dma( page0_value_dma16 ),
3930 .page0_reloc_dma( page0_reloc_dma16 ),
3931 .page0_valid_dma( page0_valid_dma16 ),
3932 .page1_mask_dma ( page1_mask_dma16 ),
3933 .page1_value_dma( page1_value_dma16 ),
3934 .page1_reloc_dma( page1_reloc_dma16 ),
3935 .page1_valid_dma( page1_valid_dma16 ),
3936 .dmc_txc_dma_page_handle( dmc_txc_dma16_page_handle ),
3937 .txc_dmc_dma_inc_head(txc_dmc_dma16_inc_head),
3938 .dmc_txc_dma_partial ( dmc_txc_dma16_partial ),
3939 .NoOfValidEntries ( NoOfValidEntries),
3940 .inc_DMAHeadShadow(inc_DMA16HeadShadow),
3941 .updateCacheWritePtrs(updateCacheWritePtrs[16] ),
3942 .receivedErrorResp(receivedErrorResp[16]),
3943 .ResetDMARdPtr(ResetDMA16RdPtr),
3944 .meta_resp_address(meta_resp_address[2:0]),
3945 .updateCacheContext(updateCacheContext[16]),
3946 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma16_staddr[37:0]),
3947 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
3948 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
3949 .DMA_UpdateAddress ( DMA_UpdateAddress ),
3950 .tx_rng_cfg_dma_len(tx_rng_cfg_dma16_len[`RNG_LENGTH_WIDTH -1 :0]),
3951 .tx_rng_tail_dma(tx_rng_tail_dma16[`PTR_WIDTH:0]),
3952 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma16_stall),
3953 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma16_rst ),
3954 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma16_stop),
3955 .dma_reset_done_hold (dma16_reset_done_hold),
3956 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
3957 .DMANumToReq(DMANumToReq[4:0]),
3958 .dmc_txc_dma_cacheready(dmc_txc_dma16_cacheready),
3959 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
3960 .IncrDMARdPtr(IncrDMA16RdPtr),
3961 .SysClk(SysClk),
3962 .Reset_L(Reset_L));
3963
3964// DMA17
3965niu_tdmc_dmacontext niu_tdmc_dmacontext_17 (/*AUTOJUNK*/
3966 // Outputs
3967 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA17[`PTR_WIDTH - 1 :0]),
3968 .DMA_Address(DMA17_Address[63:0]),
3969 .DMA_Ring_Wrapped(DMA17_Ring_Wrapped),
3970 .DMA_RingLength(DMA17_RingLength[`PTR_WIDTH - 1 :0]),
3971 .DMACacheEntryValid(DMA17CacheEntryValid),
3972 .dmc_txc_dma_active(dmc_txc_dma17_active),
3973 .dmc_txc_dma_eoflist(dmc_txc_dma17_eoflist),
3974 .DMA_EmptySpace(DMA17_EmptySpace[3:0]),
3975 .tx_rng_head_dma(tx_rng_head_dma17[`PTR_WIDTH:0]),
3976 .DMA_AvailableFor_Fetch(DMA17_AvailableFor_Fetch),
3977 .DMA_ReqPending(DMA17_ReqPending),
3978 .DMA_EntriesValid(DMA17_EntriesValid[4:0]),
3979 .DMA_CacheEmpty(DMA17_CacheEmpty),
3980 .DMA_CacheReadPtr(DMA17_CacheReadPtr[3:0]),
3981 .DMA_CacheWritePtrReOrder(DMA17_CacheWritePtrReOrder[3:0]),
3982 .dma_reset_scheduled ( dma17_reset_scheduled ),
3983 .dma_clear_reset ( dma17_clear_reset ),
3984 .set_conf_part_error_dma(set_conf_part_error_dma17),
3985 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma17),
3986 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma17_stop_state),
3987 .meta_entries_requested_dma(meta_entries_requested_dma17),
3988 .dma_debug_port (dma17_debug_port),
3989
3990 // Inputs
3991 .page0_mask_dma ( page0_mask_dma17 ),
3992 .page0_value_dma( page0_value_dma17 ),
3993 .page0_reloc_dma( page0_reloc_dma17 ),
3994 .page0_valid_dma( page0_valid_dma17 ),
3995 .page1_mask_dma ( page1_mask_dma17 ),
3996 .page1_value_dma( page1_value_dma17 ),
3997 .page1_reloc_dma( page1_reloc_dma17 ),
3998 .page1_valid_dma( page1_valid_dma17 ),
3999 .dmc_txc_dma_page_handle( dmc_txc_dma17_page_handle ),
4000 .txc_dmc_dma_inc_head(txc_dmc_dma17_inc_head),
4001 .dmc_txc_dma_partial ( dmc_txc_dma17_partial ),
4002 .NoOfValidEntries ( NoOfValidEntries),
4003 .inc_DMAHeadShadow(inc_DMA17HeadShadow),
4004 .updateCacheWritePtrs(updateCacheWritePtrs[17] ),
4005 .receivedErrorResp(receivedErrorResp[17]),
4006 .ResetDMARdPtr(ResetDMA17RdPtr),
4007 .meta_resp_address(meta_resp_address[2:0]),
4008 .updateCacheContext(updateCacheContext[17]),
4009 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma17_staddr[37:0]),
4010 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4011 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4012 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4013 .tx_rng_cfg_dma_len(tx_rng_cfg_dma17_len[`RNG_LENGTH_WIDTH -1 :0]),
4014 .tx_rng_tail_dma(tx_rng_tail_dma17[`PTR_WIDTH:0]),
4015 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma17_stall),
4016 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma17_rst ),
4017 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma17_stop),
4018 .dma_reset_done_hold (dma17_reset_done_hold),
4019 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4020 .DMANumToReq(DMANumToReq[4:0]),
4021 .dmc_txc_dma_cacheready(dmc_txc_dma17_cacheready),
4022 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4023 .IncrDMARdPtr(IncrDMA17RdPtr),
4024 .SysClk(SysClk),
4025 .Reset_L(Reset_L));
4026
4027// DMA18
4028niu_tdmc_dmacontext niu_tdmc_dmacontext_18 (/*AUTOJUNK*/
4029 // Outputs
4030 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA18[`PTR_WIDTH - 1 :0]),
4031 .DMA_Address(DMA18_Address[63:0]),
4032 .DMA_Ring_Wrapped(DMA18_Ring_Wrapped),
4033 .DMA_RingLength(DMA18_RingLength[`PTR_WIDTH - 1 :0]),
4034 .DMACacheEntryValid(DMA18CacheEntryValid),
4035 .dmc_txc_dma_active(dmc_txc_dma18_active),
4036 .dmc_txc_dma_eoflist(dmc_txc_dma18_eoflist),
4037 .DMA_EmptySpace(DMA18_EmptySpace[3:0]),
4038 .tx_rng_head_dma(tx_rng_head_dma18[`PTR_WIDTH:0]),
4039 .DMA_AvailableFor_Fetch(DMA18_AvailableFor_Fetch),
4040 .DMA_ReqPending(DMA18_ReqPending),
4041 .DMA_EntriesValid(DMA18_EntriesValid[4:0]),
4042 .DMA_CacheEmpty(DMA18_CacheEmpty),
4043 .DMA_CacheReadPtr(DMA18_CacheReadPtr[3:0]),
4044 .DMA_CacheWritePtrReOrder(DMA18_CacheWritePtrReOrder[3:0]),
4045 .dma_reset_scheduled ( dma18_reset_scheduled ),
4046 .dma_clear_reset ( dma18_clear_reset ),
4047 .set_conf_part_error_dma(set_conf_part_error_dma18),
4048 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma18),
4049 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma18_stop_state),
4050 .meta_entries_requested_dma(meta_entries_requested_dma18),
4051 .dma_debug_port (dma18_debug_port),
4052
4053 // Inputs
4054 .page0_mask_dma ( page0_mask_dma18 ),
4055 .page0_value_dma( page0_value_dma18 ),
4056 .page0_reloc_dma( page0_reloc_dma18 ),
4057 .page0_valid_dma( page0_valid_dma18 ),
4058 .page1_mask_dma ( page1_mask_dma18 ),
4059 .page1_value_dma( page1_value_dma18 ),
4060 .page1_reloc_dma( page1_reloc_dma18 ),
4061 .page1_valid_dma( page1_valid_dma18 ),
4062 .dmc_txc_dma_page_handle( dmc_txc_dma18_page_handle ),
4063 .txc_dmc_dma_inc_head(txc_dmc_dma18_inc_head),
4064 .dmc_txc_dma_partial ( dmc_txc_dma18_partial ),
4065 .NoOfValidEntries ( NoOfValidEntries),
4066 .inc_DMAHeadShadow(inc_DMA18HeadShadow),
4067 .updateCacheWritePtrs(updateCacheWritePtrs[18] ),
4068 .receivedErrorResp(receivedErrorResp[18]),
4069 .ResetDMARdPtr(ResetDMA18RdPtr),
4070 .meta_resp_address(meta_resp_address[2:0]),
4071 .updateCacheContext(updateCacheContext[18]),
4072 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma18_staddr[37:0]),
4073 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4074 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4075 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4076 .tx_rng_cfg_dma_len(tx_rng_cfg_dma18_len[`RNG_LENGTH_WIDTH -1 :0]),
4077 .tx_rng_tail_dma(tx_rng_tail_dma18[`PTR_WIDTH:0]),
4078 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma18_stall),
4079 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma18_rst ),
4080 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma18_stop),
4081 .dma_reset_done_hold (dma18_reset_done_hold),
4082 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4083 .DMANumToReq(DMANumToReq[4:0]),
4084 .dmc_txc_dma_cacheready(dmc_txc_dma18_cacheready),
4085 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4086 .IncrDMARdPtr(IncrDMA18RdPtr),
4087 .SysClk(SysClk),
4088 .Reset_L(Reset_L));
4089
4090// DMA19
4091niu_tdmc_dmacontext niu_tdmc_dmacontext_19 (/*AUTOJUNK*/
4092 // Outputs
4093 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA19[`PTR_WIDTH - 1 :0]),
4094 .DMA_Address(DMA19_Address[63:0]),
4095 .DMA_Ring_Wrapped(DMA19_Ring_Wrapped),
4096 .DMA_RingLength(DMA19_RingLength[`PTR_WIDTH - 1 :0]),
4097 .DMACacheEntryValid(DMA19CacheEntryValid),
4098 .dmc_txc_dma_active(dmc_txc_dma19_active),
4099 .dmc_txc_dma_eoflist(dmc_txc_dma19_eoflist),
4100 .DMA_EmptySpace(DMA19_EmptySpace[3:0]),
4101 .tx_rng_head_dma(tx_rng_head_dma19[`PTR_WIDTH:0]),
4102 .DMA_AvailableFor_Fetch(DMA19_AvailableFor_Fetch),
4103 .DMA_ReqPending(DMA19_ReqPending),
4104 .DMA_EntriesValid(DMA19_EntriesValid[4:0]),
4105 .DMA_CacheEmpty(DMA19_CacheEmpty),
4106 .DMA_CacheReadPtr(DMA19_CacheReadPtr[3:0]),
4107 .DMA_CacheWritePtrReOrder(DMA19_CacheWritePtrReOrder[3:0]),
4108 .dma_reset_scheduled ( dma19_reset_scheduled ),
4109 .dma_clear_reset ( dma19_clear_reset ),
4110 .set_conf_part_error_dma(set_conf_part_error_dma19),
4111 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma19),
4112 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma19_stop_state),
4113 .meta_entries_requested_dma(meta_entries_requested_dma19),
4114 .dma_debug_port (dma19_debug_port),
4115
4116 // Inputs
4117 .page0_mask_dma ( page0_mask_dma19 ),
4118 .page0_value_dma( page0_value_dma19 ),
4119 .page0_reloc_dma( page0_reloc_dma19 ),
4120 .page0_valid_dma( page0_valid_dma19 ),
4121 .page1_mask_dma ( page1_mask_dma19 ),
4122 .page1_value_dma( page1_value_dma19 ),
4123 .page1_reloc_dma( page1_reloc_dma19 ),
4124 .page1_valid_dma( page1_valid_dma19 ),
4125 .dmc_txc_dma_page_handle( dmc_txc_dma19_page_handle ),
4126 .txc_dmc_dma_inc_head(txc_dmc_dma19_inc_head),
4127 .dmc_txc_dma_partial ( dmc_txc_dma19_partial ),
4128 .NoOfValidEntries ( NoOfValidEntries),
4129 .inc_DMAHeadShadow(inc_DMA19HeadShadow),
4130 .updateCacheWritePtrs(updateCacheWritePtrs[19] ),
4131 .receivedErrorResp(receivedErrorResp[19]),
4132 .ResetDMARdPtr(ResetDMA19RdPtr),
4133 .meta_resp_address(meta_resp_address[2:0]),
4134 .updateCacheContext(updateCacheContext[19]),
4135 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma19_staddr[37:0]),
4136 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4137 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4138 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4139 .tx_rng_cfg_dma_len(tx_rng_cfg_dma19_len[`RNG_LENGTH_WIDTH -1 :0]),
4140 .tx_rng_tail_dma(tx_rng_tail_dma19[`PTR_WIDTH:0]),
4141 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma19_stall),
4142 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma19_rst ),
4143 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma19_stop),
4144 .dma_reset_done_hold (dma19_reset_done_hold),
4145 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4146 .DMANumToReq(DMANumToReq[4:0]),
4147 .dmc_txc_dma_cacheready(dmc_txc_dma19_cacheready),
4148 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4149 .IncrDMARdPtr(IncrDMA19RdPtr),
4150 .SysClk(SysClk),
4151 .Reset_L(Reset_L));
4152
4153// DMA20
4154niu_tdmc_dmacontext niu_tdmc_dmacontext_20 (/*AUTOJUNK*/
4155 // Outputs
4156 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA20[`PTR_WIDTH - 1 :0]),
4157 .DMA_Address(DMA20_Address[63:0]),
4158 .DMA_Ring_Wrapped(DMA20_Ring_Wrapped),
4159 .DMA_RingLength(DMA20_RingLength[`PTR_WIDTH - 1 :0]),
4160 .DMACacheEntryValid(DMA20CacheEntryValid),
4161 .dmc_txc_dma_active(dmc_txc_dma20_active),
4162 .dmc_txc_dma_eoflist(dmc_txc_dma20_eoflist),
4163 .DMA_EmptySpace(DMA20_EmptySpace[3:0]),
4164 .tx_rng_head_dma(tx_rng_head_dma20[`PTR_WIDTH:0]),
4165 .DMA_AvailableFor_Fetch(DMA20_AvailableFor_Fetch),
4166 .DMA_ReqPending(DMA20_ReqPending),
4167 .DMA_EntriesValid(DMA20_EntriesValid[4:0]),
4168 .DMA_CacheEmpty(DMA20_CacheEmpty),
4169 .DMA_CacheReadPtr(DMA20_CacheReadPtr[3:0]),
4170 .DMA_CacheWritePtrReOrder(DMA20_CacheWritePtrReOrder[3:0]),
4171 .dma_reset_scheduled ( dma20_reset_scheduled ),
4172 .dma_clear_reset ( dma20_clear_reset ),
4173 .set_conf_part_error_dma(set_conf_part_error_dma20),
4174 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma20),
4175 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma20_stop_state),
4176 .meta_entries_requested_dma(meta_entries_requested_dma20),
4177 .dma_debug_port (dma20_debug_port),
4178
4179 // Inputs
4180 .page0_mask_dma ( page0_mask_dma20 ),
4181 .page0_value_dma( page0_value_dma20 ),
4182 .page0_reloc_dma( page0_reloc_dma20 ),
4183 .page0_valid_dma( page0_valid_dma20 ),
4184 .page1_mask_dma ( page1_mask_dma20 ),
4185 .page1_value_dma( page1_value_dma20 ),
4186 .page1_reloc_dma( page1_reloc_dma20 ),
4187 .page1_valid_dma( page1_valid_dma20 ),
4188 .dmc_txc_dma_page_handle( dmc_txc_dma20_page_handle ),
4189 .txc_dmc_dma_inc_head(txc_dmc_dma20_inc_head),
4190 .dmc_txc_dma_partial ( dmc_txc_dma20_partial ),
4191 .NoOfValidEntries ( NoOfValidEntries),
4192 .inc_DMAHeadShadow(inc_DMA20HeadShadow),
4193 .updateCacheWritePtrs(updateCacheWritePtrs[20] ),
4194 .receivedErrorResp(receivedErrorResp[20]),
4195 .ResetDMARdPtr(ResetDMA20RdPtr),
4196 .meta_resp_address(meta_resp_address[2:0]),
4197 .updateCacheContext(updateCacheContext[20]),
4198 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma20_staddr[37:0]),
4199 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4200 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4201 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4202 .tx_rng_cfg_dma_len(tx_rng_cfg_dma20_len[`RNG_LENGTH_WIDTH -1 :0]),
4203 .tx_rng_tail_dma(tx_rng_tail_dma20[`PTR_WIDTH:0]),
4204 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma20_stall),
4205 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma20_rst ),
4206 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma20_stop),
4207 .dma_reset_done_hold (dma20_reset_done_hold),
4208 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4209 .DMANumToReq(DMANumToReq[4:0]),
4210 .dmc_txc_dma_cacheready(dmc_txc_dma20_cacheready),
4211 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4212 .IncrDMARdPtr(IncrDMA20RdPtr),
4213 .SysClk(SysClk),
4214 .Reset_L(Reset_L));
4215
4216// DMA21
4217niu_tdmc_dmacontext niu_tdmc_dmacontext_21 (/*AUTOJUNK*/
4218 // Outputs
4219 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA21[`PTR_WIDTH - 1 :0]),
4220 .DMA_Address(DMA21_Address[63:0]),
4221 .DMA_Ring_Wrapped(DMA21_Ring_Wrapped),
4222 .DMA_RingLength(DMA21_RingLength[`PTR_WIDTH - 1 :0]),
4223 .DMACacheEntryValid(DMA21CacheEntryValid),
4224 .dmc_txc_dma_active(dmc_txc_dma21_active),
4225 .dmc_txc_dma_eoflist(dmc_txc_dma21_eoflist),
4226 .DMA_EmptySpace(DMA21_EmptySpace[3:0]),
4227 .tx_rng_head_dma(tx_rng_head_dma21[`PTR_WIDTH:0]),
4228 .DMA_AvailableFor_Fetch(DMA21_AvailableFor_Fetch),
4229 .DMA_ReqPending(DMA21_ReqPending),
4230 .DMA_EntriesValid(DMA21_EntriesValid[4:0]),
4231 .DMA_CacheEmpty(DMA21_CacheEmpty),
4232 .DMA_CacheReadPtr(DMA21_CacheReadPtr[3:0]),
4233 .DMA_CacheWritePtrReOrder(DMA21_CacheWritePtrReOrder[3:0]),
4234 .dma_reset_scheduled ( dma21_reset_scheduled ),
4235 .dma_clear_reset ( dma21_clear_reset ),
4236 .set_conf_part_error_dma(set_conf_part_error_dma21),
4237 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma21),
4238 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma21_stop_state),
4239 .meta_entries_requested_dma(meta_entries_requested_dma21),
4240 .dma_debug_port (dma21_debug_port),
4241
4242 // Inputs
4243 .page0_mask_dma ( page0_mask_dma21 ),
4244 .page0_value_dma( page0_value_dma21 ),
4245 .page0_reloc_dma( page0_reloc_dma21 ),
4246 .page0_valid_dma( page0_valid_dma21 ),
4247 .page1_mask_dma ( page1_mask_dma21 ),
4248 .page1_value_dma( page1_value_dma21 ),
4249 .page1_reloc_dma( page1_reloc_dma21 ),
4250 .page1_valid_dma( page1_valid_dma21 ),
4251 .dmc_txc_dma_page_handle( dmc_txc_dma21_page_handle ),
4252 .txc_dmc_dma_inc_head(txc_dmc_dma21_inc_head),
4253 .dmc_txc_dma_partial ( dmc_txc_dma21_partial ),
4254 .NoOfValidEntries ( NoOfValidEntries),
4255 .inc_DMAHeadShadow(inc_DMA21HeadShadow),
4256 .updateCacheWritePtrs(updateCacheWritePtrs[21] ),
4257 .receivedErrorResp(receivedErrorResp[21]),
4258 .ResetDMARdPtr(ResetDMA21RdPtr),
4259 .meta_resp_address(meta_resp_address[2:0]),
4260 .updateCacheContext(updateCacheContext[21]),
4261 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma21_staddr[37:0]),
4262 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4263 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4264 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4265 .tx_rng_cfg_dma_len(tx_rng_cfg_dma21_len[`RNG_LENGTH_WIDTH -1 :0]),
4266 .tx_rng_tail_dma(tx_rng_tail_dma21[`PTR_WIDTH:0]),
4267 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma21_stall),
4268 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma21_rst ),
4269 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma21_stop),
4270 .dma_reset_done_hold (dma21_reset_done_hold),
4271 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4272 .DMANumToReq(DMANumToReq[4:0]),
4273 .dmc_txc_dma_cacheready(dmc_txc_dma21_cacheready),
4274 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4275 .IncrDMARdPtr(IncrDMA21RdPtr),
4276 .SysClk(SysClk),
4277 .Reset_L(Reset_L));
4278
4279// DMA22
4280niu_tdmc_dmacontext niu_tdmc_dmacontext_22 (/*AUTOJUNK*/
4281 // Outputs
4282 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA22[`PTR_WIDTH - 1 :0]),
4283 .DMA_Address(DMA22_Address[63:0]),
4284 .DMA_Ring_Wrapped(DMA22_Ring_Wrapped),
4285 .DMA_RingLength(DMA22_RingLength[`PTR_WIDTH - 1 :0]),
4286 .DMACacheEntryValid(DMA22CacheEntryValid),
4287 .dmc_txc_dma_active(dmc_txc_dma22_active),
4288 .dmc_txc_dma_eoflist(dmc_txc_dma22_eoflist),
4289 .DMA_EmptySpace(DMA22_EmptySpace[3:0]),
4290 .tx_rng_head_dma(tx_rng_head_dma22[`PTR_WIDTH:0]),
4291 .DMA_AvailableFor_Fetch(DMA22_AvailableFor_Fetch),
4292 .DMA_ReqPending(DMA22_ReqPending),
4293 .DMA_EntriesValid(DMA22_EntriesValid[4:0]),
4294 .DMA_CacheEmpty(DMA22_CacheEmpty),
4295 .DMA_CacheReadPtr(DMA22_CacheReadPtr[3:0]),
4296 .DMA_CacheWritePtrReOrder(DMA22_CacheWritePtrReOrder[3:0]),
4297 .dma_reset_scheduled ( dma22_reset_scheduled ),
4298 .dma_clear_reset ( dma22_clear_reset ),
4299 .set_conf_part_error_dma(set_conf_part_error_dma22),
4300 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma22),
4301 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma22_stop_state),
4302 .meta_entries_requested_dma(meta_entries_requested_dma22),
4303 .dma_debug_port (dma22_debug_port),
4304
4305 // Inputs
4306 .page0_mask_dma ( page0_mask_dma22 ),
4307 .page0_value_dma( page0_value_dma22 ),
4308 .page0_reloc_dma( page0_reloc_dma22 ),
4309 .page0_valid_dma( page0_valid_dma22 ),
4310 .page1_mask_dma ( page1_mask_dma22 ),
4311 .page1_value_dma( page1_value_dma22 ),
4312 .page1_reloc_dma( page1_reloc_dma22 ),
4313 .page1_valid_dma( page1_valid_dma22 ),
4314 .dmc_txc_dma_page_handle( dmc_txc_dma22_page_handle ),
4315 .txc_dmc_dma_inc_head(txc_dmc_dma22_inc_head),
4316 .dmc_txc_dma_partial ( dmc_txc_dma22_partial ),
4317 .NoOfValidEntries ( NoOfValidEntries),
4318 .inc_DMAHeadShadow(inc_DMA22HeadShadow),
4319 .updateCacheWritePtrs(updateCacheWritePtrs[22] ),
4320 .receivedErrorResp(receivedErrorResp[22]),
4321 .ResetDMARdPtr(ResetDMA22RdPtr),
4322 .meta_resp_address(meta_resp_address[2:0]),
4323 .updateCacheContext(updateCacheContext[22]),
4324 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma22_staddr[37:0]),
4325 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4326 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4327 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4328 .tx_rng_cfg_dma_len(tx_rng_cfg_dma22_len[`RNG_LENGTH_WIDTH -1 :0]),
4329 .tx_rng_tail_dma(tx_rng_tail_dma22[`PTR_WIDTH:0]),
4330 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma22_stall),
4331 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma22_rst ),
4332 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma22_stop),
4333 .dma_reset_done_hold (dma22_reset_done_hold),
4334 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4335 .DMANumToReq(DMANumToReq[4:0]),
4336 .dmc_txc_dma_cacheready(dmc_txc_dma22_cacheready),
4337 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4338 .IncrDMARdPtr(IncrDMA22RdPtr),
4339 .SysClk(SysClk),
4340 .Reset_L(Reset_L));
4341
4342// DMA23
4343niu_tdmc_dmacontext niu_tdmc_dmacontext_23 (/*AUTOJUNK*/
4344 // Outputs
4345 .ShadowRingCurrentPtr_DMA(ShadowRingCurrentPtr_DMA23[`PTR_WIDTH - 1 :0]),
4346 .DMA_Address(DMA23_Address[63:0]),
4347 .DMA_Ring_Wrapped(DMA23_Ring_Wrapped),
4348 .DMA_RingLength(DMA23_RingLength[`PTR_WIDTH - 1 :0]),
4349 .DMACacheEntryValid(DMA23CacheEntryValid),
4350 .dmc_txc_dma_active(dmc_txc_dma23_active),
4351 .dmc_txc_dma_eoflist(dmc_txc_dma23_eoflist),
4352 .DMA_EmptySpace(DMA23_EmptySpace[3:0]),
4353 .tx_rng_head_dma(tx_rng_head_dma23[`PTR_WIDTH:0]),
4354 .DMA_AvailableFor_Fetch(DMA23_AvailableFor_Fetch),
4355 .DMA_ReqPending(DMA23_ReqPending),
4356 .DMA_EntriesValid(DMA23_EntriesValid[4:0]),
4357 .DMA_CacheEmpty(DMA23_CacheEmpty),
4358 .DMA_CacheReadPtr(DMA23_CacheReadPtr[3:0]),
4359 .DMA_CacheWritePtrReOrder(DMA23_CacheWritePtrReOrder[3:0]),
4360 .dma_reset_scheduled ( dma23_reset_scheduled ),
4361 .dma_clear_reset ( dma23_clear_reset ),
4362 .set_conf_part_error_dma(set_conf_part_error_dma23),
4363 .set_tx_ring_oflow_dma(set_tx_ring_oflow_dma23),
4364 .tx_dma_cfg_dma_stop_state(tx_dma_cfg_dma23_stop_state),
4365 .meta_entries_requested_dma(meta_entries_requested_dma23),
4366 .dma_debug_port (dma23_debug_port),
4367
4368 // Inputs
4369 .page0_mask_dma ( page0_mask_dma23 ),
4370 .page0_value_dma( page0_value_dma23 ),
4371 .page0_reloc_dma( page0_reloc_dma23 ),
4372 .page0_valid_dma( page0_valid_dma23 ),
4373 .page1_mask_dma ( page1_mask_dma23 ),
4374 .page1_value_dma( page1_value_dma23 ),
4375 .page1_reloc_dma( page1_reloc_dma23 ),
4376 .page1_valid_dma( page1_valid_dma23 ),
4377 .dmc_txc_dma_page_handle( dmc_txc_dma23_page_handle ),
4378 .txc_dmc_dma_inc_head(txc_dmc_dma23_inc_head),
4379 .dmc_txc_dma_partial ( dmc_txc_dma23_partial ),
4380 .NoOfValidEntries ( NoOfValidEntries),
4381 .inc_DMAHeadShadow(inc_DMA23HeadShadow),
4382 .updateCacheWritePtrs(updateCacheWritePtrs[23] ),
4383 .receivedErrorResp(receivedErrorResp[23]),
4384 .ResetDMARdPtr(ResetDMA23RdPtr),
4385 .meta_resp_address(meta_resp_address[2:0]),
4386 .updateCacheContext(updateCacheContext[23]),
4387 .tx_rng_cfg_dma_staddr(tx_rng_cfg_dma23_staddr[37:0]),
4388 .meta_req_address(DMC_TxCache_SMX_Req_Address[7:0]),
4389 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4390 .DMA_UpdateAddress ( DMA_UpdateAddress ),
4391 .tx_rng_cfg_dma_len(tx_rng_cfg_dma23_len[`RNG_LENGTH_WIDTH -1 :0]),
4392 .tx_rng_tail_dma(tx_rng_tail_dma23[`PTR_WIDTH:0]),
4393 .tx_dma_cfg_dma_stall(tx_dma_cfg_dma23_stall),
4394 .tx_dma_cfg_dma_rst (tx_dma_cfg_dma23_rst ),
4395 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma23_stop),
4396 .dma_reset_done_hold (dma23_reset_done_hold),
4397 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4398 .DMANumToReq(DMANumToReq[4:0]),
4399 .dmc_txc_dma_cacheready(dmc_txc_dma23_cacheready),
4400 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4401 .IncrDMARdPtr(IncrDMA23RdPtr),
4402 .SysClk(SysClk),
4403 .Reset_L(Reset_L));
4404
4405
4406`endif // ifdef NEPTUNE
4407
4408
4409 niu_dmc_dmaarb dma_req_arb ( .SysClk(SysClk),
4410 .Reset_L(Reset_L),
4411 .Choose_DMAs(choose_available_dmas),
4412 .DMA_Reqs(DMAs_AvailableFor_Fetch),
4413 .ArbDone(ArbDone),
4414 .DMANum(DMANumToReqArbOut),
4415 .DMAsGranted(DMANumToUpdate)
4416
4417 );
4418
4419 // this will change to accomodate new ptr manipulations
4420
4421 niu_tdmc_addrcalc niu_tdmc_addrcalc (/*AUTOJUNK*/
4422 // Outputs
4423 .NoOfDescInMem(NoOfDescInMem[`PTR_WIDTH - 1 :0]),
4424 .NoOfDescLeft(NoOfDescLeft[`PTR_WIDTH - 1 :0]),
4425 .NoOfFreeSpaceInCache(NoOfFreeSpaceInCache[4:0]),
4426 .ShadowRingWrap(ShadowRingWrap),
4427 .DMA_AddressToReq_ff(DMA_AddressToReq_ff[63:0]),
4428 // Inputs
4429 .LatchDMAPtrs(LatchDMAPtrs),
4430 .DMANumToReq(DMANumToReq[4:0]),
4431 .tx_rng_tail_dma0(tx_rng_tail_dma0[`PTR_WIDTH:0]),
4432 .ShadowRingCurrentPtr_DMA0(ShadowRingCurrentPtr_DMA0[`PTR_WIDTH - 1 :0]),
4433 .DMA0_EmptySpace(DMA0_EmptySpace[3:0]),
4434 .DMA0_RingLength(DMA0_RingLength[`PTR_WIDTH - 1 :0]),
4435 .DMA0_Ring_Wrapped(DMA0_Ring_Wrapped),
4436 .DMA0_Address(DMA0_Address[63:0]),
4437 .tx_rng_tail_dma1(tx_rng_tail_dma1[`PTR_WIDTH:0]),
4438 .ShadowRingCurrentPtr_DMA1(ShadowRingCurrentPtr_DMA1[`PTR_WIDTH - 1 :0]),
4439 .DMA1_EmptySpace(DMA1_EmptySpace[3:0]),
4440 .DMA1_RingLength(DMA1_RingLength[`PTR_WIDTH - 1 :0]),
4441 .DMA1_Ring_Wrapped(DMA1_Ring_Wrapped),
4442 .DMA1_Address(DMA1_Address[63:0]),
4443 .tx_rng_tail_dma2(tx_rng_tail_dma2[`PTR_WIDTH:0]),
4444 .ShadowRingCurrentPtr_DMA2(ShadowRingCurrentPtr_DMA2[`PTR_WIDTH - 1 :0]),
4445 .DMA2_EmptySpace(DMA2_EmptySpace[3:0]),
4446 .DMA2_RingLength(DMA2_RingLength[`PTR_WIDTH - 1 :0]),
4447 .DMA2_Ring_Wrapped(DMA2_Ring_Wrapped),
4448 .DMA2_Address(DMA2_Address[63:0]),
4449 .tx_rng_tail_dma3(tx_rng_tail_dma3[`PTR_WIDTH:0]),
4450 .ShadowRingCurrentPtr_DMA3(ShadowRingCurrentPtr_DMA3[`PTR_WIDTH - 1 :0]),
4451 .DMA3_EmptySpace(DMA3_EmptySpace[3:0]),
4452 .DMA3_RingLength(DMA3_RingLength[`PTR_WIDTH - 1 :0]),
4453 .DMA3_Ring_Wrapped(DMA3_Ring_Wrapped),
4454 .DMA3_Address(DMA3_Address[63:0]),
4455 .tx_rng_tail_dma4(tx_rng_tail_dma4[`PTR_WIDTH:0]),
4456 .ShadowRingCurrentPtr_DMA4(ShadowRingCurrentPtr_DMA4[`PTR_WIDTH - 1 :0]),
4457 .DMA4_EmptySpace(DMA4_EmptySpace[3:0]),
4458 .DMA4_RingLength(DMA4_RingLength[`PTR_WIDTH - 1 :0]),
4459 .DMA4_Ring_Wrapped(DMA4_Ring_Wrapped),
4460 .DMA4_Address(DMA4_Address[63:0]),
4461 .tx_rng_tail_dma5(tx_rng_tail_dma5[`PTR_WIDTH:0]),
4462 .ShadowRingCurrentPtr_DMA5(ShadowRingCurrentPtr_DMA5[`PTR_WIDTH - 1 :0]),
4463 .DMA5_EmptySpace(DMA5_EmptySpace[3:0]),
4464 .DMA5_RingLength(DMA5_RingLength[`PTR_WIDTH - 1 :0]),
4465 .DMA5_Ring_Wrapped(DMA5_Ring_Wrapped),
4466 .DMA5_Address(DMA5_Address[63:0]),
4467 .tx_rng_tail_dma6(tx_rng_tail_dma6[`PTR_WIDTH:0]),
4468 .ShadowRingCurrentPtr_DMA6(ShadowRingCurrentPtr_DMA6[`PTR_WIDTH - 1 :0]),
4469 .DMA6_EmptySpace(DMA6_EmptySpace[3:0]),
4470 .DMA6_RingLength(DMA6_RingLength[`PTR_WIDTH - 1 :0]),
4471 .DMA6_Ring_Wrapped(DMA6_Ring_Wrapped),
4472 .DMA6_Address(DMA6_Address[63:0]),
4473 .tx_rng_tail_dma7(tx_rng_tail_dma7[`PTR_WIDTH:0]),
4474 .ShadowRingCurrentPtr_DMA7(ShadowRingCurrentPtr_DMA7[`PTR_WIDTH - 1 :0]),
4475 .DMA7_EmptySpace(DMA7_EmptySpace[3:0]),
4476 .DMA7_RingLength(DMA7_RingLength[`PTR_WIDTH - 1 :0]),
4477 .DMA7_Ring_Wrapped(DMA7_Ring_Wrapped),
4478 .DMA7_Address(DMA7_Address[63:0]),
4479 .tx_rng_tail_dma8(tx_rng_tail_dma8[`PTR_WIDTH:0]),
4480 .ShadowRingCurrentPtr_DMA8(ShadowRingCurrentPtr_DMA8[`PTR_WIDTH - 1 :0]),
4481 .DMA8_EmptySpace(DMA8_EmptySpace[3:0]),
4482 .DMA8_RingLength(DMA8_RingLength[`PTR_WIDTH - 1 :0]),
4483 .DMA8_Ring_Wrapped(DMA8_Ring_Wrapped),
4484 .DMA8_Address(DMA8_Address[63:0]),
4485 .tx_rng_tail_dma9(tx_rng_tail_dma9[`PTR_WIDTH:0]),
4486 .ShadowRingCurrentPtr_DMA9(ShadowRingCurrentPtr_DMA9[`PTR_WIDTH - 1 :0]),
4487 .DMA9_EmptySpace(DMA9_EmptySpace[3:0]),
4488 .DMA9_RingLength(DMA9_RingLength[`PTR_WIDTH - 1 :0]),
4489 .DMA9_Ring_Wrapped(DMA9_Ring_Wrapped),
4490 .DMA9_Address(DMA9_Address[63:0]),
4491 .tx_rng_tail_dma10(tx_rng_tail_dma10[`PTR_WIDTH:0]),
4492 .ShadowRingCurrentPtr_DMA10(ShadowRingCurrentPtr_DMA10[`PTR_WIDTH - 1 :0]),
4493 .DMA10_EmptySpace(DMA10_EmptySpace[3:0]),
4494 .DMA10_RingLength(DMA10_RingLength[`PTR_WIDTH - 1 :0]),
4495 .DMA10_Ring_Wrapped(DMA10_Ring_Wrapped),
4496 .DMA10_Address(DMA10_Address[63:0]),
4497 .tx_rng_tail_dma11(tx_rng_tail_dma11[`PTR_WIDTH:0]),
4498 .ShadowRingCurrentPtr_DMA11(ShadowRingCurrentPtr_DMA11[`PTR_WIDTH - 1 :0]),
4499 .DMA11_EmptySpace(DMA11_EmptySpace[3:0]),
4500 .DMA11_RingLength(DMA11_RingLength[`PTR_WIDTH - 1 :0]),
4501 .DMA11_Ring_Wrapped(DMA11_Ring_Wrapped),
4502 .DMA11_Address(DMA11_Address[63:0]),
4503 .tx_rng_tail_dma12(tx_rng_tail_dma12[`PTR_WIDTH:0]),
4504 .ShadowRingCurrentPtr_DMA12(ShadowRingCurrentPtr_DMA12[`PTR_WIDTH - 1 :0]),
4505 .DMA12_EmptySpace(DMA12_EmptySpace[3:0]),
4506 .DMA12_RingLength(DMA12_RingLength[`PTR_WIDTH - 1 :0]),
4507 .DMA12_Ring_Wrapped(DMA12_Ring_Wrapped),
4508 .DMA12_Address(DMA12_Address[63:0]),
4509 .tx_rng_tail_dma13(tx_rng_tail_dma13[`PTR_WIDTH:0]),
4510 .ShadowRingCurrentPtr_DMA13(ShadowRingCurrentPtr_DMA13[`PTR_WIDTH - 1 :0]),
4511 .DMA13_EmptySpace(DMA13_EmptySpace[3:0]),
4512 .DMA13_RingLength(DMA13_RingLength[`PTR_WIDTH - 1 :0]),
4513 .DMA13_Ring_Wrapped(DMA13_Ring_Wrapped),
4514 .DMA13_Address(DMA13_Address[63:0]),
4515 .tx_rng_tail_dma14(tx_rng_tail_dma14[`PTR_WIDTH:0]),
4516 .ShadowRingCurrentPtr_DMA14(ShadowRingCurrentPtr_DMA14[`PTR_WIDTH - 1 :0]),
4517 .DMA14_EmptySpace(DMA14_EmptySpace[3:0]),
4518 .DMA14_RingLength(DMA14_RingLength[`PTR_WIDTH - 1 :0]),
4519 .DMA14_Ring_Wrapped(DMA14_Ring_Wrapped),
4520 .DMA14_Address(DMA14_Address[63:0]),
4521 .tx_rng_tail_dma15(tx_rng_tail_dma15[`PTR_WIDTH:0]),
4522 .ShadowRingCurrentPtr_DMA15(ShadowRingCurrentPtr_DMA15[`PTR_WIDTH - 1 :0]),
4523 .DMA15_EmptySpace(DMA15_EmptySpace[3:0]),
4524 .DMA15_RingLength(DMA15_RingLength[`PTR_WIDTH - 1 :0]),
4525 .DMA15_Ring_Wrapped(DMA15_Ring_Wrapped),
4526 .DMA15_Address(DMA15_Address[63:0]),
4527`ifdef NEPTUNE
4528
4529 .tx_rng_tail_dma16(tx_rng_tail_dma16[`PTR_WIDTH:0]),
4530 .ShadowRingCurrentPtr_DMA16(ShadowRingCurrentPtr_DMA16[`PTR_WIDTH - 1 :0]),
4531 .DMA16_EmptySpace(DMA16_EmptySpace[3:0]),
4532 .DMA16_RingLength(DMA16_RingLength[`PTR_WIDTH - 1 :0]),
4533 .DMA16_Ring_Wrapped(DMA16_Ring_Wrapped),
4534 .DMA16_Address(DMA16_Address[63:0]),
4535 .tx_rng_tail_dma17(tx_rng_tail_dma17[`PTR_WIDTH:0]),
4536 .ShadowRingCurrentPtr_DMA17(ShadowRingCurrentPtr_DMA17[`PTR_WIDTH - 1 :0]),
4537 .DMA17_EmptySpace(DMA17_EmptySpace[3:0]),
4538 .DMA17_RingLength(DMA17_RingLength[`PTR_WIDTH - 1 :0]),
4539 .DMA17_Ring_Wrapped(DMA17_Ring_Wrapped),
4540 .DMA17_Address(DMA17_Address[63:0]),
4541 .tx_rng_tail_dma18(tx_rng_tail_dma18[`PTR_WIDTH:0]),
4542 .ShadowRingCurrentPtr_DMA18(ShadowRingCurrentPtr_DMA18[`PTR_WIDTH - 1 :0]),
4543 .DMA18_EmptySpace(DMA18_EmptySpace[3:0]),
4544 .DMA18_RingLength(DMA18_RingLength[`PTR_WIDTH - 1 :0]),
4545 .DMA18_Ring_Wrapped(DMA18_Ring_Wrapped),
4546 .DMA18_Address(DMA18_Address[63:0]),
4547 .tx_rng_tail_dma19(tx_rng_tail_dma19[`PTR_WIDTH:0]),
4548 .ShadowRingCurrentPtr_DMA19(ShadowRingCurrentPtr_DMA19[`PTR_WIDTH - 1 :0]),
4549 .DMA19_EmptySpace(DMA19_EmptySpace[3:0]),
4550 .DMA19_RingLength(DMA19_RingLength[`PTR_WIDTH - 1 :0]),
4551 .DMA19_Ring_Wrapped(DMA19_Ring_Wrapped),
4552 .DMA19_Address(DMA19_Address[63:0]),
4553 .tx_rng_tail_dma20(tx_rng_tail_dma20[`PTR_WIDTH:0]),
4554 .ShadowRingCurrentPtr_DMA20(ShadowRingCurrentPtr_DMA20[`PTR_WIDTH - 1 :0]),
4555 .DMA20_EmptySpace(DMA20_EmptySpace[3:0]),
4556 .DMA20_RingLength(DMA20_RingLength[`PTR_WIDTH - 1 :0]),
4557 .DMA20_Ring_Wrapped(DMA20_Ring_Wrapped),
4558 .DMA20_Address(DMA20_Address[63:0]),
4559 .tx_rng_tail_dma21(tx_rng_tail_dma21[`PTR_WIDTH:0]),
4560 .ShadowRingCurrentPtr_DMA21(ShadowRingCurrentPtr_DMA21[`PTR_WIDTH - 1 :0]),
4561 .DMA21_EmptySpace(DMA21_EmptySpace[3:0]),
4562 .DMA21_RingLength(DMA21_RingLength[`PTR_WIDTH - 1 :0]),
4563 .DMA21_Ring_Wrapped(DMA21_Ring_Wrapped),
4564 .DMA21_Address(DMA21_Address[63:0]),
4565 .tx_rng_tail_dma22(tx_rng_tail_dma22[`PTR_WIDTH:0]),
4566 .ShadowRingCurrentPtr_DMA22(ShadowRingCurrentPtr_DMA22[`PTR_WIDTH - 1 :0]),
4567 .DMA22_EmptySpace(DMA22_EmptySpace[3:0]),
4568 .DMA22_RingLength(DMA22_RingLength[`PTR_WIDTH - 1 :0]),
4569 .DMA22_Ring_Wrapped(DMA22_Ring_Wrapped),
4570 .DMA22_Address(DMA22_Address[63:0]),
4571 .tx_rng_tail_dma23(tx_rng_tail_dma23[`PTR_WIDTH:0]),
4572 .ShadowRingCurrentPtr_DMA23(ShadowRingCurrentPtr_DMA23[`PTR_WIDTH - 1 :0]),
4573 .DMA23_EmptySpace(DMA23_EmptySpace[3:0]),
4574 .DMA23_RingLength(DMA23_RingLength[`PTR_WIDTH - 1 :0]),
4575 .DMA23_Ring_Wrapped(DMA23_Ring_Wrapped),
4576 .DMA23_Address(DMA23_Address[63:0]),
4577`endif // ifdef NEPTUNE
4578
4579
4580 .SysClk(SysClk),
4581 .Reset_L(Reset_L));
4582
4583
4584 niu_tdmc_cachefetch niu_tdmc_cachefetch (/*AUTOJUNK*/
4585 // Outputs
4586 .choose_available_dmas(choose_available_dmas),
4587 .TxCacheFetchState(TxCacheFetchState),
4588 .updateCacheContext(updateCacheContext[`NO_OF_DMAS - 1 :0]),
4589 .DMC_TxCache_SMX_Req(DMC_TxCache_SMX_Req),
4590 .DMC_TxCache_SMX_Req_Port_Num(DMC_TxCache_SMX_Req_Port_Num[1:0]),
4591 .DMC_TxCache_SMX_Req_Address(DMC_TxCache_SMX_Req_Address[63:0]),
4592 .DMA_UpdateAddress(DMA_UpdateAddress[43:0]),
4593 .DMC_TxCache_SMX_Req_Length(DMC_TxCache_SMX_Req_Length[13:0]),
4594 .DMC_TxCache_SMX_Req_Cmd(DMC_TxCache_SMX_Req_Cmd[7:0]),
4595 .DMC_TxCache_SMX_Req_DMA_Num(DMC_TxCache_SMX_Req_DMA_Num[4:0]),
4596 .tdmc_arb1_req_func_num(tdmc_arb1_req_func_num),
4597 .LatchDMAPtrs(LatchDMAPtrs),
4598 .DMANumToReq(DMANumToReq[4:0]),
4599 .NoOfCacheWritesDispatched(NoOfCacheWritesDispatched[3:0]),
4600 .DMAs_AvailableFor_Fetch(DMAs_AvailableFor_Fetch[31:0]),
4601 // Inputs
4602 .SysClk(SysClk),
4603 .Reset_L(Reset_L),
4604 .DMA0_AvailableFor_Fetch(DMA0_AvailableFor_Fetch),
4605 .DMA1_AvailableFor_Fetch(DMA1_AvailableFor_Fetch),
4606 .DMA2_AvailableFor_Fetch(DMA2_AvailableFor_Fetch),
4607 .DMA3_AvailableFor_Fetch(DMA3_AvailableFor_Fetch),
4608 .DMA4_AvailableFor_Fetch(DMA4_AvailableFor_Fetch),
4609 .DMA5_AvailableFor_Fetch(DMA5_AvailableFor_Fetch),
4610 .DMA6_AvailableFor_Fetch(DMA6_AvailableFor_Fetch),
4611 .DMA7_AvailableFor_Fetch(DMA7_AvailableFor_Fetch),
4612 .DMA8_AvailableFor_Fetch(DMA8_AvailableFor_Fetch),
4613 .DMA9_AvailableFor_Fetch(DMA9_AvailableFor_Fetch),
4614 .DMA10_AvailableFor_Fetch(DMA10_AvailableFor_Fetch),
4615 .DMA11_AvailableFor_Fetch(DMA11_AvailableFor_Fetch),
4616 .DMA12_AvailableFor_Fetch(DMA12_AvailableFor_Fetch),
4617 .DMA13_AvailableFor_Fetch(DMA13_AvailableFor_Fetch),
4618 .DMA14_AvailableFor_Fetch(DMA14_AvailableFor_Fetch),
4619 .DMA15_AvailableFor_Fetch(DMA15_AvailableFor_Fetch),
4620`ifdef NEPTUNE
4621 .DMA16_AvailableFor_Fetch(DMA16_AvailableFor_Fetch),
4622 .DMA17_AvailableFor_Fetch(DMA17_AvailableFor_Fetch),
4623 .DMA18_AvailableFor_Fetch(DMA18_AvailableFor_Fetch),
4624 .DMA19_AvailableFor_Fetch(DMA19_AvailableFor_Fetch),
4625 .DMA20_AvailableFor_Fetch(DMA20_AvailableFor_Fetch),
4626 .DMA21_AvailableFor_Fetch(DMA21_AvailableFor_Fetch),
4627 .DMA22_AvailableFor_Fetch(DMA22_AvailableFor_Fetch),
4628 .DMA23_AvailableFor_Fetch(DMA23_AvailableFor_Fetch),
4629`else
4630 .DMA16_AvailableFor_Fetch(1'b0),
4631 .DMA17_AvailableFor_Fetch(1'b0),
4632 .DMA18_AvailableFor_Fetch(1'b0),
4633 .DMA19_AvailableFor_Fetch(1'b0),
4634 .DMA20_AvailableFor_Fetch(1'b0),
4635 .DMA21_AvailableFor_Fetch(1'b0),
4636 .DMA22_AvailableFor_Fetch(1'b0),
4637 .DMA23_AvailableFor_Fetch(1'b0),
4638`endif // ifdef NEPTUNE
4639
4640
4641
4642 .DMA0_ReqPending(DMA0_ReqPending),
4643 .DMA1_ReqPending(DMA1_ReqPending),
4644 .DMA2_ReqPending(DMA2_ReqPending),
4645 .DMA3_ReqPending(DMA3_ReqPending),
4646 .DMA4_ReqPending(DMA4_ReqPending),
4647 .DMA5_ReqPending(DMA5_ReqPending),
4648 .DMA6_ReqPending(DMA6_ReqPending),
4649 .DMA7_ReqPending(DMA7_ReqPending),
4650 .DMA8_ReqPending(DMA8_ReqPending),
4651 .DMA9_ReqPending(DMA9_ReqPending),
4652 .DMA10_ReqPending(DMA10_ReqPending),
4653 .DMA11_ReqPending(DMA11_ReqPending),
4654 .DMA12_ReqPending(DMA12_ReqPending),
4655 .DMA13_ReqPending(DMA13_ReqPending),
4656 .DMA14_ReqPending(DMA14_ReqPending),
4657 .DMA15_ReqPending(DMA15_ReqPending),
4658`ifdef NEPTUNE
4659 .DMA16_ReqPending(DMA16_ReqPending),
4660 .DMA17_ReqPending(DMA17_ReqPending),
4661 .DMA18_ReqPending(DMA18_ReqPending),
4662 .DMA19_ReqPending(DMA19_ReqPending),
4663 .DMA20_ReqPending(DMA20_ReqPending),
4664 .DMA21_ReqPending(DMA21_ReqPending),
4665 .DMA22_ReqPending(DMA22_ReqPending),
4666 .DMA23_ReqPending(DMA23_ReqPending),
4667`else // !ifdef NEPTUNE
4668 .DMA16_ReqPending(1'b0),
4669 .DMA17_ReqPending(1'b0),
4670 .DMA18_ReqPending(1'b0),
4671 .DMA19_ReqPending(1'b0),
4672 .DMA20_ReqPending(1'b0),
4673 .DMA21_ReqPending(1'b0),
4674 .DMA22_ReqPending(1'b0),
4675 .DMA23_ReqPending(1'b0),
4676`endif // ifdef NEPTUNE
4677
4678
4679 .dmc_txc_dma0_func_num(dmc_txc_dma0_func_num[1:0]),
4680 .dmc_txc_dma1_func_num(dmc_txc_dma1_func_num[1:0]),
4681 .dmc_txc_dma2_func_num(dmc_txc_dma2_func_num[1:0]),
4682 .dmc_txc_dma3_func_num(dmc_txc_dma3_func_num[1:0]),
4683 .dmc_txc_dma4_func_num(dmc_txc_dma4_func_num[1:0]),
4684 .dmc_txc_dma5_func_num(dmc_txc_dma5_func_num[1:0]),
4685 .dmc_txc_dma6_func_num(dmc_txc_dma6_func_num[1:0]),
4686 .dmc_txc_dma7_func_num(dmc_txc_dma7_func_num[1:0]),
4687 .dmc_txc_dma8_func_num(dmc_txc_dma8_func_num[1:0]),
4688 .dmc_txc_dma9_func_num(dmc_txc_dma9_func_num[1:0]),
4689 .dmc_txc_dma10_func_num(dmc_txc_dma10_func_num[1:0]),
4690 .dmc_txc_dma11_func_num(dmc_txc_dma11_func_num[1:0]),
4691 .dmc_txc_dma12_func_num(dmc_txc_dma12_func_num[1:0]),
4692 .dmc_txc_dma13_func_num(dmc_txc_dma13_func_num[1:0]),
4693 .dmc_txc_dma14_func_num(dmc_txc_dma14_func_num[1:0]),
4694 .dmc_txc_dma15_func_num(dmc_txc_dma15_func_num[1:0]),
4695
4696`ifdef NEPTUNE
4697 .dmc_txc_dma16_func_num(dmc_txc_dma16_func_num[1:0]),
4698 .dmc_txc_dma17_func_num(dmc_txc_dma17_func_num[1:0]),
4699 .dmc_txc_dma18_func_num(dmc_txc_dma18_func_num[1:0]),
4700 .dmc_txc_dma19_func_num(dmc_txc_dma19_func_num[1:0]),
4701 .dmc_txc_dma20_func_num(dmc_txc_dma20_func_num[1:0]),
4702 .dmc_txc_dma21_func_num(dmc_txc_dma21_func_num[1:0]),
4703 .dmc_txc_dma22_func_num(dmc_txc_dma22_func_num[1:0]),
4704 .dmc_txc_dma23_func_num(dmc_txc_dma23_func_num[1:0]),
4705`else // !ifdef NEPTUNE
4706 .dmc_txc_dma16_func_num(2'h0),
4707 .dmc_txc_dma17_func_num(2'h0),
4708 .dmc_txc_dma18_func_num(2'h0),
4709 .dmc_txc_dma19_func_num(2'h0),
4710 .dmc_txc_dma20_func_num(2'h0),
4711 .dmc_txc_dma21_func_num(2'h0),
4712 .dmc_txc_dma22_func_num(2'h0),
4713 .dmc_txc_dma23_func_num(2'h0),
4714`endif // ifdef NEPTUNE
4715
4716
4717 .ArbDone(ArbDone),
4718 .DMANumToReqArbOut(DMANumToReqArbOut[4:0]),
4719 .DMANumToUpdate(DMANumToUpdate[31:0]),
4720 .SMX_DMC_TxCache_Req_Ack(SMX_DMC_TxCache_Req_Ack),
4721 .NoOfDescInMem(NoOfDescInMem[`PTR_WIDTH - 1 :0]),
4722 .NoOfDescLeft(NoOfDescLeft[`PTR_WIDTH - 1 :0]),
4723 .NoOfFreeSpaceInCache(NoOfFreeSpaceInCache[4:0]),
4724 .ShadowRingWrap(ShadowRingWrap),
4725 .DMA_AddressToReq_ff(DMA_AddressToReq_ff[63:0]),
4726 .dmc_txc_tx_addr_md(dmc_txc_tx_addr_md));
4727
4728
4729
4730 // end of module for fetch sm
4731
4732
4733 niu_tdmc_cachewrite niu_tdmc_cachewrite(/*AUTOJUNK*/
4734 // Outputs
4735 .DMC_TxCache_SMX_Resp_Accept(DMC_TxCache_SMX_Resp_Accept),
4736 .updateCacheWritePtrs(updateCacheWritePtrs[`NO_OF_DMAS - 1 :0]),
4737 .receivedErrorResp(receivedErrorResp[`NO_OF_DMAS - 1 :0]),
4738 .meta_resp_dma_num(meta_resp_dma_num[4:0]),
4739 .meta_resp_address(meta_resp_address[3:0]),
4740 .DMA_TxCacheWritePtr(DMA_TxCacheWritePtr[7:0]),
4741 .DMA_TxCacheWrite(DMA_TxCacheWrite),
4742 .NoOfValidEntries(NoOfValidEntries[4:0]),
4743 .DMA_TxCacheWriteEntriesValid(DMA_TxCacheWriteEntriesValid[3:0]),
4744 .DMA_TxCacheWriteData(DMA_TxCacheWriteData[127:0]),
4745 .txpref_dma_nack_resp(txpref_dma_nack_resp[`NO_OF_DMAS - 1 :0]),
4746 .txpref_nack_resp(txpref_nack_resp),
4747 .txpref_nack_rd_addr(txpref_nack_rd_addr[43:0]),
4748 .parity_corrupt_dma_match(parity_corrupt_dma_match),
4749 // Inputs
4750 .SMX_DMC_TxCache_Resp_Rdy(SMX_DMC_TxCache_Resp_Rdy),
4751 .SMX_DMC_TxCache_Resp_DMA_Num(SMX_DMC_TxCache_Resp_DMA_Num[4:0]),
4752 .SMX_DMC_TxCache_Resp_Address(SMX_DMC_TxCache_Resp_Address[63:0]),
4753 .SMX_DMC_TxCache_Trans_Complete(SMX_DMC_TxCache_Trans_Complete),
4754 .SMX_DMC_TxCache_Resp_Complete(SMX_DMC_TxCache_Resp_Complete),
4755 .SMX_DMC_TxCache_Resp_ByteEnables(SMX_DMC_TxCache_Resp_ByteEnables[15:0]),
4756 .SMX_DMC_TxCache_Resp_Data_Length(SMX_DMC_TxCache_Resp_Data_Length[13:0]),
4757 .SMX_DMC_TxCache_Resp_Data_Valid(SMX_DMC_TxCache_Resp_Data_Valid),
4758 .SMX_DMC_TxCache_Resp_Data(SMX_DMC_TxCache_Resp_Data[127:0]),
4759 .meta_dmc_resp_cmd(meta_dmc_resp_cmd[7:0]),
4760 .meta_dmc_resp_cmd_status(meta_dmc_resp_cmd_status[3:0]),
4761 .meta_dmc_data_status(meta_dmc_data_status[3:0]),
4762 .DMA0_CacheWritePtrReOrder(DMA0_CacheWritePtrReOrder[3:0]),
4763 .DMA1_CacheWritePtrReOrder(DMA1_CacheWritePtrReOrder[3:0]),
4764 .DMA2_CacheWritePtrReOrder(DMA2_CacheWritePtrReOrder[3:0]),
4765 .DMA3_CacheWritePtrReOrder(DMA3_CacheWritePtrReOrder[3:0]),
4766 .DMA4_CacheWritePtrReOrder(DMA4_CacheWritePtrReOrder[3:0]),
4767 .DMA5_CacheWritePtrReOrder(DMA5_CacheWritePtrReOrder[3:0]),
4768 .DMA6_CacheWritePtrReOrder(DMA6_CacheWritePtrReOrder[3:0]),
4769 .DMA7_CacheWritePtrReOrder(DMA7_CacheWritePtrReOrder[3:0]),
4770 .DMA8_CacheWritePtrReOrder(DMA8_CacheWritePtrReOrder[3:0]),
4771 .DMA9_CacheWritePtrReOrder(DMA9_CacheWritePtrReOrder[3:0]),
4772 .DMA10_CacheWritePtrReOrder(DMA10_CacheWritePtrReOrder[3:0]),
4773 .DMA11_CacheWritePtrReOrder(DMA11_CacheWritePtrReOrder[3:0]),
4774 .DMA12_CacheWritePtrReOrder(DMA12_CacheWritePtrReOrder[3:0]),
4775 .DMA13_CacheWritePtrReOrder(DMA13_CacheWritePtrReOrder[3:0]),
4776 .DMA14_CacheWritePtrReOrder(DMA14_CacheWritePtrReOrder[3:0]),
4777 .DMA15_CacheWritePtrReOrder(DMA15_CacheWritePtrReOrder[3:0]),
4778`ifdef NEPTUNE
4779
4780 .DMA16_CacheWritePtrReOrder(DMA16_CacheWritePtrReOrder[3:0]),
4781 .DMA17_CacheWritePtrReOrder(DMA17_CacheWritePtrReOrder[3:0]),
4782 .DMA18_CacheWritePtrReOrder(DMA18_CacheWritePtrReOrder[3:0]),
4783 .DMA19_CacheWritePtrReOrder(DMA19_CacheWritePtrReOrder[3:0]),
4784 .DMA20_CacheWritePtrReOrder(DMA20_CacheWritePtrReOrder[3:0]),
4785 .DMA21_CacheWritePtrReOrder(DMA21_CacheWritePtrReOrder[3:0]),
4786 .DMA22_CacheWritePtrReOrder(DMA22_CacheWritePtrReOrder[3:0]),
4787 .DMA23_CacheWritePtrReOrder(DMA23_CacheWritePtrReOrder[3:0]),
4788`endif // ifdef NEPTUNE
4789
4790 .meta_entries_requested_dma0(meta_entries_requested_dma0),
4791 .meta_entries_requested_dma1(meta_entries_requested_dma1),
4792 .meta_entries_requested_dma2(meta_entries_requested_dma2),
4793 .meta_entries_requested_dma3(meta_entries_requested_dma3),
4794 .meta_entries_requested_dma4(meta_entries_requested_dma4),
4795 .meta_entries_requested_dma5(meta_entries_requested_dma5),
4796 .meta_entries_requested_dma6(meta_entries_requested_dma6),
4797 .meta_entries_requested_dma7(meta_entries_requested_dma7),
4798 .meta_entries_requested_dma8(meta_entries_requested_dma8),
4799 .meta_entries_requested_dma9(meta_entries_requested_dma9),
4800 .meta_entries_requested_dma10(meta_entries_requested_dma10),
4801 .meta_entries_requested_dma11(meta_entries_requested_dma11),
4802 .meta_entries_requested_dma12(meta_entries_requested_dma12),
4803 .meta_entries_requested_dma13(meta_entries_requested_dma13),
4804 .meta_entries_requested_dma14(meta_entries_requested_dma14),
4805 .meta_entries_requested_dma15(meta_entries_requested_dma15),
4806`ifdef NEPTUNE
4807 .meta_entries_requested_dma16(meta_entries_requested_dma16),
4808 .meta_entries_requested_dma17(meta_entries_requested_dma17),
4809 .meta_entries_requested_dma18(meta_entries_requested_dma18),
4810 .meta_entries_requested_dma19(meta_entries_requested_dma19),
4811 .meta_entries_requested_dma20(meta_entries_requested_dma20),
4812 .meta_entries_requested_dma21(meta_entries_requested_dma21),
4813 .meta_entries_requested_dma22(meta_entries_requested_dma22),
4814 .meta_entries_requested_dma23(meta_entries_requested_dma23),
4815`endif // ifdef NEPTUNE
4816
4817
4818 .SysClk(SysClk),
4819 .Reset_L(Reset_L));
4820
4821
4822
4823
4824 // TxCache Update Logic--
4825
4826 /*
4827 Tx Cache Organization-
4828
4829 Total Avaibale size - 4K for Tx - 32DMA Channels, 2 cache line (64 bytes) worth of descriptors
4830
4831 The cache RAM is 128 bits wide, and 256 deep
4832
4833 Each DMA can occupy 4 entries in this cache 4*16 - 64Bytes
4834 pointer size - 2 bits + 1 bit for wrap around detection
4835
4836
4837 */
4838
4839
4840
4841 niu_tdmc_cacheread niu_tdmc_cacheread(/*AUTOJUNK*/
4842 // Outputs
4843 .DMA_TxCacheRead(DMA_TxCacheRead),
4844 .DMA_TxCacheReadPtr(DMA_TxCacheReadPtr[7:0]),
4845 .DMA0_CacheReadGnt(DMA0_CacheReadGnt),
4846 .DMA1_CacheReadGnt(DMA1_CacheReadGnt),
4847 .DMA2_CacheReadGnt(DMA2_CacheReadGnt),
4848 .DMA3_CacheReadGnt(DMA3_CacheReadGnt),
4849 .DMA4_CacheReadGnt(DMA4_CacheReadGnt),
4850 .DMA5_CacheReadGnt(DMA5_CacheReadGnt),
4851 .DMA6_CacheReadGnt(DMA6_CacheReadGnt),
4852 .DMA7_CacheReadGnt(DMA7_CacheReadGnt),
4853 .DMA8_CacheReadGnt(DMA8_CacheReadGnt),
4854 .DMA9_CacheReadGnt(DMA9_CacheReadGnt),
4855 .DMA10_CacheReadGnt(DMA10_CacheReadGnt),
4856 .DMA11_CacheReadGnt(DMA11_CacheReadGnt),
4857 .DMA12_CacheReadGnt(DMA12_CacheReadGnt),
4858 .DMA13_CacheReadGnt(DMA13_CacheReadGnt),
4859 .DMA14_CacheReadGnt(DMA14_CacheReadGnt),
4860 .DMA15_CacheReadGnt(DMA15_CacheReadGnt),
4861`ifdef NEPTUNE
4862
4863 .DMA16_CacheReadGnt(DMA16_CacheReadGnt),
4864 .DMA17_CacheReadGnt(DMA17_CacheReadGnt),
4865 .DMA18_CacheReadGnt(DMA18_CacheReadGnt),
4866 .DMA19_CacheReadGnt(DMA19_CacheReadGnt),
4867 .DMA20_CacheReadGnt(DMA20_CacheReadGnt),
4868 .DMA21_CacheReadGnt(DMA21_CacheReadGnt),
4869 .DMA22_CacheReadGnt(DMA22_CacheReadGnt),
4870 .DMA23_CacheReadGnt(DMA23_CacheReadGnt),
4871`endif // ifdef NEPTUNE
4872
4873 // Inputs
4874 .DMA0_CacheReadPtr(DMA0_CacheReadPtr[3:0]),
4875 .DMA0_CacheReadReq(DMA0_CacheReadReq),
4876 .DMA1_CacheReadPtr(DMA1_CacheReadPtr[3:0]),
4877 .DMA1_CacheReadReq(DMA1_CacheReadReq),
4878 .DMA2_CacheReadPtr(DMA2_CacheReadPtr[3:0]),
4879 .DMA2_CacheReadReq(DMA2_CacheReadReq),
4880 .DMA3_CacheReadPtr(DMA3_CacheReadPtr[3:0]),
4881 .DMA3_CacheReadReq(DMA3_CacheReadReq),
4882 .DMA4_CacheReadPtr(DMA4_CacheReadPtr[3:0]),
4883 .DMA4_CacheReadReq(DMA4_CacheReadReq),
4884 .DMA5_CacheReadPtr(DMA5_CacheReadPtr[3:0]),
4885 .DMA5_CacheReadReq(DMA5_CacheReadReq),
4886 .DMA6_CacheReadPtr(DMA6_CacheReadPtr[3:0]),
4887 .DMA6_CacheReadReq(DMA6_CacheReadReq),
4888 .DMA7_CacheReadPtr(DMA7_CacheReadPtr[3:0]),
4889 .DMA7_CacheReadReq(DMA7_CacheReadReq),
4890 .DMA8_CacheReadPtr(DMA8_CacheReadPtr[3:0]),
4891 .DMA8_CacheReadReq(DMA8_CacheReadReq),
4892 .DMA9_CacheReadPtr(DMA9_CacheReadPtr[3:0]),
4893 .DMA9_CacheReadReq(DMA9_CacheReadReq),
4894 .DMA10_CacheReadPtr(DMA10_CacheReadPtr[3:0]),
4895 .DMA10_CacheReadReq(DMA10_CacheReadReq),
4896 .DMA11_CacheReadPtr(DMA11_CacheReadPtr[3:0]),
4897 .DMA11_CacheReadReq(DMA11_CacheReadReq),
4898 .DMA12_CacheReadPtr(DMA12_CacheReadPtr[3:0]),
4899 .DMA12_CacheReadReq(DMA12_CacheReadReq),
4900 .DMA13_CacheReadPtr(DMA13_CacheReadPtr[3:0]),
4901 .DMA13_CacheReadReq(DMA13_CacheReadReq),
4902 .DMA14_CacheReadPtr(DMA14_CacheReadPtr[3:0]),
4903 .DMA14_CacheReadReq(DMA14_CacheReadReq),
4904 .DMA15_CacheReadPtr(DMA15_CacheReadPtr[3:0]),
4905 .DMA15_CacheReadReq(DMA15_CacheReadReq),
4906`ifdef NEPTUNE
4907
4908 .DMA16_CacheReadPtr(DMA16_CacheReadPtr[3:0]),
4909 .DMA16_CacheReadReq(DMA16_CacheReadReq),
4910 .DMA17_CacheReadPtr(DMA17_CacheReadPtr[3:0]),
4911 .DMA17_CacheReadReq(DMA17_CacheReadReq),
4912 .DMA18_CacheReadPtr(DMA18_CacheReadPtr[3:0]),
4913 .DMA18_CacheReadReq(DMA18_CacheReadReq),
4914 .DMA19_CacheReadPtr(DMA19_CacheReadPtr[3:0]),
4915 .DMA19_CacheReadReq(DMA19_CacheReadReq),
4916 .DMA20_CacheReadPtr(DMA20_CacheReadPtr[3:0]),
4917 .DMA20_CacheReadReq(DMA20_CacheReadReq),
4918 .DMA21_CacheReadPtr(DMA21_CacheReadPtr[3:0]),
4919 .DMA21_CacheReadReq(DMA21_CacheReadReq),
4920 .DMA22_CacheReadPtr(DMA22_CacheReadPtr[3:0]),
4921 .DMA22_CacheReadReq(DMA22_CacheReadReq),
4922 .DMA23_CacheReadPtr(DMA23_CacheReadPtr[3:0]),
4923 .DMA23_CacheReadReq(DMA23_CacheReadReq),
4924`else // !ifdef NEPTUNE
4925
4926 .DMA16_CacheReadPtr(4'h0),
4927 .DMA16_CacheReadReq(1'b0),
4928 .DMA17_CacheReadPtr(4'h0),
4929 .DMA17_CacheReadReq(1'b0),
4930 .DMA18_CacheReadPtr(4'h0),
4931 .DMA18_CacheReadReq(1'b0),
4932 .DMA19_CacheReadPtr(4'h0),
4933 .DMA19_CacheReadReq(1'b0),
4934 .DMA20_CacheReadPtr(4'h0),
4935 .DMA20_CacheReadReq(1'b0),
4936 .DMA21_CacheReadPtr(4'h0),
4937 .DMA21_CacheReadReq(1'b0),
4938 .DMA22_CacheReadPtr(4'h0),
4939 .DMA22_CacheReadReq(1'b0),
4940 .DMA23_CacheReadPtr(4'h0),
4941 .DMA23_CacheReadReq(1'b0),
4942`endif // ifdef NEPTUNE
4943
4944
4945
4946 .SysClk(SysClk),
4947 .Reset_L(Reset_L));
4948
4949 niu_dmc_txcache niu_dmc_txcache( /*AUTOJUNK*/
4950`ifdef NEPTUNE
4951`else
4952 .tcu_aclk (tcu_aclk),
4953 .tcu_bclk (tcu_bclk),
4954 .tcu_se_scancollar_in (tcu_se_scancollar_in),
4955 .tcu_se_scancollar_out (tcu_se_scancollar_out),
4956 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
4957 .tds_tdmc_mbist_scan_in (tds_tdmc_mbist_scan_in),
4958 .tds_tdmc_mbist_scan_out (tds_tdmc_mbist_scan_out),
4959 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
4960 .tcu_tds_tdmc_mbist_start (tcu_tds_tdmc_mbist_start),
4961 .tds_tdmc_tcu_mbist_fail (tds_tdmc_tcu_mbist_fail),
4962 .tds_tdmc_tcu_mbist_done (tds_tdmc_tcu_mbist_done),
4963 .tcu_mbist_user_mode (tcu_mbist_user_mode),
4964 .tcu_scan_en (tcu_scan_en ),
4965 .l2clk_2x(l2clk_2x),
4966 .iol2clk(iol2clk),
4967 .hdr_sram_rvalue_tdmc (hdr_sram_rvalue_tdmc),
4968 .hdr_sram_rid_tdmc (hdr_sram_rid_tdmc),
4969 .hdr_sram_wr_en_tdmc (hdr_sram_wr_en_tdmc),
4970 .hdr_sram_red_clr_tdmc (hdr_sram_red_clr_tdmc),
4971 .sram_hdr_read_data_tdmc (sram_hdr_read_data_tdmc),
4972 .tds_tcu_dmo_data_out (tds_tcu_dmo_data_out),
4973 .sram_reset (sram_reset),
4974
4975`endif // ifdef NEPTUNE
4976
4977
4978 .WriteStrobe(DMA_TxCacheWrite),
4979 .WriteClock(SysClk),
4980 .Reset_L(Reset_L),
4981 .ReadStrobe(DMA_TxCacheRead),
4982 .ReadAddr(DMA_TxCacheReadPtr),
4983 .WriteAddr(DMA_TxCacheWritePtr),
4984 .DataIn({DMA_TxCacheWriteEntriesValid,DMA_TxCacheWriteData}),
4985 .DataOut({DMA_TxCacheTags,DMA_TxCacheReadData}),
4986 .ParityStatus(ParityStatus),
4987`ifdef NEPTUNE
4988 .parity_corrupt_dma_match({8'h0,parity_corrupt_dma_match}),
4989`else // !ifdef NEPTUNE
4990 .parity_corrupt_dma_match({16'h0,parity_corrupt_dma_match}),
4991`endif // ifdef NEPTUNE
4992
4993 .parity_corrupt_config(parity_corrupt_config)
4994
4995 );
4996
4997
4998
4999 // TXC Interfaces-
5000
5001
5002
5003// DMA0
5004 niu_dmc_txcif TxCacheIf0 (.incr_read_ptr(IncrDMA0RdPtr) ,
5005 .gotnxtdesc(dmc_txc_dma0_gotnxtdesc),
5006 .dma_cache_readdata(DMA_TxCacheReadData),
5007 .read_req(DMA0_CacheReadReq),
5008 .read_gnt(DMA0_CacheReadGnt),
5009 .getnxtdesc(txc_dmc_dma0_getnxtdesc),
5010 .dmc_txc_dma_descriptor(dmc_txc_dma0_descriptor),
5011 .dmc_txc_dma_partial ( dmc_txc_dma0_partial),
5012 .empty(DMA0_CacheEmpty),
5013 .cache_ready(dmc_txc_dma0_cacheready),
5014 .inc_head_shadow(inc_DMA0HeadShadow),
5015 .cache_entry_valid(DMA0CacheEntryValid),
5016 .cache_filled_size(DMA0_EntriesValid),
5017 .reset_cache_pointers(ResetDMA0RdPtr),
5018 .dma_cache_tags(DMA_TxCacheTags),
5019 .cache_parity_status (ParityStatus),
5020 .page0_mask_dma ( page0_mask_dma0 ),
5021 .page0_value_dma( page0_value_dma0 ),
5022 .page0_reloc_dma( page0_reloc_dma0 ),
5023 .page0_valid_dma( page0_valid_dma0 ),
5024 .page1_mask_dma ( page1_mask_dma0 ),
5025 .page1_value_dma( page1_value_dma0 ),
5026 .page1_reloc_dma( page1_reloc_dma0 ),
5027 .page1_valid_dma( page1_valid_dma0 ),
5028 .dma_reset_scheduled ( dma0_reset_scheduled ),
5029 .dma_reset_done_hold ( dma0_reset_done_hold ),
5030 .txc_dmc_dma_reset_done ( txc_dmc_dma0_reset_done ),
5031 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma0_stop),
5032 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma0_reset_scheduled ),
5033 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma0),
5034 .set_pkt_part_err_dma(set_pkt_part_err_dma0),
5035 .pkt_part_error_address_dma(pkt_part_error_address_dma0),
5036 .SysClk(SysClk),
5037 .Reset_L(Reset_L)
5038 ); // For DMA0
5039
5040// DMA1
5041 niu_dmc_txcif TxCacheIf1 (.incr_read_ptr(IncrDMA1RdPtr) ,
5042 .gotnxtdesc(dmc_txc_dma1_gotnxtdesc),
5043 .dma_cache_readdata(DMA_TxCacheReadData),
5044 .read_req(DMA1_CacheReadReq),
5045 .read_gnt(DMA1_CacheReadGnt),
5046 .getnxtdesc(txc_dmc_dma1_getnxtdesc),
5047 .dmc_txc_dma_descriptor(dmc_txc_dma1_descriptor),
5048 .dmc_txc_dma_partial ( dmc_txc_dma1_partial),
5049 .empty(DMA1_CacheEmpty),
5050 .cache_ready(dmc_txc_dma1_cacheready),
5051 .inc_head_shadow(inc_DMA1HeadShadow),
5052 .cache_entry_valid(DMA1CacheEntryValid),
5053 .cache_filled_size(DMA1_EntriesValid),
5054 .reset_cache_pointers(ResetDMA1RdPtr),
5055 .dma_cache_tags(DMA_TxCacheTags),
5056 .cache_parity_status (ParityStatus),
5057 .page0_mask_dma ( page0_mask_dma1 ),
5058 .page0_value_dma( page0_value_dma1 ),
5059 .page0_reloc_dma( page0_reloc_dma1 ),
5060 .page0_valid_dma( page0_valid_dma1 ),
5061 .page1_mask_dma ( page1_mask_dma1 ),
5062 .page1_value_dma( page1_value_dma1 ),
5063 .page1_reloc_dma( page1_reloc_dma1 ),
5064 .page1_valid_dma( page1_valid_dma1 ),
5065 .dma_reset_scheduled ( dma1_reset_scheduled ),
5066 .dma_reset_done_hold ( dma1_reset_done_hold ),
5067 .txc_dmc_dma_reset_done ( txc_dmc_dma1_reset_done ),
5068 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma1_stop),
5069 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma1_reset_scheduled ),
5070 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma1),
5071 .set_pkt_part_err_dma(set_pkt_part_err_dma1),
5072 .pkt_part_error_address_dma(pkt_part_error_address_dma1),
5073 .SysClk(SysClk),
5074 .Reset_L(Reset_L)
5075 ); // For DMA1
5076
5077// DMA2
5078 niu_dmc_txcif TxCacheIf2 (.incr_read_ptr(IncrDMA2RdPtr) ,
5079 .gotnxtdesc(dmc_txc_dma2_gotnxtdesc),
5080 .dma_cache_readdata(DMA_TxCacheReadData),
5081 .read_req(DMA2_CacheReadReq),
5082 .read_gnt(DMA2_CacheReadGnt),
5083 .getnxtdesc(txc_dmc_dma2_getnxtdesc),
5084 .dmc_txc_dma_descriptor(dmc_txc_dma2_descriptor),
5085 .dmc_txc_dma_partial ( dmc_txc_dma2_partial),
5086 .empty(DMA2_CacheEmpty),
5087 .cache_ready(dmc_txc_dma2_cacheready),
5088 .inc_head_shadow(inc_DMA2HeadShadow),
5089 .cache_entry_valid(DMA2CacheEntryValid),
5090 .cache_filled_size(DMA2_EntriesValid),
5091 .reset_cache_pointers(ResetDMA2RdPtr),
5092 .dma_cache_tags(DMA_TxCacheTags),
5093 .cache_parity_status (ParityStatus),
5094 .page0_mask_dma ( page0_mask_dma2 ),
5095 .page0_value_dma( page0_value_dma2 ),
5096 .page0_reloc_dma( page0_reloc_dma2 ),
5097 .page0_valid_dma( page0_valid_dma2 ),
5098 .page1_mask_dma ( page1_mask_dma2 ),
5099 .page1_value_dma( page1_value_dma2 ),
5100 .page1_reloc_dma( page1_reloc_dma2 ),
5101 .page1_valid_dma( page1_valid_dma2 ),
5102 .dma_reset_scheduled ( dma2_reset_scheduled ),
5103 .dma_reset_done_hold ( dma2_reset_done_hold ),
5104 .txc_dmc_dma_reset_done ( txc_dmc_dma2_reset_done ),
5105 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma2_stop),
5106 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma2_reset_scheduled ),
5107 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma2),
5108 .set_pkt_part_err_dma(set_pkt_part_err_dma2),
5109 .pkt_part_error_address_dma(pkt_part_error_address_dma2),
5110 .SysClk(SysClk),
5111 .Reset_L(Reset_L)
5112 ); // For DMA2
5113
5114// DMA3
5115 niu_dmc_txcif TxCacheIf3 (.incr_read_ptr(IncrDMA3RdPtr) ,
5116 .gotnxtdesc(dmc_txc_dma3_gotnxtdesc),
5117 .dma_cache_readdata(DMA_TxCacheReadData),
5118 .read_req(DMA3_CacheReadReq),
5119 .read_gnt(DMA3_CacheReadGnt),
5120 .getnxtdesc(txc_dmc_dma3_getnxtdesc),
5121 .dmc_txc_dma_descriptor(dmc_txc_dma3_descriptor),
5122 .dmc_txc_dma_partial ( dmc_txc_dma3_partial),
5123 .empty(DMA3_CacheEmpty),
5124 .cache_ready(dmc_txc_dma3_cacheready),
5125 .inc_head_shadow(inc_DMA3HeadShadow),
5126 .cache_entry_valid(DMA3CacheEntryValid),
5127 .cache_filled_size(DMA3_EntriesValid),
5128 .reset_cache_pointers(ResetDMA3RdPtr),
5129 .dma_cache_tags(DMA_TxCacheTags),
5130 .cache_parity_status (ParityStatus),
5131 .page0_mask_dma ( page0_mask_dma3 ),
5132 .page0_value_dma( page0_value_dma3 ),
5133 .page0_reloc_dma( page0_reloc_dma3 ),
5134 .page0_valid_dma( page0_valid_dma3 ),
5135 .page1_mask_dma ( page1_mask_dma3 ),
5136 .page1_value_dma( page1_value_dma3 ),
5137 .page1_reloc_dma( page1_reloc_dma3 ),
5138 .page1_valid_dma( page1_valid_dma3 ),
5139 .dma_reset_scheduled ( dma3_reset_scheduled ),
5140 .dma_reset_done_hold ( dma3_reset_done_hold ),
5141 .txc_dmc_dma_reset_done ( txc_dmc_dma3_reset_done ),
5142 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma3_stop),
5143 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma3_reset_scheduled ),
5144 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma3),
5145 .set_pkt_part_err_dma(set_pkt_part_err_dma3),
5146 .pkt_part_error_address_dma(pkt_part_error_address_dma3),
5147 .SysClk(SysClk),
5148 .Reset_L(Reset_L)
5149 ); // For DMA3
5150
5151// DMA4
5152 niu_dmc_txcif TxCacheIf4 (.incr_read_ptr(IncrDMA4RdPtr) ,
5153 .gotnxtdesc(dmc_txc_dma4_gotnxtdesc),
5154 .dma_cache_readdata(DMA_TxCacheReadData),
5155 .read_req(DMA4_CacheReadReq),
5156 .read_gnt(DMA4_CacheReadGnt),
5157 .getnxtdesc(txc_dmc_dma4_getnxtdesc),
5158 .dmc_txc_dma_descriptor(dmc_txc_dma4_descriptor),
5159 .dmc_txc_dma_partial ( dmc_txc_dma4_partial),
5160 .empty(DMA4_CacheEmpty),
5161 .cache_ready(dmc_txc_dma4_cacheready),
5162 .inc_head_shadow(inc_DMA4HeadShadow),
5163 .cache_entry_valid(DMA4CacheEntryValid),
5164 .cache_filled_size(DMA4_EntriesValid),
5165 .reset_cache_pointers(ResetDMA4RdPtr),
5166 .dma_cache_tags(DMA_TxCacheTags),
5167 .cache_parity_status (ParityStatus),
5168 .page0_mask_dma ( page0_mask_dma4 ),
5169 .page0_value_dma( page0_value_dma4 ),
5170 .page0_reloc_dma( page0_reloc_dma4 ),
5171 .page0_valid_dma( page0_valid_dma4 ),
5172 .page1_mask_dma ( page1_mask_dma4 ),
5173 .page1_value_dma( page1_value_dma4 ),
5174 .page1_reloc_dma( page1_reloc_dma4 ),
5175 .page1_valid_dma( page1_valid_dma4 ),
5176 .dma_reset_scheduled ( dma4_reset_scheduled ),
5177 .dma_reset_done_hold ( dma4_reset_done_hold ),
5178 .txc_dmc_dma_reset_done ( txc_dmc_dma4_reset_done ),
5179 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma4_stop),
5180 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma4_reset_scheduled ),
5181 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma4),
5182 .set_pkt_part_err_dma(set_pkt_part_err_dma4),
5183 .pkt_part_error_address_dma(pkt_part_error_address_dma4),
5184 .SysClk(SysClk),
5185 .Reset_L(Reset_L)
5186 ); // For DMA4
5187
5188// DMA5
5189 niu_dmc_txcif TxCacheIf5 (.incr_read_ptr(IncrDMA5RdPtr) ,
5190 .gotnxtdesc(dmc_txc_dma5_gotnxtdesc),
5191 .dma_cache_readdata(DMA_TxCacheReadData),
5192 .read_req(DMA5_CacheReadReq),
5193 .read_gnt(DMA5_CacheReadGnt),
5194 .getnxtdesc(txc_dmc_dma5_getnxtdesc),
5195 .dmc_txc_dma_descriptor(dmc_txc_dma5_descriptor),
5196 .dmc_txc_dma_partial ( dmc_txc_dma5_partial),
5197 .empty(DMA5_CacheEmpty),
5198 .cache_ready(dmc_txc_dma5_cacheready),
5199 .inc_head_shadow(inc_DMA5HeadShadow),
5200 .cache_entry_valid(DMA5CacheEntryValid),
5201 .cache_filled_size(DMA5_EntriesValid),
5202 .reset_cache_pointers(ResetDMA5RdPtr),
5203 .dma_cache_tags(DMA_TxCacheTags),
5204 .cache_parity_status (ParityStatus),
5205 .page0_mask_dma ( page0_mask_dma5 ),
5206 .page0_value_dma( page0_value_dma5 ),
5207 .page0_reloc_dma( page0_reloc_dma5 ),
5208 .page0_valid_dma( page0_valid_dma5 ),
5209 .page1_mask_dma ( page1_mask_dma5 ),
5210 .page1_value_dma( page1_value_dma5 ),
5211 .page1_reloc_dma( page1_reloc_dma5 ),
5212 .page1_valid_dma( page1_valid_dma5 ),
5213 .dma_reset_scheduled ( dma5_reset_scheduled ),
5214 .dma_reset_done_hold ( dma5_reset_done_hold ),
5215 .txc_dmc_dma_reset_done ( txc_dmc_dma5_reset_done ),
5216 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma5_stop),
5217 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma5_reset_scheduled ),
5218 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma5),
5219 .set_pkt_part_err_dma(set_pkt_part_err_dma5),
5220 .pkt_part_error_address_dma(pkt_part_error_address_dma5),
5221 .SysClk(SysClk),
5222 .Reset_L(Reset_L)
5223 ); // For DMA5
5224
5225// DMA6
5226 niu_dmc_txcif TxCacheIf6 (.incr_read_ptr(IncrDMA6RdPtr) ,
5227 .gotnxtdesc(dmc_txc_dma6_gotnxtdesc),
5228 .dma_cache_readdata(DMA_TxCacheReadData),
5229 .read_req(DMA6_CacheReadReq),
5230 .read_gnt(DMA6_CacheReadGnt),
5231 .getnxtdesc(txc_dmc_dma6_getnxtdesc),
5232 .dmc_txc_dma_descriptor(dmc_txc_dma6_descriptor),
5233 .dmc_txc_dma_partial ( dmc_txc_dma6_partial),
5234 .empty(DMA6_CacheEmpty),
5235 .cache_ready(dmc_txc_dma6_cacheready),
5236 .inc_head_shadow(inc_DMA6HeadShadow),
5237 .cache_entry_valid(DMA6CacheEntryValid),
5238 .cache_filled_size(DMA6_EntriesValid),
5239 .reset_cache_pointers(ResetDMA6RdPtr),
5240 .dma_cache_tags(DMA_TxCacheTags),
5241 .cache_parity_status (ParityStatus),
5242 .page0_mask_dma ( page0_mask_dma6 ),
5243 .page0_value_dma( page0_value_dma6 ),
5244 .page0_reloc_dma( page0_reloc_dma6 ),
5245 .page0_valid_dma( page0_valid_dma6 ),
5246 .page1_mask_dma ( page1_mask_dma6 ),
5247 .page1_value_dma( page1_value_dma6 ),
5248 .page1_reloc_dma( page1_reloc_dma6 ),
5249 .page1_valid_dma( page1_valid_dma6 ),
5250 .dma_reset_scheduled ( dma6_reset_scheduled ),
5251 .dma_reset_done_hold ( dma6_reset_done_hold ),
5252 .txc_dmc_dma_reset_done ( txc_dmc_dma6_reset_done ),
5253 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma6_stop),
5254 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma6_reset_scheduled ),
5255 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma6),
5256 .set_pkt_part_err_dma(set_pkt_part_err_dma6),
5257 .pkt_part_error_address_dma(pkt_part_error_address_dma6),
5258 .SysClk(SysClk),
5259 .Reset_L(Reset_L)
5260 ); // For DMA6
5261
5262// DMA7
5263 niu_dmc_txcif TxCacheIf7 (.incr_read_ptr(IncrDMA7RdPtr) ,
5264 .gotnxtdesc(dmc_txc_dma7_gotnxtdesc),
5265 .dma_cache_readdata(DMA_TxCacheReadData),
5266 .read_req(DMA7_CacheReadReq),
5267 .read_gnt(DMA7_CacheReadGnt),
5268 .getnxtdesc(txc_dmc_dma7_getnxtdesc),
5269 .dmc_txc_dma_descriptor(dmc_txc_dma7_descriptor),
5270 .dmc_txc_dma_partial ( dmc_txc_dma7_partial),
5271 .empty(DMA7_CacheEmpty),
5272 .cache_ready(dmc_txc_dma7_cacheready),
5273 .inc_head_shadow(inc_DMA7HeadShadow),
5274 .cache_entry_valid(DMA7CacheEntryValid),
5275 .cache_filled_size(DMA7_EntriesValid),
5276 .reset_cache_pointers(ResetDMA7RdPtr),
5277 .dma_cache_tags(DMA_TxCacheTags),
5278 .cache_parity_status (ParityStatus),
5279 .page0_mask_dma ( page0_mask_dma7 ),
5280 .page0_value_dma( page0_value_dma7 ),
5281 .page0_reloc_dma( page0_reloc_dma7 ),
5282 .page0_valid_dma( page0_valid_dma7 ),
5283 .page1_mask_dma ( page1_mask_dma7 ),
5284 .page1_value_dma( page1_value_dma7 ),
5285 .page1_reloc_dma( page1_reloc_dma7 ),
5286 .page1_valid_dma( page1_valid_dma7 ),
5287 .dma_reset_scheduled ( dma7_reset_scheduled ),
5288 .dma_reset_done_hold ( dma7_reset_done_hold ),
5289 .txc_dmc_dma_reset_done ( txc_dmc_dma7_reset_done ),
5290 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma7_stop),
5291 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma7_reset_scheduled ),
5292 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma7),
5293 .set_pkt_part_err_dma(set_pkt_part_err_dma7),
5294 .pkt_part_error_address_dma(pkt_part_error_address_dma7),
5295 .SysClk(SysClk),
5296 .Reset_L(Reset_L)
5297 ); // For DMA7
5298
5299// DMA8
5300 niu_dmc_txcif TxCacheIf8 (.incr_read_ptr(IncrDMA8RdPtr) ,
5301 .gotnxtdesc(dmc_txc_dma8_gotnxtdesc),
5302 .dma_cache_readdata(DMA_TxCacheReadData),
5303 .read_req(DMA8_CacheReadReq),
5304 .read_gnt(DMA8_CacheReadGnt),
5305 .getnxtdesc(txc_dmc_dma8_getnxtdesc),
5306 .dmc_txc_dma_descriptor(dmc_txc_dma8_descriptor),
5307 .dmc_txc_dma_partial ( dmc_txc_dma8_partial),
5308 .empty(DMA8_CacheEmpty),
5309 .cache_ready(dmc_txc_dma8_cacheready),
5310 .inc_head_shadow(inc_DMA8HeadShadow),
5311 .cache_entry_valid(DMA8CacheEntryValid),
5312 .cache_filled_size(DMA8_EntriesValid),
5313 .reset_cache_pointers(ResetDMA8RdPtr),
5314 .dma_cache_tags(DMA_TxCacheTags),
5315 .cache_parity_status (ParityStatus),
5316 .page0_mask_dma ( page0_mask_dma8 ),
5317 .page0_value_dma( page0_value_dma8 ),
5318 .page0_reloc_dma( page0_reloc_dma8 ),
5319 .page0_valid_dma( page0_valid_dma8 ),
5320 .page1_mask_dma ( page1_mask_dma8 ),
5321 .page1_value_dma( page1_value_dma8 ),
5322 .page1_reloc_dma( page1_reloc_dma8 ),
5323 .page1_valid_dma( page1_valid_dma8 ),
5324 .dma_reset_scheduled ( dma8_reset_scheduled ),
5325 .dma_reset_done_hold ( dma8_reset_done_hold ),
5326 .txc_dmc_dma_reset_done ( txc_dmc_dma8_reset_done ),
5327 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma8_stop),
5328 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma8_reset_scheduled ),
5329 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma8),
5330 .set_pkt_part_err_dma(set_pkt_part_err_dma8),
5331 .pkt_part_error_address_dma(pkt_part_error_address_dma8),
5332 .SysClk(SysClk),
5333 .Reset_L(Reset_L)
5334 ); // For DMA8
5335
5336// DMA9
5337 niu_dmc_txcif TxCacheIf9 (.incr_read_ptr(IncrDMA9RdPtr) ,
5338 .gotnxtdesc(dmc_txc_dma9_gotnxtdesc),
5339 .dma_cache_readdata(DMA_TxCacheReadData),
5340 .read_req(DMA9_CacheReadReq),
5341 .read_gnt(DMA9_CacheReadGnt),
5342 .getnxtdesc(txc_dmc_dma9_getnxtdesc),
5343 .dmc_txc_dma_descriptor(dmc_txc_dma9_descriptor),
5344 .dmc_txc_dma_partial ( dmc_txc_dma9_partial),
5345 .empty(DMA9_CacheEmpty),
5346 .cache_ready(dmc_txc_dma9_cacheready),
5347 .inc_head_shadow(inc_DMA9HeadShadow),
5348 .cache_entry_valid(DMA9CacheEntryValid),
5349 .cache_filled_size(DMA9_EntriesValid),
5350 .reset_cache_pointers(ResetDMA9RdPtr),
5351 .dma_cache_tags(DMA_TxCacheTags),
5352 .cache_parity_status (ParityStatus),
5353 .page0_mask_dma ( page0_mask_dma9 ),
5354 .page0_value_dma( page0_value_dma9 ),
5355 .page0_reloc_dma( page0_reloc_dma9 ),
5356 .page0_valid_dma( page0_valid_dma9 ),
5357 .page1_mask_dma ( page1_mask_dma9 ),
5358 .page1_value_dma( page1_value_dma9 ),
5359 .page1_reloc_dma( page1_reloc_dma9 ),
5360 .page1_valid_dma( page1_valid_dma9 ),
5361 .dma_reset_scheduled ( dma9_reset_scheduled ),
5362 .dma_reset_done_hold ( dma9_reset_done_hold ),
5363 .txc_dmc_dma_reset_done ( txc_dmc_dma9_reset_done ),
5364 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma9_stop),
5365 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma9_reset_scheduled ),
5366 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma9),
5367 .set_pkt_part_err_dma(set_pkt_part_err_dma9),
5368 .pkt_part_error_address_dma(pkt_part_error_address_dma9),
5369 .SysClk(SysClk),
5370 .Reset_L(Reset_L)
5371 ); // For DMA9
5372
5373// DMA10
5374 niu_dmc_txcif TxCacheIf10 (.incr_read_ptr(IncrDMA10RdPtr) ,
5375 .gotnxtdesc(dmc_txc_dma10_gotnxtdesc),
5376 .dma_cache_readdata(DMA_TxCacheReadData),
5377 .read_req(DMA10_CacheReadReq),
5378 .read_gnt(DMA10_CacheReadGnt),
5379 .getnxtdesc(txc_dmc_dma10_getnxtdesc),
5380 .dmc_txc_dma_descriptor(dmc_txc_dma10_descriptor),
5381 .dmc_txc_dma_partial ( dmc_txc_dma10_partial),
5382 .empty(DMA10_CacheEmpty),
5383 .cache_ready(dmc_txc_dma10_cacheready),
5384 .inc_head_shadow(inc_DMA10HeadShadow),
5385 .cache_entry_valid(DMA10CacheEntryValid),
5386 .cache_filled_size(DMA10_EntriesValid),
5387 .reset_cache_pointers(ResetDMA10RdPtr),
5388 .dma_cache_tags(DMA_TxCacheTags),
5389 .cache_parity_status (ParityStatus),
5390 .page0_mask_dma ( page0_mask_dma10 ),
5391 .page0_value_dma( page0_value_dma10 ),
5392 .page0_reloc_dma( page0_reloc_dma10 ),
5393 .page0_valid_dma( page0_valid_dma10 ),
5394 .page1_mask_dma ( page1_mask_dma10 ),
5395 .page1_value_dma( page1_value_dma10 ),
5396 .page1_reloc_dma( page1_reloc_dma10 ),
5397 .page1_valid_dma( page1_valid_dma10 ),
5398 .dma_reset_scheduled ( dma10_reset_scheduled ),
5399 .dma_reset_done_hold ( dma10_reset_done_hold ),
5400 .txc_dmc_dma_reset_done ( txc_dmc_dma10_reset_done ),
5401 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma10_stop),
5402 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma10_reset_scheduled ),
5403 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma10),
5404 .set_pkt_part_err_dma(set_pkt_part_err_dma10),
5405 .pkt_part_error_address_dma(pkt_part_error_address_dma10),
5406 .SysClk(SysClk),
5407 .Reset_L(Reset_L)
5408 ); // For DMA10
5409
5410// DMA11
5411 niu_dmc_txcif TxCacheIf11 (.incr_read_ptr(IncrDMA11RdPtr) ,
5412 .gotnxtdesc(dmc_txc_dma11_gotnxtdesc),
5413 .dma_cache_readdata(DMA_TxCacheReadData),
5414 .read_req(DMA11_CacheReadReq),
5415 .read_gnt(DMA11_CacheReadGnt),
5416 .getnxtdesc(txc_dmc_dma11_getnxtdesc),
5417 .dmc_txc_dma_descriptor(dmc_txc_dma11_descriptor),
5418 .dmc_txc_dma_partial ( dmc_txc_dma11_partial),
5419 .empty(DMA11_CacheEmpty),
5420 .cache_ready(dmc_txc_dma11_cacheready),
5421 .inc_head_shadow(inc_DMA11HeadShadow),
5422 .cache_entry_valid(DMA11CacheEntryValid),
5423 .cache_filled_size(DMA11_EntriesValid),
5424 .reset_cache_pointers(ResetDMA11RdPtr),
5425 .dma_cache_tags(DMA_TxCacheTags),
5426 .cache_parity_status (ParityStatus),
5427 .page0_mask_dma ( page0_mask_dma11 ),
5428 .page0_value_dma( page0_value_dma11 ),
5429 .page0_reloc_dma( page0_reloc_dma11 ),
5430 .page0_valid_dma( page0_valid_dma11 ),
5431 .page1_mask_dma ( page1_mask_dma11 ),
5432 .page1_value_dma( page1_value_dma11 ),
5433 .page1_reloc_dma( page1_reloc_dma11 ),
5434 .page1_valid_dma( page1_valid_dma11 ),
5435 .dma_reset_scheduled ( dma11_reset_scheduled ),
5436 .dma_reset_done_hold ( dma11_reset_done_hold ),
5437 .txc_dmc_dma_reset_done ( txc_dmc_dma11_reset_done ),
5438 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma11_stop),
5439 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma11_reset_scheduled ),
5440 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma11),
5441 .set_pkt_part_err_dma(set_pkt_part_err_dma11),
5442 .pkt_part_error_address_dma(pkt_part_error_address_dma11),
5443 .SysClk(SysClk),
5444 .Reset_L(Reset_L)
5445 ); // For DMA11
5446
5447// DMA12
5448 niu_dmc_txcif TxCacheIf12 (.incr_read_ptr(IncrDMA12RdPtr) ,
5449 .gotnxtdesc(dmc_txc_dma12_gotnxtdesc),
5450 .dma_cache_readdata(DMA_TxCacheReadData),
5451 .read_req(DMA12_CacheReadReq),
5452 .read_gnt(DMA12_CacheReadGnt),
5453 .getnxtdesc(txc_dmc_dma12_getnxtdesc),
5454 .dmc_txc_dma_descriptor(dmc_txc_dma12_descriptor),
5455 .dmc_txc_dma_partial ( dmc_txc_dma12_partial),
5456 .empty(DMA12_CacheEmpty),
5457 .cache_ready(dmc_txc_dma12_cacheready),
5458 .inc_head_shadow(inc_DMA12HeadShadow),
5459 .cache_entry_valid(DMA12CacheEntryValid),
5460 .cache_filled_size(DMA12_EntriesValid),
5461 .reset_cache_pointers(ResetDMA12RdPtr),
5462 .dma_cache_tags(DMA_TxCacheTags),
5463 .cache_parity_status (ParityStatus),
5464 .page0_mask_dma ( page0_mask_dma12 ),
5465 .page0_value_dma( page0_value_dma12 ),
5466 .page0_reloc_dma( page0_reloc_dma12 ),
5467 .page0_valid_dma( page0_valid_dma12 ),
5468 .page1_mask_dma ( page1_mask_dma12 ),
5469 .page1_value_dma( page1_value_dma12 ),
5470 .page1_reloc_dma( page1_reloc_dma12 ),
5471 .page1_valid_dma( page1_valid_dma12 ),
5472 .dma_reset_scheduled ( dma12_reset_scheduled ),
5473 .dma_reset_done_hold ( dma12_reset_done_hold ),
5474 .txc_dmc_dma_reset_done ( txc_dmc_dma12_reset_done ),
5475 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma12_stop),
5476 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma12_reset_scheduled ),
5477 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma12),
5478 .set_pkt_part_err_dma(set_pkt_part_err_dma12),
5479 .pkt_part_error_address_dma(pkt_part_error_address_dma12),
5480 .SysClk(SysClk),
5481 .Reset_L(Reset_L)
5482 ); // For DMA12
5483
5484// DMA13
5485 niu_dmc_txcif TxCacheIf13 (.incr_read_ptr(IncrDMA13RdPtr) ,
5486 .gotnxtdesc(dmc_txc_dma13_gotnxtdesc),
5487 .dma_cache_readdata(DMA_TxCacheReadData),
5488 .read_req(DMA13_CacheReadReq),
5489 .read_gnt(DMA13_CacheReadGnt),
5490 .getnxtdesc(txc_dmc_dma13_getnxtdesc),
5491 .dmc_txc_dma_descriptor(dmc_txc_dma13_descriptor),
5492 .dmc_txc_dma_partial ( dmc_txc_dma13_partial),
5493 .empty(DMA13_CacheEmpty),
5494 .cache_ready(dmc_txc_dma13_cacheready),
5495 .inc_head_shadow(inc_DMA13HeadShadow),
5496 .cache_entry_valid(DMA13CacheEntryValid),
5497 .cache_filled_size(DMA13_EntriesValid),
5498 .reset_cache_pointers(ResetDMA13RdPtr),
5499 .dma_cache_tags(DMA_TxCacheTags),
5500 .cache_parity_status (ParityStatus),
5501 .page0_mask_dma ( page0_mask_dma13 ),
5502 .page0_value_dma( page0_value_dma13 ),
5503 .page0_reloc_dma( page0_reloc_dma13 ),
5504 .page0_valid_dma( page0_valid_dma13 ),
5505 .page1_mask_dma ( page1_mask_dma13 ),
5506 .page1_value_dma( page1_value_dma13 ),
5507 .page1_reloc_dma( page1_reloc_dma13 ),
5508 .page1_valid_dma( page1_valid_dma13 ),
5509 .dma_reset_scheduled ( dma13_reset_scheduled ),
5510 .dma_reset_done_hold ( dma13_reset_done_hold ),
5511 .txc_dmc_dma_reset_done ( txc_dmc_dma13_reset_done ),
5512 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma13_stop),
5513 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma13_reset_scheduled ),
5514 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma13),
5515 .set_pkt_part_err_dma(set_pkt_part_err_dma13),
5516 .pkt_part_error_address_dma(pkt_part_error_address_dma13),
5517 .SysClk(SysClk),
5518 .Reset_L(Reset_L)
5519 ); // For DMA13
5520
5521// DMA14
5522 niu_dmc_txcif TxCacheIf14 (.incr_read_ptr(IncrDMA14RdPtr) ,
5523 .gotnxtdesc(dmc_txc_dma14_gotnxtdesc),
5524 .dma_cache_readdata(DMA_TxCacheReadData),
5525 .read_req(DMA14_CacheReadReq),
5526 .read_gnt(DMA14_CacheReadGnt),
5527 .getnxtdesc(txc_dmc_dma14_getnxtdesc),
5528 .dmc_txc_dma_descriptor(dmc_txc_dma14_descriptor),
5529 .dmc_txc_dma_partial ( dmc_txc_dma14_partial),
5530 .empty(DMA14_CacheEmpty),
5531 .cache_ready(dmc_txc_dma14_cacheready),
5532 .inc_head_shadow(inc_DMA14HeadShadow),
5533 .cache_entry_valid(DMA14CacheEntryValid),
5534 .cache_filled_size(DMA14_EntriesValid),
5535 .reset_cache_pointers(ResetDMA14RdPtr),
5536 .dma_cache_tags(DMA_TxCacheTags),
5537 .cache_parity_status (ParityStatus),
5538 .page0_mask_dma ( page0_mask_dma14 ),
5539 .page0_value_dma( page0_value_dma14 ),
5540 .page0_reloc_dma( page0_reloc_dma14 ),
5541 .page0_valid_dma( page0_valid_dma14 ),
5542 .page1_mask_dma ( page1_mask_dma14 ),
5543 .page1_value_dma( page1_value_dma14 ),
5544 .page1_reloc_dma( page1_reloc_dma14 ),
5545 .page1_valid_dma( page1_valid_dma14 ),
5546 .dma_reset_scheduled ( dma14_reset_scheduled ),
5547 .dma_reset_done_hold ( dma14_reset_done_hold ),
5548 .txc_dmc_dma_reset_done ( txc_dmc_dma14_reset_done ),
5549 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma14_stop),
5550 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma14_reset_scheduled ),
5551 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma14),
5552 .set_pkt_part_err_dma(set_pkt_part_err_dma14),
5553 .pkt_part_error_address_dma(pkt_part_error_address_dma14),
5554 .SysClk(SysClk),
5555 .Reset_L(Reset_L)
5556 ); // For DMA14
5557
5558// DMA15
5559 niu_dmc_txcif TxCacheIf15 (.incr_read_ptr(IncrDMA15RdPtr) ,
5560 .gotnxtdesc(dmc_txc_dma15_gotnxtdesc),
5561 .dma_cache_readdata(DMA_TxCacheReadData),
5562 .read_req(DMA15_CacheReadReq),
5563 .read_gnt(DMA15_CacheReadGnt),
5564 .getnxtdesc(txc_dmc_dma15_getnxtdesc),
5565 .dmc_txc_dma_descriptor(dmc_txc_dma15_descriptor),
5566 .dmc_txc_dma_partial ( dmc_txc_dma15_partial),
5567 .empty(DMA15_CacheEmpty),
5568 .cache_ready(dmc_txc_dma15_cacheready),
5569 .inc_head_shadow(inc_DMA15HeadShadow),
5570 .cache_entry_valid(DMA15CacheEntryValid),
5571 .cache_filled_size(DMA15_EntriesValid),
5572 .reset_cache_pointers(ResetDMA15RdPtr),
5573 .dma_cache_tags(DMA_TxCacheTags),
5574 .cache_parity_status (ParityStatus),
5575 .page0_mask_dma ( page0_mask_dma15 ),
5576 .page0_value_dma( page0_value_dma15 ),
5577 .page0_reloc_dma( page0_reloc_dma15 ),
5578 .page0_valid_dma( page0_valid_dma15 ),
5579 .page1_mask_dma ( page1_mask_dma15 ),
5580 .page1_value_dma( page1_value_dma15 ),
5581 .page1_reloc_dma( page1_reloc_dma15 ),
5582 .page1_valid_dma( page1_valid_dma15 ),
5583 .dma_reset_scheduled ( dma15_reset_scheduled ),
5584 .dma_reset_done_hold ( dma15_reset_done_hold ),
5585 .txc_dmc_dma_reset_done ( txc_dmc_dma15_reset_done ),
5586 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma15_stop),
5587 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma15_reset_scheduled ),
5588 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma15),
5589 .set_pkt_part_err_dma(set_pkt_part_err_dma15),
5590 .pkt_part_error_address_dma(pkt_part_error_address_dma15),
5591 .SysClk(SysClk),
5592 .Reset_L(Reset_L)
5593 ); // For DMA15
5594
5595`ifdef NEPTUNE
5596
5597// DMA16
5598 niu_dmc_txcif TxCacheIf16 (.incr_read_ptr(IncrDMA16RdPtr) ,
5599 .gotnxtdesc(dmc_txc_dma16_gotnxtdesc),
5600 .dma_cache_readdata(DMA_TxCacheReadData),
5601 .read_req(DMA16_CacheReadReq),
5602 .read_gnt(DMA16_CacheReadGnt),
5603 .getnxtdesc(txc_dmc_dma16_getnxtdesc),
5604 .dmc_txc_dma_descriptor(dmc_txc_dma16_descriptor),
5605 .dmc_txc_dma_partial ( dmc_txc_dma16_partial),
5606 .empty(DMA16_CacheEmpty),
5607 .cache_ready(dmc_txc_dma16_cacheready),
5608 .inc_head_shadow(inc_DMA16HeadShadow),
5609 .cache_entry_valid(DMA16CacheEntryValid),
5610 .cache_filled_size(DMA16_EntriesValid),
5611 .reset_cache_pointers(ResetDMA16RdPtr),
5612 .dma_cache_tags(DMA_TxCacheTags),
5613 .cache_parity_status (ParityStatus),
5614 .page0_mask_dma ( page0_mask_dma16 ),
5615 .page0_value_dma( page0_value_dma16 ),
5616 .page0_reloc_dma( page0_reloc_dma16 ),
5617 .page0_valid_dma( page0_valid_dma16 ),
5618 .page1_mask_dma ( page1_mask_dma16 ),
5619 .page1_value_dma( page1_value_dma16 ),
5620 .page1_reloc_dma( page1_reloc_dma16 ),
5621 .page1_valid_dma( page1_valid_dma16 ),
5622 .dma_reset_scheduled ( dma16_reset_scheduled ),
5623 .dma_reset_done_hold ( dma16_reset_done_hold ),
5624 .txc_dmc_dma_reset_done ( txc_dmc_dma16_reset_done ),
5625 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma16_stop),
5626 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma16_reset_scheduled ),
5627 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma16),
5628 .set_pkt_part_err_dma(set_pkt_part_err_dma16),
5629 .pkt_part_error_address_dma(pkt_part_error_address_dma16),
5630 .SysClk(SysClk),
5631 .Reset_L(Reset_L)
5632 ); // For DMA16
5633
5634// DMA17
5635 niu_dmc_txcif TxCacheIf17 (.incr_read_ptr(IncrDMA17RdPtr) ,
5636 .gotnxtdesc(dmc_txc_dma17_gotnxtdesc),
5637 .dma_cache_readdata(DMA_TxCacheReadData),
5638 .read_req(DMA17_CacheReadReq),
5639 .read_gnt(DMA17_CacheReadGnt),
5640 .getnxtdesc(txc_dmc_dma17_getnxtdesc),
5641 .dmc_txc_dma_descriptor(dmc_txc_dma17_descriptor),
5642 .dmc_txc_dma_partial ( dmc_txc_dma17_partial),
5643 .empty(DMA17_CacheEmpty),
5644 .cache_ready(dmc_txc_dma17_cacheready),
5645 .inc_head_shadow(inc_DMA17HeadShadow),
5646 .cache_entry_valid(DMA17CacheEntryValid),
5647 .cache_filled_size(DMA17_EntriesValid),
5648 .reset_cache_pointers(ResetDMA17RdPtr),
5649 .dma_cache_tags(DMA_TxCacheTags),
5650 .cache_parity_status (ParityStatus),
5651 .page0_mask_dma ( page0_mask_dma17 ),
5652 .page0_value_dma( page0_value_dma17 ),
5653 .page0_reloc_dma( page0_reloc_dma17 ),
5654 .page0_valid_dma( page0_valid_dma17 ),
5655 .page1_mask_dma ( page1_mask_dma17 ),
5656 .page1_value_dma( page1_value_dma17 ),
5657 .page1_reloc_dma( page1_reloc_dma17 ),
5658 .page1_valid_dma( page1_valid_dma17 ),
5659 .dma_reset_scheduled ( dma17_reset_scheduled ),
5660 .dma_reset_done_hold ( dma17_reset_done_hold ),
5661 .txc_dmc_dma_reset_done ( txc_dmc_dma17_reset_done ),
5662 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma17_stop),
5663 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma17_reset_scheduled ),
5664 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma17),
5665 .set_pkt_part_err_dma(set_pkt_part_err_dma17),
5666 .pkt_part_error_address_dma(pkt_part_error_address_dma17),
5667 .SysClk(SysClk),
5668 .Reset_L(Reset_L)
5669 ); // For DMA17
5670
5671// DMA18
5672 niu_dmc_txcif TxCacheIf18 (.incr_read_ptr(IncrDMA18RdPtr) ,
5673 .gotnxtdesc(dmc_txc_dma18_gotnxtdesc),
5674 .dma_cache_readdata(DMA_TxCacheReadData),
5675 .read_req(DMA18_CacheReadReq),
5676 .read_gnt(DMA18_CacheReadGnt),
5677 .getnxtdesc(txc_dmc_dma18_getnxtdesc),
5678 .dmc_txc_dma_descriptor(dmc_txc_dma18_descriptor),
5679 .dmc_txc_dma_partial ( dmc_txc_dma18_partial),
5680 .empty(DMA18_CacheEmpty),
5681 .cache_ready(dmc_txc_dma18_cacheready),
5682 .inc_head_shadow(inc_DMA18HeadShadow),
5683 .cache_entry_valid(DMA18CacheEntryValid),
5684 .cache_filled_size(DMA18_EntriesValid),
5685 .reset_cache_pointers(ResetDMA18RdPtr),
5686 .dma_cache_tags(DMA_TxCacheTags),
5687 .cache_parity_status (ParityStatus),
5688 .page0_mask_dma ( page0_mask_dma18 ),
5689 .page0_value_dma( page0_value_dma18 ),
5690 .page0_reloc_dma( page0_reloc_dma18 ),
5691 .page0_valid_dma( page0_valid_dma18 ),
5692 .page1_mask_dma ( page1_mask_dma18 ),
5693 .page1_value_dma( page1_value_dma18 ),
5694 .page1_reloc_dma( page1_reloc_dma18 ),
5695 .page1_valid_dma( page1_valid_dma18 ),
5696 .dma_reset_scheduled ( dma18_reset_scheduled ),
5697 .dma_reset_done_hold ( dma18_reset_done_hold ),
5698 .txc_dmc_dma_reset_done ( txc_dmc_dma18_reset_done ),
5699 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma18_stop),
5700 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma18_reset_scheduled ),
5701 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma18),
5702 .set_pkt_part_err_dma(set_pkt_part_err_dma18),
5703 .pkt_part_error_address_dma(pkt_part_error_address_dma18),
5704 .SysClk(SysClk),
5705 .Reset_L(Reset_L)
5706 ); // For DMA18
5707
5708// DMA19
5709 niu_dmc_txcif TxCacheIf19 (.incr_read_ptr(IncrDMA19RdPtr) ,
5710 .gotnxtdesc(dmc_txc_dma19_gotnxtdesc),
5711 .dma_cache_readdata(DMA_TxCacheReadData),
5712 .read_req(DMA19_CacheReadReq),
5713 .read_gnt(DMA19_CacheReadGnt),
5714 .getnxtdesc(txc_dmc_dma19_getnxtdesc),
5715 .dmc_txc_dma_descriptor(dmc_txc_dma19_descriptor),
5716 .dmc_txc_dma_partial ( dmc_txc_dma19_partial),
5717 .empty(DMA19_CacheEmpty),
5718 .cache_ready(dmc_txc_dma19_cacheready),
5719 .inc_head_shadow(inc_DMA19HeadShadow),
5720 .cache_entry_valid(DMA19CacheEntryValid),
5721 .cache_filled_size(DMA19_EntriesValid),
5722 .reset_cache_pointers(ResetDMA19RdPtr),
5723 .dma_cache_tags(DMA_TxCacheTags),
5724 .cache_parity_status (ParityStatus),
5725 .page0_mask_dma ( page0_mask_dma19 ),
5726 .page0_value_dma( page0_value_dma19 ),
5727 .page0_reloc_dma( page0_reloc_dma19 ),
5728 .page0_valid_dma( page0_valid_dma19 ),
5729 .page1_mask_dma ( page1_mask_dma19 ),
5730 .page1_value_dma( page1_value_dma19 ),
5731 .page1_reloc_dma( page1_reloc_dma19 ),
5732 .page1_valid_dma( page1_valid_dma19 ),
5733 .dma_reset_scheduled ( dma19_reset_scheduled ),
5734 .dma_reset_done_hold ( dma19_reset_done_hold ),
5735 .txc_dmc_dma_reset_done ( txc_dmc_dma19_reset_done ),
5736 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma19_stop),
5737 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma19_reset_scheduled ),
5738 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma19),
5739 .set_pkt_part_err_dma(set_pkt_part_err_dma19),
5740 .pkt_part_error_address_dma(pkt_part_error_address_dma19),
5741 .SysClk(SysClk),
5742 .Reset_L(Reset_L)
5743 ); // For DMA19
5744
5745// DMA20
5746 niu_dmc_txcif TxCacheIf20 (.incr_read_ptr(IncrDMA20RdPtr) ,
5747 .gotnxtdesc(dmc_txc_dma20_gotnxtdesc),
5748 .dma_cache_readdata(DMA_TxCacheReadData),
5749 .read_req(DMA20_CacheReadReq),
5750 .read_gnt(DMA20_CacheReadGnt),
5751 .getnxtdesc(txc_dmc_dma20_getnxtdesc),
5752 .dmc_txc_dma_descriptor(dmc_txc_dma20_descriptor),
5753 .dmc_txc_dma_partial ( dmc_txc_dma20_partial),
5754 .empty(DMA20_CacheEmpty),
5755 .cache_ready(dmc_txc_dma20_cacheready),
5756 .inc_head_shadow(inc_DMA20HeadShadow),
5757 .cache_entry_valid(DMA20CacheEntryValid),
5758 .cache_filled_size(DMA20_EntriesValid),
5759 .reset_cache_pointers(ResetDMA20RdPtr),
5760 .dma_cache_tags(DMA_TxCacheTags),
5761 .cache_parity_status (ParityStatus),
5762 .page0_mask_dma ( page0_mask_dma20 ),
5763 .page0_value_dma( page0_value_dma20 ),
5764 .page0_reloc_dma( page0_reloc_dma20 ),
5765 .page0_valid_dma( page0_valid_dma20 ),
5766 .page1_mask_dma ( page1_mask_dma20 ),
5767 .page1_value_dma( page1_value_dma20 ),
5768 .page1_reloc_dma( page1_reloc_dma20 ),
5769 .page1_valid_dma( page1_valid_dma20 ),
5770 .dma_reset_scheduled ( dma20_reset_scheduled ),
5771 .dma_reset_done_hold ( dma20_reset_done_hold ),
5772 .txc_dmc_dma_reset_done ( txc_dmc_dma20_reset_done ),
5773 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma20_stop),
5774 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma20_reset_scheduled ),
5775 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma20),
5776 .set_pkt_part_err_dma(set_pkt_part_err_dma20),
5777 .pkt_part_error_address_dma(pkt_part_error_address_dma20),
5778 .SysClk(SysClk),
5779 .Reset_L(Reset_L)
5780 ); // For DMA20
5781
5782// DMA21
5783 niu_dmc_txcif TxCacheIf21 (.incr_read_ptr(IncrDMA21RdPtr) ,
5784 .gotnxtdesc(dmc_txc_dma21_gotnxtdesc),
5785 .dma_cache_readdata(DMA_TxCacheReadData),
5786 .read_req(DMA21_CacheReadReq),
5787 .read_gnt(DMA21_CacheReadGnt),
5788 .getnxtdesc(txc_dmc_dma21_getnxtdesc),
5789 .dmc_txc_dma_descriptor(dmc_txc_dma21_descriptor),
5790 .dmc_txc_dma_partial ( dmc_txc_dma21_partial),
5791 .empty(DMA21_CacheEmpty),
5792 .cache_ready(dmc_txc_dma21_cacheready),
5793 .inc_head_shadow(inc_DMA21HeadShadow),
5794 .cache_entry_valid(DMA21CacheEntryValid),
5795 .cache_filled_size(DMA21_EntriesValid),
5796 .reset_cache_pointers(ResetDMA21RdPtr),
5797 .dma_cache_tags(DMA_TxCacheTags),
5798 .cache_parity_status (ParityStatus),
5799 .page0_mask_dma ( page0_mask_dma21 ),
5800 .page0_value_dma( page0_value_dma21 ),
5801 .page0_reloc_dma( page0_reloc_dma21 ),
5802 .page0_valid_dma( page0_valid_dma21 ),
5803 .page1_mask_dma ( page1_mask_dma21 ),
5804 .page1_value_dma( page1_value_dma21 ),
5805 .page1_reloc_dma( page1_reloc_dma21 ),
5806 .page1_valid_dma( page1_valid_dma21 ),
5807 .dma_reset_scheduled ( dma21_reset_scheduled ),
5808 .dma_reset_done_hold ( dma21_reset_done_hold ),
5809 .txc_dmc_dma_reset_done ( txc_dmc_dma21_reset_done ),
5810 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma21_stop),
5811 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma21_reset_scheduled ),
5812 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma21),
5813 .set_pkt_part_err_dma(set_pkt_part_err_dma21),
5814 .pkt_part_error_address_dma(pkt_part_error_address_dma21),
5815 .SysClk(SysClk),
5816 .Reset_L(Reset_L)
5817 ); // For DMA21
5818
5819// DMA22
5820 niu_dmc_txcif TxCacheIf22 (.incr_read_ptr(IncrDMA22RdPtr) ,
5821 .gotnxtdesc(dmc_txc_dma22_gotnxtdesc),
5822 .dma_cache_readdata(DMA_TxCacheReadData),
5823 .read_req(DMA22_CacheReadReq),
5824 .read_gnt(DMA22_CacheReadGnt),
5825 .getnxtdesc(txc_dmc_dma22_getnxtdesc),
5826 .dmc_txc_dma_descriptor(dmc_txc_dma22_descriptor),
5827 .dmc_txc_dma_partial ( dmc_txc_dma22_partial),
5828 .empty(DMA22_CacheEmpty),
5829 .cache_ready(dmc_txc_dma22_cacheready),
5830 .inc_head_shadow(inc_DMA22HeadShadow),
5831 .cache_entry_valid(DMA22CacheEntryValid),
5832 .cache_filled_size(DMA22_EntriesValid),
5833 .reset_cache_pointers(ResetDMA22RdPtr),
5834 .dma_cache_tags(DMA_TxCacheTags),
5835 .cache_parity_status (ParityStatus),
5836 .page0_mask_dma ( page0_mask_dma22 ),
5837 .page0_value_dma( page0_value_dma22 ),
5838 .page0_reloc_dma( page0_reloc_dma22 ),
5839 .page0_valid_dma( page0_valid_dma22 ),
5840 .page1_mask_dma ( page1_mask_dma22 ),
5841 .page1_value_dma( page1_value_dma22 ),
5842 .page1_reloc_dma( page1_reloc_dma22 ),
5843 .page1_valid_dma( page1_valid_dma22 ),
5844 .dma_reset_scheduled ( dma22_reset_scheduled ),
5845 .dma_reset_done_hold ( dma22_reset_done_hold ),
5846 .txc_dmc_dma_reset_done ( txc_dmc_dma22_reset_done ),
5847 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma22_stop),
5848 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma22_reset_scheduled ),
5849 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma22),
5850 .set_pkt_part_err_dma(set_pkt_part_err_dma22),
5851 .pkt_part_error_address_dma(pkt_part_error_address_dma22),
5852 .SysClk(SysClk),
5853 .Reset_L(Reset_L)
5854 ); // For DMA22
5855
5856// DMA23
5857 niu_dmc_txcif TxCacheIf23 (.incr_read_ptr(IncrDMA23RdPtr) ,
5858 .gotnxtdesc(dmc_txc_dma23_gotnxtdesc),
5859 .dma_cache_readdata(DMA_TxCacheReadData),
5860 .read_req(DMA23_CacheReadReq),
5861 .read_gnt(DMA23_CacheReadGnt),
5862 .getnxtdesc(txc_dmc_dma23_getnxtdesc),
5863 .dmc_txc_dma_descriptor(dmc_txc_dma23_descriptor),
5864 .dmc_txc_dma_partial ( dmc_txc_dma23_partial),
5865 .empty(DMA23_CacheEmpty),
5866 .cache_ready(dmc_txc_dma23_cacheready),
5867 .inc_head_shadow(inc_DMA23HeadShadow),
5868 .cache_entry_valid(DMA23CacheEntryValid),
5869 .cache_filled_size(DMA23_EntriesValid),
5870 .reset_cache_pointers(ResetDMA23RdPtr),
5871 .dma_cache_tags(DMA_TxCacheTags),
5872 .cache_parity_status (ParityStatus),
5873 .page0_mask_dma ( page0_mask_dma23 ),
5874 .page0_value_dma( page0_value_dma23 ),
5875 .page0_reloc_dma( page0_reloc_dma23 ),
5876 .page0_valid_dma( page0_valid_dma23 ),
5877 .page1_mask_dma ( page1_mask_dma23 ),
5878 .page1_value_dma( page1_value_dma23 ),
5879 .page1_reloc_dma( page1_reloc_dma23 ),
5880 .page1_valid_dma( page1_valid_dma23 ),
5881 .dma_reset_scheduled ( dma23_reset_scheduled ),
5882 .dma_reset_done_hold ( dma23_reset_done_hold ),
5883 .txc_dmc_dma_reset_done ( txc_dmc_dma23_reset_done ),
5884 .tx_dma_cfg_dma_stop(tx_dma_cfg_dma23_stop),
5885 .dmc_txc_dma_reset_scheduled ( dmc_txc_dma23_reset_scheduled ),
5886 .set_pref_buf_par_err_dma(set_pref_buf_par_err_dma23),
5887 .set_pkt_part_err_dma(set_pkt_part_err_dma23),
5888 .pkt_part_error_address_dma(pkt_part_error_address_dma23),
5889 .SysClk(SysClk),
5890 .Reset_L(Reset_L)
5891 ); // For DMA23
5892`endif // ifdef NEPTUNE
5893
5894endmodule
5895
Full OpenSPARC design & verification tarball including full HDL.