[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_dmc_dmaarb.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_dmc_dmaarb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/*********************************************************************
 *
 **********************************************************************/


`include "txc_defines.h"
`include "niu_dmc_reg_defines.h"

module niu_dmc_dmaarb (/*AUTOARG*/
   // Outputs
   ArbDone, DMANum, DMAsGranted, 
   // Inputs
   SysClk, Reset_L, Choose_DMAs, DMA_Reqs
   );


   input SysClk;
   input Reset_L;
   input Choose_DMAs;
   input [31:0] DMA_Reqs;
   
   output ArbDone;
   output [4:0] DMANum;
   output [31:0] DMAsGranted;
   

   reg [31:0] 	  DMAsGranted;
   reg [31:0] 	  Select_DMA_Grant;
   reg [3:0] 	  DMA_Request_ArbState;
   reg 		  ArbDone;
   reg [4:0] 	  DMANum;
   

   parameter DMA_REQ_ARB_IDLE   = 4'h0,
	     SELECT_DMA_NUM = 4'h1,
	     DMA_REQ_ARB_DONE = 4'h2; 

  //VCS coverage off
  // synopsys translate_off
   reg [192:1] 	  CACHE_REQ_ARB_STATE;

     always @(DMA_Request_ArbState)
     begin
	case(DMA_Request_ArbState)
	  DMA_REQ_ARB_IDLE :            CACHE_REQ_ARB_STATE = "DMA_REQ_ARB_IDLE";
	  SELECT_DMA_NUM:    CACHE_REQ_ARB_STATE = "SELECT_DMA_NUM";
	  DMA_REQ_ARB_DONE :   CACHE_REQ_ARB_STATE = "DMA_REQ_ARB_DONE";
	  default :            CACHE_REQ_ARB_STATE = "UNKNOWN";
	endcase
     end
   // synopsys translate_on
   //VCS coverage on
   

  always@(posedge SysClk ) begin
     if(!Reset_L)begin
	DMA_Request_ArbState <= DMA_REQ_ARB_IDLE;
	DMAsGranted <= 32'h0;
	Select_DMA_Grant <= 32'h0;
	ArbDone <= 1'b1;
	DMANum<= 5'h0;
     end else 
       begin
	 case(DMA_Request_ArbState) // synopsys parallel_case
	   DMA_REQ_ARB_IDLE: begin
	      ArbDone <=1'b0;
	      if(Choose_DMAs) begin
		 Select_DMA_Grant <= DMA_Reqs & ~DMAsGranted;
		 DMA_Request_ArbState <= SELECT_DMA_NUM;
	      end else begin // if (choose_available_dmas)
		 DMAsGranted <= 32'h0;
		 Select_DMA_Grant <= 32'h0;
	      end // else: !if(choose_available_dmas)
	   end // case: DMA_REQ_ARB_IDLE
	   SELECT_DMA_NUM: begin
	      ArbDone <=1'b1;
	      casex(Select_DMA_Grant) // Synopsys full_case 
		32'b0000_0000_0000_0000_0000_0000_0000_0001: begin
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0001;
		   DMANum<= `DMA_CHANNEL_ZERO;
		end // case: 32'b0000_0000_0000_0000_0000_0000_0000_0001
		32'b????_????_????_????_????_????_????_??1?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0010;
		   DMANum<= `DMA_CHANNEL_ONE;
		end
		32'b????_????_????_????_????_????_????_?10?: begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0100;
		   DMANum<= `DMA_CHANNEL_TWO; 
		  end
		32'b????_????_????_????_????_????_????_100?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_1000; 
		   DMANum<= `DMA_CHANNEL_THREE;
		end
		32'b????_????_????_????_????_????_???1_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0001_0000; 
		   DMANum<= `DMA_CHANNEL_FOUR;
		end
		32'b????_????_????_????_????_????_??10_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0010_0000; 
		   DMANum<= `DMA_CHANNEL_FIVE;
		end
		32'b????_????_????_????_????_????_?100_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0100_0000; 
		   DMANum<= `DMA_CHANNEL_SIX;

		end
		32'b????_????_????_????_????_????_1000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_1000_0000; 
		   DMANum<= `DMA_CHANNEL_SEVEN;
		end
		32'b????_????_????_????_????_???1_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0001_0000_0000; 
		   DMANum<= `DMA_CHANNEL_EIGHT;
		end
		32'b????_????_????_????_????_??10_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0010_0000_0000; 
		   DMANum<= `DMA_CHANNEL_NINE;
		end
		32'b????_????_????_????_????_?100_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_0100_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TEN;
		end
		32'b????_????_????_????_????_1000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0000_1000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_ELEVEN;
		end
		32'b????_????_????_????_???1_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0001_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TWELVE;
		end
		32'b????_????_????_????_??10_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0010_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_THIRTEEN;
		end
		32'b????_????_????_????_?100_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_0100_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_FOURTEEN;
		end
		32'b????_????_????_????_1000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0000_1000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_FIFTEEN;
		end
		32'b????_????_????_???1_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0001_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_SIXTEEN;
		end
		32'b????_????_????_??10_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0010_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_SEVENTEEN;  
		end
		32'b????_????_????_?100_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_0100_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_EIGHTEEN;
		end
		32'b????_????_????_1000_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0000_1000_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_NINETEEN;
		end
		32'b????_????_???1_0000_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0001_0000_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TWENTY;
		end
		32'b????_????_??10_0000_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0010_0000_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TWENTYONE;
		end
		32'b????_????_?100_0000_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_0100_0000_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TWENTYTWO;
		end
		32'b????_????_1000_0000_0000_0000_0000_000?:  begin 
		   DMAsGranted <= 32'b0000_0000_1000_0000_0000_0000_0000_0000; 
		   DMANum<= `DMA_CHANNEL_TWENTYTHREE;
		end
		default:   begin
		   DMAsGranted <= 32'b0;
		   DMANum<=`DMA_CHANNEL_ZERO;
		end
		     
	      endcase // case(DMA_Request_ArbState)
	      DMA_Request_ArbState <= DMA_REQ_ARB_DONE; 
	   end // case: SELECT_DMA_NUM
	   DMA_REQ_ARB_DONE: begin
	      DMA_Request_ArbState <= DMA_REQ_ARB_IDLE; 
	      ArbDone <=1'b0;
	   end // case: DMA_REQ_ARB_DONE
	 endcase // case(DMA_Request_ArbState)
       end // else: !if(!Reset_L)
  end // always@ (posedge SysClk )
endmodule // niu_dmc_dmaarb
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_dmc_dmaarb.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/*********************************************************************
	36	*
	37	**********************************************************************/
	38
	39
	40	`include "txc_defines.h"
	41	`include "niu_dmc_reg_defines.h"
	42
	43	module niu_dmc_dmaarb (/AUTOARG/
	44	// Outputs
	45	ArbDone, DMANum, DMAsGranted,
	46	// Inputs
	47	SysClk, Reset_L, Choose_DMAs, DMA_Reqs
	48	);
	49
	50
	51	input SysClk;
	52	input Reset_L;
	53	input Choose_DMAs;
	54	input [31:0] DMA_Reqs;
	55
	56	output ArbDone;
	57	output [4:0] DMANum;
	58	output [31:0] DMAsGranted;
	59
	60
	61
	62	reg [31:0] DMAsGranted;
	63	reg [31:0] Select_DMA_Grant;
	64	reg [3:0] DMA_Request_ArbState;
65	reg ArbDone;
66	reg [4:0] DMANum;
67
68
69
70	parameter DMA_REQ_ARB_IDLE = 4'h0,
71	SELECT_DMA_NUM = 4'h1,
72	DMA_REQ_ARB_DONE = 4'h2;
73
74	//VCS coverage off
75	// synopsys translate_off
76	reg [192:1] CACHE_REQ_ARB_STATE;
77
78	always @(DMA_Request_ArbState)
79	begin
80	case(DMA_Request_ArbState)
81	DMA_REQ_ARB_IDLE : CACHE_REQ_ARB_STATE = "DMA_REQ_ARB_IDLE";
82	SELECT_DMA_NUM: CACHE_REQ_ARB_STATE = "SELECT_DMA_NUM";
83	DMA_REQ_ARB_DONE : CACHE_REQ_ARB_STATE = "DMA_REQ_ARB_DONE";
84	default : CACHE_REQ_ARB_STATE = "UNKNOWN";
85	endcase
86	end
87	// synopsys translate_on
88	//VCS coverage on
89
90
91	always@(posedge SysClk ) begin
92	if(!Reset_L)begin
93	DMA_Request_ArbState <= DMA_REQ_ARB_IDLE;
94	DMAsGranted <= 32'h0;
95	Select_DMA_Grant <= 32'h0;
96	ArbDone <= 1'b1;
97	DMANum<= 5'h0;
98	end else
99	begin
100	case(DMA_Request_ArbState) // synopsys parallel_case
101	DMA_REQ_ARB_IDLE: begin
102	ArbDone <=1'b0;
103	if(Choose_DMAs) begin
104	Select_DMA_Grant <= DMA_Reqs & ~DMAsGranted;
105	DMA_Request_ArbState <= SELECT_DMA_NUM;
106	end else begin // if (choose_available_dmas)
107	DMAsGranted <= 32'h0;
108	Select_DMA_Grant <= 32'h0;
109	end // else: !if(choose_available_dmas)
110	end // case: DMA_REQ_ARB_IDLE
111	SELECT_DMA_NUM: begin
112	ArbDone <=1'b1;
113	casex(Select_DMA_Grant) // Synopsys full_case
114	32'b0000_0000_0000_0000_0000_0000_0000_0001: begin
115	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0001;
116	DMANum<= `DMA_CHANNEL_ZERO;
117	end // case: 32'b0000_0000_0000_0000_0000_0000_0000_0001
118	32'b????_????_????_????_????_????_????_??1?: begin
119	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0010;
120	DMANum<= `DMA_CHANNEL_ONE;
121	end
122	32'b????_????_????_????_????_????_????_?10?: begin
123	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_0100;
124	DMANum<= `DMA_CHANNEL_TWO;
125	end
126	32'b????_????_????_????_????_????_????_100?: begin
127	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0000_1000;
128	DMANum<= `DMA_CHANNEL_THREE;
129	end
130	32'b????_????_????_????_????_????_???1_000?: begin
131	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0001_0000;
132	DMANum<= `DMA_CHANNEL_FOUR;
133	end
134	32'b????_????_????_????_????_????_??10_000?: begin
135	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0010_0000;
136	DMANum<= `DMA_CHANNEL_FIVE;
137	end
138	32'b????_????_????_????_????_????_?100_000?: begin
139	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_0100_0000;
140	DMANum<= `DMA_CHANNEL_SIX;
141
142	end
143	32'b????_????_????_????_????_????_1000_000?: begin
144	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0000_1000_0000;
145	DMANum<= `DMA_CHANNEL_SEVEN;
146	end
147	32'b????_????_????_????_????_???1_0000_000?: begin
148	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0001_0000_0000;
149	DMANum<= `DMA_CHANNEL_EIGHT;
150	end
151	32'b????_????_????_????_????_??10_0000_000?: begin
152	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0010_0000_0000;
153	DMANum<= `DMA_CHANNEL_NINE;
154	end
155	32'b????_????_????_????_????_?100_0000_000?: begin
156	DMAsGranted <= 32'b0000_0000_0000_0000_0000_0100_0000_0000;
157	DMANum<= `DMA_CHANNEL_TEN;
158	end
159	32'b????_????_????_????_????_1000_0000_000?: begin
160	DMAsGranted <= 32'b0000_0000_0000_0000_0000_1000_0000_0000;
161	DMANum<= `DMA_CHANNEL_ELEVEN;
162	end
163	32'b????_????_????_????_???1_0000_0000_000?: begin
164	DMAsGranted <= 32'b0000_0000_0000_0000_0001_0000_0000_0000;
165	DMANum<= `DMA_CHANNEL_TWELVE;
166	end
167	32'b????_????_????_????_??10_0000_0000_000?: begin
168	DMAsGranted <= 32'b0000_0000_0000_0000_0010_0000_0000_0000;
169	DMANum<= `DMA_CHANNEL_THIRTEEN;
170	end
171	32'b????_????_????_????_?100_0000_0000_000?: begin
172	DMAsGranted <= 32'b0000_0000_0000_0000_0100_0000_0000_0000;
173	DMANum<= `DMA_CHANNEL_FOURTEEN;
174	end
175	32'b????_????_????_????_1000_0000_0000_000?: begin
176	DMAsGranted <= 32'b0000_0000_0000_0000_1000_0000_0000_0000;
177	DMANum<= `DMA_CHANNEL_FIFTEEN;
178	end
179	32'b????_????_????_???1_0000_0000_0000_000?: begin
180	DMAsGranted <= 32'b0000_0000_0000_0001_0000_0000_0000_0000;
181	DMANum<= `DMA_CHANNEL_SIXTEEN;
182	end
183	32'b????_????_????_??10_0000_0000_0000_000?: begin
184	DMAsGranted <= 32'b0000_0000_0000_0010_0000_0000_0000_0000;
185	DMANum<= `DMA_CHANNEL_SEVENTEEN;
186	end
187	32'b????_????_????_?100_0000_0000_0000_000?: begin
188	DMAsGranted <= 32'b0000_0000_0000_0100_0000_0000_0000_0000;
189	DMANum<= `DMA_CHANNEL_EIGHTEEN;
190	end
191	32'b????_????_????_1000_0000_0000_0000_000?: begin
192	DMAsGranted <= 32'b0000_0000_0000_1000_0000_0000_0000_0000;
193	DMANum<= `DMA_CHANNEL_NINETEEN;
194	end
195	32'b????_????_???1_0000_0000_0000_0000_000?: begin
196	DMAsGranted <= 32'b0000_0000_0001_0000_0000_0000_0000_0000;
197	DMANum<= `DMA_CHANNEL_TWENTY;
198	end
199	32'b????_????_??10_0000_0000_0000_0000_000?: begin
200	DMAsGranted <= 32'b0000_0000_0010_0000_0000_0000_0000_0000;
201	DMANum<= `DMA_CHANNEL_TWENTYONE;
202	end
203	32'b????_????_?100_0000_0000_0000_0000_000?: begin
204	DMAsGranted <= 32'b0000_0000_0100_0000_0000_0000_0000_0000;
205	DMANum<= `DMA_CHANNEL_TWENTYTWO;
206	end
207	32'b????_????_1000_0000_0000_0000_0000_000?: begin
208	DMAsGranted <= 32'b0000_0000_1000_0000_0000_0000_0000_0000;
209	DMANum<= `DMA_CHANNEL_TWENTYTHREE;
210	end
211	default: begin
212	DMAsGranted <= 32'b0;
213	DMANum<=`DMA_CHANNEL_ZERO;
214	end
215
216	endcase // case(DMA_Request_ArbState)
217	DMA_Request_ArbState <= DMA_REQ_ARB_DONE;
218	end // case: SELECT_DMA_NUM
219	DMA_REQ_ARB_DONE: begin
220	DMA_Request_ArbState <= DMA_REQ_ARB_IDLE;
221	ArbDone <=1'b0;
222	end // case: DMA_REQ_ARB_DONE
223	endcase // case(DMA_Request_ArbState)
224	end // else: !if(!Reset_L)
225	end // always@ (posedge SysClk )
226	endmodule // niu_dmc_dmaarb
227