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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_dmc_reg_defines.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niu_dmc_reg_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38
39`ifdef NEPTUNE
40`define NO_OF_DMAS 24
41`else
42`define NO_OF_DMAS 16
43`endif
44// `define PTR_WIDTH 19
45// `define PTR_WIDTH_PLUS1 20
46// `define RNG_LENGTH_WIDTH 16
47
48`define PTR_WIDTH 16
49`define PTR_WIDTH_PLUS1 17
50`define RNG_LENGTH_WIDTH 13
51
52// OFFSET for the cache ram
53 `define DMA0_Cache_OFFSET 8'h00
54 `define DMA1_Cache_OFFSET 8'h08
55 `define DMA2_Cache_OFFSET 8'h10
56 `define DMA3_Cache_OFFSET 8'h18
57 `define DMA4_Cache_OFFSET 8'h20
58 `define DMA5_Cache_OFFSET 8'h28
59 `define DMA6_Cache_OFFSET 8'h30
60 `define DMA7_Cache_OFFSET 8'h38
61 `define DMA8_Cache_OFFSET 8'h40
62 `define DMA9_Cache_OFFSET 8'h48
63 `define DMA10_Cache_OFFSET 8'h50
64 `define DMA11_Cache_OFFSET 8'h58
65 `define DMA12_Cache_OFFSET 8'h60
66 `define DMA13_Cache_OFFSET 8'h68
67 `define DMA14_Cache_OFFSET 8'h70
68 `define DMA15_Cache_OFFSET 8'h78
69 `define DMA16_Cache_OFFSET 8'h80
70 `define DMA17_Cache_OFFSET 8'h88
71 `define DMA18_Cache_OFFSET 8'h90
72 `define DMA19_Cache_OFFSET 8'h98
73 `define DMA20_Cache_OFFSET 8'hA0
74 `define DMA21_Cache_OFFSET 8'hA8
75 `define DMA22_Cache_OFFSET 8'hB0
76 `define DMA23_Cache_OFFSET 8'hB8
77 `define DMA24_Cache_OFFSET 8'hC0
78 `define DMA25_Cache_OFFSET 8'hC8
79 `define DMA26_Cache_OFFSET 8'hD0
80 `define DMA27_Cache_OFFSET 8'hD8
81 `define DMA28_Cache_OFFSET 8'hE0
82 `define DMA29_Cache_OFFSET 8'hE8
83 `define DMA30_Cache_OFFSET 8'hF0
84 `define DMA31_Cache_OFFSET 8'hF8
85
86
87// ERROR CODE Definations for ERROR LOG
88
89`define ERR_CODE_PKT_SIZE_ERR 3'b110
90`define ERR_CODE_PREF_BUF_PAR_ERR 3'b100
91`define ERR_CODE_TX_RING_OFLOW 3'b101
92`define ERR_CODE_NACK_PREF 3'b011
93`define ERR_CODE_NACK_PKT_RD 3'b010
94`define ERR_CODE_CONF_PART_ERR 3'b001
95`define ERR_CODE_PKT_PART_ERR 3'b000
96
97
98`define RESP_ERROR 8'hff
99
100`define DMC_DMA0_SPACE 11'h200
101`define DMC_DMA1_SPACE 11'h201
102`define DMC_DMA2_SPACE 11'h202
103`define DMC_DMA3_SPACE 11'h203
104`define DMC_DMA4_SPACE 11'h204
105`define DMC_DMA5_SPACE 11'h205
106`define DMC_DMA6_SPACE 11'h206
107`define DMC_DMA7_SPACE 11'h207
108`define DMC_DMA8_SPACE 11'h208
109`define DMC_DMA9_SPACE 11'h209
110`define DMC_DMA10_SPACE 11'h20A
111`define DMC_DMA11_SPACE 11'h20B
112`define DMC_DMA12_SPACE 11'h20C
113`define DMC_DMA13_SPACE 11'h20D
114`define DMC_DMA14_SPACE 11'h20E
115`define DMC_DMA15_SPACE 11'h20F
116`define DMC_DMA16_SPACE 11'h210
117`define DMC_DMA17_SPACE 11'h211
118`define DMC_DMA18_SPACE 11'h212
119`define DMC_DMA19_SPACE 11'h213
120`define DMC_DMA20_SPACE 11'h214
121`define DMC_DMA21_SPACE 11'h215
122`define DMC_DMA22_SPACE 11'h216
123`define DMC_DMA23_SPACE 11'h217
124`define DMC_DMA24_SPACE 11'h218
125`define DMC_DMA25_SPACE 11'h219
126`define DMC_DMA26_SPACE 11'h21A
127`define DMC_DMA27_SPACE 11'h21B
128`define DMC_DMA28_SPACE 11'h21C
129`define DMC_DMA29_SPACE 11'h21D
130`define DMC_DMA30_SPACE 11'h21E
131`define DMC_DMA31_SPACE 11'h21F
132
133`define TDMC_RSVD 11'h220
134
135
136`define DMC_DMA_RSV_SPACE 9'h070
137
138`define TX_ADDR_MD 20'h45000
139`define TX_CACHE_PAR_CORRUPT 20'h45040
140`define TDMC_DEBUG_SELECT 20'h45080
141`define TDMC_TRAINING_VECTOR 20'h45088
142
143`define TDMC_MEM_ADDR 20'h45090
144`define TDMC_MEM_DATA0 20'h45098
145`define TDMC_MEM_DATA1 20'h450A0
146`define TDMC_MEM_DATA2 20'h450A8
147`define TDMC_MEM_DATA3 20'h450B0
148`define TDMC_MEM_DATA4 20'h450B8
149
150// DMA_0 Defines
151
152`define TXDMA_RNG_CFIG_DMA0 9'h000
153`define TXDMA_RNG_CFIG_DMA0_H 9'h004
154
155`define TXDMA_RNG_HDH_DMA0 9'h008
156`define TXDMA_RNG_HDL_DMA0 9'h010
157`define TXDMA_RING_KICK_DMA0 9'h018
158`define TXDMA_ENT_MASK_DMA0 9'h020
159
160`define TXDMA_CS_DMA0 9'h028
161`define TXDMA_CS_DMA0_H 9'h02C
162
163`define TXDMA_MBH_DMA0 9'h030
164`define TXDMA_MBL_DMA0 9'h038
165`define TXDMA_ST_DMA0 9'h040
166`define TXDMA_RNG_ERR_LOGH_DMA0 9'h048
167`define TXDMA_RNG_ERR_LOGL_DMA0 9'h050
168`define TXDMA_INTR_DBG_DMA0 9'h060
169`define TXDMA_CS_DBG_DMA0 9'h068
170`define SHTXDMA_RNG_ERR_LOGL_DMA0 9'h068
171`define TXDMA_DUMMY0_DMA0 9'h070
172`define TXDMA_DUMMY1_DMA0 9'h078
173`define TXDMA_DUMMY2_DMA0 9'h080
174`define TXDMA_DUMMY3_DMA0 9'h088
175`define TXDMA_DUMMY4_DMA0 9'h090
176`define TXDMA_DUMMY5_DMA0 9'h098
177`define TXDMA_DUMMY6_DMA0 9'h0A0
178`define TXDMA_DUMMY7_DMA0 9'h0A8
179`define TXDMA_DUMMY8_DMA0 9'h0B0
180`define TXDMA_DUMMY9_DMA0 9'h0B8
181
182
183// FZC DEFINES
184`define TXDMA_LOG_PAGE_VLD_DMA0 9'h000
185`define TXDMA_LOG_PAGE_MASK0_DMA0 9'h008
186`define TXDMA_LOG_PAGE_VALUE0_DMA0 9'h010
187`define TXDMA_LOG_PAGE_MASK1_DMA0 9'h018
188`define TXDMA_LOG_PAGE_VALUE1_DMA0 9'h020
189`define TXDMA_LOG_PAGE_RELOC0_DMA0 9'h028
190`define TXDMA_LOG_PAGE_RELOC1_DMA0 9'h030
191`define TXDMA_LOG_PAGE_HANDLE_DMA0 9'h038
192
193// DMA_1 Defines
194
195`define TXDMA_RNG_CFIG_DMA1 9'h000
196`define TXDMA_RNG_CFIG_DMA1_H 9'h004
197
198`define TXDMA_RNG_HDH_DMA1 9'h008
199`define TXDMA_RNG_HDL_DMA1 9'h010
200`define TXDMA_RING_KICK_DMA1 9'h018
201`define TXDMA_ENT_MASK_DMA1 9'h020
202
203`define TXDMA_CS_DMA1 9'h028
204`define TXDMA_CS_DMA1_H 9'h02c
205
206`define TXDMA_MBH_DMA1 9'h030
207`define TXDMA_MBL_DMA1 9'h038
208`define TXDMA_ST_DMA1 9'h040
209`define TXDMA_RNG_ERR_LOGH_DMA1 9'h048
210`define TXDMA_RNG_ERR_LOGL_DMA1 9'h050
211`define TXDMA_INTR_DBG_DMA1 9'h060
212`define TXDMA_CS_DBG_DMA1 9'h068
213`define SHTXDMA_RNG_ERR_LOGL_DMA1 9'h068
214`define TXDMA_DUMMY0_DMA1 9'h070
215`define TXDMA_DUMMY1_DMA1 9'h078
216`define TXDMA_DUMMY2_DMA1 9'h080
217`define TXDMA_DUMMY3_DMA1 9'h088
218`define TXDMA_DUMMY4_DMA1 9'h090
219`define TXDMA_DUMMY5_DMA1 9'h098
220`define TXDMA_DUMMY6_DMA1 9'h0A0
221`define TXDMA_DUMMY7_DMA1 9'h0A8
222`define TXDMA_DUMMY8_DMA1 9'h0B0
223`define TXDMA_DUMMY9_DMA1 9'h0B8
224
225
226// FZC DEFINES
227`define TXDMA_LOG_PAGE_VLD_DMA1 9'h000
228`define TXDMA_LOG_PAGE_MASK0_DMA1 9'h008
229`define TXDMA_LOG_PAGE_VALUE0_DMA1 9'h010
230`define TXDMA_LOG_PAGE_MASK1_DMA1 9'h018
231`define TXDMA_LOG_PAGE_VALUE1_DMA1 9'h020
232`define TXDMA_LOG_PAGE_RELOC0_DMA1 9'h028
233`define TXDMA_LOG_PAGE_RELOC1_DMA1 9'h030
234`define TXDMA_LOG_PAGE_HANDLE_DMA1 9'h038
235
236// DMA_2 Defines
237
238`define TXDMA_RNG_CFIG_DMA2 9'h000
239`define TXDMA_RNG_CFIG_DMA2_H 9'h004
240
241`define TXDMA_RNG_HDH_DMA2 9'h008
242`define TXDMA_RNG_HDL_DMA2 9'h010
243`define TXDMA_RING_KICK_DMA2 9'h018
244`define TXDMA_ENT_MASK_DMA2 9'h020
245
246`define TXDMA_CS_DMA2 9'h028
247`define TXDMA_CS_DMA2_H 9'h02c
248
249`define TXDMA_MBH_DMA2 9'h030
250`define TXDMA_MBL_DMA2 9'h038
251`define TXDMA_ST_DMA2 9'h040
252`define TXDMA_RNG_ERR_LOGH_DMA2 9'h048
253`define TXDMA_RNG_ERR_LOGL_DMA2 9'h050
254`define TXDMA_INTR_DBG_DMA2 9'h060
255`define TXDMA_CS_DBG_DMA2 9'h068
256`define SHTXDMA_RNG_ERR_LOGL_DMA2 9'h068
257`define TXDMA_DUMMY0_DMA2 9'h070
258`define TXDMA_DUMMY1_DMA2 9'h078
259`define TXDMA_DUMMY2_DMA2 9'h080
260`define TXDMA_DUMMY3_DMA2 9'h088
261`define TXDMA_DUMMY4_DMA2 9'h090
262`define TXDMA_DUMMY5_DMA2 9'h098
263`define TXDMA_DUMMY6_DMA2 9'h0A0
264`define TXDMA_DUMMY7_DMA2 9'h0A8
265`define TXDMA_DUMMY8_DMA2 9'h0B0
266`define TXDMA_DUMMY9_DMA2 9'h0B8
267
268
269// FZC DEFINES
270`define TXDMA_LOG_PAGE_VLD_DMA2 9'h000
271`define TXDMA_LOG_PAGE_MASK0_DMA2 9'h008
272`define TXDMA_LOG_PAGE_VALUE0_DMA2 9'h010
273`define TXDMA_LOG_PAGE_MASK1_DMA2 9'h018
274`define TXDMA_LOG_PAGE_VALUE1_DMA2 9'h020
275`define TXDMA_LOG_PAGE_RELOC0_DMA2 9'h028
276`define TXDMA_LOG_PAGE_RELOC1_DMA2 9'h030
277`define TXDMA_LOG_PAGE_HANDLE_DMA2 9'h038
278
279// DMA_3 Defines
280
281`define TXDMA_RNG_CFIG_DMA3 9'h000
282`define TXDMA_RNG_CFIG_DMA3_H 9'h004
283
284`define TXDMA_RNG_HDH_DMA3 9'h008
285`define TXDMA_RNG_HDL_DMA3 9'h010
286`define TXDMA_RING_KICK_DMA3 9'h018
287`define TXDMA_ENT_MASK_DMA3 9'h020
288
289`define TXDMA_CS_DMA3 9'h028
290`define TXDMA_CS_DMA3_H 9'h02c
291
292`define TXDMA_MBH_DMA3 9'h030
293`define TXDMA_MBL_DMA3 9'h038
294`define TXDMA_ST_DMA3 9'h040
295`define TXDMA_RNG_ERR_LOGH_DMA3 9'h048
296`define TXDMA_RNG_ERR_LOGL_DMA3 9'h050
297`define TXDMA_INTR_DBG_DMA3 9'h060
298`define TXDMA_CS_DBG_DMA3 9'h068
299`define SHTXDMA_RNG_ERR_LOGL_DMA3 9'h068
300`define TXDMA_DUMMY0_DMA3 9'h070
301`define TXDMA_DUMMY1_DMA3 9'h078
302`define TXDMA_DUMMY2_DMA3 9'h080
303`define TXDMA_DUMMY3_DMA3 9'h088
304`define TXDMA_DUMMY4_DMA3 9'h090
305`define TXDMA_DUMMY5_DMA3 9'h098
306`define TXDMA_DUMMY6_DMA3 9'h0A0
307`define TXDMA_DUMMY7_DMA3 9'h0A8
308`define TXDMA_DUMMY8_DMA3 9'h0B0
309`define TXDMA_DUMMY9_DMA3 9'h0B8
310
311
312// FZC DEFINES
313`define TXDMA_LOG_PAGE_VLD_DMA3 9'h000
314`define TXDMA_LOG_PAGE_MASK0_DMA3 9'h008
315`define TXDMA_LOG_PAGE_VALUE0_DMA3 9'h010
316`define TXDMA_LOG_PAGE_MASK1_DMA3 9'h018
317`define TXDMA_LOG_PAGE_VALUE1_DMA3 9'h020
318`define TXDMA_LOG_PAGE_RELOC0_DMA3 9'h028
319`define TXDMA_LOG_PAGE_RELOC1_DMA3 9'h030
320`define TXDMA_LOG_PAGE_HANDLE_DMA3 9'h038
321
322// Debug port selects
323`define TDMC_CACHE_FETCH_STATE 6'h1
324`define TDMC_MBOX_STATE 6'h2
325
326`define TDMC_DMA0_DEBUG_SEL 6'd3
327`define TDMC_DMA1_DEBUG_SEL 6'd4
328`define TDMC_DMA2_DEBUG_SEL 6'd5
329`define TDMC_DMA3_DEBUG_SEL 6'd6
330`define TDMC_DMA4_DEBUG_SEL 6'd7
331`define TDMC_DMA5_DEBUG_SEL 6'd8
332`define TDMC_DMA6_DEBUG_SEL 6'd9
333`define TDMC_DMA7_DEBUG_SEL 6'd10
334`define TDMC_DMA8_DEBUG_SEL 6'd11
335`define TDMC_DMA9_DEBUG_SEL 6'd12
336`define TDMC_DMA10_DEBUG_SEL 6'd13
337`define TDMC_DMA11_DEBUG_SEL 6'd14
338`define TDMC_DMA12_DEBUG_SEL 6'd15
339`define TDMC_DMA13_DEBUG_SEL 6'd16
340`define TDMC_DMA14_DEBUG_SEL 6'd17
341`define TDMC_DMA15_DEBUG_SEL 6'd18
342`define TDMC_DMA16_DEBUG_SEL 6'd19
343`define TDMC_DMA17_DEBUG_SEL 6'd20
344`define TDMC_DMA18_DEBUG_SEL 6'd21
345`define TDMC_DMA19_DEBUG_SEL 6'd22
346`define TDMC_DMA20_DEBUG_SEL 6'd23
347`define TDMC_DMA21_DEBUG_SEL 6'd24
348`define TDMC_DMA22_DEBUG_SEL 6'd25
349`define TDMC_DMA23_DEBUG_SEL 6'd26
350
351`define TDMC_TRAINING_SET 6'h3E
352`define TDMC_TRAINING_LOAD 6'h3F
353//
354
355
356
357
358
359
Full OpenSPARC design & verification tarball including full HDL.