Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_ipp_dmc_checker.v
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3// OpenSPARC T2 Processor File: niu_ipp_dmc_checker.v
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35/**********************************************************
36***********************************************************
37
38 Project : Niu
39
40 File name : niu_ipp_dmc_checker.v
41
42 Module(s) name : niu_ipp_dmc_checker
43
44 Parent modules : ipp.v
45
46 Child modules : sum_unit.v
47
48 Author's name : George chu
49
50 Date : March. 2004
51
52 Description : This file contains check sum unit
53
54 Synthesis Notes:
55
56 Modification History:
57
58 Date Description
59 ---- -----------
60
61************************************************************
62***********************************************************/
63
64module niu_ipp_dmc_checker (
65 ipp_dmc_data,
66 ipp_dmc_dat_ack,
67 ipp_dmc_ful_pkt,
68 reset,
69 clk,
70 dmc_ipp_dat_req,
71 dmc_sum_prt_fail,
72 dmc_sum_prt_cksum,
73 dmc_sum_prt_state,
74 dmc_sum_prt_valid);
75
76input [129:0] ipp_dmc_data; //
77input ipp_dmc_dat_ack; //
78input ipp_dmc_ful_pkt; //
79
80input reset;
81input clk; // clock
82
83output dmc_ipp_dat_req; //
84output dmc_sum_prt_fail;
85output [15:0] dmc_sum_prt_cksum;
86output [31:0] dmc_sum_prt_state;
87output dmc_sum_prt_valid;
88
89reg dmc_ipp_dat_req;
90wire dmc_sum_prt_fail;
91wire [15:0] dmc_sum_prt_cksum;
92wire [31:0] dmc_sum_prt_state;
93wire dmc_sum_prt_valid;
94
95//*********************************************************
96
97// from dmc_driver
98wire [16:0] ipp_max_bytes = /* geo */ 17'hffff;
99
100reg [127:0] dmc_stwd_status_wd_r;
101wire [127:0] dmc_stwd_status_wd;
102wire [39:0] dmc_stwd_mac_status_wd = dmc_stwd_status_wd[127:88];
103wire [2:0] dmc_stwd_reserve_3 = dmc_stwd_status_wd[087:85];
104wire [12:0] dmc_stwd_sop_addr = dmc_stwd_status_wd[084:72];
105wire [13:0] dmc_stwd_reserve_2 = dmc_stwd_status_wd[071:58];
106wire dmc_stwd_hfifo_par_err = dmc_stwd_status_wd[057];
107wire dmc_stwd_hfifo_under_run = dmc_stwd_status_wd[056];
108wire dmc_stwd_hfifo_over_run = dmc_stwd_status_wd[055];
109wire dmc_stwd_status_rd_abort = dmc_stwd_status_wd[054];
110wire dmc_stwd_mac_drp_crc = dmc_stwd_status_wd[053];
111wire dmc_stwd_ipp_disc_pkt = dmc_stwd_status_wd[052];
112wire [1:0] dmc_stwd_reserve_1 = dmc_stwd_status_wd[051:50];
113wire [13:0] dmc_stwd_pkt_ffl_sum_info = dmc_stwd_status_wd[049:36];
114wire [35:0] dmc_stwd_cksum_info = dmc_stwd_status_wd[035:0];
115
116wire [3:0] dmc_stwd_flp_pkt_id = dmc_stwd_pkt_ffl_sum_info[13:10];
117wire [1:0] dmc_stwd_la4_prot = dmc_stwd_pkt_ffl_sum_info[09:08];
118wire [3:0] dmc_stwd_ip4_hdr_leng = dmc_stwd_pkt_ffl_sum_info[07:04];
119wire [1:0] dmc_stwd_la3_vers = dmc_stwd_pkt_ffl_sum_info[03:02];
120wire [1:0] dmc_stwd_la2_opti = dmc_stwd_pkt_ffl_sum_info[01:00];
121
122wire [15:0] dmc_stwd_ip_length = dmc_stwd_cksum_info[35:20];
123wire dmc_stwd_reserve_0 = dmc_stwd_cksum_info[19];
124wire dmc_stwd_full_cksum_ena = dmc_stwd_cksum_info[18];
125wire dmc_stwd_full_cksum_fail = dmc_stwd_cksum_info[17];
126wire dmc_stwd_full_cksum = dmc_stwd_cksum_info[16];
127wire [15:0] dmc_stwd_cksum = dmc_stwd_cksum_info[15:0];
128
129wire [15:0] dmc_sum_prt_length;
130
131wire dmc_sum_prt_started_0;
132wire dmc_sum_prt_valid_0;
133wire dmc_sum_prt_fail_0;
134wire [15:0] dmc_sum_prt_cksum_0;
135wire [15:0] dmc_sum_prt_length_0;
136wire [31:0] dmc_sum_prt_state_0;
137
138wire dmc_sum_prt_started_1;
139wire dmc_sum_prt_valid_1;
140wire dmc_sum_prt_fail_1;
141wire [15:0] dmc_sum_prt_cksum_1;
142wire [15:0] dmc_sum_prt_length_1;
143wire [31:0] dmc_sum_prt_state_1;
144
145reg [15:0] dmc_pkt_cnt;
146reg dmc_checksum_unit;
147
148reg dmc_ipp_dat_req_d;
149
150reg [1:0] c_dmc_ipp_st, n_dmc_ipp_st;
151
152 parameter DMC_IPP_IDLE = 2'b00,
153 DMC_IPP_GET_DATA = 2'b01,
154 DMC_IPP_1ST_DATA = 2'b10;
155
156wire ipp_dfifo_dout_eop = ipp_dmc_data[129];
157wire ipp_dfifo_dout_sop = ipp_dmc_data[128];
158reg ipp_dfifo_dout_eop_d;
159
160wire ack_rd_dfifo_sop = ipp_dmc_ful_pkt &&
161 ipp_dmc_dat_ack &&
162 (c_dmc_ipp_st==DMC_IPP_IDLE) &&
163 ipp_dfifo_dout_sop;
164
165reg ipp_dmc_dat_ack_d;
166reg dmc_start_tcp;
167reg dmc_start_tcp_d;
168
169 always @(ack_rd_dfifo_sop or ipp_dmc_dat_ack or ipp_dfifo_dout_eop or
170 dmc_stwd_full_cksum_ena or
171 c_dmc_ipp_st)
172 begin
173 dmc_start_tcp = 1'h0;
174 dmc_ipp_dat_req = 1'h0;
175 n_dmc_ipp_st = DMC_IPP_IDLE;
176
177 case (c_dmc_ipp_st)
178 (DMC_IPP_IDLE):
179 if (ack_rd_dfifo_sop)
180 begin
181 dmc_ipp_dat_req = 1'h1; // geo: NOT sufficient
182 n_dmc_ipp_st = DMC_IPP_1ST_DATA;
183 end
184 else
185 begin
186 n_dmc_ipp_st = c_dmc_ipp_st;
187 end
188
189 (DMC_IPP_1ST_DATA):
190 if (ipp_dmc_dat_ack)
191 begin
192 dmc_start_tcp = dmc_stwd_full_cksum_ena;
193 n_dmc_ipp_st = DMC_IPP_GET_DATA;
194 end
195 else
196 begin
197 n_dmc_ipp_st = c_dmc_ipp_st;
198 end
199
200 (DMC_IPP_GET_DATA):
201 if (ipp_dfifo_dout_eop)
202 begin
203 n_dmc_ipp_st = DMC_IPP_IDLE;
204 end
205 else
206 begin
207 dmc_ipp_dat_req = 1'h1;
208 n_dmc_ipp_st = c_dmc_ipp_st;
209 end
210 default: n_dmc_ipp_st = DMC_IPP_IDLE;
211 endcase
212 end
213
214 assign dmc_stwd_status_wd = ack_rd_dfifo_sop ? ipp_dmc_data[127:0] : dmc_stwd_status_wd_r[127:0];
215
216 niu_ipp_sum_unit dmc_out_sum (
217 .ipp_din_dat (ipp_dmc_data[127:0]),
218 .port_num (1'h1 /* geo */),
219 .ipp_full_cksum (1'h1 /* geo */),
220 .ipp_la4_prot (dmc_stwd_la4_prot[1:0]),
221 .ipp_la3_vers (dmc_stwd_la3_vers[1:0]),
222 .ipp_la2_opti (dmc_stwd_la2_opti[1:0]),
223 .ip4_hdr_leng (dmc_stwd_ip4_hdr_leng[3:0]),
224 .ipp_info_valid (ipp_dmc_dat_ack),
225 .ipp_start_tcp (dmc_start_tcp && !dmc_checksum_unit),
226 .ipp_pkt_end (ipp_dfifo_dout_eop && !ipp_dfifo_dout_eop_d),
227 .ipp_max_bytes (ipp_max_bytes[16:0]),
228 .reset (reset),
229 .clk (clk),
230 .sum_prt_started (dmc_sum_prt_started_0),
231 .sum_prt_valid (dmc_sum_prt_valid_0),
232 .sum_prt_fail (dmc_sum_prt_fail_0),
233 .sum_prt_cksum (dmc_sum_prt_cksum_0[15:0]),
234 .sum_prt_length (dmc_sum_prt_length_0[15:0]),
235 .sum_prt_state (dmc_sum_prt_state_0[31:0])
236 );
237
238 niu_ipp_sum_unit dmc_out_sum_1 (
239 .ipp_din_dat (ipp_dmc_data[127:0]),
240 .port_num (1'h1 /* geo */),
241 .ipp_full_cksum (1'h1 /* geo */),
242 .ipp_la4_prot (dmc_stwd_la4_prot[1:0]),
243 .ipp_la3_vers (dmc_stwd_la3_vers[1:0]),
244 .ipp_la2_opti (dmc_stwd_la2_opti[1:0]),
245 .ip4_hdr_leng (dmc_stwd_ip4_hdr_leng[3:0]),
246 .ipp_info_valid (ipp_dmc_dat_ack),
247 .ipp_start_tcp (dmc_start_tcp && dmc_checksum_unit),
248 .ipp_pkt_end (ipp_dfifo_dout_eop && !ipp_dfifo_dout_eop_d),
249 .ipp_max_bytes (ipp_max_bytes[16:0]),
250 .reset (reset),
251 .clk (clk),
252 .sum_prt_started (dmc_sum_prt_started_1),
253 .sum_prt_valid (dmc_sum_prt_valid_1),
254 .sum_prt_fail (dmc_sum_prt_fail_1),
255 .sum_prt_cksum (dmc_sum_prt_cksum_1[15:0]),
256 .sum_prt_length (dmc_sum_prt_length_1[15:0]),
257 .sum_prt_state (dmc_sum_prt_state_1[31:0])
258 );
259
260 assign dmc_sum_prt_valid = dmc_sum_prt_valid_0 || dmc_sum_prt_valid_1;
261 assign dmc_sum_prt_fail = dmc_sum_prt_fail_0 || dmc_sum_prt_fail_1;
262 assign dmc_sum_prt_cksum = {16{dmc_sum_prt_started_0}} & dmc_sum_prt_cksum_0[15:0] |
263 {16{dmc_sum_prt_started_1}} & dmc_sum_prt_cksum_1[15:0];
264 assign dmc_sum_prt_length = {16{dmc_sum_prt_started_0}} & dmc_sum_prt_length_0[15:0] |
265 {16{dmc_sum_prt_started_1}} & dmc_sum_prt_length_1[15:0];
266 assign dmc_sum_prt_state = {32{dmc_sum_prt_started_0}} & dmc_sum_prt_state_0[31:0] |
267 {32{dmc_sum_prt_started_1}} & dmc_sum_prt_state_1[31:0];
268
269 always @(posedge clk)
270 if (reset) begin
271 dmc_ipp_dat_req_d <= #1 1'h0;
272 ipp_dfifo_dout_eop_d <= #1 1'h0;
273 ipp_dmc_dat_ack_d <= #1 1'h0;
274
275 dmc_stwd_status_wd_r <= #1 128'h0;
276 dmc_start_tcp_d <= #1 1'h0;
277
278 c_dmc_ipp_st <= #1 2'h0;
279 end
280
281 else begin
282 dmc_ipp_dat_req_d <= #1 dmc_ipp_dat_req;
283 ipp_dfifo_dout_eop_d <= #1 ipp_dfifo_dout_eop;
284 ipp_dmc_dat_ack_d <= #1 ipp_dmc_dat_ack;
285
286 dmc_stwd_status_wd_r <= #1 dmc_stwd_status_wd[127:0];
287 dmc_start_tcp_d <= #1 dmc_start_tcp;
288
289 c_dmc_ipp_st <= #1 n_dmc_ipp_st;
290 end
291
292 always @(posedge clk)
293 if (reset) begin
294 dmc_checksum_unit <= #1 1'h0;
295 dmc_pkt_cnt <= #1 16'h0;
296 end
297 else if (dmc_start_tcp && !dmc_start_tcp_d) begin
298 dmc_checksum_unit <= #1 !dmc_checksum_unit;
299 dmc_pkt_cnt <= #1 (dmc_pkt_cnt + 16'h1);
300 end
301 else begin
302 dmc_checksum_unit <= #1 dmc_checksum_unit;
303 dmc_pkt_cnt <= #1 dmc_pkt_cnt;
304 end
305
306// synopsys translate_off
307 always @ (posedge clk)
308 if (!reset)
309 begin
310 if (dmc_sum_prt_fail && dmc_sum_prt_valid)
311 $display("\n -> Warning at sim time = %d, dmc_sum_prt_fail.", $stime);
312 else ;
313 end
314// synopsys translate_on
315
316endmodule
317