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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_ipp_hdr_fifo.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************** | |
36 | *********************************************************** | |
37 | ||
38 | Project : Niu | |
39 | ||
40 | File name : niu_ipp_hdr_fifo.v | |
41 | ||
42 | Module(s) name : niu_ipp_hdr_fifo | |
43 | Original: : ipp_fifo.v main/16 label: IPP_VERIF_1.79 | |
44 | ||
45 | Parent modules : niu_ipp.v | |
46 | ||
47 | Child modules : niu_ipp.h, sram module | |
48 | ||
49 | Author's name : George Chu | |
50 | ||
51 | Date : January 2004 | |
52 | ||
53 | Description : This file contains a 146 bit by 64 latch array used as | |
54 | FIFO for receiving data from receive MAC. | |
55 | This is a 1 read port and 1 write port register file. | |
56 | ||
57 | Synthesis Notes: | |
58 | ||
59 | Modification History: | |
60 | ||
61 | Date Description | |
62 | ---- ----------- | |
63 | ||
64 | ************************************************************ | |
65 | ***********************************************************/ | |
66 | ||
67 | module niu_ipp_hdr_fifo( | |
68 | `ifdef NEPTUNE | |
69 | `else | |
70 | iol2clk, | |
71 | tcu_aclk, | |
72 | tcu_bclk, | |
73 | tcu_se_scancollar_in, | |
74 | tcu_array_wr_inhibit, | |
75 | scan_in, | |
76 | scan_out, | |
77 | mbi_wdata, | |
78 | mbi_rd_adr, | |
79 | mbi_wr_adr, | |
80 | mbi_wr_en, | |
81 | mbi_rd_en, | |
82 | mbi_run, | |
83 | `endif | |
84 | ipp_hfifo_rden, | |
85 | ipp_hfifo_rptr, | |
86 | ipp_hfifo_wptr, ipp_hfifo_wten, | |
87 | ipp_hfifo_dinp, inc_hfifo_dat_rptr_d, // geo: Vega sim MUST have "fifo_rd_en" | |
88 | ipp_ffl_dvalid_n, clr_ipp_hfifo_par_err, | |
89 | reset, clk, | |
90 | ipp_hfifo_dout, ipp_hfifo_par_err, | |
91 | ipp_hfifo_par_addr | |
92 | ); | |
93 | ||
94 | `ifdef NEPTUNE | |
95 | `else | |
96 | parameter DATA_WIDTH_MINUS1 = 145; | |
97 | parameter ADDR_WIDTH_MINUS1 = 5; | |
98 | ||
99 | input iol2clk; | |
100 | input tcu_aclk; | |
101 | input tcu_bclk; | |
102 | input tcu_se_scancollar_in; | |
103 | input tcu_array_wr_inhibit; | |
104 | input scan_in; | |
105 | output scan_out; | |
106 | ||
107 | input [DATA_WIDTH_MINUS1:0] mbi_wdata; | |
108 | input [ADDR_WIDTH_MINUS1:0] mbi_rd_adr; | |
109 | input [ADDR_WIDTH_MINUS1:0] mbi_wr_adr; | |
110 | input mbi_wr_en; | |
111 | input mbi_rd_en; | |
112 | input mbi_run; | |
113 | `endif | |
114 | ||
115 | input ipp_hfifo_rden; // from ipp_load module | |
116 | input [5:0] ipp_hfifo_rptr; // from ipp_load module | |
117 | input [5:0] ipp_hfifo_wptr; // from load_sm module | |
118 | input ipp_hfifo_wten; // from load_sm module | |
119 | input [129:0] ipp_hfifo_dinp; // from load_sm module | |
120 | input inc_hfifo_dat_rptr_d; | |
121 | input ipp_ffl_dvalid_n; // from load_sm module | |
122 | input clr_ipp_hfifo_par_err; // from post_ctrl module | |
123 | ||
124 | input reset; | |
125 | input clk; // clock | |
126 | ||
127 | output [145:0] ipp_hfifo_dout; // to unload module | |
128 | output ipp_hfifo_par_err; // to ipp_post module | |
129 | output [5:0] ipp_hfifo_par_addr; | |
130 | ||
131 | wire [145:0] ipp_hfifo_dout; // to unload module | |
132 | reg ipp_hfifo_par_err; | |
133 | reg [5:0] ipp_hfifo_par_addr; | |
134 | ||
135 | reg [5:0] ipp_hfifo_rptr_d1; | |
136 | wire [5:0] ipp_hfifo_par_addr_n; | |
137 | wire ipp_hfifo_check_parity = (ipp_ffl_dvalid_n || inc_hfifo_dat_rptr_d); | |
138 | reg ipp_hfifo_par_err_n_ram; | |
139 | wire ipp_hfifo_par_err_n; | |
140 | ||
141 | reg [15:0] header_parity; | |
142 | ||
143 | wire [15:0] parity_data_in = | |
144 | {^ipp_hfifo_dinp[007:000], ^ipp_hfifo_dinp[015:008], | |
145 | ^ipp_hfifo_dinp[023:016], ^ipp_hfifo_dinp[031:024], | |
146 | ^ipp_hfifo_dinp[039:032], ^ipp_hfifo_dinp[047:040], | |
147 | ^ipp_hfifo_dinp[055:048], ^ipp_hfifo_dinp[063:056], | |
148 | ^ipp_hfifo_dinp[071:064], ^ipp_hfifo_dinp[079:072], | |
149 | ^ipp_hfifo_dinp[087:080], ^ipp_hfifo_dinp[095:088], | |
150 | ^ipp_hfifo_dinp[103:096], ^ipp_hfifo_dinp[111:104], | |
151 | ^ipp_hfifo_dinp[120:112], ^ipp_hfifo_dinp[129:121]}; | |
152 | ||
153 | //********************************************************* | |
154 | //***** ipp_hfifo_mem (130+16)-bit x 64-entry 1K-byte data | |
155 | //********************************************************* | |
156 | ||
157 | niu_ram_64_146 ram_64_146_0 ( | |
158 | `ifdef NEPTUNE | |
159 | .clk (clk), | |
160 | `else | |
161 | .clk (iol2clk), | |
162 | .tcu_aclk (tcu_aclk), | |
163 | .tcu_bclk (tcu_bclk), | |
164 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
165 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
166 | .scan_in (scan_in), | |
167 | .scan_out (scan_out), | |
168 | .mbi_wdata (mbi_wdata), | |
169 | .mbi_rd_adr (mbi_rd_adr), | |
170 | .mbi_wr_adr (mbi_wr_adr), | |
171 | .mbi_wr_en (mbi_wr_en), | |
172 | .mbi_rd_en (mbi_rd_en), | |
173 | .mbi_run (mbi_run), | |
174 | `endif .data_inp ({parity_data_in[15:0],ipp_hfifo_dinp[129:0]}), | |
175 | .addr_rd (ipp_hfifo_rptr[5:0]), | |
176 | .addr_wt (ipp_hfifo_wptr[5:0]), | |
177 | .wt_enable (ipp_hfifo_wten), | |
178 | .cs_rd (ipp_hfifo_rden /* geo 1'h1 */), | |
179 | .data_out (ipp_hfifo_dout[145:0]) | |
180 | ); | |
181 | ||
182 | //****** parity gen ******/ | |
183 | always @(ipp_hfifo_dout) | |
184 | begin | |
185 | header_parity = {^ipp_hfifo_dout[007:000], ^ipp_hfifo_dout[015:008], | |
186 | ^ipp_hfifo_dout[023:016], ^ipp_hfifo_dout[031:024], | |
187 | ^ipp_hfifo_dout[039:032], ^ipp_hfifo_dout[047:040], | |
188 | ^ipp_hfifo_dout[055:048], ^ipp_hfifo_dout[063:056], | |
189 | ^ipp_hfifo_dout[071:064], ^ipp_hfifo_dout[079:072], | |
190 | ^ipp_hfifo_dout[087:080], ^ipp_hfifo_dout[095:088], | |
191 | ^ipp_hfifo_dout[103:096], ^ipp_hfifo_dout[111:104], | |
192 | ^ipp_hfifo_dout[120:112], ^ipp_hfifo_dout[129:121]}; | |
193 | ||
194 | ipp_hfifo_par_err_n_ram = !(ipp_hfifo_dout[145:130] == header_parity[15:0]); | |
195 | end | |
196 | ||
197 | assign ipp_hfifo_par_err_n = ipp_hfifo_check_parity && ipp_hfifo_par_err_n_ram || ipp_hfifo_par_err; | |
198 | ||
199 | assign ipp_hfifo_par_addr_n = ipp_hfifo_par_err_n && !ipp_hfifo_par_err ? ipp_hfifo_rptr_d1[5:0] : | |
200 | ipp_hfifo_par_addr[5:0]; | |
201 | ||
202 | always @(posedge clk) | |
203 | if (reset || clr_ipp_hfifo_par_err) | |
204 | begin | |
205 | ipp_hfifo_par_err <= 1'h0; | |
206 | ipp_hfifo_rptr_d1 <= 6'h0; | |
207 | ipp_hfifo_par_addr <= 6'h0; | |
208 | end | |
209 | else | |
210 | begin | |
211 | ipp_hfifo_par_err <= ipp_hfifo_par_err_n; | |
212 | ipp_hfifo_rptr_d1 <= ipp_hfifo_rptr[5:0]; | |
213 | ipp_hfifo_par_addr <= ipp_hfifo_par_addr_n[5:0]; | |
214 | end | |
215 | ||
216 | endmodule | |
217 |