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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_ipp_slv.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************** | |
36 | *********************************************************** | |
37 | ||
38 | Project : Vega | |
39 | ||
40 | File name : niu_ipp_slv.v | |
41 | ||
42 | Module(s) name : niu_ipp_slv | |
43 | Original: : ipp_slv.v main.18, | |
44 | ||
45 | Parent modules : niu_ipp.v | |
46 | ||
47 | Child modules : niu_ipp_lib.v | |
48 | ||
49 | Author's name : Jonathan Shen, George Chu | |
50 | ||
51 | Date : May. 2002 | |
52 | ||
53 | Description : Slave module for PIO access. | |
54 | ||
55 | Synthesis Notes: | |
56 | ||
57 | Modification History: | |
58 | ||
59 | Date Description | |
60 | ---- ----------- | |
61 | ||
62 | ************************************************************ | |
63 | ***********************************************************/ | |
64 | ||
65 | module niu_ipp_slv ( | |
66 | ||
67 | fifo_data_out_reg, // from ipp_fifo | |
68 | fifo_wr_data_reg, // to ipp_load | |
69 | fifo_wr_data_reg_wr_en_pls, // to ipp_load | |
70 | inc_pkt_disc_cntr, // from niu_ipp_pkt_dsc | |
71 | sum_prt_fail, // from cksum | |
72 | sum_prt_valid, // from cksum | |
73 | fifo_over_run, // from ipp_load | |
74 | fifo_under_run, // from ipp_load | |
75 | par_err, // from ipp_fifo | |
76 | ipp_hfifo_par_addr, // from ipp_fifo | |
77 | fwd_vec_cycle1, // from ipp_ffl | |
78 | vec_cycle1_wr_en, // to ipp_ffl | |
79 | ippfifo_rd_ptr_pio_wr_en, // to ipp_load | |
80 | ippfifo_wr_ptr_pio_wr_en, // to ipp_load | |
81 | fifo_rd_ptr, // from ipp_load | |
82 | fifo_wr_ptr, // from ipp_load | |
83 | ipp_dfifo_rptr, // from ipp_unload_ctl | |
84 | ipp_dfifo_wptr, // from ipp_unload_ctl, addr[10:0] of 2k-entry | |
85 | ipp_dfifo_dout1, // from ipp_dfifo data_out_1 | |
86 | ipp_dfifo_dout1_ecc, | |
87 | ipp_dfifo_dout1_ecc_syn, | |
88 | dfifo_miss_eop, | |
89 | dfifo_miss_sop, | |
90 | ecc_pkt_corrupted, | |
91 | dfifo_wt_data_reg_wr_en_pls, // to ipp_unload_dat | |
92 | dfifo_rd_ptr_pio_wr_en, | |
93 | dfifo_wt_ptr_pio_wr_en, | |
94 | // for ipp enable | |
95 | rst_ipp_en, // from ipp | |
96 | wr_ipp_en_bit0, // to ipp | |
97 | // state machine | |
98 | state_mach0, // from ipp | |
99 | state_mach1, // from ipp | |
100 | state_mach2, // from ipp | |
101 | state_mach3, // from ipp | |
102 | state_mach4, // from ipp | |
103 | state_mach5, // from ipp | |
104 | state_mach6, // from ipp | |
105 | state_mach7, // from ipp | |
106 | state_mach8, // from ipp | |
107 | state_mach9, // from ipp | |
108 | state_mach10, // from ipp | |
109 | state_mach11, // from ipp | |
110 | state_mach12, // from ipp | |
111 | state_mach13, // from ipp | |
112 | state_mach14, // from ipp | |
113 | state_mach15, // from ipp | |
114 | // pio interface | |
115 | ipp_pio_sel, | |
116 | ipp_pio_addr, | |
117 | ipp_pio_rd, | |
118 | ipp_pio_wdata, | |
119 | ipp_pio_ack, | |
120 | ipp_pio_rdata, | |
121 | ipp_pio_err, | |
122 | ipp_pio_intr, | |
123 | // for debug_bus | |
124 | mac_ipp_req, | |
125 | xmac_ipp_ack, | |
126 | mac_ipp_tag, | |
127 | mac_ipp_data, | |
128 | mac_ipp_ctrl, | |
129 | mac_ipp_stat, | |
130 | ipp_mac_ack, | |
131 | ipp_xmac_req, | |
132 | ffl_ipp_dvalid, | |
133 | ffl_ipp_data, | |
134 | ffl_ipp_ready, | |
135 | ipp_ffl_mac_default, | |
136 | ipp_ffl_dvalid, | |
137 | ffl_arb_ack, | |
138 | ipp_ffl_req, | |
139 | // global | |
140 | config_reg, // to ipp | |
141 | ipp_debug, // to ipp | |
142 | ipp_ecc_corrupt_sop, | |
143 | ipp_ecc_corrupt_2nd, | |
144 | ipp_ecc_corrupt_eop, | |
145 | ipp_ecc_corrupt_sing, | |
146 | ipp_ecc_corrupt_doub, | |
147 | ipp_ecc_corrupt_no_uncor, | |
148 | ecc_pkt_corrupted_clr, | |
149 | clk, | |
150 | reset, | |
151 | reset2 | |
152 | ); // end of pin definition | |
153 | ||
154 | input [145:0] fifo_data_out_reg; | |
155 | input inc_pkt_disc_cntr; | |
156 | input sum_prt_fail; | |
157 | input sum_prt_valid; | |
158 | input fifo_over_run; | |
159 | input fifo_under_run; | |
160 | input par_err; | |
161 | input [5:0] ipp_hfifo_par_addr; | |
162 | input [13:0] fwd_vec_cycle1; | |
163 | ||
164 | input [5:0] fifo_rd_ptr; | |
165 | input [6:0] fifo_wr_ptr; | |
166 | ||
167 | input [11:0] ipp_dfifo_rptr; // from ipp_unload_ctl | |
168 | input [11:0] ipp_dfifo_wptr; // from ipp_unload_ctl, addr[11:0] of 2k-entry+1.wrap | |
169 | input [129:0] ipp_dfifo_dout1; // from ipp_dfifo data_out_1 | |
170 | input [18:0] ipp_dfifo_dout1_ecc; | |
171 | input [15:0] ipp_dfifo_dout1_ecc_syn; | |
172 | input dfifo_miss_eop; | |
173 | input dfifo_miss_sop; | |
174 | input ecc_pkt_corrupted; | |
175 | ||
176 | input rst_ipp_en; | |
177 | ||
178 | input [3:0] state_mach0; | |
179 | input [3:0] state_mach1; | |
180 | input [3:0] state_mach2; | |
181 | input [3:0] state_mach3; | |
182 | input [3:0] state_mach4; | |
183 | input [3:0] state_mach5; | |
184 | input [3:0] state_mach6; | |
185 | input [3:0] state_mach7; | |
186 | input [3:0] state_mach8; | |
187 | input [3:0] state_mach9; | |
188 | input [3:0] state_mach10; | |
189 | input [3:0] state_mach11; | |
190 | input [3:0] state_mach12; | |
191 | input [3:0] state_mach13; | |
192 | input [3:0] state_mach14; | |
193 | input [3:0] state_mach15; | |
194 | ||
195 | input ipp_pio_sel; | |
196 | `ifdef NEPTUNE | |
197 | input [13:0] ipp_pio_addr; | |
198 | `else | |
199 | input [14:0] ipp_pio_addr; | |
200 | `endif | |
201 | input ipp_pio_rd; | |
202 | input [31:0] ipp_pio_wdata; | |
203 | ||
204 | input mac_ipp_req; // bmac sends the request to ipp | |
205 | input xmac_ipp_ack; // xmac sends the ack to ipp | |
206 | input mac_ipp_tag; // mac identifies the last part packet | |
207 | input [63:0] mac_ipp_data; // mac writing the data to ipp | |
208 | input mac_ipp_ctrl; // active high for control information | |
209 | input [22:0] mac_ipp_stat; // mac writing the status to ipp | |
210 | input ipp_mac_ack; // ack from ipp to bmac | |
211 | input ipp_xmac_req; // req(as rdy) from ipp to xmac | |
212 | ||
213 | input [13:0] ffl_ipp_data; | |
214 | input ffl_ipp_dvalid; | |
215 | input ffl_ipp_ready; | |
216 | input [11:0] ipp_ffl_mac_default; | |
217 | input ipp_ffl_dvalid; | |
218 | input ffl_arb_ack; | |
219 | input ipp_ffl_req; | |
220 | ||
221 | input clk, reset; | |
222 | ||
223 | output [129:0] fifo_wr_data_reg; | |
224 | output fifo_wr_data_reg_wr_en_pls; | |
225 | output [24:0] config_reg; | |
226 | output [31:0] ipp_debug; | |
227 | output ipp_ecc_corrupt_sop; | |
228 | output ipp_ecc_corrupt_2nd; | |
229 | output ipp_ecc_corrupt_eop; | |
230 | output ipp_ecc_corrupt_sing; | |
231 | output ipp_ecc_corrupt_doub; | |
232 | output ipp_ecc_corrupt_no_uncor; | |
233 | output ecc_pkt_corrupted_clr; | |
234 | output vec_cycle1_wr_en; | |
235 | output ippfifo_rd_ptr_pio_wr_en; | |
236 | output ippfifo_wr_ptr_pio_wr_en; | |
237 | output dfifo_wt_data_reg_wr_en_pls; // to ipp_unload_dat | |
238 | output dfifo_rd_ptr_pio_wr_en; | |
239 | output dfifo_wt_ptr_pio_wr_en; | |
240 | ||
241 | output wr_ipp_en_bit0; | |
242 | ||
243 | output ipp_pio_ack; | |
244 | output [31:0] ipp_pio_rdata; | |
245 | output ipp_pio_err; | |
246 | output ipp_pio_intr; | |
247 | ||
248 | output reset2; | |
249 | ||
250 | /*************************************** | |
251 | ** Register declaration | |
252 | ***************************************/ | |
253 | reg [31:0] rd_data; | |
254 | reg non_qualified_addr_err; | |
255 | reg config_wr_en; | |
256 | reg ipp_soft_reset; | |
257 | reg pkt_disc_cntr_wr_en; | |
258 | reg pkt_disc_cntr_auto_clr; | |
259 | reg bad_chksum_cntr_wr_en; | |
260 | reg bad_chksum_cntr_auto_clr; | |
261 | reg ecc_error_cntr_wr_en; | |
262 | reg ecc_error_cntr_auto_clr; | |
263 | reg ld_status; | |
264 | reg interr_stat_auto_clr; | |
265 | reg interr_mask_wr_en; | |
266 | reg [7:0] interr_mask_reg; | |
267 | reg fifo_wr_data_reg_wr_en; | |
268 | reg fifo_wr_data_reg0_wr_en; | |
269 | reg fifo_wr_data_reg1_wr_en; | |
270 | reg fifo_wr_data_reg2_wr_en; | |
271 | reg fifo_wr_data_reg3_wr_en; | |
272 | reg fifo_wr_data_reg4_wr_en; | |
273 | reg ippfifo_rd_ptr_pio_wr_en; | |
274 | reg ippfifo_wr_ptr_pio_wr_en; | |
275 | reg vec_cycle1_wr_en; | |
276 | reg ipp_pio_intr; | |
277 | reg debug_wr_en; | |
278 | ||
279 | reg dfifo_wt_data_reg_wr_en; | |
280 | wire dfifo_wt_data_reg_wr_en_pls; | |
281 | reg dfifo_rd_ptr_pio_wr_en; | |
282 | reg dfifo_wt_ptr_pio_wr_en; | |
283 | /*************************************** | |
284 | ** Wire declaration | |
285 | ***************************************/ | |
286 | `ifdef NEPTUNE | |
287 | wire [13:0] reg_offset; | |
288 | `else | |
289 | wire [14:0] reg_offset; | |
290 | `endif | |
291 | wire [31:0] ipp_pio_wdata; | |
292 | wire [31:0] wr_data; | |
293 | wire rd_wr, wr_en; | |
294 | //wire rd_en; | |
295 | wire rac_pls; | |
296 | wire core_sel; | |
297 | wire core_sel_lead; | |
298 | //wire core_sel_trail; | |
299 | wire addr_err; | |
300 | wire [24:0] config_reg; | |
301 | wire [31:0] ipp_debug; | |
302 | wire [13:0] pkt_disc_cntr_reg; | |
303 | wire [13:0] bad_chksum_cntr_reg; | |
304 | wire [7:0] ecc_error_cntr_reg; | |
305 | wire dfifo_miss_tag = dfifo_miss_eop || dfifo_miss_sop; | |
306 | wire dfifo_miss_eop_oc; | |
307 | wire dfifo_miss_sop_oc; | |
308 | wire par_err_oc; | |
309 | wire [5:0] hfifo_par_addr_oc; | |
310 | wire fifo_over_run_oc; | |
311 | wire fifo_under_run_oc; | |
312 | wire max_pkt_disc_cntr_reached; | |
313 | wire max_bad_chksum_cntr_reached; | |
314 | wire max_ecc_error_cntr_reached; | |
315 | wire fifo_wr_data_reg_wr_en_pls; | |
316 | wire n_reset2 = reset | ipp_soft_reset; | |
317 | reg reset2; | |
318 | wire [3:0] debug_reg; | |
319 | ||
320 | wire datfifo_pio_wr_ena = config_reg[5]; | |
321 | wire [17:0] ipp_dfifo_dout1_ecc_sti; | |
322 | wire [15:0] ipp_dfifo_dout1_ecc_syn_sti; | |
323 | wire uncorr_error1_found = ipp_dfifo_dout1_ecc[18]; | |
324 | wire uncorr_error1_found_d; | |
325 | wire [10:0] ipp_dfifo_rptr1 = ipp_dfifo_dout1_ecc[17:7]; | |
326 | wire [10:0] ipp_dfifo_rptr1_d; | |
327 | wire ecc_no_error = ipp_dfifo_dout1_ecc[0]; | |
328 | wire ecc_no_error_d; | |
329 | wire [1:0] ecc_uncorrect_error = ipp_dfifo_dout1_ecc[6:5]; | |
330 | wire wt_ecc_status = |ecc_uncorrect_error[1:0]; | |
331 | reg rac_ecc_syndrome; | |
332 | reg wt_ecc_corrupt_reg; | |
333 | wire [31:0] n_ipp_ecc_corrupt_reg; | |
334 | wire [31:0] ipp_ecc_corrupt_reg; | |
335 | wire ipp_ecc_corrupt_sop; | |
336 | wire ipp_ecc_corrupt_2nd; | |
337 | wire ipp_ecc_corrupt_eop; | |
338 | wire ipp_ecc_corrupt_sing = ipp_ecc_corrupt_reg[16]; | |
339 | wire ipp_ecc_corrupt_doub = ipp_ecc_corrupt_reg[17]; | |
340 | wire ipp_ecc_corrupt_no_uncor = ipp_ecc_corrupt_reg[31]; | |
341 | wire ecc_pkt_corrupted_clr; | |
342 | wire ipp_ecc_corrupt_one_pkt = ipp_ecc_corrupt_reg[8]; | |
343 | wire ipp_ecc_corrupt_all_pkt = ipp_ecc_corrupt_reg[10]; | |
344 | reg ipp_ecc_corrupt_ena; | |
345 | wire [11:0] ipp_dfifo_rptr_d; | |
346 | reg wt_dfifo_rptr; | |
347 | reg rac_dfifo_rptr; | |
348 | wire [11:0] ipp_dfifo_rptr_sti; | |
349 | ||
350 | wire [31:0] interr_stat_bus = {dfifo_miss_sop_oc, | |
351 | dfifo_miss_eop_oc, // bit 30 | |
352 | ipp_dfifo_dout1_ecc_sti[17:0], // bit 12~29 | |
353 | par_err_oc, // bit 11 | |
354 | max_ecc_error_cntr_reached, // bit 10 | |
355 | hfifo_par_addr_oc[5:0], // bit 4~9 | |
356 | fifo_over_run_oc, // bit 3 | |
357 | fifo_under_run_oc, // bit 2 | |
358 | max_bad_chksum_cntr_reached, // bit 1 | |
359 | max_pkt_disc_cntr_reached // bit 0 | |
360 | }; | |
361 | ||
362 | wire inc_bad_chksum_cntr = sum_prt_fail && sum_prt_valid; | |
363 | wire inc_ecc_error_cntr = !ecc_no_error_d && !(ipp_dfifo_rptr1[10:0]==ipp_dfifo_rptr1_d[10:0]) || | |
364 | uncorr_error1_found && !uncorr_error1_found_d; | |
365 | ||
366 | `ifdef NEPTUNE | |
367 | `define IPP_SLV_ZEROS 1'h0 | |
368 | `else | |
369 | `define IPP_SLV_ZEROS 2'h0 | |
370 | `endif | |
371 | ||
372 | always @ (posedge clk) | |
373 | ipp_pio_intr <= ((~interr_mask_reg[6]) & (interr_stat_bus[31] || interr_stat_bus[30])) || | |
374 | ((~interr_mask_reg[5]) & (interr_stat_bus[29] || interr_stat_bus[28])) || | |
375 | ((~interr_mask_reg[4]) & interr_stat_bus[11]) || | |
376 | ((~interr_mask_reg[7]) & interr_stat_bus[10]) || | |
377 | ((~interr_mask_reg[3]) & interr_stat_bus[3]) | | |
378 | ((~interr_mask_reg[2]) & interr_stat_bus[2]) | | |
379 | ((~interr_mask_reg[1]) & interr_stat_bus[1]) | | |
380 | ((~interr_mask_reg[0]) & interr_stat_bus[0]); | |
381 | ||
382 | /*************************************** | |
383 | ** Read and Write logic | |
384 | ***************************************/ | |
385 | ||
386 | ipp_FD1 rd_wr_FD1 (.D(ipp_pio_rd), .CP(clk), .Q(rd_wr)); | |
387 | ||
388 | ipp_FD1 core_sel_FD1 (.D(ipp_pio_sel), .CP(clk), .Q(core_sel)); | |
389 | ||
390 | `ifdef NEPTUNE | |
391 | ipp_RegDff #(14) reg_offset_RegDff (.din(ipp_pio_addr[13:0]), | |
392 | .clk(clk), | |
393 | .qout(reg_offset[13:0])); | |
394 | `else | |
395 | ipp_RegDff #(15) reg_offset_RegDff (.din(ipp_pio_addr[14:0]), | |
396 | .clk(clk), | |
397 | .qout(reg_offset[14:0])); | |
398 | `endif | |
399 | ||
400 | ipp_RegDff #(32) wr_data_RegDff (.din(ipp_pio_wdata[31:0]), | |
401 | .clk(clk), | |
402 | .qout(wr_data[31:0])); | |
403 | ||
404 | ipp_PlsGen2 core_sel_PlsGen2 (.sig_in(core_sel),. clk(clk), | |
405 | .lead(core_sel_lead), | |
406 | .trail(/*core_sel_trail*/)); | |
407 | ||
408 | //assign rd_en = core_sel & rd_wr; | |
409 | wire rac_ok = core_sel_lead & rd_wr; | |
410 | assign wr_en = core_sel_lead & (~rd_wr); | |
411 | ||
412 | ipp_RegDff #(32) pio_rd_data_RegDff (.din(rd_data),.clk(clk), | |
413 | .qout(ipp_pio_rdata)); | |
414 | ||
415 | ipp_FD1 pio_ack_FD1 (.D(core_sel_lead), .CP(clk), .Q(ipp_pio_ack)); | |
416 | ||
417 | ipp_FD1 rac_pls_FD1 (.D(rac_ok), .CP(clk), .Q(rac_pls)); | |
418 | ||
419 | assign addr_err = non_qualified_addr_err & core_sel_lead; | |
420 | ||
421 | ipp_FD1 pio_err_FD1 (.D(addr_err), .CP(clk), .Q(ipp_pio_err)); | |
422 | ||
423 | //***** ipp local Reset Logic ***** | |
424 | always @ (posedge clk) begin | |
425 | ipp_soft_reset <= config_wr_en & wr_data[31] && !reset; | |
426 | reset2 <= n_reset2; | |
427 | end | |
428 | ||
429 | /*************************************** | |
430 | ** Read and Write Address Decoder | |
431 | ***************************************/ | |
432 | always @ (rac_ok or wr_en or reg_offset or config_reg or ipp_soft_reset or rac_pls | |
433 | or pkt_disc_cntr_reg or bad_chksum_cntr_reg or interr_stat_bus or | |
434 | interr_mask_reg or fifo_data_out_reg or fifo_wr_data_reg or | |
435 | fifo_rd_ptr or fifo_wr_ptr or | |
436 | ipp_dfifo_dout1 or ipp_dfifo_rptr or ipp_dfifo_wptr or | |
437 | state_mach0 or state_mach1 or state_mach2 or | |
438 | state_mach3 or state_mach4 or state_mach5 or state_mach6 or | |
439 | state_mach7 or state_mach8 or state_mach9 or state_mach10 or | |
440 | state_mach11 or state_mach12 or state_mach13 or state_mach14 or | |
441 | state_mach15 or fwd_vec_cycle1 or | |
442 | ecc_error_cntr_reg or ipp_ecc_corrupt_reg or | |
443 | ipp_dfifo_dout1_ecc_syn_sti or | |
444 | ipp_dfifo_rptr_sti or | |
445 | debug_reg) | |
446 | begin | |
447 | non_qualified_addr_err = 0; | |
448 | rd_data = 32'hDEAD_BEEF; | |
449 | config_wr_en = 1'b0; | |
450 | pkt_disc_cntr_wr_en = 1'b0; | |
451 | pkt_disc_cntr_auto_clr = 1'b0; | |
452 | bad_chksum_cntr_wr_en = 1'b0; | |
453 | bad_chksum_cntr_auto_clr = 1'b0; | |
454 | ld_status = 1'b0; | |
455 | interr_stat_auto_clr = 1'b0; | |
456 | interr_mask_wr_en = 1'b0; | |
457 | fifo_wr_data_reg_wr_en = 1'b0; | |
458 | fifo_wr_data_reg0_wr_en = 1'b0; | |
459 | fifo_wr_data_reg1_wr_en = 1'b0; | |
460 | fifo_wr_data_reg2_wr_en = 1'b0; | |
461 | fifo_wr_data_reg3_wr_en = 1'b0; | |
462 | fifo_wr_data_reg4_wr_en = 1'b0; | |
463 | ippfifo_rd_ptr_pio_wr_en = 1'b0; | |
464 | ippfifo_wr_ptr_pio_wr_en = 1'b0; | |
465 | vec_cycle1_wr_en = 1'b0; | |
466 | debug_wr_en = 1'b0; | |
467 | ||
468 | dfifo_wt_data_reg_wr_en = 1'h0; | |
469 | dfifo_rd_ptr_pio_wr_en = 1'h0; | |
470 | dfifo_wt_ptr_pio_wr_en = 1'h0; | |
471 | ecc_error_cntr_wr_en = 1'h0; | |
472 | ecc_error_cntr_auto_clr = 1'h0; | |
473 | wt_ecc_corrupt_reg = 1'h0; | |
474 | rac_ecc_syndrome = 1'h0; | |
475 | wt_dfifo_rptr = 1'h0; | |
476 | rac_dfifo_rptr = 1'h0; | |
477 | ||
478 | case (reg_offset) //synopsys parallel_case full_case | |
479 | {`IPP_SLV_ZEROS,13'h000}: begin | |
480 | config_wr_en = wr_en; | |
481 | rd_data = {ipp_soft_reset,6'h0,config_reg[24:0]}; | |
482 | end | |
483 | {`IPP_SLV_ZEROS,13'h004}: begin | |
484 | rd_data = 32'h0; | |
485 | end | |
486 | {`IPP_SLV_ZEROS,13'h020}: begin | |
487 | pkt_disc_cntr_wr_en = wr_en; | |
488 | pkt_disc_cntr_auto_clr = rac_pls; | |
489 | rd_data = {18'b0, pkt_disc_cntr_reg[13:0]}; | |
490 | end | |
491 | {`IPP_SLV_ZEROS,13'h024}: begin | |
492 | rd_data = 32'h0; | |
493 | end | |
494 | {`IPP_SLV_ZEROS,13'h028}: begin | |
495 | bad_chksum_cntr_wr_en = wr_en; | |
496 | bad_chksum_cntr_auto_clr = rac_pls; | |
497 | rd_data = {18'b0, bad_chksum_cntr_reg[13:0]}; | |
498 | end | |
499 | {`IPP_SLV_ZEROS,13'h02c}: begin | |
500 | rd_data = 32'h0; | |
501 | end | |
502 | {`IPP_SLV_ZEROS,13'h030}: begin | |
503 | ecc_error_cntr_wr_en = wr_en; | |
504 | ecc_error_cntr_auto_clr = rac_pls; | |
505 | rd_data = {24'b0, ecc_error_cntr_reg[7:0]}; | |
506 | end | |
507 | {`IPP_SLV_ZEROS,13'h034}: begin | |
508 | rd_data = 32'h0; | |
509 | end | |
510 | {`IPP_SLV_ZEROS,13'h040}: begin // both R/W and RAC | |
511 | ld_status = wr_en; | |
512 | interr_stat_auto_clr = rac_pls; | |
513 | rd_data = interr_stat_bus; | |
514 | end | |
515 | {`IPP_SLV_ZEROS,13'h044}: begin | |
516 | rd_data = 32'h0; | |
517 | end | |
518 | {`IPP_SLV_ZEROS,13'h048}: begin // "1" means Mask Enable | |
519 | interr_mask_wr_en = wr_en; | |
520 | rd_data = {{24{1'h0}}, interr_mask_reg[7:0]}; | |
521 | end | |
522 | {`IPP_SLV_ZEROS,13'h04c}: begin | |
523 | rd_data = 32'h0; | |
524 | end | |
525 | {`IPP_SLV_ZEROS,13'h060}: begin // fifo_data_out_reg[31:0]; RO | |
526 | rd_data = fifo_data_out_reg[31:0]; | |
527 | end | |
528 | {`IPP_SLV_ZEROS,13'h064}: begin | |
529 | rd_data = 32'h0; | |
530 | end | |
531 | {`IPP_SLV_ZEROS,13'h068}: begin // fifo_data_out_reg[63:32]; RO | |
532 | rd_data = fifo_data_out_reg[63:32]; | |
533 | end | |
534 | {`IPP_SLV_ZEROS,13'h06c}: begin | |
535 | rd_data = 32'h0; | |
536 | end | |
537 | {`IPP_SLV_ZEROS,13'h070}: begin // fifo_data_out_reg[95:64]; RO | |
538 | rd_data = fifo_data_out_reg[95:64]; | |
539 | end | |
540 | {`IPP_SLV_ZEROS,13'h074}: begin | |
541 | rd_data = 32'h0; | |
542 | end | |
543 | {`IPP_SLV_ZEROS,13'h078}: begin // fifo_data_out_reg[127:96]; RO | |
544 | rd_data = fifo_data_out_reg[127:96]; | |
545 | end | |
546 | {`IPP_SLV_ZEROS,13'h07c}: begin | |
547 | rd_data = 32'h0; | |
548 | end | |
549 | {`IPP_SLV_ZEROS,13'h080}: begin // fifo_data_out_reg[145:128]; RO | |
550 | rd_data = {14'b0, fifo_data_out_reg[145:128]}; | |
551 | end | |
552 | {`IPP_SLV_ZEROS,13'h084}: begin | |
553 | rd_data = 32'h0; | |
554 | end | |
555 | {`IPP_SLV_ZEROS,13'h088}: begin | |
556 | fifo_wr_data_reg0_wr_en = wr_en; | |
557 | rd_data = fifo_wr_data_reg[31:0]; | |
558 | end | |
559 | {`IPP_SLV_ZEROS,13'h08c}: begin | |
560 | rd_data = 32'h0; | |
561 | end | |
562 | {`IPP_SLV_ZEROS,13'h090}: begin | |
563 | fifo_wr_data_reg1_wr_en = wr_en; | |
564 | rd_data = fifo_wr_data_reg[63:32]; | |
565 | end | |
566 | {`IPP_SLV_ZEROS,13'h094}: begin | |
567 | rd_data = 32'h0; | |
568 | end | |
569 | {`IPP_SLV_ZEROS,13'h098}: begin | |
570 | fifo_wr_data_reg2_wr_en = wr_en; | |
571 | rd_data = fifo_wr_data_reg[95:64]; | |
572 | end | |
573 | {`IPP_SLV_ZEROS,13'h09c}: begin | |
574 | rd_data = 32'h0; | |
575 | end | |
576 | {`IPP_SLV_ZEROS,13'h0a0}: begin | |
577 | fifo_wr_data_reg3_wr_en = wr_en; | |
578 | rd_data = fifo_wr_data_reg[127:96]; | |
579 | end | |
580 | {`IPP_SLV_ZEROS,13'h0a4}: begin | |
581 | rd_data = 32'h0; | |
582 | end | |
583 | {`IPP_SLV_ZEROS,13'h0a8}: begin | |
584 | fifo_wr_data_reg4_wr_en = wr_en; | |
585 | fifo_wr_data_reg_wr_en = wr_en; | |
586 | rd_data = {30'b0, fifo_wr_data_reg[129:128]}; | |
587 | end | |
588 | {`IPP_SLV_ZEROS,13'h0ac}: begin | |
589 | rd_data = 32'h0; | |
590 | end | |
591 | {`IPP_SLV_ZEROS,13'h0b0}: begin | |
592 | ippfifo_rd_ptr_pio_wr_en = wr_en; | |
593 | rd_data = {26'b0, fifo_rd_ptr[5:0]}; | |
594 | end | |
595 | {`IPP_SLV_ZEROS,13'h0b4}: begin | |
596 | rd_data = 32'h0; | |
597 | end | |
598 | {`IPP_SLV_ZEROS,13'h0b8}: begin | |
599 | ippfifo_wr_ptr_pio_wr_en = wr_en; | |
600 | rd_data = {25'b0, fifo_wr_ptr[6:0]}; | |
601 | end | |
602 | {`IPP_SLV_ZEROS,13'h0bc}: begin | |
603 | rd_data = 32'h0; | |
604 | end | |
605 | ||
606 | {`IPP_SLV_ZEROS,13'h0c0}: begin // ipp_dfifo_dout1[31:0]; RO | |
607 | rd_data = ipp_dfifo_dout1[31:0]; | |
608 | end | |
609 | {`IPP_SLV_ZEROS,13'h0c4}: begin | |
610 | rd_data = 32'h0; | |
611 | end | |
612 | {`IPP_SLV_ZEROS,13'h0c8}: begin // ipp_dfifo_dout1[63:32]; RO | |
613 | rd_data = ipp_dfifo_dout1[63:32]; | |
614 | end | |
615 | {`IPP_SLV_ZEROS,13'h0cc}: begin | |
616 | rd_data = 32'h0; | |
617 | end | |
618 | {`IPP_SLV_ZEROS,13'h0d0}: begin // ipp_dfifo_dout1[95:64]; RO | |
619 | rd_data = ipp_dfifo_dout1[95:64]; | |
620 | end | |
621 | {`IPP_SLV_ZEROS,13'h0d4}: begin | |
622 | rd_data = 32'h0; | |
623 | end | |
624 | {`IPP_SLV_ZEROS,13'h0d8}: begin // ipp_dfifo_dout1[127:96]; RO | |
625 | rd_data = ipp_dfifo_dout1[127:96]; | |
626 | end | |
627 | {`IPP_SLV_ZEROS,13'h0dc}: begin | |
628 | rd_data = 32'h0; | |
629 | end | |
630 | {`IPP_SLV_ZEROS,13'h0e0}: begin // ipp_dfifo_dout1[129:128]; RO | |
631 | rd_data = {30'b0, ipp_dfifo_dout1[129:128]}; | |
632 | end | |
633 | {`IPP_SLV_ZEROS,13'h0e4}: begin | |
634 | rd_data = 32'h0; | |
635 | end | |
636 | ||
637 | {`IPP_SLV_ZEROS,13'h0e8}: begin | |
638 | fifo_wr_data_reg0_wr_en = wr_en; | |
639 | rd_data = fifo_wr_data_reg[31:0]; | |
640 | end | |
641 | {`IPP_SLV_ZEROS,13'h0ec}: begin | |
642 | rd_data = 32'h0; | |
643 | end | |
644 | {`IPP_SLV_ZEROS,13'h0f0}: begin | |
645 | fifo_wr_data_reg1_wr_en = wr_en; | |
646 | rd_data = fifo_wr_data_reg[63:32]; | |
647 | end | |
648 | {`IPP_SLV_ZEROS,13'h0f4}: begin | |
649 | rd_data = 32'h0; | |
650 | end | |
651 | {`IPP_SLV_ZEROS,13'h0f8}: begin | |
652 | fifo_wr_data_reg2_wr_en = wr_en; | |
653 | rd_data = fifo_wr_data_reg[95:64]; | |
654 | end | |
655 | {`IPP_SLV_ZEROS,13'h0fc}: begin | |
656 | rd_data = 32'h0; | |
657 | end | |
658 | {`IPP_SLV_ZEROS,13'h100}: begin | |
659 | fifo_wr_data_reg3_wr_en = wr_en; | |
660 | rd_data = fifo_wr_data_reg[127:96]; | |
661 | end | |
662 | {`IPP_SLV_ZEROS,13'h104}: begin | |
663 | rd_data = 32'h0; | |
664 | end | |
665 | {`IPP_SLV_ZEROS,13'h108}: begin | |
666 | fifo_wr_data_reg4_wr_en = wr_en; | |
667 | dfifo_wt_data_reg_wr_en = wr_en; | |
668 | rd_data = {30'h0,fifo_wr_data_reg[129:128]}; | |
669 | end | |
670 | {`IPP_SLV_ZEROS,13'h10c}: begin | |
671 | rd_data = 32'h0; | |
672 | end | |
673 | ||
674 | {`IPP_SLV_ZEROS,13'h110}: begin | |
675 | dfifo_rd_ptr_pio_wr_en = wr_en; | |
676 | rd_data = {20'h0, ipp_dfifo_rptr[11:0]}; | |
677 | end | |
678 | {`IPP_SLV_ZEROS,13'h114}: begin | |
679 | rd_data = 32'h0; | |
680 | end | |
681 | {`IPP_SLV_ZEROS,13'h118}: begin | |
682 | dfifo_wt_ptr_pio_wr_en = wr_en; | |
683 | rd_data = {20'h0, ipp_dfifo_wptr[11:0]}; | |
684 | end | |
685 | {`IPP_SLV_ZEROS,13'h11c}: begin | |
686 | rd_data = 32'h0; | |
687 | end | |
688 | ||
689 | {`IPP_SLV_ZEROS,13'h120}: begin // RO | |
690 | rd_data = {state_mach7, state_mach6, | |
691 | state_mach5, state_mach4, | |
692 | state_mach3, state_mach2, | |
693 | state_mach1, state_mach0}; | |
694 | end | |
695 | {`IPP_SLV_ZEROS,13'h124}: begin | |
696 | rd_data = 32'h0; | |
697 | end | |
698 | {`IPP_SLV_ZEROS,13'h128}: begin // RO | |
699 | rd_data = {state_mach15, state_mach14, | |
700 | state_mach13, state_mach12, | |
701 | state_mach11, state_mach10, | |
702 | state_mach9, state_mach8}; | |
703 | end | |
704 | {`IPP_SLV_ZEROS,13'h12c}: begin | |
705 | rd_data = 32'h0; | |
706 | end | |
707 | {`IPP_SLV_ZEROS,13'h130}: begin | |
708 | vec_cycle1_wr_en = wr_en; | |
709 | rd_data = {18'h0, fwd_vec_cycle1[13:0]}; | |
710 | end | |
711 | {`IPP_SLV_ZEROS,13'h134}: begin | |
712 | rd_data = 32'h0; | |
713 | end | |
714 | {`IPP_SLV_ZEROS,13'h138}: begin | |
715 | debug_wr_en = wr_en; | |
716 | rd_data = {28'b0, debug_reg[3:0]}; | |
717 | end | |
718 | {`IPP_SLV_ZEROS,13'h13c}: begin | |
719 | rd_data = 32'h0; | |
720 | end | |
721 | {`IPP_SLV_ZEROS,13'h140}: begin | |
722 | rac_ecc_syndrome = rac_pls; | |
723 | rd_data = {16'h0,ipp_dfifo_dout1_ecc_syn_sti[15:0]}; | |
724 | end | |
725 | {`IPP_SLV_ZEROS,13'h144}: begin | |
726 | rd_data = 32'h0; | |
727 | end | |
728 | {`IPP_SLV_ZEROS,13'h148}: begin | |
729 | wt_dfifo_rptr = wr_en; | |
730 | rac_dfifo_rptr = rac_pls; | |
731 | rd_data = {20'h0,ipp_dfifo_rptr_sti[11:0]}; | |
732 | end | |
733 | {`IPP_SLV_ZEROS,13'h14c}: begin | |
734 | rd_data = 32'h0; | |
735 | end | |
736 | {`IPP_SLV_ZEROS,13'h150}: begin | |
737 | wt_ecc_corrupt_reg = wr_en; | |
738 | rd_data = ipp_ecc_corrupt_reg[31:0]; | |
739 | end | |
740 | {`IPP_SLV_ZEROS,13'h154}: begin | |
741 | rd_data = 32'h0; | |
742 | end | |
743 | default: begin | |
744 | rd_data = 32'hDEAD_BEEF; | |
745 | non_qualified_addr_err = rac_ok; | |
746 | end | |
747 | ||
748 | endcase | |
749 | end | |
750 | ||
751 | // ****** Ecc Corruption Controls ***********************/ | |
752 | always @ (ecc_pkt_corrupted or | |
753 | ipp_ecc_corrupt_all_pkt or ipp_ecc_corrupt_one_pkt | |
754 | ) | |
755 | case({ecc_pkt_corrupted,ipp_ecc_corrupt_all_pkt,ipp_ecc_corrupt_one_pkt}) // synopsys parallel_case | |
756 | 3'b000: ipp_ecc_corrupt_ena = 1'h0; | |
757 | 3'b001: ipp_ecc_corrupt_ena = 1'h1; | |
758 | 3'b010: ipp_ecc_corrupt_ena = 1'h1; | |
759 | 3'b011: ipp_ecc_corrupt_ena = 1'h1; | |
760 | 3'b100: ipp_ecc_corrupt_ena = 1'h0; | |
761 | 3'b101: ipp_ecc_corrupt_ena = 1'h0; | |
762 | 3'b110: ipp_ecc_corrupt_ena = 1'h1; | |
763 | 3'b111: ipp_ecc_corrupt_ena = 1'h1; | |
764 | default: ipp_ecc_corrupt_ena = 1'h0; | |
765 | endcase | |
766 | ||
767 | assign ipp_ecc_corrupt_sop = ipp_ecc_corrupt_reg[0] && ipp_ecc_corrupt_ena; | |
768 | assign ipp_ecc_corrupt_2nd = ipp_ecc_corrupt_reg[1] && ipp_ecc_corrupt_ena; | |
769 | assign ipp_ecc_corrupt_eop = ipp_ecc_corrupt_reg[2] && ipp_ecc_corrupt_ena; | |
770 | assign ecc_pkt_corrupted_clr = !ipp_ecc_corrupt_all_pkt && !ipp_ecc_corrupt_one_pkt || reset; | |
771 | ||
772 | //****************************** | |
773 | //* Registers instantiation | |
774 | //****************************** | |
775 | ||
776 | // ****** configuration register: 25 bits (R/W) ******/ | |
777 | ipp_reg_w_s_17 reg_w_s_17_max ( | |
778 | .di (wr_data[24:8]), | |
779 | .wr (config_wr_en), | |
780 | .rs (reset), | |
781 | .ck (clk), | |
782 | .qo (config_reg[24:8]) | |
783 | ); | |
784 | ||
785 | ipp_xREG #(7) xREG_Config(.clk(clk), .reset(reset), | |
786 | .en(config_wr_en), .din(wr_data[7:1]), | |
787 | .qout(config_reg[7:1])); | |
788 | // ConfigBit0 = IPP_EN | |
789 | // ConfigBit0 can only be written with "1" value. | |
790 | // "0" value can only be written by reset hardware. | |
791 | wire wr_ipp_en_bit1 = config_wr_en & wr_data[0]; | |
792 | wire wr_ipp_en_bit0 = config_wr_en & (~wr_data[0]); | |
793 | ||
794 | ipp_xREG #(1) xREG_ConfigBit0(.clk(clk), .reset(reset | rst_ipp_en), | |
795 | .en(wr_ipp_en_bit1), .din(wr_data[0]), | |
796 | .qout(config_reg[0])); | |
797 | ||
798 | // ****** Packet Discard Counter register: 14 bits ******/ | |
799 | ipp_RAC_Plus1_Reg #(14) RAC_Plus1_Reg_PktDiscaCntr(.clk(clk), .reset(reset), | |
800 | .iInc(inc_pkt_disc_cntr), | |
801 | .iAutoClrEn(pkt_disc_cntr_auto_clr), | |
802 | .iMaxValue({14{1'b1}}), | |
803 | .iLoad(pkt_disc_cntr_wr_en), | |
804 | .iLoadValue(wr_data[13:0]), | |
805 | .oDout(pkt_disc_cntr_reg[13:0]), | |
806 | .oMaxValueReached(max_pkt_disc_cntr_reached)); | |
807 | ||
808 | // ****** Bad Chksum Counter register: 14 bits ******/ | |
809 | ipp_RAC_Plus1_Reg #(14) RAC_Plus1_Reg_BadChksumCntr(.clk(clk), .reset(reset), | |
810 | .iInc(inc_bad_chksum_cntr), | |
811 | .iAutoClrEn(bad_chksum_cntr_auto_clr), | |
812 | .iMaxValue({14{1'b1}}), | |
813 | .iLoad(bad_chksum_cntr_wr_en), | |
814 | .iLoadValue(wr_data[13:0]), | |
815 | .oDout(bad_chksum_cntr_reg[13:0]), | |
816 | .oMaxValueReached(max_bad_chksum_cntr_reached)); | |
817 | ||
818 | // ****** Ecc Error Counter register: 8 bits ******/ | |
819 | ipp_RAC_Plus1_Reg #(8) RAC_Plus1_Reg_EccErrorCntr(.clk(clk), .reset(reset), | |
820 | .iInc(inc_ecc_error_cntr), | |
821 | .iAutoClrEn(ecc_error_cntr_auto_clr), | |
822 | .iMaxValue({8{1'b1}}), | |
823 | .iLoad(ecc_error_cntr_wr_en), | |
824 | .iLoadValue(wr_data[7:0]), | |
825 | .oDout(ecc_error_cntr_reg[7:0]), | |
826 | .oMaxValueReached(max_ecc_error_cntr_reached)); | |
827 | ||
828 | // ****** Interrupt Status bits ******/ | |
829 | ipp_RAC_FF reg_rac_mis_sop (.clk(clk), .reset(reset), .set(dfifo_miss_sop), | |
830 | .rst(interr_stat_auto_clr), .load(ld_status), .load_data(wr_data[31]), | |
831 | .dout(dfifo_miss_sop_oc)); | |
832 | ||
833 | ipp_RAC_FF reg_rac_mis_eop (.clk(clk), .reset(reset), .set(dfifo_miss_eop), | |
834 | .rst(interr_stat_auto_clr), .load(ld_status), .load_data(wr_data[30]), | |
835 | .dout(dfifo_miss_eop_oc)); | |
836 | ||
837 | ipp_reg_w_sti_r_rac_1 reg_w_sti_r_rac_1_ecc_unc1 ( | |
838 | .di (ld_status ? wr_data[29] : ipp_dfifo_dout1_ecc[6]), | |
839 | .wr (ld_status || wt_ecc_status), | |
840 | .rs (reset), | |
841 | .rac (interr_stat_auto_clr), | |
842 | .ck (clk), | |
843 | .qo (ipp_dfifo_dout1_ecc_sti[17]) | |
844 | ); | |
845 | ||
846 | ipp_reg_w_sti_r_rac_1 reg_w_sti_r_rac_1_ecc_unc0 ( | |
847 | .di (ld_status ? wr_data[28] : ipp_dfifo_dout1_ecc[5]), | |
848 | .wr (ld_status || wt_ecc_status), | |
849 | .rs (reset), | |
850 | .rac (interr_stat_auto_clr), | |
851 | .ck (clk), | |
852 | .qo (ipp_dfifo_dout1_ecc_sti[16]) | |
853 | ); | |
854 | ||
855 | wire [3:0] ecc_inp_15_11 = (ld_status ? wr_data[27:24] : ipp_dfifo_dout1_ecc[4:1]); | |
856 | ||
857 | ipp_reg_w_sti_r_rac_5 reg_w_sti_r_rac_5_ecc_err ( | |
858 | .di ({ecc_inp_15_11,1'h0}), | |
859 | .wr (ld_status || wt_ecc_status), | |
860 | .rs (reset), | |
861 | .rac (interr_stat_auto_clr), | |
862 | .ck (clk), | |
863 | .qo (ipp_dfifo_dout1_ecc_sti[15:11]) | |
864 | ); | |
865 | ||
866 | ipp_reg_w_sti_r_rac_11 reg_w_sti_r_rac_11_ecc_adr ( | |
867 | .di (ld_status ? wr_data[22:12] : ipp_dfifo_dout1_ecc[17:7]), | |
868 | .wr (ld_status || wt_ecc_status), | |
869 | .rs (reset), | |
870 | .rac (interr_stat_auto_clr), | |
871 | .ck (clk), | |
872 | .qo (ipp_dfifo_dout1_ecc_sti[10:0]) | |
873 | ); | |
874 | ||
875 | // ParityErrorOc bit; bit 11 | |
876 | ipp_RAC_FF RAC_FF_parity_err(.clk(clk), .reset(reset), | |
877 | .set(par_err), .rst(interr_stat_auto_clr), | |
878 | .load(ld_status), .load_data(wr_data[11]), | |
879 | .dout(par_err_oc)); | |
880 | ||
881 | // Head_fifo_parity_addr[5:0] bit; bit [9:4] | |
882 | ipp_reg_w_sti_r_rac_6 reg_w_sti_r_rac_6_par_adr ( | |
883 | .di (ld_status ? wr_data[9:4] : ipp_hfifo_par_addr[5:0]), | |
884 | .wr (ld_status || par_err), | |
885 | .rs (reset), | |
886 | .rac (interr_stat_auto_clr), | |
887 | .ck (clk), | |
888 | .qo (hfifo_par_addr_oc[5:0]) | |
889 | ); | |
890 | ||
891 | // IPP fifoOverRunOc bit; bit 3 | |
892 | ipp_RAC_FF RAC_FF_fifo_over_run(.clk(clk), .reset(reset), | |
893 | .set(fifo_over_run), .rst(interr_stat_auto_clr), | |
894 | .load(ld_status), .load_data(wr_data[3]), | |
895 | .dout(fifo_over_run_oc)); | |
896 | ||
897 | // IPP fifoUnderRunOc bit; bit 2 | |
898 | ipp_RAC_FF RAC_FF_fifo_under_run(.clk(clk), .reset(reset), | |
899 | .set(fifo_under_run), .rst(interr_stat_auto_clr), | |
900 | .load(ld_status), .load_data(wr_data[2]), | |
901 | .dout(fifo_under_run_oc)); | |
902 | ||
903 | // synopsys translate_off | |
904 | ||
905 | // For diagnostic purpose | |
906 | always @ (reset or fifo_over_run_oc) | |
907 | if (!reset && fifo_over_run_oc) | |
908 | $display("Warning at sim time = %d, ipp fifo over run occurred.", $stime); | |
909 | else ; | |
910 | ||
911 | // For diagnostic purpose | |
912 | always @ (reset or fifo_under_run_oc) | |
913 | if (!reset && fifo_under_run_oc) | |
914 | $display("Warning at sim time = %d, ipp fifo under run occurred.", $stime); | |
915 | else ; | |
916 | // synopsys translate_on | |
917 | ||
918 | // ****** Interrupt Mask Register: 8 bits ******/ | |
919 | always @ (posedge clk) | |
920 | if (reset) | |
921 | interr_mask_reg[7:0] <= 8'b1111_1111; // reset to all "1" | |
922 | else if (interr_mask_wr_en) | |
923 | interr_mask_reg[7:0] <= wr_data[7:0]; | |
924 | else interr_mask_reg[7:0] <= interr_mask_reg[7:0]; | |
925 | ||
926 | // ****** fifo_wr_data_register0: 32 bits (R/W) ******/ | |
927 | ipp_xREG #(32) xREG_fifo_wr_data_register0(.clk(clk), .reset(reset), | |
928 | .en(fifo_wr_data_reg0_wr_en), | |
929 | .din(wr_data[31:0]), | |
930 | .qout(fifo_wr_data_reg[31:0])); | |
931 | ||
932 | // ****** fifo_wr_data_register1: 32 bits (R/W) ******/ | |
933 | ipp_xREG #(32) xREG_fifo_wr_data_register1(.clk(clk), .reset(reset), | |
934 | .en(fifo_wr_data_reg1_wr_en), | |
935 | .din(wr_data[31:0]), | |
936 | .qout(fifo_wr_data_reg[63:32])); | |
937 | ||
938 | // ****** fifo_wr_data_register2: 32 bits (R/W) ******/ | |
939 | ipp_xREG #(32) xREG_fifo_wr_data_register2(.clk(clk), .reset(reset), | |
940 | .en(fifo_wr_data_reg2_wr_en), | |
941 | .din(wr_data[31:0]), | |
942 | .qout(fifo_wr_data_reg[95:64])); | |
943 | ||
944 | // ****** fifo_wr_data_register3: 32 bits (R/W) ******/ | |
945 | ipp_xREG #(32) xREG_fifo_wr_data_register3(.clk(clk), .reset(reset), | |
946 | .en(fifo_wr_data_reg3_wr_en), | |
947 | .din(wr_data[31:0]), | |
948 | .qout(fifo_wr_data_reg[127:96])); | |
949 | ||
950 | // ****** fifo_wr_data_register4: 2 bits (R/W) ******/ | |
951 | ipp_xREG #(2) xREG_fifo_wr_data_register4(.clk(clk), .reset(reset), | |
952 | .en(fifo_wr_data_reg4_wr_en), | |
953 | .din(wr_data[1:0]), | |
954 | .qout(fifo_wr_data_reg[129:128])); | |
955 | ||
956 | // fifo_wr_data_reg write enable | |
957 | ipp_falling_edge_puls_gen falling_edge_puls_gen_fifo_wr_data_reg_wr_en_pls( | |
958 | .reset(reset), .clk(clk), | |
959 | .signal_in(fifo_wr_data_reg_wr_en), | |
960 | .puls_out(fifo_wr_data_reg_wr_en_pls)); | |
961 | ||
962 | // dfifo_wt_data_reg write enable | |
963 | ipp_falling_edge_puls_gen falling_edge_puls_gen_dfifo_wt_data_reg_wr_en_pls( | |
964 | .reset (reset), | |
965 | .clk (clk), | |
966 | .signal_in (dfifo_wt_data_reg_wr_en && datfifo_pio_wr_ena), | |
967 | .puls_out (dfifo_wt_data_reg_wr_en_pls)); | |
968 | ||
969 | // ****** debug register ******/ | |
970 | ipp_xREG #(4) debug_reg_xREG(.clk(clk), .reset(reset), | |
971 | .en(debug_wr_en), | |
972 | .din(wr_data[3:0]), | |
973 | .qout(debug_reg[3:0])); | |
974 | ||
975 | reg [31:0] debug_din; | |
976 | wire [3:0] ipp_debug_sel = debug_reg[3:0]; | |
977 | wire [31:0] debug_bus0; | |
978 | wire [31:0] debug_bus1; | |
979 | wire [31:0] debug_bus2; | |
980 | wire [31:0] debug_bus3; | |
981 | wire [31:0] debug_bus4; | |
982 | wire [31:0] debug_bus5; | |
983 | wire [31:0] debug_bus6; | |
984 | wire [31:0] debug_bus7; | |
985 | wire [31:0] debug_bus8; | |
986 | ||
987 | wire [1:0] xface_arb = {ffl_arb_ack,ipp_ffl_req}; | |
988 | wire [12:0] xface_to_ffl = {ipp_ffl_dvalid,ipp_ffl_mac_default[11:0]}; | |
989 | wire [15:0] xface_fr_ffl = {ffl_ipp_ready,ffl_ipp_dvalid,ffl_ipp_data[13:0]}; | |
990 | wire [31:0] xface_ffl_bus = {xface_arb[1:0],1'h0,xface_to_ffl[12:0],xface_fr_ffl[15:0]}; | |
991 | ||
992 | assign debug_bus0 = {state_mach2[1:0], 1'b0, | |
993 | state_mach10[0], state_mach9[3:0], state_mach8[3:0], | |
994 | state_mach7[1:0], state_mach6[1:0], | |
995 | state_mach5[3:0], | |
996 | state_mach1[3:0], | |
997 | state_mach0[2:0], | |
998 | state_mach4[0], state_mach3[3:0]}; | |
999 | ||
1000 | assign debug_bus1 = {3'b0, mac_ipp_req, ipp_mac_ack, mac_ipp_ctrl, | |
1001 | xmac_ipp_ack, ipp_xmac_req, mac_ipp_tag, | |
1002 | mac_ipp_stat[22:0]}; | |
1003 | ||
1004 | assign debug_bus2 = {mac_ipp_data[63:32]}; | |
1005 | assign debug_bus3 = {mac_ipp_data[31:0]}; | |
1006 | ||
1007 | assign debug_bus4 = xface_ffl_bus[31:0]; | |
1008 | ||
1009 | assign debug_bus5 = {fifo_data_out_reg[031:00]}; | |
1010 | assign debug_bus6 = {fifo_data_out_reg[063:32]}; | |
1011 | assign debug_bus7 = {fifo_data_out_reg[095:64]}; | |
1012 | assign debug_bus8 = {fifo_data_out_reg[127:96]}; | |
1013 | ||
1014 | always @ ( ipp_debug_sel or debug_bus0 or debug_bus1 or debug_bus2 or | |
1015 | debug_bus3 or debug_bus4 or debug_bus5 or debug_bus6 or debug_bus7 or debug_bus8) | |
1016 | ||
1017 | casex (ipp_debug_sel) // synopsys parallel_case full_case | |
1018 | 4'd0: debug_din = debug_bus0; | |
1019 | 4'd1: debug_din = debug_bus1; | |
1020 | 4'd2: debug_din = debug_bus2; | |
1021 | 4'd3: debug_din = debug_bus3; | |
1022 | 4'd4: debug_din = debug_bus4; | |
1023 | 4'd5: debug_din = debug_bus5; | |
1024 | 4'd6: debug_din = debug_bus6; | |
1025 | 4'd7: debug_din = debug_bus7; | |
1026 | 4'd8: debug_din = debug_bus8; | |
1027 | default: debug_din = debug_bus0; | |
1028 | endcase // casex(ipp_debug_sel) | |
1029 | ||
1030 | ipp_RegDff #(32) ipp_debug_RegDff(.din(debug_din[31:0]), .clk(clk), | |
1031 | .qout(ipp_debug[31:0])); | |
1032 | ||
1033 | ipp_reg_r_12 reg_r_12_dfi_rpt ( | |
1034 | .di (ipp_dfifo_rptr[11:0]), | |
1035 | .rs (reset), | |
1036 | .ck (clk), | |
1037 | .qo (ipp_dfifo_rptr_d[11:0]) | |
1038 | ); | |
1039 | ||
1040 | ipp_reg_w_sti_r_rac_16 reg_w_sti_r_rac_16_ecc_syn ( | |
1041 | .di (ipp_dfifo_dout1_ecc_syn[15:0]), | |
1042 | .wr (wt_ecc_status), | |
1043 | .rs (reset), | |
1044 | .rac (rac_ecc_syndrome), | |
1045 | .ck (clk), | |
1046 | .qo (ipp_dfifo_dout1_ecc_syn_sti[15:0]) | |
1047 | ); | |
1048 | ||
1049 | assign n_ipp_ecc_corrupt_reg[31] = wr_data[31]; | |
1050 | assign n_ipp_ecc_corrupt_reg[30:18] = 13'h0; | |
1051 | assign n_ipp_ecc_corrupt_reg[17:16] = wr_data[17:16]; | |
1052 | assign n_ipp_ecc_corrupt_reg[15:11] = 5'h0; | |
1053 | assign n_ipp_ecc_corrupt_reg[10] = wr_data[10]; | |
1054 | assign n_ipp_ecc_corrupt_reg[9] = 1'h0; | |
1055 | assign n_ipp_ecc_corrupt_reg[8] = wr_data[8]; | |
1056 | assign n_ipp_ecc_corrupt_reg[7:3] = 5'h0; | |
1057 | assign n_ipp_ecc_corrupt_reg[2:0] = wr_data[2:0]; | |
1058 | ||
1059 | ipp_reg_w_r_32 reg_w_r_32_ecc_corrupt ( | |
1060 | .di (n_ipp_ecc_corrupt_reg[31:0]), | |
1061 | .wr (wt_ecc_corrupt_reg), | |
1062 | .rs (reset), | |
1063 | .ck (clk), | |
1064 | .qo (ipp_ecc_corrupt_reg[31:0]) | |
1065 | ); | |
1066 | ||
1067 | ipp_reg_w_sti_r_rac_12 reg_w_sti_r_rac_12_tag_rpt ( | |
1068 | .di (wt_dfifo_rptr ? wr_data[11:0] : ipp_dfifo_rptr_d[11:0]), | |
1069 | .wr (wt_dfifo_rptr || dfifo_miss_tag), | |
1070 | .rs (reset), | |
1071 | .rac (rac_dfifo_rptr), | |
1072 | .ck (clk), | |
1073 | .qo (ipp_dfifo_rptr_sti[11:0]) | |
1074 | ); | |
1075 | ||
1076 | ipp_reg_r_11 reg_r_11_ecc_rptr ( | |
1077 | .di (ipp_dfifo_rptr1[10:0]), | |
1078 | .rs (reset), | |
1079 | .ck (clk), | |
1080 | .qo (ipp_dfifo_rptr1_d[10:0]) | |
1081 | ); | |
1082 | ||
1083 | ipp_reg_r_1 reg_r_1_ecc_no_err ( | |
1084 | .di (ecc_no_error), | |
1085 | .rs (reset), | |
1086 | .ck (clk), | |
1087 | .qo (ecc_no_error_d) | |
1088 | ); | |
1089 | ||
1090 | ipp_reg_r_1 reg_r_1_uncorr_error1_found( | |
1091 | .di (uncorr_error1_found), | |
1092 | .rs (reset), | |
1093 | .ck (clk), | |
1094 | .qo (uncorr_error1_found_d) | |
1095 | ); | |
1096 | ||
1097 | `ifdef NEPTUNE | |
1098 | wire [3:0] do_nad; | |
1099 | wire [3:0] do_nor; | |
1100 | wire [3:0] do_inv; | |
1101 | wire [3:0] do_mux; | |
1102 | wire [3:0] do_q; | |
1103 | wire so; | |
1104 | ||
1105 | nep_spare_ipp spare_ipp_0 ( | |
1106 | .di_nd3 ({1'h1, 1'h1, do_q[3]}), | |
1107 | .di_nd2 ({1'h1, 1'h1, do_q[2]}), | |
1108 | .di_nd1 ({1'h1, 1'h1, do_q[1]}), | |
1109 | .di_nd0 ({1'h1, 1'h1, do_q[0]}), | |
1110 | .di_nr3 ({1'h0, 1'h0}), | |
1111 | .di_nr2 ({1'h0, 1'h0}), | |
1112 | .di_nr1 ({1'h0, 1'h0}), | |
1113 | .di_nr0 ({1'h0, 1'h0}), | |
1114 | .di_inv (do_nad[3:0]), | |
1115 | .di_mx3 ({1'h0, 1'h0}), | |
1116 | .di_mx2 ({1'h0, 1'h0}), | |
1117 | .di_mx1 ({1'h0, 1'h0}), | |
1118 | .di_mx0 ({1'h0, 1'h0}), | |
1119 | .mx_sel (do_nor[3:0]), | |
1120 | .di_reg (do_inv[3:0]), | |
1121 | .wt_ena (do_mux[3:0]), | |
1122 | .rst ({reset,reset,reset,reset}), | |
1123 | .si (1'h0), | |
1124 | .se (1'h0), | |
1125 | .clk (clk), | |
1126 | .do_nad (do_nad[3:0]), | |
1127 | .do_nor (do_nor[3:0]), | |
1128 | .do_inv (do_inv[3:0]), | |
1129 | .do_mux (do_mux[3:0]), | |
1130 | .do_q (do_q[3:0]), | |
1131 | .so (so) | |
1132 | ); | |
1133 | `endif | |
1134 | ||
1135 | endmodule | |
1136 |