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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_mac.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // ########################################################## | |
36 | // # File Name : niu_mac.v | |
37 | // # Author Name : John Lo | |
38 | // # Description : It contains mac_2ports and phy_clock_2ports. | |
39 | // # It is for N2. | |
40 | // # | |
41 | // # Parent Module: | |
42 | // # Child Module: | |
43 | // # Interface Mod: | |
44 | // # Date Created : 7/26/04 | |
45 | // # | |
46 | // # Copyright (c) 2020, Sun Microsystems, Inc. | |
47 | // # Sun Proprietary and Confidential | |
48 | // ########################################################## | |
49 | ||
50 | ||
51 | module niu_mac | |
52 | (/*AUTOARG*/ | |
53 | // Outputs | |
54 | scan_out, mif_pio_intr, mdo, mdc, mac_txc_req1, mac_txc_req0, | |
55 | mac_rxc_tag1, mac_rxc_tag0, mac_rxc_stat1, mac_rxc_stat0, | |
56 | mac_rxc_data1, mac_rxc_data0, mac_rxc_ctrl1, mac_rxc_ctrl0, | |
57 | mac_rxc_ack1, mac_rxc_ack0, mac_pio_rdata, mac_pio_intr1, | |
58 | mac_pio_intr0, mac_pio_err, mac_pio_ack, mac_esr_txd3_1, | |
59 | mac_esr_txd3_0, mac_esr_txd2_1, mac_esr_txd2_0, mac_esr_txd1_1, | |
60 | mac_esr_txd1_0, mac_esr_txd0_1, mac_esr_txd0_0, mac_esr_tclk_1, | |
61 | mac_esr_tclk_0, mac_debug_port, XAUI_MDIO, XAUI_MDC, | |
62 | XAUI_LINK_LED_1, XAUI_LINK_LED_0, XAUI_ACT_LED_1, XAUI_ACT_LED_0, | |
63 | // Inputs | |
64 | txc_mac_tag1, txc_mac_tag0, txc_mac_stat1, txc_mac_stat0, | |
65 | txc_mac_data1, txc_mac_data0, txc_mac_ack1, txc_mac_ack0, | |
66 | txc_mac_abort1, txc_mac_abort0, tcu_scan_mode, tcu_scan_en, | |
67 | tcu_pce_ov, tcu_clk_stop, tcu_bclk, tcu_aclk, scan_in, | |
68 | rxc_mac_req1, rxc_mac_req0, reset, pio_mac_sel, pio_clients_wdata, | |
69 | pio_clients_rd, pio_clients_addr, mdi_1, mdi_0, mdi, mac_reset1, | |
70 | mac_reset0, mac_312tx_test_clk, mac_312rx_test_clk, | |
71 | mac_156tx_test_clk, mac_156rx_test_clk, mac_125tx_test_clk, | |
72 | mac_125rx_test_clk, esr_mac_tclk_1, esr_mac_tclk_0, | |
73 | esr_mac_sync_1, esr_mac_sync_0, esr_mac_rxd3_1, esr_mac_rxd3_0, | |
74 | esr_mac_rxd2_1, esr_mac_rxd2_0, esr_mac_rxd1_1, esr_mac_rxd1_0, | |
75 | esr_mac_rxd0_1, esr_mac_rxd0_0, esr_mac_rclk_1, esr_mac_rclk_0, | |
76 | esr_mac_oddcg1_1, esr_mac_oddcg1_0, esr_mac_los_1, esr_mac_los_0, | |
77 | clk | |
78 | ); | |
79 | ||
80 | /*AUTOINPUT*/ | |
81 | // Beginning of automatic inputs (from unused autoinst inputs) | |
82 | input clk; // To mac_2ports of mac_2ports.v | |
83 | input [3:0] esr_mac_los_0; // To mac_2ports of mac_2ports.v | |
84 | input [3:0] esr_mac_los_1; // To mac_2ports of mac_2ports.v | |
85 | input esr_mac_oddcg1_0; // To mac_2ports of mac_2ports.v | |
86 | input esr_mac_oddcg1_1; // To mac_2ports of mac_2ports.v | |
87 | input [3:0] esr_mac_rclk_0; // To phy_clock_2ports of phy_clock_2ports.v | |
88 | input [3:0] esr_mac_rclk_1; // To phy_clock_2ports of phy_clock_2ports.v | |
89 | input [9:0] esr_mac_rxd0_0; // To mac_2ports of mac_2ports.v | |
90 | input [9:0] esr_mac_rxd0_1; // To mac_2ports of mac_2ports.v | |
91 | input [9:0] esr_mac_rxd1_0; // To mac_2ports of mac_2ports.v | |
92 | input [9:0] esr_mac_rxd1_1; // To mac_2ports of mac_2ports.v | |
93 | input [9:0] esr_mac_rxd2_0; // To mac_2ports of mac_2ports.v | |
94 | input [9:0] esr_mac_rxd2_1; // To mac_2ports of mac_2ports.v | |
95 | input [9:0] esr_mac_rxd3_0; // To mac_2ports of mac_2ports.v | |
96 | input [9:0] esr_mac_rxd3_1; // To mac_2ports of mac_2ports.v | |
97 | input [3:0] esr_mac_sync_0; // To mac_2ports of mac_2ports.v | |
98 | input [3:0] esr_mac_sync_1; // To mac_2ports of mac_2ports.v | |
99 | input esr_mac_tclk_0; // To phy_clock_2ports of phy_clock_2ports.v | |
100 | input esr_mac_tclk_1; // To phy_clock_2ports of phy_clock_2ports.v | |
101 | input mac_125rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
102 | input mac_125tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
103 | input mac_156rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
104 | input mac_156tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
105 | input mac_312rx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
106 | input mac_312tx_test_clk; // To phy_clock_2ports of phy_clock_2ports.v | |
107 | input mac_reset0; // To mac_2ports of mac_2ports.v | |
108 | input mac_reset1; // To mac_2ports of mac_2ports.v | |
109 | input mdi; // To mac_2ports of mac_2ports.v | |
110 | input mdi_0; // To mac_2ports of mac_2ports.v | |
111 | input mdi_1; // To mac_2ports of mac_2ports.v | |
112 | input [19:0] pio_clients_addr; // To mac_2ports of mac_2ports.v | |
113 | input pio_clients_rd; // To mac_2ports of mac_2ports.v | |
114 | input [31:0] pio_clients_wdata; // To mac_2ports of mac_2ports.v | |
115 | input pio_mac_sel; // To mac_2ports of mac_2ports.v | |
116 | input reset; // To mac_2ports of mac_2ports.v, ... | |
117 | input rxc_mac_req0; // To mac_2ports of mac_2ports.v | |
118 | input rxc_mac_req1; // To mac_2ports of mac_2ports.v | |
119 | input scan_in; // To dummy_mac_dft of dummy_mac_dft.v | |
120 | input tcu_aclk; // To dummy_mac_dft of dummy_mac_dft.v | |
121 | input tcu_bclk; // To dummy_mac_dft of dummy_mac_dft.v | |
122 | input tcu_clk_stop; // To dummy_mac_dft of dummy_mac_dft.v | |
123 | input tcu_pce_ov; // To dummy_mac_dft of dummy_mac_dft.v | |
124 | input tcu_scan_en; // To dummy_mac_dft of dummy_mac_dft.v | |
125 | input tcu_scan_mode; // To phy_clock_2ports of phy_clock_2ports.v | |
126 | input txc_mac_abort0; // To mac_2ports of mac_2ports.v | |
127 | input txc_mac_abort1; // To mac_2ports of mac_2ports.v | |
128 | input txc_mac_ack0; // To mac_2ports of mac_2ports.v | |
129 | input txc_mac_ack1; // To mac_2ports of mac_2ports.v | |
130 | input [63:0] txc_mac_data0; // To mac_2ports of mac_2ports.v | |
131 | input [63:0] txc_mac_data1; // To mac_2ports of mac_2ports.v | |
132 | input [3:0] txc_mac_stat0; // To mac_2ports of mac_2ports.v | |
133 | input [3:0] txc_mac_stat1; // To mac_2ports of mac_2ports.v | |
134 | input txc_mac_tag0; // To mac_2ports of mac_2ports.v | |
135 | input txc_mac_tag1; // To mac_2ports of mac_2ports.v | |
136 | // End of automatics | |
137 | ||
138 | /*AUTOOUTPUT*/ | |
139 | // Beginning of automatic outputs (from unused autoinst outputs) | |
140 | output XAUI_ACT_LED_0; // From mac_2ports of mac_2ports.v | |
141 | output XAUI_ACT_LED_1; // From mac_2ports of mac_2ports.v | |
142 | output XAUI_LINK_LED_0; // From mac_2ports of mac_2ports.v | |
143 | output XAUI_LINK_LED_1; // From mac_2ports of mac_2ports.v | |
144 | output XAUI_MDC; // From mac_2ports of mac_2ports.v | |
145 | output XAUI_MDIO; // From mac_2ports of mac_2ports.v | |
146 | output [31:0] mac_debug_port; // From mac_2ports of mac_2ports.v | |
147 | output mac_esr_tclk_0; // From mac_2ports of mac_2ports.v | |
148 | output mac_esr_tclk_1; // From mac_2ports of mac_2ports.v | |
149 | output [9:0] mac_esr_txd0_0; // From mac_2ports of mac_2ports.v | |
150 | output [9:0] mac_esr_txd0_1; // From mac_2ports of mac_2ports.v | |
151 | output [9:0] mac_esr_txd1_0; // From mac_2ports of mac_2ports.v | |
152 | output [9:0] mac_esr_txd1_1; // From mac_2ports of mac_2ports.v | |
153 | output [9:0] mac_esr_txd2_0; // From mac_2ports of mac_2ports.v | |
154 | output [9:0] mac_esr_txd2_1; // From mac_2ports of mac_2ports.v | |
155 | output [9:0] mac_esr_txd3_0; // From mac_2ports of mac_2ports.v | |
156 | output [9:0] mac_esr_txd3_1; // From mac_2ports of mac_2ports.v | |
157 | output mac_pio_ack; // From mac_2ports of mac_2ports.v | |
158 | output mac_pio_err; // From mac_2ports of mac_2ports.v | |
159 | output mac_pio_intr0; // From mac_2ports of mac_2ports.v | |
160 | output mac_pio_intr1; // From mac_2ports of mac_2ports.v | |
161 | output [63:0] mac_pio_rdata; // From mac_2ports of mac_2ports.v | |
162 | output mac_rxc_ack0; // From mac_2ports of mac_2ports.v | |
163 | output mac_rxc_ack1; // From mac_2ports of mac_2ports.v | |
164 | output mac_rxc_ctrl0; // From mac_2ports of mac_2ports.v | |
165 | output mac_rxc_ctrl1; // From mac_2ports of mac_2ports.v | |
166 | output [63:0] mac_rxc_data0; // From mac_2ports of mac_2ports.v | |
167 | output [63:0] mac_rxc_data1; // From mac_2ports of mac_2ports.v | |
168 | output [22:0] mac_rxc_stat0; // From mac_2ports of mac_2ports.v | |
169 | output [22:0] mac_rxc_stat1; // From mac_2ports of mac_2ports.v | |
170 | output mac_rxc_tag0; // From mac_2ports of mac_2ports.v | |
171 | output mac_rxc_tag1; // From mac_2ports of mac_2ports.v | |
172 | output mac_txc_req0; // From mac_2ports of mac_2ports.v | |
173 | output mac_txc_req1; // From mac_2ports of mac_2ports.v | |
174 | output mdc; // From mac_2ports of mac_2ports.v | |
175 | output mdo; // From mac_2ports of mac_2ports.v | |
176 | output mif_pio_intr; // From mac_2ports of mac_2ports.v | |
177 | output scan_out; // From dummy_mac_dft of dummy_mac_dft.v | |
178 | // End of automatics | |
179 | ||
180 | /*AUTOWIRE*/ | |
181 | // Beginning of automatic wires (for undeclared instantiated-module outputs) | |
182 | wire tx_clk_312mhz_muxd0; // From phy_clock_2ports of phy_clock_2ports.v | |
183 | wire tx_clk_312mhz_muxd1; // From phy_clock_2ports of phy_clock_2ports.v | |
184 | // End of automatics | |
185 | wire gmii_mode0; | |
186 | wire gmii_mode1; | |
187 | wire loopback0; | |
188 | wire loopback1; | |
189 | wire mii_mode0; | |
190 | wire mii_mode1; | |
191 | wire pcs_bypass0; | |
192 | wire pcs_bypass1; | |
193 | wire rbc0_a_muxd0; | |
194 | wire rbc0_a_muxd1; | |
195 | wire rbc0_b_muxd0; | |
196 | wire rbc0_b_muxd1; | |
197 | wire rbc0_c_muxd0; | |
198 | wire rbc0_c_muxd1; | |
199 | wire rbc0_d_muxd0; | |
200 | wire rbc0_d_muxd1; | |
201 | wire rx_clk_muxd0; | |
202 | wire rx_clk_muxd1; | |
203 | wire [3:0] rx_heart_beat_timer0; | |
204 | wire [3:0] rx_heart_beat_timer1; | |
205 | wire rx_nbclk_muxd0; | |
206 | wire rx_nbclk_muxd1; | |
207 | wire sel_clk_25mhz0; | |
208 | wire sel_clk_25mhz1; | |
209 | wire tx_clk_muxd0; | |
210 | wire tx_clk_muxd1; | |
211 | wire [3:0] tx_heart_beat_timer0; | |
212 | wire [3:0] tx_heart_beat_timer1; | |
213 | wire tx_nbclk_muxd0; | |
214 | wire tx_nbclk_muxd1; | |
215 | wire xpcs_bypass0; | |
216 | wire xpcs_bypass1; | |
217 | wire xpcs_loopback0; | |
218 | wire xpcs_loopback1; | |
219 | ||
220 | mac_2ports mac_2ports | |
221 | (/*AUTOINST*/ | |
222 | // Outputs | |
223 | .mac_debug_port (mac_debug_port[31:0]), | |
224 | .mac_pio_ack (mac_pio_ack), | |
225 | .mac_pio_rdata (mac_pio_rdata[63:0]), | |
226 | .mac_pio_err (mac_pio_err), | |
227 | .mac_pio_intr0 (mac_pio_intr0), | |
228 | .mac_pio_intr1 (mac_pio_intr1), | |
229 | .mac_esr_tclk_0 (mac_esr_tclk_0), | |
230 | .tx_heart_beat_timer0 (tx_heart_beat_timer0[3:0]), | |
231 | .rx_heart_beat_timer0 (rx_heart_beat_timer0[3:0]), | |
232 | .mac_txc_req0 (mac_txc_req0), | |
233 | .mac_rxc_ack0 (mac_rxc_ack0), | |
234 | .mac_rxc_tag0 (mac_rxc_tag0), | |
235 | .mac_rxc_data0 (mac_rxc_data0[63:0]), | |
236 | .mac_rxc_ctrl0 (mac_rxc_ctrl0), | |
237 | .mac_rxc_stat0 (mac_rxc_stat0[22:0]), | |
238 | .mdc (mdc), | |
239 | .mdo (mdo), | |
240 | .XAUI_MDC (XAUI_MDC), | |
241 | .XAUI_MDIO (XAUI_MDIO), | |
242 | .loopback0 (loopback0), | |
243 | .sel_clk_25mhz0 (sel_clk_25mhz0), | |
244 | .mii_mode0 (mii_mode0), | |
245 | .gmii_mode0 (gmii_mode0), | |
246 | .pcs_bypass0 (pcs_bypass0), | |
247 | .xpcs_bypass0 (xpcs_bypass0), | |
248 | .xpcs_loopback0 (xpcs_loopback0), | |
249 | .XAUI_ACT_LED_0 (XAUI_ACT_LED_0), | |
250 | .XAUI_LINK_LED_0 (XAUI_LINK_LED_0), | |
251 | .mac_esr_tclk_1 (mac_esr_tclk_1), | |
252 | .tx_heart_beat_timer1 (tx_heart_beat_timer1[3:0]), | |
253 | .rx_heart_beat_timer1 (rx_heart_beat_timer1[3:0]), | |
254 | .mac_txc_req1 (mac_txc_req1), | |
255 | .mac_rxc_ack1 (mac_rxc_ack1), | |
256 | .mac_rxc_tag1 (mac_rxc_tag1), | |
257 | .mac_rxc_data1 (mac_rxc_data1[63:0]), | |
258 | .mac_rxc_ctrl1 (mac_rxc_ctrl1), | |
259 | .mac_rxc_stat1 (mac_rxc_stat1[22:0]), | |
260 | .loopback1 (loopback1), | |
261 | .sel_clk_25mhz1 (sel_clk_25mhz1), | |
262 | .mii_mode1 (mii_mode1), | |
263 | .gmii_mode1 (gmii_mode1), | |
264 | .pcs_bypass1 (pcs_bypass1), | |
265 | .xpcs_bypass1 (xpcs_bypass1), | |
266 | .xpcs_loopback1 (xpcs_loopback1), | |
267 | .XAUI_ACT_LED_1 (XAUI_ACT_LED_1), | |
268 | .XAUI_LINK_LED_1 (XAUI_LINK_LED_1), | |
269 | .mac_esr_txd0_0 (mac_esr_txd0_0[9:0]), | |
270 | .mac_esr_txd1_0 (mac_esr_txd1_0[9:0]), | |
271 | .mac_esr_txd2_0 (mac_esr_txd2_0[9:0]), | |
272 | .mac_esr_txd3_0 (mac_esr_txd3_0[9:0]), | |
273 | .mac_esr_txd0_1 (mac_esr_txd0_1[9:0]), | |
274 | .mac_esr_txd1_1 (mac_esr_txd1_1[9:0]), | |
275 | .mac_esr_txd2_1 (mac_esr_txd2_1[9:0]), | |
276 | .mac_esr_txd3_1 (mac_esr_txd3_1[9:0]), | |
277 | .mif_pio_intr (mif_pio_intr), | |
278 | // Inputs | |
279 | .clk (clk), | |
280 | .reset (reset), | |
281 | .pio_clients_addr (pio_clients_addr[19:0]), | |
282 | .pio_clients_rd (pio_clients_rd), | |
283 | .pio_clients_wdata (pio_clients_wdata[31:0]), | |
284 | .pio_mac_sel (pio_mac_sel), | |
285 | .mac_reset0 (mac_reset0), | |
286 | .mac_reset1 (mac_reset1), | |
287 | .tx_clk_muxd0 (tx_clk_muxd0), | |
288 | .tx_nbclk_muxd0 (tx_nbclk_muxd0), | |
289 | .tx_clk_312mhz_muxd0 (tx_clk_312mhz_muxd0), | |
290 | .rx_clk_muxd0 (rx_clk_muxd0), | |
291 | .rx_nbclk_muxd0 (rx_nbclk_muxd0), | |
292 | .txc_mac_ack0 (txc_mac_ack0), | |
293 | .txc_mac_tag0 (txc_mac_tag0), | |
294 | .txc_mac_data0 (txc_mac_data0[63:0]), | |
295 | .txc_mac_stat0 (txc_mac_stat0[3:0]), | |
296 | .txc_mac_abort0 (txc_mac_abort0), | |
297 | .rxc_mac_req0 (rxc_mac_req0), | |
298 | .mdi (mdi), | |
299 | .mdi_0 (mdi_0), | |
300 | .mdi_1 (mdi_1), | |
301 | .rbc0_a_muxd0 (rbc0_a_muxd0), | |
302 | .rbc0_b_muxd0 (rbc0_b_muxd0), | |
303 | .rbc0_c_muxd0 (rbc0_c_muxd0), | |
304 | .rbc0_d_muxd0 (rbc0_d_muxd0), | |
305 | .tx_clk_muxd1 (tx_clk_muxd1), | |
306 | .tx_nbclk_muxd1 (tx_nbclk_muxd1), | |
307 | .tx_clk_312mhz_muxd1 (tx_clk_312mhz_muxd1), | |
308 | .rx_clk_muxd1 (rx_clk_muxd1), | |
309 | .rx_nbclk_muxd1 (rx_nbclk_muxd1), | |
310 | .txc_mac_ack1 (txc_mac_ack1), | |
311 | .txc_mac_tag1 (txc_mac_tag1), | |
312 | .txc_mac_data1 (txc_mac_data1[63:0]), | |
313 | .txc_mac_stat1 (txc_mac_stat1[3:0]), | |
314 | .txc_mac_abort1 (txc_mac_abort1), | |
315 | .rxc_mac_req1 (rxc_mac_req1), | |
316 | .rbc0_a_muxd1 (rbc0_a_muxd1), | |
317 | .rbc0_b_muxd1 (rbc0_b_muxd1), | |
318 | .rbc0_c_muxd1 (rbc0_c_muxd1), | |
319 | .rbc0_d_muxd1 (rbc0_d_muxd1), | |
320 | .esr_mac_rxd0_0 (esr_mac_rxd0_0[9:0]), | |
321 | .esr_mac_rxd1_0 (esr_mac_rxd1_0[9:0]), | |
322 | .esr_mac_rxd2_0 (esr_mac_rxd2_0[9:0]), | |
323 | .esr_mac_rxd3_0 (esr_mac_rxd3_0[9:0]), | |
324 | .esr_mac_sync_0 (esr_mac_sync_0[3:0]), | |
325 | .esr_mac_los_0 (esr_mac_los_0[3:0]), | |
326 | .esr_mac_oddcg1_0 (esr_mac_oddcg1_0), | |
327 | .esr_mac_rxd0_1 (esr_mac_rxd0_1[9:0]), | |
328 | .esr_mac_rxd1_1 (esr_mac_rxd1_1[9:0]), | |
329 | .esr_mac_rxd2_1 (esr_mac_rxd2_1[9:0]), | |
330 | .esr_mac_rxd3_1 (esr_mac_rxd3_1[9:0]), | |
331 | .esr_mac_sync_1 (esr_mac_sync_1[3:0]), | |
332 | .esr_mac_los_1 (esr_mac_los_1[3:0]), | |
333 | .esr_mac_oddcg1_1 (esr_mac_oddcg1_1)); | |
334 | ||
335 | ||
336 | phy_clock_2ports phy_clock_2ports | |
337 | (/*AUTOINST*/ | |
338 | // Outputs | |
339 | .tx_nbclk_muxd0 (tx_nbclk_muxd0), | |
340 | .tx_clk_muxd0 (tx_clk_muxd0), | |
341 | .tx_clk_312mhz_muxd0 (tx_clk_312mhz_muxd0), | |
342 | .rx_nbclk_muxd0 (rx_nbclk_muxd0), | |
343 | .rx_clk_muxd0 (rx_clk_muxd0), | |
344 | .rbc0_a_muxd0 (rbc0_a_muxd0), | |
345 | .rbc0_b_muxd0 (rbc0_b_muxd0), | |
346 | .rbc0_c_muxd0 (rbc0_c_muxd0), | |
347 | .rbc0_d_muxd0 (rbc0_d_muxd0), | |
348 | .tx_nbclk_muxd1 (tx_nbclk_muxd1), | |
349 | .tx_clk_muxd1 (tx_clk_muxd1), | |
350 | .tx_clk_312mhz_muxd1 (tx_clk_312mhz_muxd1), | |
351 | .rx_nbclk_muxd1 (rx_nbclk_muxd1), | |
352 | .rx_clk_muxd1 (rx_clk_muxd1), | |
353 | .rbc0_a_muxd1 (rbc0_a_muxd1), | |
354 | .rbc0_b_muxd1 (rbc0_b_muxd1), | |
355 | .rbc0_c_muxd1 (rbc0_c_muxd1), | |
356 | .rbc0_d_muxd1 (rbc0_d_muxd1), | |
357 | // Inputs | |
358 | .tcu_scan_mode (tcu_scan_mode), | |
359 | .mac_312tx_test_clk (mac_312tx_test_clk), | |
360 | .mac_312rx_test_clk (mac_312rx_test_clk), | |
361 | .mac_156tx_test_clk (mac_156tx_test_clk), | |
362 | .mac_156rx_test_clk (mac_156rx_test_clk), | |
363 | .mac_125tx_test_clk (mac_125tx_test_clk), | |
364 | .mac_125rx_test_clk (mac_125rx_test_clk), | |
365 | .reset (reset), | |
366 | .loopback0 (loopback0), | |
367 | .sel_clk_25mhz0 (sel_clk_25mhz0), | |
368 | .mii_mode0 (mii_mode0), | |
369 | .gmii_mode0 (gmii_mode0), | |
370 | .pcs_bypass0 (pcs_bypass0), | |
371 | .xpcs_bypass0 (xpcs_bypass0), | |
372 | .xpcs_loopback0 (xpcs_loopback0), | |
373 | .tx_heart_beat_timer0 (tx_heart_beat_timer0[3:0]), | |
374 | .rx_heart_beat_timer0 (rx_heart_beat_timer0[3:0]), | |
375 | .esr_mac_rclk_0 (esr_mac_rclk_0[3:0]), | |
376 | .esr_mac_tclk_0 (esr_mac_tclk_0), | |
377 | .loopback1 (loopback1), | |
378 | .sel_clk_25mhz1 (sel_clk_25mhz1), | |
379 | .mii_mode1 (mii_mode1), | |
380 | .gmii_mode1 (gmii_mode1), | |
381 | .pcs_bypass1 (pcs_bypass1), | |
382 | .xpcs_bypass1 (xpcs_bypass1), | |
383 | .xpcs_loopback1 (xpcs_loopback1), | |
384 | .tx_heart_beat_timer1 (tx_heart_beat_timer1[3:0]), | |
385 | .rx_heart_beat_timer1 (rx_heart_beat_timer1[3:0]), | |
386 | .esr_mac_rclk_1 (esr_mac_rclk_1[3:0]), | |
387 | .esr_mac_tclk_1 (esr_mac_tclk_1)); | |
388 | ||
389 | ||
390 | dummy_mac_dft dummy_mac_dft | |
391 | (/*AUTOINST*/ | |
392 | // Outputs | |
393 | .scan_out (scan_out), | |
394 | // Inputs | |
395 | .tcu_scan_en (tcu_scan_en), | |
396 | .tcu_aclk (tcu_aclk), | |
397 | .tcu_bclk (tcu_bclk), | |
398 | .tcu_clk_stop (tcu_clk_stop), | |
399 | .tcu_pce_ov (tcu_pce_ov), | |
400 | .scan_in (scan_in)); | |
401 | ||
402 | ||
403 | endmodule // niu_mac | |
404 | ||
405 | ||
406 | module dummy_mac_dft | |
407 | (/*AUTOARG*/ | |
408 | // Outputs | |
409 | scan_out, | |
410 | // Inputs | |
411 | tcu_scan_en, tcu_aclk, tcu_bclk, tcu_clk_stop, tcu_pce_ov, | |
412 | scan_in | |
413 | ); | |
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | input tcu_scan_en; | |
420 | input tcu_aclk; | |
421 | input tcu_bclk; | |
422 | input tcu_clk_stop; | |
423 | input tcu_pce_ov; | |
424 | input scan_in; | |
425 | output scan_out; | |
426 | ||
427 | wire tcu_scan_en; | |
428 | wire tcu_aclk; | |
429 | wire tcu_bclk; | |
430 | wire tcu_clk_stop; | |
431 | wire tcu_pce_ov; | |
432 | wire scan_in; | |
433 | wire scan_out; | |
434 | ||
435 | endmodule // dummy_mac_dft | |
436 |