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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_mb2.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | /////////////////////////////////////////////////////////////////////////////// | |
37 | // | |
38 | // | |
39 | // Released: 12/06/02 | |
40 | // Contacts: carlos.castil@sun.com / shahryar.aryani@sun.com | |
41 | // Description: Memory BIST Controller for Niagara2 NIU core | |
42 | // Block Type: Control Block | |
43 | // Chip Name: | |
44 | // Unit Name: | |
45 | // Module: mbist_engine | |
46 | // Where Instantiated: | |
47 | // | |
48 | // | |
49 | // (c) 2005 Sun Microsystems, Inc. | |
50 | // Sun Proprietary/Confidential | |
51 | // Internal use only. | |
52 | // | |
53 | // All rights reserved. No part of this design may be reproduced stored | |
54 | // in a retrieval system, or transmitted, in any form or by any means, | |
55 | // electronic, mechanical, photocopying, recording, or otherwise, without | |
56 | // prior written permission of Sun Microsystems, Inc. | |
57 | // | |
58 | /////////////////////////////////////////////////////////////////////////////// | |
59 | ||
60 | ||
61 | module niu_mb2 ( | |
62 | niu_mb2_rd_en, | |
63 | niu_mb2_wr_en, | |
64 | niu_mb2_addr, | |
65 | niu_mb2_wdata, | |
66 | niu_mb2_run, | |
67 | niu_tcu_mbist_fail_2, | |
68 | niu_tcu_mbist_done_2, | |
69 | mb2_scan_out, | |
70 | mb2_dmo_dout, | |
71 | l1clk, | |
72 | rst_l, | |
73 | tcu_mbist_user_mode, | |
74 | mb2_scan_in, | |
75 | tcu_aclk, | |
76 | tcu_bclk, | |
77 | tcu_niu_mbist_start_2, | |
78 | niu_mb2_tdmc_data_out, | |
79 | tcu_mbist_bisi_en); | |
80 | wire siclk; | |
81 | wire soclk; | |
82 | wire reset; | |
83 | wire config_reg_scanin; | |
84 | wire config_reg_scanout; | |
85 | wire [8:0] config_in; | |
86 | wire [8:0] config_out; | |
87 | wire start_transition; | |
88 | wire reset_engine; | |
89 | wire mbist_user_loop_mode; | |
90 | wire mbist_done; | |
91 | wire run; | |
92 | wire bisi; | |
93 | wire user_mode; | |
94 | wire user_data_mode; | |
95 | wire user_addr_mode; | |
96 | wire user_loop_mode; | |
97 | wire user_cmpsel_hold; | |
98 | wire ten_n_mode; | |
99 | wire mbist_user_data_mode; | |
100 | wire mbist_user_addr_mode; | |
101 | wire mbist_user_cmpsel_hold; | |
102 | wire mbist_ten_n_mode; | |
103 | wire user_data_reg_scanin; | |
104 | wire user_data_reg_scanout; | |
105 | wire [7:0] user_data_in; | |
106 | wire [7:0] user_data_out; | |
107 | wire user_start_addr_reg_scanin; | |
108 | wire user_start_addr_reg_scanout; | |
109 | wire [7:0] user_start_addr_in; | |
110 | wire [7:0] user_start_addr; | |
111 | wire user_stop_addr_reg_scanin; | |
112 | wire user_stop_addr_reg_scanout; | |
113 | wire [7:0] user_stop_addr_in; | |
114 | wire [7:0] user_stop_addr; | |
115 | wire user_incr_addr_reg_scanin; | |
116 | wire user_incr_addr_reg_scanout; | |
117 | wire [7:0] user_incr_addr_in; | |
118 | wire [7:0] user_incr_addr; | |
119 | wire user_cmpsel_reg_scanin; | |
120 | wire user_cmpsel_reg_scanout; | |
121 | wire [1:0] user_cmpsel_in; | |
122 | wire [1:0] user_cmpsel; | |
123 | wire user_bisi_wr_reg_scanin; | |
124 | wire user_bisi_wr_reg_scanout; | |
125 | wire user_bisi_wr_mode_in; | |
126 | wire user_bisi_wr_mode; | |
127 | wire user_bisi_rd_reg_scanin; | |
128 | wire user_bisi_rd_reg_scanout; | |
129 | wire user_bisi_rd_mode_in; | |
130 | wire user_bisi_rd_mode; | |
131 | wire mbist_user_bisi_wr_mode; | |
132 | wire mbist_user_bisi_wr_rd_mode; | |
133 | wire start_transition_reg_scanin; | |
134 | wire start_transition_reg_scanout; | |
135 | wire start_transition_piped; | |
136 | wire run_reg_scanin; | |
137 | wire run_reg_scanout; | |
138 | wire run1_reg_scanin; | |
139 | wire run1_reg_scanout; | |
140 | wire run1_in; | |
141 | wire run1_out; | |
142 | wire run2_reg_scanin; | |
143 | wire run2_reg_scanout; | |
144 | wire run2_in; | |
145 | wire run2_out; | |
146 | wire run_piped3; | |
147 | wire msb; | |
148 | wire control_reg_scanin; | |
149 | wire control_reg_scanout; | |
150 | wire [21:0] control_in; | |
151 | wire [21:0] control_out; | |
152 | wire bisi_wr_rd; | |
153 | wire [1:0] comp_sel; | |
154 | wire [1:0] data_control; | |
155 | wire address_mix; | |
156 | wire [3:0] march_element; | |
157 | wire [7:0] array_address; | |
158 | wire upaddress_march; | |
159 | wire [2:0] read_write_control; | |
160 | wire five_cycle_march; | |
161 | wire increment_addr; | |
162 | wire [7:0] start_addr; | |
163 | wire [7:0] next_array_address; | |
164 | wire next_upaddr_march; | |
165 | wire next_downaddr_march; | |
166 | wire [7:0] stop_addr; | |
167 | wire [8:0] overflow_addr; | |
168 | wire [7:0] incr_addr; | |
169 | wire overflow; | |
170 | wire [8:0] compare_addr; | |
171 | wire [7:0] add; | |
172 | wire [7:0] adj_address; | |
173 | wire [7:0] mbist_address; | |
174 | wire increment_march_elem; | |
175 | wire [1:0] next_cmpsel; | |
176 | wire [1:0] next_data_control; | |
177 | wire next_address_mix; | |
178 | wire [3:0] next_march_element; | |
179 | wire array_write; | |
180 | wire one_op_march; | |
181 | wire array_read; | |
182 | wire [7:0] mbist_wdata; | |
183 | wire true_data; | |
184 | wire [7:0] data_pattern; | |
185 | wire [7:0] exp_read_data; | |
186 | wire done_counter_reg_scanin; | |
187 | wire done_counter_reg_scanout; | |
188 | wire [2:0] done_counter_in; | |
189 | wire [2:0] done_counter_out; | |
190 | wire done_reg_in; | |
191 | wire done_reg_out; | |
192 | wire done_reg_scanin; | |
193 | wire done_reg_scanout; | |
194 | wire data_pipe_reg1_scanin; | |
195 | wire data_pipe_reg1_scanout; | |
196 | wire [7:0] data_pipe_reg1_in; | |
197 | wire [7:0] data_pipe_out1; | |
198 | wire data_pipe_reg2_scanin; | |
199 | wire data_pipe_reg2_scanout; | |
200 | wire [7:0] data_pipe_reg2_in; | |
201 | wire [7:0] data_pipe_out2; | |
202 | wire [7:0] old_piped_data; | |
203 | wire comp_sel_reg1_scanin; | |
204 | wire comp_sel_reg1_scanout; | |
205 | wire [1:0] comp_sel_reg1_in; | |
206 | wire [1:0] comp_sel_reg1_out1; | |
207 | wire [1:0] comp_sel_pipe1; | |
208 | wire ren_pipe_reg1_scanin; | |
209 | wire ren_pipe_reg1_scanout; | |
210 | wire ren_pipe_reg1_in; | |
211 | wire ren_pipe_out1; | |
212 | wire ren_pipe_reg2_scanin; | |
213 | wire ren_pipe_reg2_scanout; | |
214 | wire ren_pipe_reg2_in; | |
215 | wire ren_pipe_out2; | |
216 | wire old_piped_ren; | |
217 | wire fail_out_reg_in; | |
218 | wire fail; | |
219 | wire fail_out_reg_out; | |
220 | wire fail_out_reg_scanin; | |
221 | wire fail_out_reg_scanout; | |
222 | wire [39:0] read_data_reg_in; | |
223 | wire [39:0] read_data_mux2; | |
224 | wire [39:0] read_data_reg_out; | |
225 | wire read_data_pipe_reg_scanin; | |
226 | wire read_data_pipe_reg_scanout; | |
227 | wire fail_reg_scanin; | |
228 | wire fail_reg_scanout; | |
229 | wire fail_reg_in; | |
230 | wire fail_reg_out; | |
231 | wire fail_detect; | |
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | // ///////////////////////////////////////////////////////////////////////////// | |
238 | // Outputs | |
239 | // ///////////////////////////////////////////////////////////////////////////// | |
240 | ||
241 | output niu_mb2_rd_en; | |
242 | output niu_mb2_wr_en; | |
243 | ||
244 | output [7:0] niu_mb2_addr; | |
245 | output [7:0] niu_mb2_wdata; | |
246 | ||
247 | output niu_mb2_run; | |
248 | ||
249 | output niu_tcu_mbist_fail_2; | |
250 | output niu_tcu_mbist_done_2; | |
251 | ||
252 | output mb2_scan_out; | |
253 | ||
254 | output [39:0] mb2_dmo_dout; | |
255 | ||
256 | ||
257 | // ///////////////////////////////////////////////////////////////////////////// | |
258 | // Inputs | |
259 | // ///////////////////////////////////////////////////////////////////////////// | |
260 | ||
261 | input l1clk; | |
262 | input rst_l; | |
263 | input tcu_mbist_user_mode; | |
264 | ||
265 | input mb2_scan_in; | |
266 | input tcu_aclk; | |
267 | input tcu_bclk; | |
268 | ||
269 | input tcu_niu_mbist_start_2; | |
270 | ||
271 | input [147:0] niu_mb2_tdmc_data_out; | |
272 | ||
273 | input tcu_mbist_bisi_en; | |
274 | ||
275 | ||
276 | // ///////////////////////////////////////////////////////////////////////////// | |
277 | // Scan Renames | |
278 | // ///////////////////////////////////////////////////////////////////////////// | |
279 | ||
280 | // assign se = tcu_scan_en; | |
281 | // assign pce_ov = tcu_pce_ov; | |
282 | // assign stop = tcu_clk_stop; | |
283 | ||
284 | assign siclk = tcu_aclk; | |
285 | assign soclk = tcu_bclk; | |
286 | ||
287 | ||
288 | // ///////////////////////////////////////////////////////////////////////////// | |
289 | // Invert reset | |
290 | // ///////////////////////////////////////////////////////////////////////////// | |
291 | ||
292 | assign reset = rst_l; | |
293 | ||
294 | ||
295 | //////////////////////////////////////////////////////////////////////////////// | |
296 | // Clock header | |
297 | ||
298 | // l1clkhdr_ctl_macro clkgen ( | |
299 | // .l2clk (iol2clk ), | |
300 | // .l1en (1'b1 ), | |
301 | // .l1clk (l1clk ) | |
302 | // ); | |
303 | // assign siclk = 1'b0; | |
304 | // assign soclk = 1'b0; | |
305 | ||
306 | ||
307 | // ///////////////////////////////////////////////////////////////////////////// | |
308 | // | |
309 | // MBIST Config Register | |
310 | // | |
311 | // ///////////////////////////////////////////////////////////////////////////// | |
312 | // | |
313 | // A low to high transition on mbist_start will reset and start the engine. | |
314 | // mbist_start must remain active high for the duration of MBIST. | |
315 | // If mbist_start deasserts the engine will stop but not reset. | |
316 | // Once MBIST has completed niu_tcu_mbist_done_2 will assert and the fail status | |
317 | // signals will be valid. | |
318 | // To run MBIST again the mbist_start signal must transition low then high. | |
319 | // | |
320 | // Loop on Address will disable the address mix function. | |
321 | // | |
322 | // ///////////////////////////////////////////////////////////////////////////// | |
323 | ||
324 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_9 config_reg ( | |
325 | .scan_in(config_reg_scanin), | |
326 | .scan_out(config_reg_scanout), | |
327 | .din ( config_in[8:0] ), | |
328 | .dout ( config_out[8:0] ), | |
329 | .reset(reset), | |
330 | .l1clk(l1clk), | |
331 | .siclk(siclk), | |
332 | .soclk(soclk)); | |
333 | ||
334 | ||
335 | assign config_in[0] = tcu_niu_mbist_start_2; | |
336 | assign config_in[1] = config_out[0]; | |
337 | assign start_transition = config_out[0] & ~config_out[1]; | |
338 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
339 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
340 | ||
341 | assign config_in[2] = start_transition ? tcu_mbist_bisi_en: config_out[2]; | |
342 | assign bisi = config_out[2]; | |
343 | ||
344 | assign config_in[3] = start_transition ? tcu_mbist_user_mode : config_out[3]; | |
345 | assign user_mode = config_out[3]; | |
346 | ||
347 | assign config_in[4] = config_out[4]; | |
348 | assign user_data_mode = config_out[4]; | |
349 | ||
350 | assign config_in[5] = config_out[5]; | |
351 | assign user_addr_mode = config_out[5]; | |
352 | ||
353 | assign config_in[6] = config_out[6]; | |
354 | assign user_loop_mode = config_out[6]; | |
355 | ||
356 | assign config_in[7] = config_out[7]; | |
357 | assign user_cmpsel_hold = config_out[7]; //cmpsel_hold = 0 : Default, All cominations | |
358 | // = 1 : | |
359 | // User-specified cmpsel | |
360 | ||
361 | assign config_in[8] = config_out[8]; | |
362 | assign ten_n_mode = config_out[8]; | |
363 | ||
364 | ||
365 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
366 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
367 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
368 | assign mbist_user_cmpsel_hold = user_mode & user_cmpsel_hold; | |
369 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
370 | ||
371 | ||
372 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( | |
373 | .scan_in(user_data_reg_scanin), | |
374 | .scan_out(user_data_reg_scanout), | |
375 | .din ( user_data_in[7:0] ), | |
376 | .dout ( user_data_out[7:0] ), | |
377 | .reset(reset), | |
378 | .l1clk(l1clk), | |
379 | .siclk(siclk), | |
380 | .soclk(soclk)); | |
381 | ||
382 | ||
383 | assign user_data_in[7:0] = user_data_out[7:0]; | |
384 | ||
385 | ||
386 | // Defining User start, stop, and increment addresses. | |
387 | ||
388 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 user_start_addr_reg ( | |
389 | .scan_in(user_start_addr_reg_scanin), | |
390 | .scan_out(user_start_addr_reg_scanout), | |
391 | .din ( user_start_addr_in[7:0] ), | |
392 | .dout ( user_start_addr[7:0] ), | |
393 | .reset(reset), | |
394 | .l1clk(l1clk), | |
395 | .siclk(siclk), | |
396 | .soclk(soclk)); | |
397 | ||
398 | assign user_start_addr_in[7:0] = user_start_addr[7:0]; | |
399 | ||
400 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 user_stop_addr_reg ( | |
401 | .scan_in(user_stop_addr_reg_scanin), | |
402 | .scan_out(user_stop_addr_reg_scanout), | |
403 | .din ( user_stop_addr_in[7:0] ), | |
404 | .dout ( user_stop_addr[7:0] ), | |
405 | .reset(reset), | |
406 | .l1clk(l1clk), | |
407 | .siclk(siclk), | |
408 | .soclk(soclk)); | |
409 | ||
410 | assign user_stop_addr_in[7:0] = user_stop_addr[7:0]; | |
411 | ||
412 | ||
413 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 user_incr_addr_reg ( | |
414 | .scan_in(user_incr_addr_reg_scanin), | |
415 | .scan_out(user_incr_addr_reg_scanout), | |
416 | .din ( user_incr_addr_in[7:0] ), | |
417 | .dout ( user_incr_addr[7:0] ), | |
418 | .reset(reset), | |
419 | .l1clk(l1clk), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk)); | |
422 | ||
423 | assign user_incr_addr_in[7:0] = user_incr_addr[7:0]; | |
424 | ||
425 | // Defining User cmpsel. | |
426 | ||
427 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_2 user_cmpsel_reg ( | |
428 | .scan_in(user_cmpsel_reg_scanin), | |
429 | .scan_out(user_cmpsel_reg_scanout), | |
430 | .din ( user_cmpsel_in[1:0] ), | |
431 | .dout ( user_cmpsel[1:0] ), | |
432 | .reset(reset), | |
433 | .l1clk(l1clk), | |
434 | .siclk(siclk), | |
435 | .soclk(soclk)); | |
436 | ||
437 | assign user_cmpsel_in[1:0] = user_cmpsel[1:0]; | |
438 | ||
439 | // Defining user_bisi write and read registers | |
440 | ||
441 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( | |
442 | .scan_in(user_bisi_wr_reg_scanin), | |
443 | .scan_out(user_bisi_wr_reg_scanout), | |
444 | .din ( user_bisi_wr_mode_in ), | |
445 | .dout ( user_bisi_wr_mode ), | |
446 | .reset(reset), | |
447 | .l1clk(l1clk), | |
448 | .siclk(siclk), | |
449 | .soclk(soclk)); | |
450 | ||
451 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
452 | ||
453 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( | |
454 | .scan_in(user_bisi_rd_reg_scanin), | |
455 | .scan_out(user_bisi_rd_reg_scanout), | |
456 | .din ( user_bisi_rd_mode_in ), | |
457 | .dout ( user_bisi_rd_mode ), | |
458 | .reset(reset), | |
459 | .l1clk(l1clk), | |
460 | .siclk(siclk), | |
461 | .soclk(soclk)); | |
462 | ||
463 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
464 | ||
465 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
466 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
467 | ||
468 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
469 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
470 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
471 | ||
472 | ||
473 | //////////////////////////////////////////////////////////////////////////////// | |
474 | // Piping start_transition | |
475 | //////////////////////////////////////////////////////////////////////////////// | |
476 | ||
477 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( | |
478 | .scan_in(start_transition_reg_scanin), | |
479 | .scan_out(start_transition_reg_scanout), | |
480 | .din ( start_transition ), | |
481 | .dout ( start_transition_piped ), | |
482 | .reset(reset), | |
483 | .l1clk(l1clk), | |
484 | .siclk(siclk), | |
485 | .soclk(soclk)); | |
486 | ||
487 | ||
488 | //////////////////////////////////////////////////////////////////////////////// | |
489 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. | |
490 | //////////////////////////////////////////////////////////////////////////////// | |
491 | ||
492 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( | |
493 | .scan_in(run_reg_scanin), | |
494 | .scan_out(run_reg_scanout), | |
495 | .din ( run ), | |
496 | .dout ( niu_mb2_run ), | |
497 | .reset(reset), | |
498 | .l1clk(l1clk), | |
499 | .siclk(siclk), | |
500 | .soclk(soclk)); | |
501 | ||
502 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( | |
503 | .scan_in(run1_reg_scanin), | |
504 | .scan_out(run1_reg_scanout), | |
505 | .din ( run1_in ), | |
506 | .dout ( run1_out ), | |
507 | .reset(reset), | |
508 | .l1clk(l1clk), | |
509 | .siclk(siclk), | |
510 | .soclk(soclk)); | |
511 | ||
512 | assign run1_in = reset_engine ? 1'b0: niu_mb2_run; | |
513 | ||
514 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( | |
515 | .scan_in(run2_reg_scanin), | |
516 | .scan_out(run2_reg_scanout), | |
517 | .din ( run2_in ), | |
518 | .dout ( run2_out ), | |
519 | .reset(reset), | |
520 | .l1clk(l1clk), | |
521 | .siclk(siclk), | |
522 | .soclk(soclk)); | |
523 | ||
524 | assign run2_in = reset_engine ? 1'b0: run1_out; | |
525 | assign run_piped3 = config_out[0] & run2_out & ~msb; | |
526 | ||
527 | ||
528 | ||
529 | // ///////////////////////////////////////////////////////////////////////////// | |
530 | // | |
531 | // MBIST Control Register | |
532 | // | |
533 | // ///////////////////////////////////////////////////////////////////////////// | |
534 | // Remove Address mix disable before delivery | |
535 | // ///////////////////////////////////////////////////////////////////////////// | |
536 | ||
537 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_22 control_reg ( | |
538 | .scan_in(control_reg_scanin), | |
539 | .scan_out(control_reg_scanout), | |
540 | .din ( control_in[21:0] ), | |
541 | .dout ( control_out[21:0] ), | |
542 | .reset(reset), | |
543 | .l1clk(l1clk), | |
544 | .siclk(siclk), | |
545 | .soclk(soclk)); | |
546 | ||
547 | assign msb = control_out[21]; | |
548 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[20] : 1'b1; | |
549 | assign comp_sel[1:0] = mbist_user_cmpsel_hold ? user_cmpsel[1:0] : control_out[19:18]; | |
550 | assign data_control[1:0] = control_out[17:16]; | |
551 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[15]; | |
552 | assign march_element[3:0] = control_out[14:11]; | |
553 | ||
554 | assign array_address[7:0] = upaddress_march ? control_out[10:3] : ~control_out[10:3]; | |
555 | ||
556 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
557 | control_out[2:0]; | |
558 | ||
559 | assign control_in[2:0] = reset_engine ? 3'b0: | |
560 | ~run_piped3 ? control_out[2:0]: | |
561 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
562 | (read_write_control[2:0] == 3'b110 ) ? 3'b000: | |
563 | control_out[2:0] + 3'b001; | |
564 | ||
565 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
566 | (read_write_control[2:0] == 3'b110); | |
567 | ||
568 | assign control_in[10:3] = (start_transition_piped || reset_engine ) ? start_addr[7:0]: | |
569 | (~run_piped3) || (~increment_addr) ? control_out[10:3]: | |
570 | next_array_address[7:0]; | |
571 | ||
572 | assign next_array_address[7:0] = next_upaddr_march ? start_addr[7:0]: | |
573 | next_downaddr_march ? ~stop_addr[7:0]: | |
574 | (overflow_addr[7:0]); // array_addr + incr_addr | |
575 | ||
576 | assign start_addr[7:0] = mbist_user_addr_mode ? user_start_addr[7:0] : 8'b00000000; | |
577 | assign stop_addr[7:0] = mbist_user_addr_mode ? user_stop_addr[7:0] : 8'b11111111; | |
578 | assign incr_addr[7:0] = mbist_user_addr_mode ? user_incr_addr[7:0] : 8'b00000001; | |
579 | ||
580 | assign overflow_addr[8:0] = {1'b0,control_out[10:3]} + {1'b0,incr_addr[7:0]}; | |
581 | assign overflow = compare_addr[8:0] < overflow_addr[8:0]; | |
582 | ||
583 | assign compare_addr[8:0] = upaddress_march ? {1'b0, stop_addr[7:0]} : | |
584 | {1'b0, ~start_addr[7:0]}; | |
585 | ||
586 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
587 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
588 | (march_element[3:0] == 4'h8) ) && overflow; | |
589 | ||
590 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
591 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
592 | overflow; | |
593 | ||
594 | assign add[7:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
595 | (read_write_control[2:0] == 3'h3)) ? | |
596 | adj_address[7:0]: array_address[7:0]; | |
597 | ||
598 | assign adj_address[7:0] = address_mix ? { array_address[7:1], ~array_address[0] } : | |
599 | { array_address[7:3], ~array_address[2], array_address[1:0]}; | |
600 | ||
601 | // The order of add bits for address_mix may need to change! | |
602 | assign mbist_address[7:0] = address_mix ? {add[5:0], add[7:6]} : // Fast row | |
603 | add[7:0]; // Fast column | |
604 | ||
605 | assign increment_march_elem = increment_addr && overflow; | |
606 | ||
607 | assign control_in[21:11] = reset_engine ? 11'b0: | |
608 | ~run_piped3 ? control_out[21:11]: | |
609 | {msb, bisi_wr_rd, next_cmpsel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + | |
610 | {10'b0, increment_march_elem}; | |
611 | ||
612 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; | |
613 | ||
614 | assign next_cmpsel[1:0] = ( mbist_user_cmpsel_hold || (~bisi_wr_rd) || mbist_user_bisi_wr_mode ) ? 2'b11 : control_out[19:18]; | |
615 | ||
616 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
617 | data_control[1:0]; | |
618 | ||
619 | // Incorporated ten_n_mode! | |
620 | assign next_march_element[3:0] = ( bisi || | |
621 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
622 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
623 | && overflow ? 4'b1111: march_element[3:0]; | |
624 | ||
625 | assign array_write = ~run_piped3 ? 1'b0: | |
626 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
627 | (read_write_control[2:0] == 3'h1) || | |
628 | (read_write_control[2:0] == 3'h4): | |
629 | (~five_cycle_march & ~one_op_march) ? (read_write_control[0] == 1'b0) : | |
630 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); | |
631 | ||
632 | assign array_read = (~five_cycle_march & ~one_op_march) ? run_piped3 : | |
633 | (~array_write) && run_piped3; | |
634 | ||
635 | // assign mbist_done = msb; | |
636 | ||
637 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
638 | ||
639 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
640 | assign one_op_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
641 | (march_element[3:0] == 4'h7); | |
642 | ||
643 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
644 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
645 | (march_element[3:0] == 4'h7); | |
646 | ||
647 | ||
648 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
649 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
650 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
651 | ((read_write_control[2:0] == 3'h1) || | |
652 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
653 | one_op_march ? (march_element[3:0] == 4'h7) : | |
654 | (march_element[3:0] == 4'h1) || (march_element[3:0] == 4'h3); | |
655 | ||
656 | ||
657 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
658 | mbist_user_data_mode ? user_data_out[7:0]: | |
659 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
660 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
661 | (data_control[1:0] == 2'h1) ? 8'h99: | |
662 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
663 | 8'h00; | |
664 | ||
665 | ||
666 | // May need pipelining !!! | |
667 | ||
668 | assign niu_mb2_addr[7:0] = mbist_address[7:0]; | |
669 | assign niu_mb2_wr_en = array_write; | |
670 | assign niu_mb2_rd_en = array_read; | |
671 | assign niu_mb2_wdata[7:0] = mbist_wdata[7:0]; | |
672 | assign exp_read_data[7:0] = (~five_cycle_march & ~one_op_march) ? ~mbist_wdata[7:0] : mbist_wdata[7:0]; | |
673 | ||
674 | ///////////////////////////////////////////////////////////////////////// | |
675 | // Creating the mbist_done signal | |
676 | ///////////////////////////////////////////////////////////////////////// | |
677 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
678 | // a generic solution for done going high after the last fail has come back! | |
679 | ||
680 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( | |
681 | .scan_in(done_counter_reg_scanin), | |
682 | .scan_out(done_counter_reg_scanout), | |
683 | .din ( done_counter_in[2:0] ), | |
684 | .dout ( done_counter_out[2:0] ), | |
685 | .reset(reset), | |
686 | .l1clk(l1clk), | |
687 | .siclk(siclk), | |
688 | .soclk(soclk)); | |
689 | ||
690 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
691 | // goes low. | |
692 | ||
693 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
694 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
695 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
696 | done_counter_out[2:0]; | |
697 | ||
698 | ||
699 | // ///////////////////////////////////////////////////////////////////////////// | |
700 | // Done Detection | |
701 | // ///////////////////////////////////////////////////////////////////////////// | |
702 | ||
703 | assign done_reg_in = mbist_done; | |
704 | assign niu_tcu_mbist_done_2 = done_reg_out; | |
705 | ||
706 | ||
707 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( | |
708 | .scan_in(done_reg_scanin), | |
709 | .scan_out(done_reg_scanout), | |
710 | .din ( done_reg_in ), | |
711 | .dout ( done_reg_out ), | |
712 | .reset(reset), | |
713 | .l1clk(l1clk), | |
714 | .siclk(siclk), | |
715 | .soclk(soclk)); | |
716 | ||
717 | ||
718 | // ///////////////////////////////////////////////////////////////////////////// | |
719 | // Pipeline for Address, wdata, and Read_en | |
720 | // ///////////////////////////////////////////////////////////////////////////// | |
721 | ||
722 | // ///////////////////////////////////////////////////////////////////////////// | |
723 | // Pipeline for Address | |
724 | // ///////////////////////////////////////////////////////////////////////////// | |
725 | ||
726 | // NONE | |
727 | ||
728 | // ///////////////////////////////////////////////////////////////////////////// | |
729 | // Pipeline for wdata | |
730 | // ///////////////////////////////////////////////////////////////////////////// | |
731 | ||
732 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( | |
733 | .scan_in(data_pipe_reg1_scanin), | |
734 | .scan_out(data_pipe_reg1_scanout), | |
735 | .din ( data_pipe_reg1_in[7:0] ), | |
736 | .dout ( data_pipe_out1[7:0] ), | |
737 | .reset(reset), | |
738 | .l1clk(l1clk), | |
739 | .siclk(siclk), | |
740 | .soclk(soclk)); | |
741 | ||
742 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( | |
743 | .scan_in(data_pipe_reg2_scanin), | |
744 | .scan_out(data_pipe_reg2_scanout), | |
745 | .din ( data_pipe_reg2_in[7:0] ), | |
746 | .dout ( data_pipe_out2[7:0] ), | |
747 | .reset(reset), | |
748 | .l1clk(l1clk), | |
749 | .siclk(siclk), | |
750 | .soclk(soclk)); | |
751 | ||
752 | //Adding an extra level of pipe since piping the read_data | |
753 | //msff_ctl_macro data_pipe_reg3 (width=8, library=a1, reset=1)( | |
754 | // .scan_in(data_pipe_reg3_scanin), | |
755 | // .scan_out(data_pipe_reg3_scanout), | |
756 | // .din ( data_pipe_reg3_in[7:0] ), | |
757 | // .dout ( data_pipe_out3[7:0] )); | |
758 | ||
759 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: exp_read_data[7:0]; | |
760 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
761 | //assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
762 | //assign old_piped_data[7:0] = data_pipe_out3[7:0]; | |
763 | assign old_piped_data[7:0] = data_pipe_out2[7:0]; | |
764 | ||
765 | // ///////////////////////////////////////////////////////////////////////////// | |
766 | // Pipeline for comp sel | |
767 | // ///////////////////////////////////////////////////////////////////////////// | |
768 | ||
769 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_2 comp_sel_reg1 ( | |
770 | .scan_in(comp_sel_reg1_scanin), | |
771 | .scan_out(comp_sel_reg1_scanout), | |
772 | .din ( comp_sel_reg1_in[ 1 : 0 ] ), | |
773 | .dout ( comp_sel_reg1_out1[ 1 : 0 ] ), | |
774 | .reset(reset), | |
775 | .l1clk(l1clk), | |
776 | .siclk(siclk), | |
777 | .soclk(soclk)); | |
778 | ||
779 | assign comp_sel_reg1_in[ 1 : 0 ] = comp_sel[ 1 : 0 ]; | |
780 | ||
781 | assign comp_sel_pipe1[ 1 : 0 ] = comp_sel_reg1_out1[ 1 : 0 ]; | |
782 | ||
783 | ||
784 | // ///////////////////////////////////////////////////////////////////////////// | |
785 | // Pipeline for Read_en | |
786 | // ///////////////////////////////////////////////////////////////////////////// | |
787 | ||
788 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg1 ( | |
789 | .scan_in(ren_pipe_reg1_scanin), | |
790 | .scan_out(ren_pipe_reg1_scanout), | |
791 | .din ( ren_pipe_reg1_in ), | |
792 | .dout ( ren_pipe_out1 ), | |
793 | .reset(reset), | |
794 | .l1clk(l1clk), | |
795 | .siclk(siclk), | |
796 | .soclk(soclk)); | |
797 | ||
798 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg2 ( | |
799 | .scan_in(ren_pipe_reg2_scanin), | |
800 | .scan_out(ren_pipe_reg2_scanout), | |
801 | .din ( ren_pipe_reg2_in ), | |
802 | .dout ( ren_pipe_out2 ), | |
803 | .reset(reset), | |
804 | .l1clk(l1clk), | |
805 | .siclk(siclk), | |
806 | .soclk(soclk)); | |
807 | ||
808 | //Adding an extra level of pipe since piping the read_data | |
809 | //msff_ctl_macro ren_pipe_reg3 (width=1, library=a1, reset=1)( | |
810 | // .scan_in(ren_pipe_reg3_scanin), | |
811 | // .scan_out(ren_pipe_reg3_scanout), | |
812 | // .din ( ren_pipe_reg3_in ), | |
813 | // .dout ( ren_pipe_out3 )); | |
814 | ||
815 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; | |
816 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; | |
817 | //assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; | |
818 | // assign old_piped_ren = ren_pipe_out3; | |
819 | assign old_piped_ren = ren_pipe_out2; | |
820 | ||
821 | // ///////////////////////////////////////////////////////////////////////////// | |
822 | // Fail Detection | |
823 | // ///////////////////////////////////////////////////////////////////////////// | |
824 | ||
825 | assign fail_out_reg_in = fail; | |
826 | assign niu_tcu_mbist_fail_2 = fail_out_reg_out; | |
827 | ||
828 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 fail_out_reg ( | |
829 | .scan_in(fail_out_reg_scanin), | |
830 | .scan_out(fail_out_reg_scanout), | |
831 | .din ( fail_out_reg_in ), | |
832 | .dout ( fail_out_reg_out ), | |
833 | .reset(reset), | |
834 | .l1clk(l1clk), | |
835 | .siclk(siclk), | |
836 | .soclk(soclk)); | |
837 | ||
838 | // ///////////////////////////////////////////////////////////////////////////// | |
839 | // Fail Detection | |
840 | // ///////////////////////////////////////////////////////////////////////////// | |
841 | ||
842 | assign read_data_reg_in[ 39 : 0 ] = read_data_mux2[ 39 : 0 ]; | |
843 | assign mb2_dmo_dout[ 39 : 0 ] = read_data_reg_out[ 39 : 0 ]; | |
844 | ||
845 | ||
846 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_40 read_data_pipe_reg ( | |
847 | .scan_in(read_data_pipe_reg_scanin), | |
848 | .scan_out(read_data_pipe_reg_scanout), | |
849 | .din ( read_data_reg_in[ 39 : 0 ] ), | |
850 | .dout ( read_data_reg_out[ 39 : 0 ] ), | |
851 | .reset(reset), | |
852 | .l1clk(l1clk), | |
853 | .siclk(siclk), | |
854 | .soclk(soclk)); | |
855 | ||
856 | ||
857 | niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 fail_reg ( | |
858 | .scan_in(fail_reg_scanin), | |
859 | .scan_out(fail_reg_scanout), | |
860 | .din ( fail_reg_in ), | |
861 | .dout ( fail_reg_out ), | |
862 | .reset(reset), | |
863 | .l1clk(l1clk), | |
864 | .siclk(siclk), | |
865 | .soclk(soclk)); | |
866 | ||
867 | assign fail_reg_in = reset_engine ? 1'b0 : fail_detect | fail_reg_out; | |
868 | ||
869 | assign fail_detect = ({old_piped_data[ 7 : 0 ], | |
870 | old_piped_data[ 7 : 0 ], | |
871 | old_piped_data[ 7 : 0 ], | |
872 | old_piped_data[ 7 : 0 ], | |
873 | old_piped_data[ 7 : 0 ]}) != mb2_dmo_dout[ 39 : 0 ] && old_piped_ren; | |
874 | ||
875 | assign fail = mbist_done ? fail_reg_out : fail_detect; | |
876 | ||
877 | ||
878 | // Pipelining the read_data to meet the timing requirement | |
879 | // Check if need to reset?? | |
880 | ||
881 | assign read_data_mux2[ 39 : 0 ] = (comp_sel_pipe1[ 1 : 0 ] == 2'b00) ? niu_mb2_tdmc_data_out[ 39 : 0 ] : | |
882 | (comp_sel_pipe1[ 1 : 0 ] == 2'b01) ? niu_mb2_tdmc_data_out[ 79 : 40 ] : | |
883 | (comp_sel_pipe1[ 1 : 0 ] == 2'b10) ? niu_mb2_tdmc_data_out[ 119 : 80 ] : | |
884 | {data_pipe_out1[ 7 : 0 ], data_pipe_out1[ 7 : 4 ], niu_mb2_tdmc_data_out[ 147 : 120 ]} ; | |
885 | ||
886 | // ///////////////////////////////////////////////////////////////////////////// | |
887 | // Fail Address and Control Reg Store | |
888 | // ///////////////////////////////////////////////////////////////////////////// | |
889 | ||
890 | supply0 vss; // <- port for ground | |
891 | supply1 vdd; // <- port for power | |
892 | // ///////////////////////////////////////////////////////////////////////////// | |
893 | // fixscan start: | |
894 | assign config_reg_scanin = mb2_scan_in ; | |
895 | assign user_data_reg_scanin = config_reg_scanout ; | |
896 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
897 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
898 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
899 | assign user_cmpsel_reg_scanin = user_incr_addr_reg_scanout; | |
900 | assign user_bisi_wr_reg_scanin = user_cmpsel_reg_scanout ; | |
901 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
902 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
903 | assign run_reg_scanin = start_transition_reg_scanout; | |
904 | assign run1_reg_scanin = run_reg_scanout ; | |
905 | assign run2_reg_scanin = run1_reg_scanout ; | |
906 | assign control_reg_scanin = run2_reg_scanout ; | |
907 | assign done_counter_reg_scanin = control_reg_scanout ; | |
908 | assign done_reg_scanin = done_counter_reg_scanout ; | |
909 | assign data_pipe_reg1_scanin = done_reg_scanout ; | |
910 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
911 | assign comp_sel_reg1_scanin = data_pipe_reg2_scanout ; | |
912 | assign ren_pipe_reg1_scanin = comp_sel_reg1_scanout ; | |
913 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; | |
914 | assign fail_out_reg_scanin = ren_pipe_reg2_scanout ; | |
915 | assign read_data_pipe_reg_scanin = fail_out_reg_scanout ; | |
916 | assign fail_reg_scanin = read_data_pipe_reg_scanout; | |
917 | assign mb2_scan_out = fail_reg_scanout ; | |
918 | // fixscan end: | |
919 | endmodule | |
920 | // ///////////////////////////////////////////////////////////////////////////// | |
921 | ||
922 | ||
923 | ||
924 | ||
925 | ||
926 | ||
927 | // any PARAMS parms go into naming of macro | |
928 | ||
929 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_9 ( | |
930 | din, | |
931 | reset, | |
932 | l1clk, | |
933 | scan_in, | |
934 | siclk, | |
935 | soclk, | |
936 | dout, | |
937 | scan_out); | |
938 | wire [8:0] fdin; | |
939 | wire [8:1] sout; | |
940 | ||
941 | input [8:0] din; | |
942 | input reset; | |
943 | input l1clk; | |
944 | input scan_in; | |
945 | ||
946 | ||
947 | input siclk; | |
948 | input soclk; | |
949 | ||
950 | output [8:0] dout; | |
951 | output scan_out; | |
952 | assign fdin[8:0] = din[8:0] & {9 {reset}}; | |
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | cl_a1_msff_syrst_4x d0_0 ( | |
971 | .l1clk(l1clk), | |
972 | .siclk(siclk), | |
973 | .soclk(soclk), | |
974 | .d(fdin[0]), | |
975 | .si(sout[1]), | |
976 | .so(scan_out), | |
977 | .reset(reset), | |
978 | .q(dout[0]) | |
979 | ); | |
980 | cl_a1_msff_syrst_4x d0_1 ( | |
981 | .l1clk(l1clk), | |
982 | .siclk(siclk), | |
983 | .soclk(soclk), | |
984 | .d(fdin[1]), | |
985 | .si(sout[2]), | |
986 | .so(sout[1]), | |
987 | .reset(reset), | |
988 | .q(dout[1]) | |
989 | ); | |
990 | cl_a1_msff_syrst_4x d0_2 ( | |
991 | .l1clk(l1clk), | |
992 | .siclk(siclk), | |
993 | .soclk(soclk), | |
994 | .d(fdin[2]), | |
995 | .si(sout[3]), | |
996 | .so(sout[2]), | |
997 | .reset(reset), | |
998 | .q(dout[2]) | |
999 | ); | |
1000 | cl_a1_msff_syrst_4x d0_3 ( | |
1001 | .l1clk(l1clk), | |
1002 | .siclk(siclk), | |
1003 | .soclk(soclk), | |
1004 | .d(fdin[3]), | |
1005 | .si(sout[4]), | |
1006 | .so(sout[3]), | |
1007 | .reset(reset), | |
1008 | .q(dout[3]) | |
1009 | ); | |
1010 | cl_a1_msff_syrst_4x d0_4 ( | |
1011 | .l1clk(l1clk), | |
1012 | .siclk(siclk), | |
1013 | .soclk(soclk), | |
1014 | .d(fdin[4]), | |
1015 | .si(sout[5]), | |
1016 | .so(sout[4]), | |
1017 | .reset(reset), | |
1018 | .q(dout[4]) | |
1019 | ); | |
1020 | cl_a1_msff_syrst_4x d0_5 ( | |
1021 | .l1clk(l1clk), | |
1022 | .siclk(siclk), | |
1023 | .soclk(soclk), | |
1024 | .d(fdin[5]), | |
1025 | .si(sout[6]), | |
1026 | .so(sout[5]), | |
1027 | .reset(reset), | |
1028 | .q(dout[5]) | |
1029 | ); | |
1030 | cl_a1_msff_syrst_4x d0_6 ( | |
1031 | .l1clk(l1clk), | |
1032 | .siclk(siclk), | |
1033 | .soclk(soclk), | |
1034 | .d(fdin[6]), | |
1035 | .si(sout[7]), | |
1036 | .so(sout[6]), | |
1037 | .reset(reset), | |
1038 | .q(dout[6]) | |
1039 | ); | |
1040 | cl_a1_msff_syrst_4x d0_7 ( | |
1041 | .l1clk(l1clk), | |
1042 | .siclk(siclk), | |
1043 | .soclk(soclk), | |
1044 | .d(fdin[7]), | |
1045 | .si(sout[8]), | |
1046 | .so(sout[7]), | |
1047 | .reset(reset), | |
1048 | .q(dout[7]) | |
1049 | ); | |
1050 | cl_a1_msff_syrst_4x d0_8 ( | |
1051 | .l1clk(l1clk), | |
1052 | .siclk(siclk), | |
1053 | .soclk(soclk), | |
1054 | .d(fdin[8]), | |
1055 | .si(scan_in), | |
1056 | .so(sout[8]), | |
1057 | .reset(reset), | |
1058 | .q(dout[8]) | |
1059 | ); | |
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | endmodule | |
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | // any PARAMS parms go into naming of macro | |
1079 | ||
1080 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_8 ( | |
1081 | din, | |
1082 | reset, | |
1083 | l1clk, | |
1084 | scan_in, | |
1085 | siclk, | |
1086 | soclk, | |
1087 | dout, | |
1088 | scan_out); | |
1089 | wire [7:0] fdin; | |
1090 | wire [7:1] sout; | |
1091 | ||
1092 | input [7:0] din; | |
1093 | input reset; | |
1094 | input l1clk; | |
1095 | input scan_in; | |
1096 | ||
1097 | ||
1098 | input siclk; | |
1099 | input soclk; | |
1100 | ||
1101 | output [7:0] dout; | |
1102 | output scan_out; | |
1103 | assign fdin[7:0] = din[7:0] & {8 {reset}}; | |
1104 | ||
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | ||
1121 | cl_a1_msff_syrst_4x d0_0 ( | |
1122 | .l1clk(l1clk), | |
1123 | .siclk(siclk), | |
1124 | .soclk(soclk), | |
1125 | .d(fdin[0]), | |
1126 | .si(sout[1]), | |
1127 | .so(scan_out), | |
1128 | .reset(reset), | |
1129 | .q(dout[0]) | |
1130 | ); | |
1131 | cl_a1_msff_syrst_4x d0_1 ( | |
1132 | .l1clk(l1clk), | |
1133 | .siclk(siclk), | |
1134 | .soclk(soclk), | |
1135 | .d(fdin[1]), | |
1136 | .si(sout[2]), | |
1137 | .so(sout[1]), | |
1138 | .reset(reset), | |
1139 | .q(dout[1]) | |
1140 | ); | |
1141 | cl_a1_msff_syrst_4x d0_2 ( | |
1142 | .l1clk(l1clk), | |
1143 | .siclk(siclk), | |
1144 | .soclk(soclk), | |
1145 | .d(fdin[2]), | |
1146 | .si(sout[3]), | |
1147 | .so(sout[2]), | |
1148 | .reset(reset), | |
1149 | .q(dout[2]) | |
1150 | ); | |
1151 | cl_a1_msff_syrst_4x d0_3 ( | |
1152 | .l1clk(l1clk), | |
1153 | .siclk(siclk), | |
1154 | .soclk(soclk), | |
1155 | .d(fdin[3]), | |
1156 | .si(sout[4]), | |
1157 | .so(sout[3]), | |
1158 | .reset(reset), | |
1159 | .q(dout[3]) | |
1160 | ); | |
1161 | cl_a1_msff_syrst_4x d0_4 ( | |
1162 | .l1clk(l1clk), | |
1163 | .siclk(siclk), | |
1164 | .soclk(soclk), | |
1165 | .d(fdin[4]), | |
1166 | .si(sout[5]), | |
1167 | .so(sout[4]), | |
1168 | .reset(reset), | |
1169 | .q(dout[4]) | |
1170 | ); | |
1171 | cl_a1_msff_syrst_4x d0_5 ( | |
1172 | .l1clk(l1clk), | |
1173 | .siclk(siclk), | |
1174 | .soclk(soclk), | |
1175 | .d(fdin[5]), | |
1176 | .si(sout[6]), | |
1177 | .so(sout[5]), | |
1178 | .reset(reset), | |
1179 | .q(dout[5]) | |
1180 | ); | |
1181 | cl_a1_msff_syrst_4x d0_6 ( | |
1182 | .l1clk(l1clk), | |
1183 | .siclk(siclk), | |
1184 | .soclk(soclk), | |
1185 | .d(fdin[6]), | |
1186 | .si(sout[7]), | |
1187 | .so(sout[6]), | |
1188 | .reset(reset), | |
1189 | .q(dout[6]) | |
1190 | ); | |
1191 | cl_a1_msff_syrst_4x d0_7 ( | |
1192 | .l1clk(l1clk), | |
1193 | .siclk(siclk), | |
1194 | .soclk(soclk), | |
1195 | .d(fdin[7]), | |
1196 | .si(scan_in), | |
1197 | .so(sout[7]), | |
1198 | .reset(reset), | |
1199 | .q(dout[7]) | |
1200 | ); | |
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | endmodule | |
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | // any PARAMS parms go into naming of macro | |
1220 | ||
1221 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_2 ( | |
1222 | din, | |
1223 | reset, | |
1224 | l1clk, | |
1225 | scan_in, | |
1226 | siclk, | |
1227 | soclk, | |
1228 | dout, | |
1229 | scan_out); | |
1230 | wire [1:0] fdin; | |
1231 | wire [1:1] sout; | |
1232 | ||
1233 | input [1:0] din; | |
1234 | input reset; | |
1235 | input l1clk; | |
1236 | input scan_in; | |
1237 | ||
1238 | ||
1239 | input siclk; | |
1240 | input soclk; | |
1241 | ||
1242 | output [1:0] dout; | |
1243 | output scan_out; | |
1244 | assign fdin[1:0] = din[1:0] & {2 {reset}}; | |
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | cl_a1_msff_syrst_4x d0_0 ( | |
1263 | .l1clk(l1clk), | |
1264 | .siclk(siclk), | |
1265 | .soclk(soclk), | |
1266 | .d(fdin[0]), | |
1267 | .si(sout[1]), | |
1268 | .so(scan_out), | |
1269 | .reset(reset), | |
1270 | .q(dout[0]) | |
1271 | ); | |
1272 | cl_a1_msff_syrst_4x d0_1 ( | |
1273 | .l1clk(l1clk), | |
1274 | .siclk(siclk), | |
1275 | .soclk(soclk), | |
1276 | .d(fdin[1]), | |
1277 | .si(scan_in), | |
1278 | .so(sout[1]), | |
1279 | .reset(reset), | |
1280 | .q(dout[1]) | |
1281 | ); | |
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | endmodule | |
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | // any PARAMS parms go into naming of macro | |
1301 | ||
1302 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_1 ( | |
1303 | din, | |
1304 | reset, | |
1305 | l1clk, | |
1306 | scan_in, | |
1307 | siclk, | |
1308 | soclk, | |
1309 | dout, | |
1310 | scan_out); | |
1311 | wire [0:0] fdin; | |
1312 | ||
1313 | input [0:0] din; | |
1314 | input reset; | |
1315 | input l1clk; | |
1316 | input scan_in; | |
1317 | ||
1318 | ||
1319 | input siclk; | |
1320 | input soclk; | |
1321 | ||
1322 | output [0:0] dout; | |
1323 | output scan_out; | |
1324 | assign fdin[0:0] = din[0:0] & {1 {reset}}; | |
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | cl_a1_msff_syrst_4x d0_0 ( | |
1343 | .l1clk(l1clk), | |
1344 | .siclk(siclk), | |
1345 | .soclk(soclk), | |
1346 | .d(fdin[0]), | |
1347 | .si(scan_in), | |
1348 | .so(scan_out), | |
1349 | .reset(reset), | |
1350 | .q(dout[0]) | |
1351 | ); | |
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | endmodule | |
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | // any PARAMS parms go into naming of macro | |
1371 | ||
1372 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_22 ( | |
1373 | din, | |
1374 | reset, | |
1375 | l1clk, | |
1376 | scan_in, | |
1377 | siclk, | |
1378 | soclk, | |
1379 | dout, | |
1380 | scan_out); | |
1381 | wire [21:0] fdin; | |
1382 | wire [21:1] sout; | |
1383 | ||
1384 | input [21:0] din; | |
1385 | input reset; | |
1386 | input l1clk; | |
1387 | input scan_in; | |
1388 | ||
1389 | ||
1390 | input siclk; | |
1391 | input soclk; | |
1392 | ||
1393 | output [21:0] dout; | |
1394 | output scan_out; | |
1395 | assign fdin[21:0] = din[21:0] & {22 {reset}}; | |
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | cl_a1_msff_syrst_4x d0_0 ( | |
1414 | .l1clk(l1clk), | |
1415 | .siclk(siclk), | |
1416 | .soclk(soclk), | |
1417 | .d(fdin[0]), | |
1418 | .si(sout[1]), | |
1419 | .so(scan_out), | |
1420 | .reset(reset), | |
1421 | .q(dout[0]) | |
1422 | ); | |
1423 | cl_a1_msff_syrst_4x d0_1 ( | |
1424 | .l1clk(l1clk), | |
1425 | .siclk(siclk), | |
1426 | .soclk(soclk), | |
1427 | .d(fdin[1]), | |
1428 | .si(sout[2]), | |
1429 | .so(sout[1]), | |
1430 | .reset(reset), | |
1431 | .q(dout[1]) | |
1432 | ); | |
1433 | cl_a1_msff_syrst_4x d0_2 ( | |
1434 | .l1clk(l1clk), | |
1435 | .siclk(siclk), | |
1436 | .soclk(soclk), | |
1437 | .d(fdin[2]), | |
1438 | .si(sout[3]), | |
1439 | .so(sout[2]), | |
1440 | .reset(reset), | |
1441 | .q(dout[2]) | |
1442 | ); | |
1443 | cl_a1_msff_syrst_4x d0_3 ( | |
1444 | .l1clk(l1clk), | |
1445 | .siclk(siclk), | |
1446 | .soclk(soclk), | |
1447 | .d(fdin[3]), | |
1448 | .si(sout[4]), | |
1449 | .so(sout[3]), | |
1450 | .reset(reset), | |
1451 | .q(dout[3]) | |
1452 | ); | |
1453 | cl_a1_msff_syrst_4x d0_4 ( | |
1454 | .l1clk(l1clk), | |
1455 | .siclk(siclk), | |
1456 | .soclk(soclk), | |
1457 | .d(fdin[4]), | |
1458 | .si(sout[5]), | |
1459 | .so(sout[4]), | |
1460 | .reset(reset), | |
1461 | .q(dout[4]) | |
1462 | ); | |
1463 | cl_a1_msff_syrst_4x d0_5 ( | |
1464 | .l1clk(l1clk), | |
1465 | .siclk(siclk), | |
1466 | .soclk(soclk), | |
1467 | .d(fdin[5]), | |
1468 | .si(sout[6]), | |
1469 | .so(sout[5]), | |
1470 | .reset(reset), | |
1471 | .q(dout[5]) | |
1472 | ); | |
1473 | cl_a1_msff_syrst_4x d0_6 ( | |
1474 | .l1clk(l1clk), | |
1475 | .siclk(siclk), | |
1476 | .soclk(soclk), | |
1477 | .d(fdin[6]), | |
1478 | .si(sout[7]), | |
1479 | .so(sout[6]), | |
1480 | .reset(reset), | |
1481 | .q(dout[6]) | |
1482 | ); | |
1483 | cl_a1_msff_syrst_4x d0_7 ( | |
1484 | .l1clk(l1clk), | |
1485 | .siclk(siclk), | |
1486 | .soclk(soclk), | |
1487 | .d(fdin[7]), | |
1488 | .si(sout[8]), | |
1489 | .so(sout[7]), | |
1490 | .reset(reset), | |
1491 | .q(dout[7]) | |
1492 | ); | |
1493 | cl_a1_msff_syrst_4x d0_8 ( | |
1494 | .l1clk(l1clk), | |
1495 | .siclk(siclk), | |
1496 | .soclk(soclk), | |
1497 | .d(fdin[8]), | |
1498 | .si(sout[9]), | |
1499 | .so(sout[8]), | |
1500 | .reset(reset), | |
1501 | .q(dout[8]) | |
1502 | ); | |
1503 | cl_a1_msff_syrst_4x d0_9 ( | |
1504 | .l1clk(l1clk), | |
1505 | .siclk(siclk), | |
1506 | .soclk(soclk), | |
1507 | .d(fdin[9]), | |
1508 | .si(sout[10]), | |
1509 | .so(sout[9]), | |
1510 | .reset(reset), | |
1511 | .q(dout[9]) | |
1512 | ); | |
1513 | cl_a1_msff_syrst_4x d0_10 ( | |
1514 | .l1clk(l1clk), | |
1515 | .siclk(siclk), | |
1516 | .soclk(soclk), | |
1517 | .d(fdin[10]), | |
1518 | .si(sout[11]), | |
1519 | .so(sout[10]), | |
1520 | .reset(reset), | |
1521 | .q(dout[10]) | |
1522 | ); | |
1523 | cl_a1_msff_syrst_4x d0_11 ( | |
1524 | .l1clk(l1clk), | |
1525 | .siclk(siclk), | |
1526 | .soclk(soclk), | |
1527 | .d(fdin[11]), | |
1528 | .si(sout[12]), | |
1529 | .so(sout[11]), | |
1530 | .reset(reset), | |
1531 | .q(dout[11]) | |
1532 | ); | |
1533 | cl_a1_msff_syrst_4x d0_12 ( | |
1534 | .l1clk(l1clk), | |
1535 | .siclk(siclk), | |
1536 | .soclk(soclk), | |
1537 | .d(fdin[12]), | |
1538 | .si(sout[13]), | |
1539 | .so(sout[12]), | |
1540 | .reset(reset), | |
1541 | .q(dout[12]) | |
1542 | ); | |
1543 | cl_a1_msff_syrst_4x d0_13 ( | |
1544 | .l1clk(l1clk), | |
1545 | .siclk(siclk), | |
1546 | .soclk(soclk), | |
1547 | .d(fdin[13]), | |
1548 | .si(sout[14]), | |
1549 | .so(sout[13]), | |
1550 | .reset(reset), | |
1551 | .q(dout[13]) | |
1552 | ); | |
1553 | cl_a1_msff_syrst_4x d0_14 ( | |
1554 | .l1clk(l1clk), | |
1555 | .siclk(siclk), | |
1556 | .soclk(soclk), | |
1557 | .d(fdin[14]), | |
1558 | .si(sout[15]), | |
1559 | .so(sout[14]), | |
1560 | .reset(reset), | |
1561 | .q(dout[14]) | |
1562 | ); | |
1563 | cl_a1_msff_syrst_4x d0_15 ( | |
1564 | .l1clk(l1clk), | |
1565 | .siclk(siclk), | |
1566 | .soclk(soclk), | |
1567 | .d(fdin[15]), | |
1568 | .si(sout[16]), | |
1569 | .so(sout[15]), | |
1570 | .reset(reset), | |
1571 | .q(dout[15]) | |
1572 | ); | |
1573 | cl_a1_msff_syrst_4x d0_16 ( | |
1574 | .l1clk(l1clk), | |
1575 | .siclk(siclk), | |
1576 | .soclk(soclk), | |
1577 | .d(fdin[16]), | |
1578 | .si(sout[17]), | |
1579 | .so(sout[16]), | |
1580 | .reset(reset), | |
1581 | .q(dout[16]) | |
1582 | ); | |
1583 | cl_a1_msff_syrst_4x d0_17 ( | |
1584 | .l1clk(l1clk), | |
1585 | .siclk(siclk), | |
1586 | .soclk(soclk), | |
1587 | .d(fdin[17]), | |
1588 | .si(sout[18]), | |
1589 | .so(sout[17]), | |
1590 | .reset(reset), | |
1591 | .q(dout[17]) | |
1592 | ); | |
1593 | cl_a1_msff_syrst_4x d0_18 ( | |
1594 | .l1clk(l1clk), | |
1595 | .siclk(siclk), | |
1596 | .soclk(soclk), | |
1597 | .d(fdin[18]), | |
1598 | .si(sout[19]), | |
1599 | .so(sout[18]), | |
1600 | .reset(reset), | |
1601 | .q(dout[18]) | |
1602 | ); | |
1603 | cl_a1_msff_syrst_4x d0_19 ( | |
1604 | .l1clk(l1clk), | |
1605 | .siclk(siclk), | |
1606 | .soclk(soclk), | |
1607 | .d(fdin[19]), | |
1608 | .si(sout[20]), | |
1609 | .so(sout[19]), | |
1610 | .reset(reset), | |
1611 | .q(dout[19]) | |
1612 | ); | |
1613 | cl_a1_msff_syrst_4x d0_20 ( | |
1614 | .l1clk(l1clk), | |
1615 | .siclk(siclk), | |
1616 | .soclk(soclk), | |
1617 | .d(fdin[20]), | |
1618 | .si(sout[21]), | |
1619 | .so(sout[20]), | |
1620 | .reset(reset), | |
1621 | .q(dout[20]) | |
1622 | ); | |
1623 | cl_a1_msff_syrst_4x d0_21 ( | |
1624 | .l1clk(l1clk), | |
1625 | .siclk(siclk), | |
1626 | .soclk(soclk), | |
1627 | .d(fdin[21]), | |
1628 | .si(scan_in), | |
1629 | .so(sout[21]), | |
1630 | .reset(reset), | |
1631 | .q(dout[21]) | |
1632 | ); | |
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | endmodule | |
1638 | ||
1639 | ||
1640 | ||
1641 | ||
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | // any PARAMS parms go into naming of macro | |
1652 | ||
1653 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_3 ( | |
1654 | din, | |
1655 | reset, | |
1656 | l1clk, | |
1657 | scan_in, | |
1658 | siclk, | |
1659 | soclk, | |
1660 | dout, | |
1661 | scan_out); | |
1662 | wire [2:0] fdin; | |
1663 | wire [2:1] sout; | |
1664 | ||
1665 | input [2:0] din; | |
1666 | input reset; | |
1667 | input l1clk; | |
1668 | input scan_in; | |
1669 | ||
1670 | ||
1671 | input siclk; | |
1672 | input soclk; | |
1673 | ||
1674 | output [2:0] dout; | |
1675 | output scan_out; | |
1676 | assign fdin[2:0] = din[2:0] & {3 {reset}}; | |
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | ||
1687 | ||
1688 | ||
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | cl_a1_msff_syrst_4x d0_0 ( | |
1695 | .l1clk(l1clk), | |
1696 | .siclk(siclk), | |
1697 | .soclk(soclk), | |
1698 | .d(fdin[0]), | |
1699 | .si(sout[1]), | |
1700 | .so(scan_out), | |
1701 | .reset(reset), | |
1702 | .q(dout[0]) | |
1703 | ); | |
1704 | cl_a1_msff_syrst_4x d0_1 ( | |
1705 | .l1clk(l1clk), | |
1706 | .siclk(siclk), | |
1707 | .soclk(soclk), | |
1708 | .d(fdin[1]), | |
1709 | .si(sout[2]), | |
1710 | .so(sout[1]), | |
1711 | .reset(reset), | |
1712 | .q(dout[1]) | |
1713 | ); | |
1714 | cl_a1_msff_syrst_4x d0_2 ( | |
1715 | .l1clk(l1clk), | |
1716 | .siclk(siclk), | |
1717 | .soclk(soclk), | |
1718 | .d(fdin[2]), | |
1719 | .si(scan_in), | |
1720 | .so(sout[2]), | |
1721 | .reset(reset), | |
1722 | .q(dout[2]) | |
1723 | ); | |
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | endmodule | |
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | // any PARAMS parms go into naming of macro | |
1743 | ||
1744 | module niu_mb2_msff_ctl_macro__library_a1__reset_1__width_40 ( | |
1745 | din, | |
1746 | reset, | |
1747 | l1clk, | |
1748 | scan_in, | |
1749 | siclk, | |
1750 | soclk, | |
1751 | dout, | |
1752 | scan_out); | |
1753 | wire [39:0] fdin; | |
1754 | wire [39:1] sout; | |
1755 | ||
1756 | input [39:0] din; | |
1757 | input reset; | |
1758 | input l1clk; | |
1759 | input scan_in; | |
1760 | ||
1761 | ||
1762 | input siclk; | |
1763 | input soclk; | |
1764 | ||
1765 | output [39:0] dout; | |
1766 | output scan_out; | |
1767 | assign fdin[39:0] = din[39:0] & {40 {reset}}; | |
1768 | ||
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | ||
1774 | ||
1775 | ||
1776 | ||
1777 | ||
1778 | ||
1779 | ||
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | ||
1785 | cl_a1_msff_syrst_4x d0_0 ( | |
1786 | .l1clk(l1clk), | |
1787 | .siclk(siclk), | |
1788 | .soclk(soclk), | |
1789 | .d(fdin[0]), | |
1790 | .si(sout[1]), | |
1791 | .so(scan_out), | |
1792 | .reset(reset), | |
1793 | .q(dout[0]) | |
1794 | ); | |
1795 | cl_a1_msff_syrst_4x d0_1 ( | |
1796 | .l1clk(l1clk), | |
1797 | .siclk(siclk), | |
1798 | .soclk(soclk), | |
1799 | .d(fdin[1]), | |
1800 | .si(sout[2]), | |
1801 | .so(sout[1]), | |
1802 | .reset(reset), | |
1803 | .q(dout[1]) | |
1804 | ); | |
1805 | cl_a1_msff_syrst_4x d0_2 ( | |
1806 | .l1clk(l1clk), | |
1807 | .siclk(siclk), | |
1808 | .soclk(soclk), | |
1809 | .d(fdin[2]), | |
1810 | .si(sout[3]), | |
1811 | .so(sout[2]), | |
1812 | .reset(reset), | |
1813 | .q(dout[2]) | |
1814 | ); | |
1815 | cl_a1_msff_syrst_4x d0_3 ( | |
1816 | .l1clk(l1clk), | |
1817 | .siclk(siclk), | |
1818 | .soclk(soclk), | |
1819 | .d(fdin[3]), | |
1820 | .si(sout[4]), | |
1821 | .so(sout[3]), | |
1822 | .reset(reset), | |
1823 | .q(dout[3]) | |
1824 | ); | |
1825 | cl_a1_msff_syrst_4x d0_4 ( | |
1826 | .l1clk(l1clk), | |
1827 | .siclk(siclk), | |
1828 | .soclk(soclk), | |
1829 | .d(fdin[4]), | |
1830 | .si(sout[5]), | |
1831 | .so(sout[4]), | |
1832 | .reset(reset), | |
1833 | .q(dout[4]) | |
1834 | ); | |
1835 | cl_a1_msff_syrst_4x d0_5 ( | |
1836 | .l1clk(l1clk), | |
1837 | .siclk(siclk), | |
1838 | .soclk(soclk), | |
1839 | .d(fdin[5]), | |
1840 | .si(sout[6]), | |
1841 | .so(sout[5]), | |
1842 | .reset(reset), | |
1843 | .q(dout[5]) | |
1844 | ); | |
1845 | cl_a1_msff_syrst_4x d0_6 ( | |
1846 | .l1clk(l1clk), | |
1847 | .siclk(siclk), | |
1848 | .soclk(soclk), | |
1849 | .d(fdin[6]), | |
1850 | .si(sout[7]), | |
1851 | .so(sout[6]), | |
1852 | .reset(reset), | |
1853 | .q(dout[6]) | |
1854 | ); | |
1855 | cl_a1_msff_syrst_4x d0_7 ( | |
1856 | .l1clk(l1clk), | |
1857 | .siclk(siclk), | |
1858 | .soclk(soclk), | |
1859 | .d(fdin[7]), | |
1860 | .si(sout[8]), | |
1861 | .so(sout[7]), | |
1862 | .reset(reset), | |
1863 | .q(dout[7]) | |
1864 | ); | |
1865 | cl_a1_msff_syrst_4x d0_8 ( | |
1866 | .l1clk(l1clk), | |
1867 | .siclk(siclk), | |
1868 | .soclk(soclk), | |
1869 | .d(fdin[8]), | |
1870 | .si(sout[9]), | |
1871 | .so(sout[8]), | |
1872 | .reset(reset), | |
1873 | .q(dout[8]) | |
1874 | ); | |
1875 | cl_a1_msff_syrst_4x d0_9 ( | |
1876 | .l1clk(l1clk), | |
1877 | .siclk(siclk), | |
1878 | .soclk(soclk), | |
1879 | .d(fdin[9]), | |
1880 | .si(sout[10]), | |
1881 | .so(sout[9]), | |
1882 | .reset(reset), | |
1883 | .q(dout[9]) | |
1884 | ); | |
1885 | cl_a1_msff_syrst_4x d0_10 ( | |
1886 | .l1clk(l1clk), | |
1887 | .siclk(siclk), | |
1888 | .soclk(soclk), | |
1889 | .d(fdin[10]), | |
1890 | .si(sout[11]), | |
1891 | .so(sout[10]), | |
1892 | .reset(reset), | |
1893 | .q(dout[10]) | |
1894 | ); | |
1895 | cl_a1_msff_syrst_4x d0_11 ( | |
1896 | .l1clk(l1clk), | |
1897 | .siclk(siclk), | |
1898 | .soclk(soclk), | |
1899 | .d(fdin[11]), | |
1900 | .si(sout[12]), | |
1901 | .so(sout[11]), | |
1902 | .reset(reset), | |
1903 | .q(dout[11]) | |
1904 | ); | |
1905 | cl_a1_msff_syrst_4x d0_12 ( | |
1906 | .l1clk(l1clk), | |
1907 | .siclk(siclk), | |
1908 | .soclk(soclk), | |
1909 | .d(fdin[12]), | |
1910 | .si(sout[13]), | |
1911 | .so(sout[12]), | |
1912 | .reset(reset), | |
1913 | .q(dout[12]) | |
1914 | ); | |
1915 | cl_a1_msff_syrst_4x d0_13 ( | |
1916 | .l1clk(l1clk), | |
1917 | .siclk(siclk), | |
1918 | .soclk(soclk), | |
1919 | .d(fdin[13]), | |
1920 | .si(sout[14]), | |
1921 | .so(sout[13]), | |
1922 | .reset(reset), | |
1923 | .q(dout[13]) | |
1924 | ); | |
1925 | cl_a1_msff_syrst_4x d0_14 ( | |
1926 | .l1clk(l1clk), | |
1927 | .siclk(siclk), | |
1928 | .soclk(soclk), | |
1929 | .d(fdin[14]), | |
1930 | .si(sout[15]), | |
1931 | .so(sout[14]), | |
1932 | .reset(reset), | |
1933 | .q(dout[14]) | |
1934 | ); | |
1935 | cl_a1_msff_syrst_4x d0_15 ( | |
1936 | .l1clk(l1clk), | |
1937 | .siclk(siclk), | |
1938 | .soclk(soclk), | |
1939 | .d(fdin[15]), | |
1940 | .si(sout[16]), | |
1941 | .so(sout[15]), | |
1942 | .reset(reset), | |
1943 | .q(dout[15]) | |
1944 | ); | |
1945 | cl_a1_msff_syrst_4x d0_16 ( | |
1946 | .l1clk(l1clk), | |
1947 | .siclk(siclk), | |
1948 | .soclk(soclk), | |
1949 | .d(fdin[16]), | |
1950 | .si(sout[17]), | |
1951 | .so(sout[16]), | |
1952 | .reset(reset), | |
1953 | .q(dout[16]) | |
1954 | ); | |
1955 | cl_a1_msff_syrst_4x d0_17 ( | |
1956 | .l1clk(l1clk), | |
1957 | .siclk(siclk), | |
1958 | .soclk(soclk), | |
1959 | .d(fdin[17]), | |
1960 | .si(sout[18]), | |
1961 | .so(sout[17]), | |
1962 | .reset(reset), | |
1963 | .q(dout[17]) | |
1964 | ); | |
1965 | cl_a1_msff_syrst_4x d0_18 ( | |
1966 | .l1clk(l1clk), | |
1967 | .siclk(siclk), | |
1968 | .soclk(soclk), | |
1969 | .d(fdin[18]), | |
1970 | .si(sout[19]), | |
1971 | .so(sout[18]), | |
1972 | .reset(reset), | |
1973 | .q(dout[18]) | |
1974 | ); | |
1975 | cl_a1_msff_syrst_4x d0_19 ( | |
1976 | .l1clk(l1clk), | |
1977 | .siclk(siclk), | |
1978 | .soclk(soclk), | |
1979 | .d(fdin[19]), | |
1980 | .si(sout[20]), | |
1981 | .so(sout[19]), | |
1982 | .reset(reset), | |
1983 | .q(dout[19]) | |
1984 | ); | |
1985 | cl_a1_msff_syrst_4x d0_20 ( | |
1986 | .l1clk(l1clk), | |
1987 | .siclk(siclk), | |
1988 | .soclk(soclk), | |
1989 | .d(fdin[20]), | |
1990 | .si(sout[21]), | |
1991 | .so(sout[20]), | |
1992 | .reset(reset), | |
1993 | .q(dout[20]) | |
1994 | ); | |
1995 | cl_a1_msff_syrst_4x d0_21 ( | |
1996 | .l1clk(l1clk), | |
1997 | .siclk(siclk), | |
1998 | .soclk(soclk), | |
1999 | .d(fdin[21]), | |
2000 | .si(sout[22]), | |
2001 | .so(sout[21]), | |
2002 | .reset(reset), | |
2003 | .q(dout[21]) | |
2004 | ); | |
2005 | cl_a1_msff_syrst_4x d0_22 ( | |
2006 | .l1clk(l1clk), | |
2007 | .siclk(siclk), | |
2008 | .soclk(soclk), | |
2009 | .d(fdin[22]), | |
2010 | .si(sout[23]), | |
2011 | .so(sout[22]), | |
2012 | .reset(reset), | |
2013 | .q(dout[22]) | |
2014 | ); | |
2015 | cl_a1_msff_syrst_4x d0_23 ( | |
2016 | .l1clk(l1clk), | |
2017 | .siclk(siclk), | |
2018 | .soclk(soclk), | |
2019 | .d(fdin[23]), | |
2020 | .si(sout[24]), | |
2021 | .so(sout[23]), | |
2022 | .reset(reset), | |
2023 | .q(dout[23]) | |
2024 | ); | |
2025 | cl_a1_msff_syrst_4x d0_24 ( | |
2026 | .l1clk(l1clk), | |
2027 | .siclk(siclk), | |
2028 | .soclk(soclk), | |
2029 | .d(fdin[24]), | |
2030 | .si(sout[25]), | |
2031 | .so(sout[24]), | |
2032 | .reset(reset), | |
2033 | .q(dout[24]) | |
2034 | ); | |
2035 | cl_a1_msff_syrst_4x d0_25 ( | |
2036 | .l1clk(l1clk), | |
2037 | .siclk(siclk), | |
2038 | .soclk(soclk), | |
2039 | .d(fdin[25]), | |
2040 | .si(sout[26]), | |
2041 | .so(sout[25]), | |
2042 | .reset(reset), | |
2043 | .q(dout[25]) | |
2044 | ); | |
2045 | cl_a1_msff_syrst_4x d0_26 ( | |
2046 | .l1clk(l1clk), | |
2047 | .siclk(siclk), | |
2048 | .soclk(soclk), | |
2049 | .d(fdin[26]), | |
2050 | .si(sout[27]), | |
2051 | .so(sout[26]), | |
2052 | .reset(reset), | |
2053 | .q(dout[26]) | |
2054 | ); | |
2055 | cl_a1_msff_syrst_4x d0_27 ( | |
2056 | .l1clk(l1clk), | |
2057 | .siclk(siclk), | |
2058 | .soclk(soclk), | |
2059 | .d(fdin[27]), | |
2060 | .si(sout[28]), | |
2061 | .so(sout[27]), | |
2062 | .reset(reset), | |
2063 | .q(dout[27]) | |
2064 | ); | |
2065 | cl_a1_msff_syrst_4x d0_28 ( | |
2066 | .l1clk(l1clk), | |
2067 | .siclk(siclk), | |
2068 | .soclk(soclk), | |
2069 | .d(fdin[28]), | |
2070 | .si(sout[29]), | |
2071 | .so(sout[28]), | |
2072 | .reset(reset), | |
2073 | .q(dout[28]) | |
2074 | ); | |
2075 | cl_a1_msff_syrst_4x d0_29 ( | |
2076 | .l1clk(l1clk), | |
2077 | .siclk(siclk), | |
2078 | .soclk(soclk), | |
2079 | .d(fdin[29]), | |
2080 | .si(sout[30]), | |
2081 | .so(sout[29]), | |
2082 | .reset(reset), | |
2083 | .q(dout[29]) | |
2084 | ); | |
2085 | cl_a1_msff_syrst_4x d0_30 ( | |
2086 | .l1clk(l1clk), | |
2087 | .siclk(siclk), | |
2088 | .soclk(soclk), | |
2089 | .d(fdin[30]), | |
2090 | .si(sout[31]), | |
2091 | .so(sout[30]), | |
2092 | .reset(reset), | |
2093 | .q(dout[30]) | |
2094 | ); | |
2095 | cl_a1_msff_syrst_4x d0_31 ( | |
2096 | .l1clk(l1clk), | |
2097 | .siclk(siclk), | |
2098 | .soclk(soclk), | |
2099 | .d(fdin[31]), | |
2100 | .si(sout[32]), | |
2101 | .so(sout[31]), | |
2102 | .reset(reset), | |
2103 | .q(dout[31]) | |
2104 | ); | |
2105 | cl_a1_msff_syrst_4x d0_32 ( | |
2106 | .l1clk(l1clk), | |
2107 | .siclk(siclk), | |
2108 | .soclk(soclk), | |
2109 | .d(fdin[32]), | |
2110 | .si(sout[33]), | |
2111 | .so(sout[32]), | |
2112 | .reset(reset), | |
2113 | .q(dout[32]) | |
2114 | ); | |
2115 | cl_a1_msff_syrst_4x d0_33 ( | |
2116 | .l1clk(l1clk), | |
2117 | .siclk(siclk), | |
2118 | .soclk(soclk), | |
2119 | .d(fdin[33]), | |
2120 | .si(sout[34]), | |
2121 | .so(sout[33]), | |
2122 | .reset(reset), | |
2123 | .q(dout[33]) | |
2124 | ); | |
2125 | cl_a1_msff_syrst_4x d0_34 ( | |
2126 | .l1clk(l1clk), | |
2127 | .siclk(siclk), | |
2128 | .soclk(soclk), | |
2129 | .d(fdin[34]), | |
2130 | .si(sout[35]), | |
2131 | .so(sout[34]), | |
2132 | .reset(reset), | |
2133 | .q(dout[34]) | |
2134 | ); | |
2135 | cl_a1_msff_syrst_4x d0_35 ( | |
2136 | .l1clk(l1clk), | |
2137 | .siclk(siclk), | |
2138 | .soclk(soclk), | |
2139 | .d(fdin[35]), | |
2140 | .si(sout[36]), | |
2141 | .so(sout[35]), | |
2142 | .reset(reset), | |
2143 | .q(dout[35]) | |
2144 | ); | |
2145 | cl_a1_msff_syrst_4x d0_36 ( | |
2146 | .l1clk(l1clk), | |
2147 | .siclk(siclk), | |
2148 | .soclk(soclk), | |
2149 | .d(fdin[36]), | |
2150 | .si(sout[37]), | |
2151 | .so(sout[36]), | |
2152 | .reset(reset), | |
2153 | .q(dout[36]) | |
2154 | ); | |
2155 | cl_a1_msff_syrst_4x d0_37 ( | |
2156 | .l1clk(l1clk), | |
2157 | .siclk(siclk), | |
2158 | .soclk(soclk), | |
2159 | .d(fdin[37]), | |
2160 | .si(sout[38]), | |
2161 | .so(sout[37]), | |
2162 | .reset(reset), | |
2163 | .q(dout[37]) | |
2164 | ); | |
2165 | cl_a1_msff_syrst_4x d0_38 ( | |
2166 | .l1clk(l1clk), | |
2167 | .siclk(siclk), | |
2168 | .soclk(soclk), | |
2169 | .d(fdin[38]), | |
2170 | .si(sout[39]), | |
2171 | .so(sout[38]), | |
2172 | .reset(reset), | |
2173 | .q(dout[38]) | |
2174 | ); | |
2175 | cl_a1_msff_syrst_4x d0_39 ( | |
2176 | .l1clk(l1clk), | |
2177 | .siclk(siclk), | |
2178 | .soclk(soclk), | |
2179 | .d(fdin[39]), | |
2180 | .si(scan_in), | |
2181 | .so(sout[39]), | |
2182 | .reset(reset), | |
2183 | .q(dout[39]) | |
2184 | ); | |
2185 | ||
2186 | ||
2187 | ||
2188 | ||
2189 | endmodule | |
2190 | ||
2191 | ||
2192 | ||
2193 | ||
2194 | ||
2195 | ||
2196 | ||
2197 |