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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_mb6.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | /////////////////////////////////////////////////////////////////////////////// | |
37 | // | |
38 | // | |
39 | // Released: 1/16/05 | |
40 | // Contacts: carlos.castil@sun.com / shahryar.aryani@sun.com | |
41 | // Description: Memory BIST Controller for Niagara2 NIU core | |
42 | // Block Type: Control Block | |
43 | // Chip Name: | |
44 | // Unit Name: | |
45 | // Module: | |
46 | // Where Instantiated: | |
47 | // | |
48 | // | |
49 | // (c) 2005 Sun Microsystems, Inc. | |
50 | // Sun Proprietary/Confidential | |
51 | // Internal use only. | |
52 | // | |
53 | // All rights reserved. No part of this design may be reproduced stored | |
54 | // in a retrieval system, or transmitted, in any form or by any means, | |
55 | // electronic, mechanical, photocopying, recording, or otherwise, without | |
56 | // prior written permission of Sun Microsystems, Inc. | |
57 | // | |
58 | /////////////////////////////////////////////////////////////////////////////// | |
59 | ||
60 | ||
61 | module niu_mb6 ( | |
62 | niu_mb6_tcam_array_rd_en, | |
63 | niu_mb6_tcam_array_wr_en, | |
64 | niu_mb6_vlan_rd_en, | |
65 | niu_mb6_vlan_wr_en, | |
66 | niu_mb6_addr, | |
67 | niu_mb6_wdata, | |
68 | niu_mb6_run, | |
69 | niu_tcu_mbist_fail_6, | |
70 | niu_tcu_mbist_done_6, | |
71 | mb6_scan_out, | |
72 | mb6_dmo_dout, | |
73 | l1clk, | |
74 | rst, | |
75 | tcu_mbist_user_mode, | |
76 | mb6_scan_in, | |
77 | tcu_aclk, | |
78 | tcu_bclk, | |
79 | tcu_niu_mbist_start_6, | |
80 | niu_mb6_tcam_array_data_out, | |
81 | niu_mb6_vlan_data_out, | |
82 | tcu_mbist_bisi_en); | |
83 | wire siclk; | |
84 | wire soclk; | |
85 | wire reset; | |
86 | wire config_reg_scanin; | |
87 | wire config_reg_scanout; | |
88 | wire [7:0] config_in; | |
89 | wire [7:0] config_out; | |
90 | wire start_transition; | |
91 | wire reset_engine; | |
92 | wire mbist_user_loop_mode; | |
93 | wire mbist_done; | |
94 | wire run; | |
95 | wire bisi; | |
96 | wire user_mode; | |
97 | wire user_data_mode; | |
98 | wire user_addr_mode; | |
99 | wire user_loop_mode; | |
100 | wire ten_n_mode; | |
101 | wire mbist_user_data_mode; | |
102 | wire mbist_user_addr_mode; | |
103 | wire mbist_ten_n_mode; | |
104 | wire user_data_reg_scanin; | |
105 | wire user_data_reg_scanout; | |
106 | wire [7:0] user_data_in; | |
107 | wire [7:0] user_data_out; | |
108 | wire user_start_addr_reg_scanin; | |
109 | wire user_start_addr_reg_scanout; | |
110 | wire [11:0] user_start_addr_in; | |
111 | wire [11:0] user_start_addr; | |
112 | wire user_stop_addr_reg_scanin; | |
113 | wire user_stop_addr_reg_scanout; | |
114 | wire [11:0] user_stop_addr_in; | |
115 | wire [11:0] user_stop_addr; | |
116 | wire user_incr_addr_reg_scanin; | |
117 | wire user_incr_addr_reg_scanout; | |
118 | wire [11:0] user_incr_addr_in; | |
119 | wire [11:0] user_incr_addr; | |
120 | wire user_array_sel_reg_scanin; | |
121 | wire user_array_sel_reg_scanout; | |
122 | wire user_array_sel_in; | |
123 | wire user_array_sel; | |
124 | wire user_bisi_wr_reg_scanin; | |
125 | wire user_bisi_wr_reg_scanout; | |
126 | wire user_bisi_wr_mode_in; | |
127 | wire user_bisi_wr_mode; | |
128 | wire user_bisi_rd_reg_scanin; | |
129 | wire user_bisi_rd_reg_scanout; | |
130 | wire user_bisi_rd_mode_in; | |
131 | wire user_bisi_rd_mode; | |
132 | wire mbist_user_bisi_wr_mode; | |
133 | wire mbist_user_bisi_wr_rd_mode; | |
134 | wire start_transition_reg_scanin; | |
135 | wire start_transition_reg_scanout; | |
136 | wire start_transition_piped; | |
137 | wire run_reg_scanin; | |
138 | wire run_reg_scanout; | |
139 | wire run1_reg_scanin; | |
140 | wire run1_reg_scanout; | |
141 | wire run1_in; | |
142 | wire run1_out; | |
143 | wire run2_reg_scanin; | |
144 | wire run2_reg_scanout; | |
145 | wire run2_in; | |
146 | wire run2_out; | |
147 | wire run_piped3; | |
148 | wire msb; | |
149 | wire control_reg_scanin; | |
150 | wire control_reg_scanout; | |
151 | wire [24:0] control_in; | |
152 | wire [24:0] control_out; | |
153 | wire bisi_wr_rd; | |
154 | wire array_sel; | |
155 | wire [1:0] data_control; | |
156 | wire address_mix; | |
157 | wire [3:0] march_element; | |
158 | wire [11:0] array_address; | |
159 | wire upaddress_march; | |
160 | wire [2:0] read_write_control; | |
161 | wire five_cycle_march; | |
162 | wire one_cycle_march; | |
163 | wire increment_addr; | |
164 | wire [11:0] start_addr; | |
165 | wire [11:0] next_array_address; | |
166 | wire next_upaddr_march; | |
167 | wire next_downaddr_march; | |
168 | wire [11:0] stop_addr; | |
169 | wire [12:0] overflow_addr; | |
170 | wire array_sel1; | |
171 | wire [11:0] incr_addr; | |
172 | wire overflow; | |
173 | wire [12:0] compare_addr; | |
174 | wire [11:0] add; | |
175 | wire [11:0] adj_address; | |
176 | wire [11:0] mbist_address; | |
177 | wire array_sel0; | |
178 | wire increment_march_elem; | |
179 | wire next_array_sel; | |
180 | wire [1:0] next_data_control; | |
181 | wire next_address_mix; | |
182 | wire [3:0] next_march_element; | |
183 | wire array_write; | |
184 | wire array_read; | |
185 | wire [7:0] mbist_wdata; | |
186 | wire true_data; | |
187 | wire [7:0] data_pattern; | |
188 | wire done_counter_reg_scanin; | |
189 | wire done_counter_reg_scanout; | |
190 | wire [2:0] done_counter_in; | |
191 | wire [2:0] done_counter_out; | |
192 | wire done_reg_in; | |
193 | wire done_reg_out; | |
194 | wire done_reg_scanin; | |
195 | wire done_reg_scanout; | |
196 | wire data_pipe_reg1_scanin; | |
197 | wire data_pipe_reg1_scanout; | |
198 | wire [7:0] data_pipe_reg1_in; | |
199 | wire [7:0] data_pipe_out1; | |
200 | wire data_pipe_reg2_scanin; | |
201 | wire data_pipe_reg2_scanout; | |
202 | wire [7:0] data_pipe_reg2_in; | |
203 | wire [7:0] data_pipe_out2; | |
204 | wire [7:0] old_piped_data; | |
205 | wire ren_pipe_reg1_scanin; | |
206 | wire ren_pipe_reg1_scanout; | |
207 | wire ren_pipe_reg1_in; | |
208 | wire ren_pipe_out1; | |
209 | wire ren_pipe_reg2_scanin; | |
210 | wire ren_pipe_reg2_scanout; | |
211 | wire ren_pipe_reg2_in; | |
212 | wire ren_pipe_out2; | |
213 | wire old_piped_ren; | |
214 | wire sel_pipe_reg1_scanin; | |
215 | wire sel_pipe_reg1_scanout; | |
216 | wire sel_pipe_reg1_in; | |
217 | wire sel_pipe_out1; | |
218 | wire sel_pipe_reg2_scanin; | |
219 | wire sel_pipe_reg2_scanout; | |
220 | wire sel_pipe_reg2_in; | |
221 | wire sel_pipe_out2; | |
222 | wire old_piped_sel2; | |
223 | wire read_data_pipe_reg0_scanin; | |
224 | wire read_data_pipe_reg0_scanout; | |
225 | wire [8:0] read_data_pipe0; | |
226 | wire read_data_pipe_reg1_scanin; | |
227 | wire read_data_pipe_reg1_scanout; | |
228 | wire [41:0] read_data_pipe1; | |
229 | wire fail_out_reg_in; | |
230 | wire fail; | |
231 | wire fail_out_reg_out; | |
232 | wire fail_out_reg_scanin; | |
233 | wire fail_out_reg_scanout; | |
234 | wire fail_reg_scanin; | |
235 | wire fail_reg_scanout; | |
236 | wire [1:0] fail_reg_in; | |
237 | wire [1:0] fail_reg_out; | |
238 | wire qual_old_fail1; | |
239 | wire qual_old_fail0; | |
240 | wire fail_detect; | |
241 | wire qual_old_fail; | |
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | // ///////////////////////////////////////////////////////////////////////////// | |
248 | // Outputs | |
249 | // ///////////////////////////////////////////////////////////////////////////// | |
250 | ||
251 | output niu_mb6_tcam_array_rd_en; | |
252 | output niu_mb6_tcam_array_wr_en; | |
253 | ||
254 | output niu_mb6_vlan_rd_en; | |
255 | output niu_mb6_vlan_wr_en; | |
256 | ||
257 | output [11:0] niu_mb6_addr; | |
258 | output [7:0] niu_mb6_wdata; | |
259 | ||
260 | output niu_mb6_run; | |
261 | ||
262 | output niu_tcu_mbist_fail_6; | |
263 | output niu_tcu_mbist_done_6; | |
264 | ||
265 | output mb6_scan_out; | |
266 | ||
267 | output [39:0] mb6_dmo_dout; | |
268 | ||
269 | ||
270 | // ///////////////////////////////////////////////////////////////////////////// | |
271 | // Inputs | |
272 | // ///////////////////////////////////////////////////////////////////////////// | |
273 | ||
274 | input l1clk; | |
275 | input rst; | |
276 | input tcu_mbist_user_mode; | |
277 | ||
278 | input mb6_scan_in; | |
279 | input tcu_aclk; | |
280 | input tcu_bclk; | |
281 | ||
282 | input tcu_niu_mbist_start_6; | |
283 | ||
284 | input [41:0] niu_mb6_tcam_array_data_out; | |
285 | input [8:0] niu_mb6_vlan_data_out; | |
286 | ||
287 | input tcu_mbist_bisi_en; | |
288 | ||
289 | ||
290 | // ///////////////////////////////////////////////////////////////////////////// | |
291 | // Scan Renames | |
292 | // ///////////////////////////////////////////////////////////////////////////// | |
293 | ||
294 | // assign se = tcu_scan_en; | |
295 | // assign pce_ov = tcu_pce_ov; | |
296 | // assign stop = tcu_clk_stop; | |
297 | ||
298 | assign siclk = tcu_aclk; | |
299 | assign soclk = tcu_bclk; | |
300 | ||
301 | ||
302 | // ///////////////////////////////////////////////////////////////////////////// | |
303 | // Invert reset | |
304 | // ///////////////////////////////////////////////////////////////////////////// | |
305 | ||
306 | assign reset = ~rst; | |
307 | ||
308 | ||
309 | //////////////////////////////////////////////////////////////////////////////// | |
310 | // Clock header | |
311 | ||
312 | // l1clkhdr_ctl_macro clkgen ( | |
313 | // .l2clk (iol2clk ), | |
314 | // .l1en (1'b1 ), | |
315 | // .l1clk (l1clk ) | |
316 | // ); | |
317 | //assign siclk = 1'b0; | |
318 | //assign soclk = 1'b0; | |
319 | ||
320 | ||
321 | // ///////////////////////////////////////////////////////////////////////////// | |
322 | // | |
323 | // MBIST Config Register | |
324 | // | |
325 | // ///////////////////////////////////////////////////////////////////////////// | |
326 | // | |
327 | // A low to high transition on mbist_start will reset and start the engine. | |
328 | // mbist_start must remain active high for the duration of MBIST. | |
329 | // If mbist_start deasserts the engine will stop but not reset. | |
330 | // Once MBIST has completed niu_tcu_mbist_done_6 will assert and the fail status | |
331 | // signals will be valid. | |
332 | // To run MBIST again the mbist_start signal must transition low then high. | |
333 | // | |
334 | // Loop on Address will disable the address mix function. | |
335 | // | |
336 | // ///////////////////////////////////////////////////////////////////////////// | |
337 | ||
338 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_8 config_reg ( | |
339 | .scan_in(config_reg_scanin), | |
340 | .scan_out(config_reg_scanout), | |
341 | .din ( config_in[7:0] ), | |
342 | .dout ( config_out[7:0] ), | |
343 | .reset(reset), | |
344 | .l1clk(l1clk), | |
345 | .siclk(siclk), | |
346 | .soclk(soclk)); | |
347 | ||
348 | ||
349 | assign config_in[0] = tcu_niu_mbist_start_6; | |
350 | assign config_in[1] = config_out[0]; | |
351 | assign start_transition = config_out[0] & ~config_out[1]; | |
352 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
353 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
354 | ||
355 | assign config_in[2] = start_transition ? tcu_mbist_bisi_en: config_out[2]; | |
356 | assign bisi = config_out[2]; | |
357 | ||
358 | assign config_in[3] = start_transition ? tcu_mbist_user_mode : config_out[3]; | |
359 | assign user_mode = config_out[3]; | |
360 | ||
361 | assign config_in[4] = config_out[4]; | |
362 | assign user_data_mode = config_out[4]; | |
363 | ||
364 | assign config_in[5] = config_out[5]; | |
365 | assign user_addr_mode = config_out[5]; | |
366 | ||
367 | assign config_in[6] = config_out[6]; | |
368 | assign user_loop_mode = config_out[6]; | |
369 | ||
370 | assign config_in[7] = config_out[7]; | |
371 | assign ten_n_mode = config_out[7]; | |
372 | ||
373 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
374 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
375 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
376 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
377 | ||
378 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( | |
379 | .scan_in(user_data_reg_scanin), | |
380 | .scan_out(user_data_reg_scanout), | |
381 | .din ( user_data_in[7:0] ), | |
382 | .dout ( user_data_out[7:0] ), | |
383 | .reset(reset), | |
384 | .l1clk(l1clk), | |
385 | .siclk(siclk), | |
386 | .soclk(soclk)); | |
387 | ||
388 | ||
389 | assign user_data_in[7:0] = user_data_out[7:0]; | |
390 | ||
391 | ||
392 | // Defining User start, stop, and increment addresses. | |
393 | ||
394 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_12 user_start_addr_reg ( | |
395 | .scan_in(user_start_addr_reg_scanin), | |
396 | .scan_out(user_start_addr_reg_scanout), | |
397 | .din ( user_start_addr_in[11:0] ), | |
398 | .dout ( user_start_addr[11:0] ), | |
399 | .reset(reset), | |
400 | .l1clk(l1clk), | |
401 | .siclk(siclk), | |
402 | .soclk(soclk)); | |
403 | ||
404 | assign user_start_addr_in[11:0] = user_start_addr[11:0]; | |
405 | ||
406 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_12 user_stop_addr_reg ( | |
407 | .scan_in(user_stop_addr_reg_scanin), | |
408 | .scan_out(user_stop_addr_reg_scanout), | |
409 | .din ( user_stop_addr_in[11:0] ), | |
410 | .dout ( user_stop_addr[11:0] ), | |
411 | .reset(reset), | |
412 | .l1clk(l1clk), | |
413 | .siclk(siclk), | |
414 | .soclk(soclk)); | |
415 | ||
416 | assign user_stop_addr_in[11:0] = user_stop_addr[11:0]; | |
417 | ||
418 | ||
419 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_12 user_incr_addr_reg ( | |
420 | .scan_in(user_incr_addr_reg_scanin), | |
421 | .scan_out(user_incr_addr_reg_scanout), | |
422 | .din ( user_incr_addr_in[11:0] ), | |
423 | .dout ( user_incr_addr[11:0] ), | |
424 | .reset(reset), | |
425 | .l1clk(l1clk), | |
426 | .siclk(siclk), | |
427 | .soclk(soclk)); | |
428 | ||
429 | assign user_incr_addr_in[11:0] = user_incr_addr[11:0]; | |
430 | ||
431 | // Defining User array_sel. | |
432 | ||
433 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 user_array_sel_reg ( | |
434 | .scan_in(user_array_sel_reg_scanin), | |
435 | .scan_out(user_array_sel_reg_scanout), | |
436 | .din ( user_array_sel_in ), | |
437 | .dout ( user_array_sel ), | |
438 | .reset(reset), | |
439 | .l1clk(l1clk), | |
440 | .siclk(siclk), | |
441 | .soclk(soclk)); | |
442 | ||
443 | assign user_array_sel_in = user_array_sel; | |
444 | ||
445 | // Defining user_bisi write and read registers | |
446 | ||
447 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( | |
448 | .scan_in(user_bisi_wr_reg_scanin), | |
449 | .scan_out(user_bisi_wr_reg_scanout), | |
450 | .din ( user_bisi_wr_mode_in ), | |
451 | .dout ( user_bisi_wr_mode ), | |
452 | .reset(reset), | |
453 | .l1clk(l1clk), | |
454 | .siclk(siclk), | |
455 | .soclk(soclk)); | |
456 | ||
457 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
458 | ||
459 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( | |
460 | .scan_in(user_bisi_rd_reg_scanin), | |
461 | .scan_out(user_bisi_rd_reg_scanout), | |
462 | .din ( user_bisi_rd_mode_in ), | |
463 | .dout ( user_bisi_rd_mode ), | |
464 | .reset(reset), | |
465 | .l1clk(l1clk), | |
466 | .siclk(siclk), | |
467 | .soclk(soclk)); | |
468 | ||
469 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
470 | ||
471 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
472 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
473 | ||
474 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
475 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
476 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
477 | ||
478 | //////////////////////////////////////////////////////////////////////////////// | |
479 | // Piping start_transition | |
480 | //////////////////////////////////////////////////////////////////////////////// | |
481 | ||
482 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( | |
483 | .scan_in(start_transition_reg_scanin), | |
484 | .scan_out(start_transition_reg_scanout), | |
485 | .din ( start_transition ), | |
486 | .dout ( start_transition_piped ), | |
487 | .reset(reset), | |
488 | .l1clk(l1clk), | |
489 | .siclk(siclk), | |
490 | .soclk(soclk)); | |
491 | ||
492 | ||
493 | //////////////////////////////////////////////////////////////////////////////// | |
494 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. | |
495 | //////////////////////////////////////////////////////////////////////////////// | |
496 | ||
497 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( | |
498 | .scan_in(run_reg_scanin), | |
499 | .scan_out(run_reg_scanout), | |
500 | .din ( run ), | |
501 | .dout ( niu_mb6_run ), | |
502 | .reset(reset), | |
503 | .l1clk(l1clk), | |
504 | .siclk(siclk), | |
505 | .soclk(soclk)); | |
506 | ||
507 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( | |
508 | .scan_in(run1_reg_scanin), | |
509 | .scan_out(run1_reg_scanout), | |
510 | .din ( run1_in ), | |
511 | .dout ( run1_out ), | |
512 | .reset(reset), | |
513 | .l1clk(l1clk), | |
514 | .siclk(siclk), | |
515 | .soclk(soclk)); | |
516 | ||
517 | assign run1_in = reset_engine ? 1'b0: niu_mb6_run; | |
518 | ||
519 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( | |
520 | .scan_in(run2_reg_scanin), | |
521 | .scan_out(run2_reg_scanout), | |
522 | .din ( run2_in ), | |
523 | .dout ( run2_out ), | |
524 | .reset(reset), | |
525 | .l1clk(l1clk), | |
526 | .siclk(siclk), | |
527 | .soclk(soclk)); | |
528 | ||
529 | assign run2_in = reset_engine ? 1'b0: run1_out; | |
530 | assign run_piped3 = config_out[0] & run2_out & ~msb; | |
531 | ||
532 | ||
533 | // ///////////////////////////////////////////////////////////////////////////// | |
534 | // | |
535 | // MBIST Control Register | |
536 | // | |
537 | // ///////////////////////////////////////////////////////////////////////////// | |
538 | // Remove Address mix disable before delivery | |
539 | // ///////////////////////////////////////////////////////////////////////////// | |
540 | ||
541 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_25 control_reg ( | |
542 | .scan_in(control_reg_scanin), | |
543 | .scan_out(control_reg_scanout), | |
544 | .din ( control_in[24:0] ), | |
545 | .dout ( control_out[24:0] ), | |
546 | .reset(reset), | |
547 | .l1clk(l1clk), | |
548 | .siclk(siclk), | |
549 | .soclk(soclk)); | |
550 | ||
551 | assign msb = control_out[24]; | |
552 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[23] : 1'b1; | |
553 | assign array_sel = user_mode ? user_array_sel : control_out[22]; | |
554 | assign data_control[1:0] = control_out[21:20]; | |
555 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0 : control_out[19]; | |
556 | assign march_element[3:0] = control_out[18:15]; | |
557 | ||
558 | assign array_address[11:0] = array_sel & upaddress_march ? {5'b11111, control_out[9:3]} : | |
559 | array_sel & (~upaddress_march) ? {5'b11111,~control_out[9:3]} : | |
560 | (~array_sel) & upaddress_march ? {control_out[14:3]} : ~control_out[14:3]; | |
561 | ||
562 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
563 | control_out[2:0]; | |
564 | ||
565 | ||
566 | assign control_in[2:0] = reset_engine ? 3'b0: | |
567 | ~run_piped3 ? control_out[2:0]: | |
568 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
569 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: | |
570 | control_out[2:0] + 3'b001; | |
571 | ||
572 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
573 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || | |
574 | (read_write_control[2:0] == 3'b111); | |
575 | ||
576 | // start_transition_piped was added to have the correct start_addr at the start | |
577 | // of mbist during user_addr_mode | |
578 | // assign control_in[14:3] = start_transition_piped || reset_engine ? start_addr[11:0]: | |
579 | // ~run_piped3 || ~increment_addr ? control_out[14:3]: | |
580 | // next_array_address[11:0]; | |
581 | ||
582 | assign control_in[14:3] = (start_transition_piped || reset_engine) ? start_addr[11:0]: | |
583 | ~run_piped3 || ~increment_addr ? control_out[14:3]: | |
584 | next_array_address[11:0]; | |
585 | ||
586 | ||
587 | assign next_array_address[11:0] = next_upaddr_march ? start_addr[11:0]: | |
588 | next_downaddr_march ? ~stop_addr[11:0]: | |
589 | (overflow_addr[11:0]); // array_addr + incr_addr | |
590 | ||
591 | assign start_addr[11:0] = mbist_user_addr_mode ? user_start_addr[11:0]: 12'h000; | |
592 | assign stop_addr[11:0] = mbist_user_addr_mode ? user_stop_addr[11:0] : | |
593 | array_sel1 ? 12'h07F : 12'hFFF; | |
594 | ||
595 | assign incr_addr[11:0] = mbist_user_addr_mode ? user_incr_addr[11:0] : 12'h001; | |
596 | ||
597 | assign overflow_addr[12:0] = {1'b0,control_out[14:3]} + {1'b0,incr_addr[11:0]}; | |
598 | assign overflow = compare_addr[12:0] < overflow_addr[12:0]; | |
599 | ||
600 | assign compare_addr[12:0] = upaddress_march ? {1'b0, stop_addr[11:0]} : | |
601 | {1'b0, ~start_addr[11:0]}; | |
602 | ||
603 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
604 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
605 | (march_element[3:0] == 4'h8) ) && overflow; | |
606 | ||
607 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
608 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
609 | overflow; | |
610 | ||
611 | assign add[11:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
612 | (read_write_control[2:0] == 3'h3)) ? | |
613 | adj_address[11:0] : array_address[11:0]; | |
614 | ||
615 | // cc 051505 question ? | |
616 | // is niu_mb6 testing 2 bit col addr arrays ???? cc 051505 | |
617 | // assign adj_address[5:0] = array_sel1 ? { array_address[5:3], ~array_address[2], array_address[1:0]} : //2 bit col addr | |
618 | ||
619 | assign adj_address[11:0] = array_sel1 ? { array_address[11:2], ~array_address[1], array_address[0]} : | |
620 | { array_address[11:6], ~array_address[5], array_address[4:0]}; | |
621 | // in non-address mix mode row addr collumn addr | |
622 | ||
623 | // cc 011505 question? | |
624 | // is niu_mb6 testing "Fast bank" or "Fast row" arrays ? assume Random | |
625 | // assign mbist_address[5:0] = address_mix & tdb_sel ? {add[1:0],add[8:2]}: // Fast row | |
626 | // address_mix & diu_sel ? {add[8], add[5:0], add[7:6]}: // Fast bank | |
627 | // address_mix & dma_data_sel ? {add[8:7], add[5:0], add[6]}: // Fast bank | |
628 | // address_mix & pio_data_sel ? {add[8:4], add[2:0], add[3]}: // Random | |
629 | // address_mix & dev_sel ? {add[8:4], add[2:0], add[3]}: // Random | |
630 | // address_mix & tsb_sel ? {add[8:5], add[3:0], add[4]}: // Fast bank | |
631 | // add[8:0]; // Needs to be verified!!! | |
632 | ||
633 | assign mbist_address[11:0] = (address_mix & array_sel0) ? {add[4:0], add[11:5]}: | |
634 | (address_mix & array_sel1) ? {add[11:7], add[0], add[6:1]} : add[11:0]; | |
635 | ||
636 | // Definition of the rest of the control register | |
637 | ||
638 | assign increment_march_elem = increment_addr && overflow; | |
639 | ||
640 | assign control_in[24:15] = reset_engine ? 10'b0: | |
641 | ~run_piped3 ? control_out[24:15]: | |
642 | {msb, bisi_wr_rd, next_array_sel, next_data_control[1:0], next_address_mix, next_march_element[3:0]} + | |
643 | {9'b0, increment_march_elem}; | |
644 | ||
645 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; | |
646 | ||
647 | assign next_array_sel = user_mode ? 1'b1 : control_out[22]; | |
648 | ||
649 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
650 | data_control[1:0]; | |
651 | ||
652 | // Incorporated ten_n_mode! | |
653 | assign next_march_element[3:0] = ( bisi || | |
654 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
655 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
656 | && overflow ? 4'b1111: march_element[3:0]; | |
657 | ||
658 | ||
659 | assign array_write = ~run_piped3 ? 1'b0: | |
660 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
661 | (read_write_control[2:0] == 3'h1) || | |
662 | (read_write_control[2:0] == 3'h4): | |
663 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: | |
664 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); | |
665 | ||
666 | assign array_read = ~array_write && run_piped3; // && ~initialize; | |
667 | ||
668 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
669 | ||
670 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
671 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
672 | (march_element[3:0] == 4'h7); | |
673 | ||
674 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
675 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
676 | (march_element[3:0] == 4'h7); | |
677 | ||
678 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
679 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
680 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
681 | ((read_write_control[2:0] == 3'h1) || | |
682 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
683 | one_cycle_march ? (march_element[3:0] == 4'h7): | |
684 | ~(read_write_control[0] ^ march_element[0]); | |
685 | ||
686 | ||
687 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
688 | mbist_user_data_mode ? user_data_out[7:0]: | |
689 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
690 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
691 | (data_control[1:0] == 2'h1) ? 8'h99: | |
692 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
693 | 8'h00; | |
694 | ||
695 | // ///////////////////////////////////////////////////////////////////////////// | |
696 | // Write data and address may need pipelining !!! | |
697 | // ///////////////////////////////////////////////////////////////////////////// | |
698 | ||
699 | assign niu_mb6_wdata[7:0] = mbist_wdata[7:0]; | |
700 | assign niu_mb6_addr[11:0] = mbist_address[11:0]; | |
701 | ||
702 | ||
703 | // ///////////////////////////////////////////////////////////////////////////// | |
704 | // Read and write selects | |
705 | // ///////////////////////////////////////////////////////////////////////////// | |
706 | ||
707 | assign array_sel0 = ~array_sel; | |
708 | assign array_sel1 = array_sel; | |
709 | ||
710 | assign niu_mb6_tcam_array_rd_en = (array_sel1) && array_read; | |
711 | assign niu_mb6_tcam_array_wr_en = (array_sel1) && array_write; | |
712 | ||
713 | assign niu_mb6_vlan_rd_en = (array_sel0) && array_read; | |
714 | assign niu_mb6_vlan_wr_en = (array_sel0) && array_write; | |
715 | ||
716 | ///////////////////////////////////////////////////////////////////////// | |
717 | // Creating the mbist_done signal | |
718 | ///////////////////////////////////////////////////////////////////////// | |
719 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
720 | // a generic solution for done going high after the last fail has come back! | |
721 | ||
722 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( | |
723 | .scan_in(done_counter_reg_scanin), | |
724 | .scan_out(done_counter_reg_scanout), | |
725 | .din ( done_counter_in[2:0] ), | |
726 | .dout ( done_counter_out[2:0] ), | |
727 | .reset(reset), | |
728 | .l1clk(l1clk), | |
729 | .siclk(siclk), | |
730 | .soclk(soclk)); | |
731 | ||
732 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
733 | // goes low. | |
734 | ||
735 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
736 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
737 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
738 | done_counter_out[2:0]; | |
739 | ||
740 | ||
741 | // ///////////////////////////////////////////////////////////////////////////// | |
742 | // Done Detection | |
743 | // ///////////////////////////////////////////////////////////////////////////// | |
744 | ||
745 | assign done_reg_in = mbist_done; | |
746 | assign niu_tcu_mbist_done_6 = done_reg_out; | |
747 | ||
748 | ||
749 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( | |
750 | .scan_in(done_reg_scanin), | |
751 | .scan_out(done_reg_scanout), | |
752 | .din ( done_reg_in ), | |
753 | .dout ( done_reg_out ), | |
754 | .reset(reset), | |
755 | .l1clk(l1clk), | |
756 | .siclk(siclk), | |
757 | .soclk(soclk)); | |
758 | ||
759 | ||
760 | // ///////////////////////////////////////////////////////////////////////////// | |
761 | // Pipeline for wdata, and Read_en | |
762 | // ///////////////////////////////////////////////////////////////////////////// | |
763 | ||
764 | // ///////////////////////////////////////////////////////////////////////////// | |
765 | // Pipeline for wdata | |
766 | // ///////////////////////////////////////////////////////////////////////////// | |
767 | ||
768 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( | |
769 | .scan_in(data_pipe_reg1_scanin), | |
770 | .scan_out(data_pipe_reg1_scanout), | |
771 | .din ( data_pipe_reg1_in[7:0] ), | |
772 | .dout ( data_pipe_out1[7:0] ), | |
773 | .reset(reset), | |
774 | .l1clk(l1clk), | |
775 | .siclk(siclk), | |
776 | .soclk(soclk)); | |
777 | ||
778 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( | |
779 | .scan_in(data_pipe_reg2_scanin), | |
780 | .scan_out(data_pipe_reg2_scanout), | |
781 | .din ( data_pipe_reg2_in[7:0] ), | |
782 | .dout ( data_pipe_out2[7:0] ), | |
783 | .reset(reset), | |
784 | .l1clk(l1clk), | |
785 | .siclk(siclk), | |
786 | .soclk(soclk)); | |
787 | ||
788 | //Adding an extra level of pipe since piping the read_data | |
789 | //msff_ctl_macro data_pipe_reg3 (width=8)( | |
790 | // .scan_in(data_pipe_reg3_scanin), | |
791 | // .scan_out(data_pipe_reg3_scanout), | |
792 | // .din ( data_pipe_reg3_in[7:0] ), | |
793 | // .dout ( data_pipe_out3[7:0] )); | |
794 | ||
795 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: niu_mb6_wdata[7:0]; | |
796 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
797 | //assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
798 | //assign old_piped_data[7:0] = data_pipe_out3[7:0]; | |
799 | assign old_piped_data[7:0] = data_pipe_out2[7:0]; | |
800 | ||
801 | // ///////////////////////////////////////////////////////////////////////////// | |
802 | // Pipeline for Read_en | |
803 | // ///////////////////////////////////////////////////////////////////////////// | |
804 | ||
805 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg1 ( | |
806 | .scan_in(ren_pipe_reg1_scanin), | |
807 | .scan_out(ren_pipe_reg1_scanout), | |
808 | .din ( ren_pipe_reg1_in ), | |
809 | .dout ( ren_pipe_out1 ), | |
810 | .reset(reset), | |
811 | .l1clk(l1clk), | |
812 | .siclk(siclk), | |
813 | .soclk(soclk)); | |
814 | ||
815 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg2 ( | |
816 | .scan_in(ren_pipe_reg2_scanin), | |
817 | .scan_out(ren_pipe_reg2_scanout), | |
818 | .din ( ren_pipe_reg2_in ), | |
819 | .dout ( ren_pipe_out2 ), | |
820 | .reset(reset), | |
821 | .l1clk(l1clk), | |
822 | .siclk(siclk), | |
823 | .soclk(soclk)); | |
824 | ||
825 | //Adding an extra level of pipe since piping the read_data | |
826 | //msff_ctl_macro ren_pipe_reg3 (width=1, library=a1, reset=1)( | |
827 | // .scan_in(ren_pipe_reg3_scanin), | |
828 | // .scan_out(ren_pipe_reg3_scanout), | |
829 | // .din ( ren_pipe_reg3_in ), | |
830 | // .dout ( ren_pipe_out3 )); | |
831 | ||
832 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; | |
833 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; | |
834 | //assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; | |
835 | //assign old_piped_ren = ren_pipe_out3; | |
836 | assign old_piped_ren = ren_pipe_out2; | |
837 | ||
838 | // piped sel | |
839 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg1 ( | |
840 | .scan_in(sel_pipe_reg1_scanin), | |
841 | .scan_out(sel_pipe_reg1_scanout), | |
842 | .din ( sel_pipe_reg1_in ), | |
843 | .dout ( sel_pipe_out1 ), | |
844 | .reset(reset), | |
845 | .l1clk(l1clk), | |
846 | .siclk(siclk), | |
847 | .soclk(soclk)); | |
848 | ||
849 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg2 ( | |
850 | .scan_in(sel_pipe_reg2_scanin), | |
851 | .scan_out(sel_pipe_reg2_scanout), | |
852 | .din ( sel_pipe_reg2_in ), | |
853 | .dout ( sel_pipe_out2 ), | |
854 | .reset(reset), | |
855 | .l1clk(l1clk), | |
856 | .siclk(siclk), | |
857 | .soclk(soclk)); | |
858 | ||
859 | assign sel_pipe_reg1_in = reset_engine ? 1'b0: array_sel; | |
860 | assign sel_pipe_reg2_in = reset_engine ? 1'b0: sel_pipe_out1; | |
861 | assign old_piped_sel2 = sel_pipe_out2; | |
862 | ||
863 | ||
864 | // ///////////////////////////////////////////////////////////////////////////// | |
865 | // Data out pipeline | |
866 | // ///////////////////////////////////////////////////////////////////////////// | |
867 | ||
868 | // Pipelining the read_data to meet the timing requirement | |
869 | ||
870 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_9 read_data_pipe_reg0 ( | |
871 | .scan_in(read_data_pipe_reg0_scanin), | |
872 | .scan_out(read_data_pipe_reg0_scanout), | |
873 | .din ( niu_mb6_vlan_data_out[8:0] ), | |
874 | .dout ( read_data_pipe0[8:0] ), | |
875 | .reset(reset), | |
876 | .l1clk(l1clk), | |
877 | .siclk(siclk), | |
878 | .soclk(soclk)); | |
879 | ||
880 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_42 read_data_pipe_reg1 ( | |
881 | .scan_in(read_data_pipe_reg1_scanin), | |
882 | .scan_out(read_data_pipe_reg1_scanout), | |
883 | .din ( niu_mb6_tcam_array_data_out[41:0] ), | |
884 | .dout ( read_data_pipe1[41:0] ), | |
885 | .reset(reset), | |
886 | .l1clk(l1clk), | |
887 | .siclk(siclk), | |
888 | .soclk(soclk)); | |
889 | ||
890 | // ///////////////////////////////////////////////////////////////////////////// | |
891 | // Fail Detection | |
892 | // ///////////////////////////////////////////////////////////////////////////// | |
893 | ||
894 | assign fail_out_reg_in = fail; | |
895 | assign niu_tcu_mbist_fail_6 = fail_out_reg_out; | |
896 | ||
897 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 fail_out_reg ( | |
898 | .scan_in(fail_out_reg_scanin), | |
899 | .scan_out(fail_out_reg_scanout), | |
900 | .din ( fail_out_reg_in ), | |
901 | .dout ( fail_out_reg_out ), | |
902 | .reset(reset), | |
903 | .l1clk(l1clk), | |
904 | .siclk(siclk), | |
905 | .soclk(soclk)); | |
906 | ||
907 | // ///////////////////////////////////////////////////////////////////////////// | |
908 | // Fail Detection | |
909 | // ///////////////////////////////////////////////////////////////////////////// | |
910 | ||
911 | niu_mb6_msff_ctl_macro__library_a1__reset_1__width_2 fail_reg ( | |
912 | .scan_in(fail_reg_scanin), | |
913 | .scan_out(fail_reg_scanout), | |
914 | .din ( fail_reg_in ), | |
915 | .dout ( fail_reg_out ), | |
916 | .reset(reset), | |
917 | .l1clk(l1clk), | |
918 | .siclk(siclk), | |
919 | .soclk(soclk)); | |
920 | ||
921 | assign fail_reg_in[1:0] = reset_engine ? 2'b00 : {qual_old_fail1, qual_old_fail0} | fail_reg_out[1:0]; | |
922 | ||
923 | assign qual_old_fail0 = fail_detect && !old_piped_sel2; | |
924 | assign qual_old_fail1 = fail_detect && old_piped_sel2; | |
925 | assign qual_old_fail = qual_old_fail0 || qual_old_fail1; | |
926 | ||
927 | assign mb6_dmo_dout[39:0] = old_piped_sel2 ? 40'h0000000000 : {24'h000000, 7'b0000000, read_data_pipe0[8:0]} ; | |
928 | ||
929 | assign fail_detect = old_piped_sel2 ? ({old_piped_data[1:0], | |
930 | old_piped_data[7:0], | |
931 | old_piped_data[7:0], | |
932 | old_piped_data[7:0], | |
933 | old_piped_data[7:0], | |
934 | old_piped_data[7:0]} != read_data_pipe1[41:0]) && old_piped_ren : | |
935 | ({old_piped_data[0], | |
936 | old_piped_data[7:0]} != read_data_pipe0[8:0]) && old_piped_ren; | |
937 | ||
938 | assign fail = mbist_done ? |fail_reg_out[1:0] : qual_old_fail; | |
939 | ||
940 | supply0 vss; // <- port for ground | |
941 | supply1 vdd; // <- port for power | |
942 | // ///////////////////////////////////////////////////////////////////////////// | |
943 | // fixscan start: | |
944 | assign config_reg_scanin = mb6_scan_in ; | |
945 | assign user_data_reg_scanin = config_reg_scanout ; | |
946 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
947 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
948 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
949 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; | |
950 | assign user_bisi_wr_reg_scanin = user_array_sel_reg_scanout; | |
951 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
952 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
953 | assign run_reg_scanin = start_transition_reg_scanout; | |
954 | assign run1_reg_scanin = run_reg_scanout ; | |
955 | assign run2_reg_scanin = run1_reg_scanout ; | |
956 | assign control_reg_scanin = run2_reg_scanout ; | |
957 | assign done_counter_reg_scanin = control_reg_scanout ; | |
958 | assign done_reg_scanin = done_counter_reg_scanout ; | |
959 | assign data_pipe_reg1_scanin = done_reg_scanout ; | |
960 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
961 | assign ren_pipe_reg1_scanin = data_pipe_reg2_scanout ; | |
962 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; | |
963 | assign sel_pipe_reg1_scanin = ren_pipe_reg2_scanout ; | |
964 | assign sel_pipe_reg2_scanin = sel_pipe_reg1_scanout ; | |
965 | assign read_data_pipe_reg0_scanin = sel_pipe_reg2_scanout ; | |
966 | assign read_data_pipe_reg1_scanin = read_data_pipe_reg0_scanout; | |
967 | assign fail_out_reg_scanin = read_data_pipe_reg1_scanout; | |
968 | assign fail_reg_scanin = fail_out_reg_scanout ; | |
969 | assign mb6_scan_out = fail_reg_scanout ; | |
970 | // fixscan end: | |
971 | endmodule | |
972 | // ///////////////////////////////////////////////////////////////////////////// | |
973 | ||
974 | ||
975 | ||
976 | ||
977 | ||
978 | ||
979 | // any PARAMS parms go into naming of macro | |
980 | ||
981 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_8 ( | |
982 | din, | |
983 | reset, | |
984 | l1clk, | |
985 | scan_in, | |
986 | siclk, | |
987 | soclk, | |
988 | dout, | |
989 | scan_out); | |
990 | wire [7:0] fdin; | |
991 | wire [7:1] sout; | |
992 | ||
993 | input [7:0] din; | |
994 | input reset; | |
995 | input l1clk; | |
996 | input scan_in; | |
997 | ||
998 | ||
999 | input siclk; | |
1000 | input soclk; | |
1001 | ||
1002 | output [7:0] dout; | |
1003 | output scan_out; | |
1004 | assign fdin[7:0] = din[7:0] & {8 {reset}}; | |
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | cl_a1_msff_syrst_4x d0_0 ( | |
1023 | .l1clk(l1clk), | |
1024 | .siclk(siclk), | |
1025 | .soclk(soclk), | |
1026 | .d(fdin[0]), | |
1027 | .si(sout[1]), | |
1028 | .so(scan_out), | |
1029 | .reset(reset), | |
1030 | .q(dout[0]) | |
1031 | ); | |
1032 | cl_a1_msff_syrst_4x d0_1 ( | |
1033 | .l1clk(l1clk), | |
1034 | .siclk(siclk), | |
1035 | .soclk(soclk), | |
1036 | .d(fdin[1]), | |
1037 | .si(sout[2]), | |
1038 | .so(sout[1]), | |
1039 | .reset(reset), | |
1040 | .q(dout[1]) | |
1041 | ); | |
1042 | cl_a1_msff_syrst_4x d0_2 ( | |
1043 | .l1clk(l1clk), | |
1044 | .siclk(siclk), | |
1045 | .soclk(soclk), | |
1046 | .d(fdin[2]), | |
1047 | .si(sout[3]), | |
1048 | .so(sout[2]), | |
1049 | .reset(reset), | |
1050 | .q(dout[2]) | |
1051 | ); | |
1052 | cl_a1_msff_syrst_4x d0_3 ( | |
1053 | .l1clk(l1clk), | |
1054 | .siclk(siclk), | |
1055 | .soclk(soclk), | |
1056 | .d(fdin[3]), | |
1057 | .si(sout[4]), | |
1058 | .so(sout[3]), | |
1059 | .reset(reset), | |
1060 | .q(dout[3]) | |
1061 | ); | |
1062 | cl_a1_msff_syrst_4x d0_4 ( | |
1063 | .l1clk(l1clk), | |
1064 | .siclk(siclk), | |
1065 | .soclk(soclk), | |
1066 | .d(fdin[4]), | |
1067 | .si(sout[5]), | |
1068 | .so(sout[4]), | |
1069 | .reset(reset), | |
1070 | .q(dout[4]) | |
1071 | ); | |
1072 | cl_a1_msff_syrst_4x d0_5 ( | |
1073 | .l1clk(l1clk), | |
1074 | .siclk(siclk), | |
1075 | .soclk(soclk), | |
1076 | .d(fdin[5]), | |
1077 | .si(sout[6]), | |
1078 | .so(sout[5]), | |
1079 | .reset(reset), | |
1080 | .q(dout[5]) | |
1081 | ); | |
1082 | cl_a1_msff_syrst_4x d0_6 ( | |
1083 | .l1clk(l1clk), | |
1084 | .siclk(siclk), | |
1085 | .soclk(soclk), | |
1086 | .d(fdin[6]), | |
1087 | .si(sout[7]), | |
1088 | .so(sout[6]), | |
1089 | .reset(reset), | |
1090 | .q(dout[6]) | |
1091 | ); | |
1092 | cl_a1_msff_syrst_4x d0_7 ( | |
1093 | .l1clk(l1clk), | |
1094 | .siclk(siclk), | |
1095 | .soclk(soclk), | |
1096 | .d(fdin[7]), | |
1097 | .si(scan_in), | |
1098 | .so(sout[7]), | |
1099 | .reset(reset), | |
1100 | .q(dout[7]) | |
1101 | ); | |
1102 | ||
1103 | ||
1104 | ||
1105 | ||
1106 | endmodule | |
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | // any PARAMS parms go into naming of macro | |
1121 | ||
1122 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_12 ( | |
1123 | din, | |
1124 | reset, | |
1125 | l1clk, | |
1126 | scan_in, | |
1127 | siclk, | |
1128 | soclk, | |
1129 | dout, | |
1130 | scan_out); | |
1131 | wire [11:0] fdin; | |
1132 | wire [11:1] sout; | |
1133 | ||
1134 | input [11:0] din; | |
1135 | input reset; | |
1136 | input l1clk; | |
1137 | input scan_in; | |
1138 | ||
1139 | ||
1140 | input siclk; | |
1141 | input soclk; | |
1142 | ||
1143 | output [11:0] dout; | |
1144 | output scan_out; | |
1145 | assign fdin[11:0] = din[11:0] & {12 {reset}}; | |
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | ||
1162 | ||
1163 | cl_a1_msff_syrst_4x d0_0 ( | |
1164 | .l1clk(l1clk), | |
1165 | .siclk(siclk), | |
1166 | .soclk(soclk), | |
1167 | .d(fdin[0]), | |
1168 | .si(sout[1]), | |
1169 | .so(scan_out), | |
1170 | .reset(reset), | |
1171 | .q(dout[0]) | |
1172 | ); | |
1173 | cl_a1_msff_syrst_4x d0_1 ( | |
1174 | .l1clk(l1clk), | |
1175 | .siclk(siclk), | |
1176 | .soclk(soclk), | |
1177 | .d(fdin[1]), | |
1178 | .si(sout[2]), | |
1179 | .so(sout[1]), | |
1180 | .reset(reset), | |
1181 | .q(dout[1]) | |
1182 | ); | |
1183 | cl_a1_msff_syrst_4x d0_2 ( | |
1184 | .l1clk(l1clk), | |
1185 | .siclk(siclk), | |
1186 | .soclk(soclk), | |
1187 | .d(fdin[2]), | |
1188 | .si(sout[3]), | |
1189 | .so(sout[2]), | |
1190 | .reset(reset), | |
1191 | .q(dout[2]) | |
1192 | ); | |
1193 | cl_a1_msff_syrst_4x d0_3 ( | |
1194 | .l1clk(l1clk), | |
1195 | .siclk(siclk), | |
1196 | .soclk(soclk), | |
1197 | .d(fdin[3]), | |
1198 | .si(sout[4]), | |
1199 | .so(sout[3]), | |
1200 | .reset(reset), | |
1201 | .q(dout[3]) | |
1202 | ); | |
1203 | cl_a1_msff_syrst_4x d0_4 ( | |
1204 | .l1clk(l1clk), | |
1205 | .siclk(siclk), | |
1206 | .soclk(soclk), | |
1207 | .d(fdin[4]), | |
1208 | .si(sout[5]), | |
1209 | .so(sout[4]), | |
1210 | .reset(reset), | |
1211 | .q(dout[4]) | |
1212 | ); | |
1213 | cl_a1_msff_syrst_4x d0_5 ( | |
1214 | .l1clk(l1clk), | |
1215 | .siclk(siclk), | |
1216 | .soclk(soclk), | |
1217 | .d(fdin[5]), | |
1218 | .si(sout[6]), | |
1219 | .so(sout[5]), | |
1220 | .reset(reset), | |
1221 | .q(dout[5]) | |
1222 | ); | |
1223 | cl_a1_msff_syrst_4x d0_6 ( | |
1224 | .l1clk(l1clk), | |
1225 | .siclk(siclk), | |
1226 | .soclk(soclk), | |
1227 | .d(fdin[6]), | |
1228 | .si(sout[7]), | |
1229 | .so(sout[6]), | |
1230 | .reset(reset), | |
1231 | .q(dout[6]) | |
1232 | ); | |
1233 | cl_a1_msff_syrst_4x d0_7 ( | |
1234 | .l1clk(l1clk), | |
1235 | .siclk(siclk), | |
1236 | .soclk(soclk), | |
1237 | .d(fdin[7]), | |
1238 | .si(sout[8]), | |
1239 | .so(sout[7]), | |
1240 | .reset(reset), | |
1241 | .q(dout[7]) | |
1242 | ); | |
1243 | cl_a1_msff_syrst_4x d0_8 ( | |
1244 | .l1clk(l1clk), | |
1245 | .siclk(siclk), | |
1246 | .soclk(soclk), | |
1247 | .d(fdin[8]), | |
1248 | .si(sout[9]), | |
1249 | .so(sout[8]), | |
1250 | .reset(reset), | |
1251 | .q(dout[8]) | |
1252 | ); | |
1253 | cl_a1_msff_syrst_4x d0_9 ( | |
1254 | .l1clk(l1clk), | |
1255 | .siclk(siclk), | |
1256 | .soclk(soclk), | |
1257 | .d(fdin[9]), | |
1258 | .si(sout[10]), | |
1259 | .so(sout[9]), | |
1260 | .reset(reset), | |
1261 | .q(dout[9]) | |
1262 | ); | |
1263 | cl_a1_msff_syrst_4x d0_10 ( | |
1264 | .l1clk(l1clk), | |
1265 | .siclk(siclk), | |
1266 | .soclk(soclk), | |
1267 | .d(fdin[10]), | |
1268 | .si(sout[11]), | |
1269 | .so(sout[10]), | |
1270 | .reset(reset), | |
1271 | .q(dout[10]) | |
1272 | ); | |
1273 | cl_a1_msff_syrst_4x d0_11 ( | |
1274 | .l1clk(l1clk), | |
1275 | .siclk(siclk), | |
1276 | .soclk(soclk), | |
1277 | .d(fdin[11]), | |
1278 | .si(scan_in), | |
1279 | .so(sout[11]), | |
1280 | .reset(reset), | |
1281 | .q(dout[11]) | |
1282 | ); | |
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | endmodule | |
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | // any PARAMS parms go into naming of macro | |
1302 | ||
1303 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_1 ( | |
1304 | din, | |
1305 | reset, | |
1306 | l1clk, | |
1307 | scan_in, | |
1308 | siclk, | |
1309 | soclk, | |
1310 | dout, | |
1311 | scan_out); | |
1312 | wire [0:0] fdin; | |
1313 | ||
1314 | input [0:0] din; | |
1315 | input reset; | |
1316 | input l1clk; | |
1317 | input scan_in; | |
1318 | ||
1319 | ||
1320 | input siclk; | |
1321 | input soclk; | |
1322 | ||
1323 | output [0:0] dout; | |
1324 | output scan_out; | |
1325 | assign fdin[0:0] = din[0:0] & {1 {reset}}; | |
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | cl_a1_msff_syrst_4x d0_0 ( | |
1344 | .l1clk(l1clk), | |
1345 | .siclk(siclk), | |
1346 | .soclk(soclk), | |
1347 | .d(fdin[0]), | |
1348 | .si(scan_in), | |
1349 | .so(scan_out), | |
1350 | .reset(reset), | |
1351 | .q(dout[0]) | |
1352 | ); | |
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | endmodule | |
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | ||
1371 | // any PARAMS parms go into naming of macro | |
1372 | ||
1373 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_25 ( | |
1374 | din, | |
1375 | reset, | |
1376 | l1clk, | |
1377 | scan_in, | |
1378 | siclk, | |
1379 | soclk, | |
1380 | dout, | |
1381 | scan_out); | |
1382 | wire [24:0] fdin; | |
1383 | wire [24:1] sout; | |
1384 | ||
1385 | input [24:0] din; | |
1386 | input reset; | |
1387 | input l1clk; | |
1388 | input scan_in; | |
1389 | ||
1390 | ||
1391 | input siclk; | |
1392 | input soclk; | |
1393 | ||
1394 | output [24:0] dout; | |
1395 | output scan_out; | |
1396 | assign fdin[24:0] = din[24:0] & {25 {reset}}; | |
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | cl_a1_msff_syrst_4x d0_0 ( | |
1415 | .l1clk(l1clk), | |
1416 | .siclk(siclk), | |
1417 | .soclk(soclk), | |
1418 | .d(fdin[0]), | |
1419 | .si(sout[1]), | |
1420 | .so(scan_out), | |
1421 | .reset(reset), | |
1422 | .q(dout[0]) | |
1423 | ); | |
1424 | cl_a1_msff_syrst_4x d0_1 ( | |
1425 | .l1clk(l1clk), | |
1426 | .siclk(siclk), | |
1427 | .soclk(soclk), | |
1428 | .d(fdin[1]), | |
1429 | .si(sout[2]), | |
1430 | .so(sout[1]), | |
1431 | .reset(reset), | |
1432 | .q(dout[1]) | |
1433 | ); | |
1434 | cl_a1_msff_syrst_4x d0_2 ( | |
1435 | .l1clk(l1clk), | |
1436 | .siclk(siclk), | |
1437 | .soclk(soclk), | |
1438 | .d(fdin[2]), | |
1439 | .si(sout[3]), | |
1440 | .so(sout[2]), | |
1441 | .reset(reset), | |
1442 | .q(dout[2]) | |
1443 | ); | |
1444 | cl_a1_msff_syrst_4x d0_3 ( | |
1445 | .l1clk(l1clk), | |
1446 | .siclk(siclk), | |
1447 | .soclk(soclk), | |
1448 | .d(fdin[3]), | |
1449 | .si(sout[4]), | |
1450 | .so(sout[3]), | |
1451 | .reset(reset), | |
1452 | .q(dout[3]) | |
1453 | ); | |
1454 | cl_a1_msff_syrst_4x d0_4 ( | |
1455 | .l1clk(l1clk), | |
1456 | .siclk(siclk), | |
1457 | .soclk(soclk), | |
1458 | .d(fdin[4]), | |
1459 | .si(sout[5]), | |
1460 | .so(sout[4]), | |
1461 | .reset(reset), | |
1462 | .q(dout[4]) | |
1463 | ); | |
1464 | cl_a1_msff_syrst_4x d0_5 ( | |
1465 | .l1clk(l1clk), | |
1466 | .siclk(siclk), | |
1467 | .soclk(soclk), | |
1468 | .d(fdin[5]), | |
1469 | .si(sout[6]), | |
1470 | .so(sout[5]), | |
1471 | .reset(reset), | |
1472 | .q(dout[5]) | |
1473 | ); | |
1474 | cl_a1_msff_syrst_4x d0_6 ( | |
1475 | .l1clk(l1clk), | |
1476 | .siclk(siclk), | |
1477 | .soclk(soclk), | |
1478 | .d(fdin[6]), | |
1479 | .si(sout[7]), | |
1480 | .so(sout[6]), | |
1481 | .reset(reset), | |
1482 | .q(dout[6]) | |
1483 | ); | |
1484 | cl_a1_msff_syrst_4x d0_7 ( | |
1485 | .l1clk(l1clk), | |
1486 | .siclk(siclk), | |
1487 | .soclk(soclk), | |
1488 | .d(fdin[7]), | |
1489 | .si(sout[8]), | |
1490 | .so(sout[7]), | |
1491 | .reset(reset), | |
1492 | .q(dout[7]) | |
1493 | ); | |
1494 | cl_a1_msff_syrst_4x d0_8 ( | |
1495 | .l1clk(l1clk), | |
1496 | .siclk(siclk), | |
1497 | .soclk(soclk), | |
1498 | .d(fdin[8]), | |
1499 | .si(sout[9]), | |
1500 | .so(sout[8]), | |
1501 | .reset(reset), | |
1502 | .q(dout[8]) | |
1503 | ); | |
1504 | cl_a1_msff_syrst_4x d0_9 ( | |
1505 | .l1clk(l1clk), | |
1506 | .siclk(siclk), | |
1507 | .soclk(soclk), | |
1508 | .d(fdin[9]), | |
1509 | .si(sout[10]), | |
1510 | .so(sout[9]), | |
1511 | .reset(reset), | |
1512 | .q(dout[9]) | |
1513 | ); | |
1514 | cl_a1_msff_syrst_4x d0_10 ( | |
1515 | .l1clk(l1clk), | |
1516 | .siclk(siclk), | |
1517 | .soclk(soclk), | |
1518 | .d(fdin[10]), | |
1519 | .si(sout[11]), | |
1520 | .so(sout[10]), | |
1521 | .reset(reset), | |
1522 | .q(dout[10]) | |
1523 | ); | |
1524 | cl_a1_msff_syrst_4x d0_11 ( | |
1525 | .l1clk(l1clk), | |
1526 | .siclk(siclk), | |
1527 | .soclk(soclk), | |
1528 | .d(fdin[11]), | |
1529 | .si(sout[12]), | |
1530 | .so(sout[11]), | |
1531 | .reset(reset), | |
1532 | .q(dout[11]) | |
1533 | ); | |
1534 | cl_a1_msff_syrst_4x d0_12 ( | |
1535 | .l1clk(l1clk), | |
1536 | .siclk(siclk), | |
1537 | .soclk(soclk), | |
1538 | .d(fdin[12]), | |
1539 | .si(sout[13]), | |
1540 | .so(sout[12]), | |
1541 | .reset(reset), | |
1542 | .q(dout[12]) | |
1543 | ); | |
1544 | cl_a1_msff_syrst_4x d0_13 ( | |
1545 | .l1clk(l1clk), | |
1546 | .siclk(siclk), | |
1547 | .soclk(soclk), | |
1548 | .d(fdin[13]), | |
1549 | .si(sout[14]), | |
1550 | .so(sout[13]), | |
1551 | .reset(reset), | |
1552 | .q(dout[13]) | |
1553 | ); | |
1554 | cl_a1_msff_syrst_4x d0_14 ( | |
1555 | .l1clk(l1clk), | |
1556 | .siclk(siclk), | |
1557 | .soclk(soclk), | |
1558 | .d(fdin[14]), | |
1559 | .si(sout[15]), | |
1560 | .so(sout[14]), | |
1561 | .reset(reset), | |
1562 | .q(dout[14]) | |
1563 | ); | |
1564 | cl_a1_msff_syrst_4x d0_15 ( | |
1565 | .l1clk(l1clk), | |
1566 | .siclk(siclk), | |
1567 | .soclk(soclk), | |
1568 | .d(fdin[15]), | |
1569 | .si(sout[16]), | |
1570 | .so(sout[15]), | |
1571 | .reset(reset), | |
1572 | .q(dout[15]) | |
1573 | ); | |
1574 | cl_a1_msff_syrst_4x d0_16 ( | |
1575 | .l1clk(l1clk), | |
1576 | .siclk(siclk), | |
1577 | .soclk(soclk), | |
1578 | .d(fdin[16]), | |
1579 | .si(sout[17]), | |
1580 | .so(sout[16]), | |
1581 | .reset(reset), | |
1582 | .q(dout[16]) | |
1583 | ); | |
1584 | cl_a1_msff_syrst_4x d0_17 ( | |
1585 | .l1clk(l1clk), | |
1586 | .siclk(siclk), | |
1587 | .soclk(soclk), | |
1588 | .d(fdin[17]), | |
1589 | .si(sout[18]), | |
1590 | .so(sout[17]), | |
1591 | .reset(reset), | |
1592 | .q(dout[17]) | |
1593 | ); | |
1594 | cl_a1_msff_syrst_4x d0_18 ( | |
1595 | .l1clk(l1clk), | |
1596 | .siclk(siclk), | |
1597 | .soclk(soclk), | |
1598 | .d(fdin[18]), | |
1599 | .si(sout[19]), | |
1600 | .so(sout[18]), | |
1601 | .reset(reset), | |
1602 | .q(dout[18]) | |
1603 | ); | |
1604 | cl_a1_msff_syrst_4x d0_19 ( | |
1605 | .l1clk(l1clk), | |
1606 | .siclk(siclk), | |
1607 | .soclk(soclk), | |
1608 | .d(fdin[19]), | |
1609 | .si(sout[20]), | |
1610 | .so(sout[19]), | |
1611 | .reset(reset), | |
1612 | .q(dout[19]) | |
1613 | ); | |
1614 | cl_a1_msff_syrst_4x d0_20 ( | |
1615 | .l1clk(l1clk), | |
1616 | .siclk(siclk), | |
1617 | .soclk(soclk), | |
1618 | .d(fdin[20]), | |
1619 | .si(sout[21]), | |
1620 | .so(sout[20]), | |
1621 | .reset(reset), | |
1622 | .q(dout[20]) | |
1623 | ); | |
1624 | cl_a1_msff_syrst_4x d0_21 ( | |
1625 | .l1clk(l1clk), | |
1626 | .siclk(siclk), | |
1627 | .soclk(soclk), | |
1628 | .d(fdin[21]), | |
1629 | .si(sout[22]), | |
1630 | .so(sout[21]), | |
1631 | .reset(reset), | |
1632 | .q(dout[21]) | |
1633 | ); | |
1634 | cl_a1_msff_syrst_4x d0_22 ( | |
1635 | .l1clk(l1clk), | |
1636 | .siclk(siclk), | |
1637 | .soclk(soclk), | |
1638 | .d(fdin[22]), | |
1639 | .si(sout[23]), | |
1640 | .so(sout[22]), | |
1641 | .reset(reset), | |
1642 | .q(dout[22]) | |
1643 | ); | |
1644 | cl_a1_msff_syrst_4x d0_23 ( | |
1645 | .l1clk(l1clk), | |
1646 | .siclk(siclk), | |
1647 | .soclk(soclk), | |
1648 | .d(fdin[23]), | |
1649 | .si(sout[24]), | |
1650 | .so(sout[23]), | |
1651 | .reset(reset), | |
1652 | .q(dout[23]) | |
1653 | ); | |
1654 | cl_a1_msff_syrst_4x d0_24 ( | |
1655 | .l1clk(l1clk), | |
1656 | .siclk(siclk), | |
1657 | .soclk(soclk), | |
1658 | .d(fdin[24]), | |
1659 | .si(scan_in), | |
1660 | .so(sout[24]), | |
1661 | .reset(reset), | |
1662 | .q(dout[24]) | |
1663 | ); | |
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | endmodule | |
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | // any PARAMS parms go into naming of macro | |
1683 | ||
1684 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_3 ( | |
1685 | din, | |
1686 | reset, | |
1687 | l1clk, | |
1688 | scan_in, | |
1689 | siclk, | |
1690 | soclk, | |
1691 | dout, | |
1692 | scan_out); | |
1693 | wire [2:0] fdin; | |
1694 | wire [2:1] sout; | |
1695 | ||
1696 | input [2:0] din; | |
1697 | input reset; | |
1698 | input l1clk; | |
1699 | input scan_in; | |
1700 | ||
1701 | ||
1702 | input siclk; | |
1703 | input soclk; | |
1704 | ||
1705 | output [2:0] dout; | |
1706 | output scan_out; | |
1707 | assign fdin[2:0] = din[2:0] & {3 {reset}}; | |
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | ||
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | cl_a1_msff_syrst_4x d0_0 ( | |
1726 | .l1clk(l1clk), | |
1727 | .siclk(siclk), | |
1728 | .soclk(soclk), | |
1729 | .d(fdin[0]), | |
1730 | .si(sout[1]), | |
1731 | .so(scan_out), | |
1732 | .reset(reset), | |
1733 | .q(dout[0]) | |
1734 | ); | |
1735 | cl_a1_msff_syrst_4x d0_1 ( | |
1736 | .l1clk(l1clk), | |
1737 | .siclk(siclk), | |
1738 | .soclk(soclk), | |
1739 | .d(fdin[1]), | |
1740 | .si(sout[2]), | |
1741 | .so(sout[1]), | |
1742 | .reset(reset), | |
1743 | .q(dout[1]) | |
1744 | ); | |
1745 | cl_a1_msff_syrst_4x d0_2 ( | |
1746 | .l1clk(l1clk), | |
1747 | .siclk(siclk), | |
1748 | .soclk(soclk), | |
1749 | .d(fdin[2]), | |
1750 | .si(scan_in), | |
1751 | .so(sout[2]), | |
1752 | .reset(reset), | |
1753 | .q(dout[2]) | |
1754 | ); | |
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | endmodule | |
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | // any PARAMS parms go into naming of macro | |
1774 | ||
1775 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_9 ( | |
1776 | din, | |
1777 | reset, | |
1778 | l1clk, | |
1779 | scan_in, | |
1780 | siclk, | |
1781 | soclk, | |
1782 | dout, | |
1783 | scan_out); | |
1784 | wire [8:0] fdin; | |
1785 | wire [8:1] sout; | |
1786 | ||
1787 | input [8:0] din; | |
1788 | input reset; | |
1789 | input l1clk; | |
1790 | input scan_in; | |
1791 | ||
1792 | ||
1793 | input siclk; | |
1794 | input soclk; | |
1795 | ||
1796 | output [8:0] dout; | |
1797 | output scan_out; | |
1798 | assign fdin[8:0] = din[8:0] & {9 {reset}}; | |
1799 | ||
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | cl_a1_msff_syrst_4x d0_0 ( | |
1817 | .l1clk(l1clk), | |
1818 | .siclk(siclk), | |
1819 | .soclk(soclk), | |
1820 | .d(fdin[0]), | |
1821 | .si(sout[1]), | |
1822 | .so(scan_out), | |
1823 | .reset(reset), | |
1824 | .q(dout[0]) | |
1825 | ); | |
1826 | cl_a1_msff_syrst_4x d0_1 ( | |
1827 | .l1clk(l1clk), | |
1828 | .siclk(siclk), | |
1829 | .soclk(soclk), | |
1830 | .d(fdin[1]), | |
1831 | .si(sout[2]), | |
1832 | .so(sout[1]), | |
1833 | .reset(reset), | |
1834 | .q(dout[1]) | |
1835 | ); | |
1836 | cl_a1_msff_syrst_4x d0_2 ( | |
1837 | .l1clk(l1clk), | |
1838 | .siclk(siclk), | |
1839 | .soclk(soclk), | |
1840 | .d(fdin[2]), | |
1841 | .si(sout[3]), | |
1842 | .so(sout[2]), | |
1843 | .reset(reset), | |
1844 | .q(dout[2]) | |
1845 | ); | |
1846 | cl_a1_msff_syrst_4x d0_3 ( | |
1847 | .l1clk(l1clk), | |
1848 | .siclk(siclk), | |
1849 | .soclk(soclk), | |
1850 | .d(fdin[3]), | |
1851 | .si(sout[4]), | |
1852 | .so(sout[3]), | |
1853 | .reset(reset), | |
1854 | .q(dout[3]) | |
1855 | ); | |
1856 | cl_a1_msff_syrst_4x d0_4 ( | |
1857 | .l1clk(l1clk), | |
1858 | .siclk(siclk), | |
1859 | .soclk(soclk), | |
1860 | .d(fdin[4]), | |
1861 | .si(sout[5]), | |
1862 | .so(sout[4]), | |
1863 | .reset(reset), | |
1864 | .q(dout[4]) | |
1865 | ); | |
1866 | cl_a1_msff_syrst_4x d0_5 ( | |
1867 | .l1clk(l1clk), | |
1868 | .siclk(siclk), | |
1869 | .soclk(soclk), | |
1870 | .d(fdin[5]), | |
1871 | .si(sout[6]), | |
1872 | .so(sout[5]), | |
1873 | .reset(reset), | |
1874 | .q(dout[5]) | |
1875 | ); | |
1876 | cl_a1_msff_syrst_4x d0_6 ( | |
1877 | .l1clk(l1clk), | |
1878 | .siclk(siclk), | |
1879 | .soclk(soclk), | |
1880 | .d(fdin[6]), | |
1881 | .si(sout[7]), | |
1882 | .so(sout[6]), | |
1883 | .reset(reset), | |
1884 | .q(dout[6]) | |
1885 | ); | |
1886 | cl_a1_msff_syrst_4x d0_7 ( | |
1887 | .l1clk(l1clk), | |
1888 | .siclk(siclk), | |
1889 | .soclk(soclk), | |
1890 | .d(fdin[7]), | |
1891 | .si(sout[8]), | |
1892 | .so(sout[7]), | |
1893 | .reset(reset), | |
1894 | .q(dout[7]) | |
1895 | ); | |
1896 | cl_a1_msff_syrst_4x d0_8 ( | |
1897 | .l1clk(l1clk), | |
1898 | .siclk(siclk), | |
1899 | .soclk(soclk), | |
1900 | .d(fdin[8]), | |
1901 | .si(scan_in), | |
1902 | .so(sout[8]), | |
1903 | .reset(reset), | |
1904 | .q(dout[8]) | |
1905 | ); | |
1906 | ||
1907 | ||
1908 | ||
1909 | ||
1910 | endmodule | |
1911 | ||
1912 | ||
1913 | ||
1914 | ||
1915 | ||
1916 | ||
1917 | ||
1918 | ||
1919 | ||
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | // any PARAMS parms go into naming of macro | |
1925 | ||
1926 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_42 ( | |
1927 | din, | |
1928 | reset, | |
1929 | l1clk, | |
1930 | scan_in, | |
1931 | siclk, | |
1932 | soclk, | |
1933 | dout, | |
1934 | scan_out); | |
1935 | wire [41:0] fdin; | |
1936 | wire [41:1] sout; | |
1937 | ||
1938 | input [41:0] din; | |
1939 | input reset; | |
1940 | input l1clk; | |
1941 | input scan_in; | |
1942 | ||
1943 | ||
1944 | input siclk; | |
1945 | input soclk; | |
1946 | ||
1947 | output [41:0] dout; | |
1948 | output scan_out; | |
1949 | assign fdin[41:0] = din[41:0] & {42 {reset}}; | |
1950 | ||
1951 | ||
1952 | ||
1953 | ||
1954 | ||
1955 | ||
1956 | ||
1957 | ||
1958 | ||
1959 | ||
1960 | ||
1961 | ||
1962 | ||
1963 | ||
1964 | ||
1965 | ||
1966 | ||
1967 | cl_a1_msff_syrst_4x d0_0 ( | |
1968 | .l1clk(l1clk), | |
1969 | .siclk(siclk), | |
1970 | .soclk(soclk), | |
1971 | .d(fdin[0]), | |
1972 | .si(sout[1]), | |
1973 | .so(scan_out), | |
1974 | .reset(reset), | |
1975 | .q(dout[0]) | |
1976 | ); | |
1977 | cl_a1_msff_syrst_4x d0_1 ( | |
1978 | .l1clk(l1clk), | |
1979 | .siclk(siclk), | |
1980 | .soclk(soclk), | |
1981 | .d(fdin[1]), | |
1982 | .si(sout[2]), | |
1983 | .so(sout[1]), | |
1984 | .reset(reset), | |
1985 | .q(dout[1]) | |
1986 | ); | |
1987 | cl_a1_msff_syrst_4x d0_2 ( | |
1988 | .l1clk(l1clk), | |
1989 | .siclk(siclk), | |
1990 | .soclk(soclk), | |
1991 | .d(fdin[2]), | |
1992 | .si(sout[3]), | |
1993 | .so(sout[2]), | |
1994 | .reset(reset), | |
1995 | .q(dout[2]) | |
1996 | ); | |
1997 | cl_a1_msff_syrst_4x d0_3 ( | |
1998 | .l1clk(l1clk), | |
1999 | .siclk(siclk), | |
2000 | .soclk(soclk), | |
2001 | .d(fdin[3]), | |
2002 | .si(sout[4]), | |
2003 | .so(sout[3]), | |
2004 | .reset(reset), | |
2005 | .q(dout[3]) | |
2006 | ); | |
2007 | cl_a1_msff_syrst_4x d0_4 ( | |
2008 | .l1clk(l1clk), | |
2009 | .siclk(siclk), | |
2010 | .soclk(soclk), | |
2011 | .d(fdin[4]), | |
2012 | .si(sout[5]), | |
2013 | .so(sout[4]), | |
2014 | .reset(reset), | |
2015 | .q(dout[4]) | |
2016 | ); | |
2017 | cl_a1_msff_syrst_4x d0_5 ( | |
2018 | .l1clk(l1clk), | |
2019 | .siclk(siclk), | |
2020 | .soclk(soclk), | |
2021 | .d(fdin[5]), | |
2022 | .si(sout[6]), | |
2023 | .so(sout[5]), | |
2024 | .reset(reset), | |
2025 | .q(dout[5]) | |
2026 | ); | |
2027 | cl_a1_msff_syrst_4x d0_6 ( | |
2028 | .l1clk(l1clk), | |
2029 | .siclk(siclk), | |
2030 | .soclk(soclk), | |
2031 | .d(fdin[6]), | |
2032 | .si(sout[7]), | |
2033 | .so(sout[6]), | |
2034 | .reset(reset), | |
2035 | .q(dout[6]) | |
2036 | ); | |
2037 | cl_a1_msff_syrst_4x d0_7 ( | |
2038 | .l1clk(l1clk), | |
2039 | .siclk(siclk), | |
2040 | .soclk(soclk), | |
2041 | .d(fdin[7]), | |
2042 | .si(sout[8]), | |
2043 | .so(sout[7]), | |
2044 | .reset(reset), | |
2045 | .q(dout[7]) | |
2046 | ); | |
2047 | cl_a1_msff_syrst_4x d0_8 ( | |
2048 | .l1clk(l1clk), | |
2049 | .siclk(siclk), | |
2050 | .soclk(soclk), | |
2051 | .d(fdin[8]), | |
2052 | .si(sout[9]), | |
2053 | .so(sout[8]), | |
2054 | .reset(reset), | |
2055 | .q(dout[8]) | |
2056 | ); | |
2057 | cl_a1_msff_syrst_4x d0_9 ( | |
2058 | .l1clk(l1clk), | |
2059 | .siclk(siclk), | |
2060 | .soclk(soclk), | |
2061 | .d(fdin[9]), | |
2062 | .si(sout[10]), | |
2063 | .so(sout[9]), | |
2064 | .reset(reset), | |
2065 | .q(dout[9]) | |
2066 | ); | |
2067 | cl_a1_msff_syrst_4x d0_10 ( | |
2068 | .l1clk(l1clk), | |
2069 | .siclk(siclk), | |
2070 | .soclk(soclk), | |
2071 | .d(fdin[10]), | |
2072 | .si(sout[11]), | |
2073 | .so(sout[10]), | |
2074 | .reset(reset), | |
2075 | .q(dout[10]) | |
2076 | ); | |
2077 | cl_a1_msff_syrst_4x d0_11 ( | |
2078 | .l1clk(l1clk), | |
2079 | .siclk(siclk), | |
2080 | .soclk(soclk), | |
2081 | .d(fdin[11]), | |
2082 | .si(sout[12]), | |
2083 | .so(sout[11]), | |
2084 | .reset(reset), | |
2085 | .q(dout[11]) | |
2086 | ); | |
2087 | cl_a1_msff_syrst_4x d0_12 ( | |
2088 | .l1clk(l1clk), | |
2089 | .siclk(siclk), | |
2090 | .soclk(soclk), | |
2091 | .d(fdin[12]), | |
2092 | .si(sout[13]), | |
2093 | .so(sout[12]), | |
2094 | .reset(reset), | |
2095 | .q(dout[12]) | |
2096 | ); | |
2097 | cl_a1_msff_syrst_4x d0_13 ( | |
2098 | .l1clk(l1clk), | |
2099 | .siclk(siclk), | |
2100 | .soclk(soclk), | |
2101 | .d(fdin[13]), | |
2102 | .si(sout[14]), | |
2103 | .so(sout[13]), | |
2104 | .reset(reset), | |
2105 | .q(dout[13]) | |
2106 | ); | |
2107 | cl_a1_msff_syrst_4x d0_14 ( | |
2108 | .l1clk(l1clk), | |
2109 | .siclk(siclk), | |
2110 | .soclk(soclk), | |
2111 | .d(fdin[14]), | |
2112 | .si(sout[15]), | |
2113 | .so(sout[14]), | |
2114 | .reset(reset), | |
2115 | .q(dout[14]) | |
2116 | ); | |
2117 | cl_a1_msff_syrst_4x d0_15 ( | |
2118 | .l1clk(l1clk), | |
2119 | .siclk(siclk), | |
2120 | .soclk(soclk), | |
2121 | .d(fdin[15]), | |
2122 | .si(sout[16]), | |
2123 | .so(sout[15]), | |
2124 | .reset(reset), | |
2125 | .q(dout[15]) | |
2126 | ); | |
2127 | cl_a1_msff_syrst_4x d0_16 ( | |
2128 | .l1clk(l1clk), | |
2129 | .siclk(siclk), | |
2130 | .soclk(soclk), | |
2131 | .d(fdin[16]), | |
2132 | .si(sout[17]), | |
2133 | .so(sout[16]), | |
2134 | .reset(reset), | |
2135 | .q(dout[16]) | |
2136 | ); | |
2137 | cl_a1_msff_syrst_4x d0_17 ( | |
2138 | .l1clk(l1clk), | |
2139 | .siclk(siclk), | |
2140 | .soclk(soclk), | |
2141 | .d(fdin[17]), | |
2142 | .si(sout[18]), | |
2143 | .so(sout[17]), | |
2144 | .reset(reset), | |
2145 | .q(dout[17]) | |
2146 | ); | |
2147 | cl_a1_msff_syrst_4x d0_18 ( | |
2148 | .l1clk(l1clk), | |
2149 | .siclk(siclk), | |
2150 | .soclk(soclk), | |
2151 | .d(fdin[18]), | |
2152 | .si(sout[19]), | |
2153 | .so(sout[18]), | |
2154 | .reset(reset), | |
2155 | .q(dout[18]) | |
2156 | ); | |
2157 | cl_a1_msff_syrst_4x d0_19 ( | |
2158 | .l1clk(l1clk), | |
2159 | .siclk(siclk), | |
2160 | .soclk(soclk), | |
2161 | .d(fdin[19]), | |
2162 | .si(sout[20]), | |
2163 | .so(sout[19]), | |
2164 | .reset(reset), | |
2165 | .q(dout[19]) | |
2166 | ); | |
2167 | cl_a1_msff_syrst_4x d0_20 ( | |
2168 | .l1clk(l1clk), | |
2169 | .siclk(siclk), | |
2170 | .soclk(soclk), | |
2171 | .d(fdin[20]), | |
2172 | .si(sout[21]), | |
2173 | .so(sout[20]), | |
2174 | .reset(reset), | |
2175 | .q(dout[20]) | |
2176 | ); | |
2177 | cl_a1_msff_syrst_4x d0_21 ( | |
2178 | .l1clk(l1clk), | |
2179 | .siclk(siclk), | |
2180 | .soclk(soclk), | |
2181 | .d(fdin[21]), | |
2182 | .si(sout[22]), | |
2183 | .so(sout[21]), | |
2184 | .reset(reset), | |
2185 | .q(dout[21]) | |
2186 | ); | |
2187 | cl_a1_msff_syrst_4x d0_22 ( | |
2188 | .l1clk(l1clk), | |
2189 | .siclk(siclk), | |
2190 | .soclk(soclk), | |
2191 | .d(fdin[22]), | |
2192 | .si(sout[23]), | |
2193 | .so(sout[22]), | |
2194 | .reset(reset), | |
2195 | .q(dout[22]) | |
2196 | ); | |
2197 | cl_a1_msff_syrst_4x d0_23 ( | |
2198 | .l1clk(l1clk), | |
2199 | .siclk(siclk), | |
2200 | .soclk(soclk), | |
2201 | .d(fdin[23]), | |
2202 | .si(sout[24]), | |
2203 | .so(sout[23]), | |
2204 | .reset(reset), | |
2205 | .q(dout[23]) | |
2206 | ); | |
2207 | cl_a1_msff_syrst_4x d0_24 ( | |
2208 | .l1clk(l1clk), | |
2209 | .siclk(siclk), | |
2210 | .soclk(soclk), | |
2211 | .d(fdin[24]), | |
2212 | .si(sout[25]), | |
2213 | .so(sout[24]), | |
2214 | .reset(reset), | |
2215 | .q(dout[24]) | |
2216 | ); | |
2217 | cl_a1_msff_syrst_4x d0_25 ( | |
2218 | .l1clk(l1clk), | |
2219 | .siclk(siclk), | |
2220 | .soclk(soclk), | |
2221 | .d(fdin[25]), | |
2222 | .si(sout[26]), | |
2223 | .so(sout[25]), | |
2224 | .reset(reset), | |
2225 | .q(dout[25]) | |
2226 | ); | |
2227 | cl_a1_msff_syrst_4x d0_26 ( | |
2228 | .l1clk(l1clk), | |
2229 | .siclk(siclk), | |
2230 | .soclk(soclk), | |
2231 | .d(fdin[26]), | |
2232 | .si(sout[27]), | |
2233 | .so(sout[26]), | |
2234 | .reset(reset), | |
2235 | .q(dout[26]) | |
2236 | ); | |
2237 | cl_a1_msff_syrst_4x d0_27 ( | |
2238 | .l1clk(l1clk), | |
2239 | .siclk(siclk), | |
2240 | .soclk(soclk), | |
2241 | .d(fdin[27]), | |
2242 | .si(sout[28]), | |
2243 | .so(sout[27]), | |
2244 | .reset(reset), | |
2245 | .q(dout[27]) | |
2246 | ); | |
2247 | cl_a1_msff_syrst_4x d0_28 ( | |
2248 | .l1clk(l1clk), | |
2249 | .siclk(siclk), | |
2250 | .soclk(soclk), | |
2251 | .d(fdin[28]), | |
2252 | .si(sout[29]), | |
2253 | .so(sout[28]), | |
2254 | .reset(reset), | |
2255 | .q(dout[28]) | |
2256 | ); | |
2257 | cl_a1_msff_syrst_4x d0_29 ( | |
2258 | .l1clk(l1clk), | |
2259 | .siclk(siclk), | |
2260 | .soclk(soclk), | |
2261 | .d(fdin[29]), | |
2262 | .si(sout[30]), | |
2263 | .so(sout[29]), | |
2264 | .reset(reset), | |
2265 | .q(dout[29]) | |
2266 | ); | |
2267 | cl_a1_msff_syrst_4x d0_30 ( | |
2268 | .l1clk(l1clk), | |
2269 | .siclk(siclk), | |
2270 | .soclk(soclk), | |
2271 | .d(fdin[30]), | |
2272 | .si(sout[31]), | |
2273 | .so(sout[30]), | |
2274 | .reset(reset), | |
2275 | .q(dout[30]) | |
2276 | ); | |
2277 | cl_a1_msff_syrst_4x d0_31 ( | |
2278 | .l1clk(l1clk), | |
2279 | .siclk(siclk), | |
2280 | .soclk(soclk), | |
2281 | .d(fdin[31]), | |
2282 | .si(sout[32]), | |
2283 | .so(sout[31]), | |
2284 | .reset(reset), | |
2285 | .q(dout[31]) | |
2286 | ); | |
2287 | cl_a1_msff_syrst_4x d0_32 ( | |
2288 | .l1clk(l1clk), | |
2289 | .siclk(siclk), | |
2290 | .soclk(soclk), | |
2291 | .d(fdin[32]), | |
2292 | .si(sout[33]), | |
2293 | .so(sout[32]), | |
2294 | .reset(reset), | |
2295 | .q(dout[32]) | |
2296 | ); | |
2297 | cl_a1_msff_syrst_4x d0_33 ( | |
2298 | .l1clk(l1clk), | |
2299 | .siclk(siclk), | |
2300 | .soclk(soclk), | |
2301 | .d(fdin[33]), | |
2302 | .si(sout[34]), | |
2303 | .so(sout[33]), | |
2304 | .reset(reset), | |
2305 | .q(dout[33]) | |
2306 | ); | |
2307 | cl_a1_msff_syrst_4x d0_34 ( | |
2308 | .l1clk(l1clk), | |
2309 | .siclk(siclk), | |
2310 | .soclk(soclk), | |
2311 | .d(fdin[34]), | |
2312 | .si(sout[35]), | |
2313 | .so(sout[34]), | |
2314 | .reset(reset), | |
2315 | .q(dout[34]) | |
2316 | ); | |
2317 | cl_a1_msff_syrst_4x d0_35 ( | |
2318 | .l1clk(l1clk), | |
2319 | .siclk(siclk), | |
2320 | .soclk(soclk), | |
2321 | .d(fdin[35]), | |
2322 | .si(sout[36]), | |
2323 | .so(sout[35]), | |
2324 | .reset(reset), | |
2325 | .q(dout[35]) | |
2326 | ); | |
2327 | cl_a1_msff_syrst_4x d0_36 ( | |
2328 | .l1clk(l1clk), | |
2329 | .siclk(siclk), | |
2330 | .soclk(soclk), | |
2331 | .d(fdin[36]), | |
2332 | .si(sout[37]), | |
2333 | .so(sout[36]), | |
2334 | .reset(reset), | |
2335 | .q(dout[36]) | |
2336 | ); | |
2337 | cl_a1_msff_syrst_4x d0_37 ( | |
2338 | .l1clk(l1clk), | |
2339 | .siclk(siclk), | |
2340 | .soclk(soclk), | |
2341 | .d(fdin[37]), | |
2342 | .si(sout[38]), | |
2343 | .so(sout[37]), | |
2344 | .reset(reset), | |
2345 | .q(dout[37]) | |
2346 | ); | |
2347 | cl_a1_msff_syrst_4x d0_38 ( | |
2348 | .l1clk(l1clk), | |
2349 | .siclk(siclk), | |
2350 | .soclk(soclk), | |
2351 | .d(fdin[38]), | |
2352 | .si(sout[39]), | |
2353 | .so(sout[38]), | |
2354 | .reset(reset), | |
2355 | .q(dout[38]) | |
2356 | ); | |
2357 | cl_a1_msff_syrst_4x d0_39 ( | |
2358 | .l1clk(l1clk), | |
2359 | .siclk(siclk), | |
2360 | .soclk(soclk), | |
2361 | .d(fdin[39]), | |
2362 | .si(sout[40]), | |
2363 | .so(sout[39]), | |
2364 | .reset(reset), | |
2365 | .q(dout[39]) | |
2366 | ); | |
2367 | cl_a1_msff_syrst_4x d0_40 ( | |
2368 | .l1clk(l1clk), | |
2369 | .siclk(siclk), | |
2370 | .soclk(soclk), | |
2371 | .d(fdin[40]), | |
2372 | .si(sout[41]), | |
2373 | .so(sout[40]), | |
2374 | .reset(reset), | |
2375 | .q(dout[40]) | |
2376 | ); | |
2377 | cl_a1_msff_syrst_4x d0_41 ( | |
2378 | .l1clk(l1clk), | |
2379 | .siclk(siclk), | |
2380 | .soclk(soclk), | |
2381 | .d(fdin[41]), | |
2382 | .si(scan_in), | |
2383 | .so(sout[41]), | |
2384 | .reset(reset), | |
2385 | .q(dout[41]) | |
2386 | ); | |
2387 | ||
2388 | ||
2389 | ||
2390 | ||
2391 | endmodule | |
2392 | ||
2393 | ||
2394 | ||
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | ||
2402 | ||
2403 | ||
2404 | ||
2405 | // any PARAMS parms go into naming of macro | |
2406 | ||
2407 | module niu_mb6_msff_ctl_macro__library_a1__reset_1__width_2 ( | |
2408 | din, | |
2409 | reset, | |
2410 | l1clk, | |
2411 | scan_in, | |
2412 | siclk, | |
2413 | soclk, | |
2414 | dout, | |
2415 | scan_out); | |
2416 | wire [1:0] fdin; | |
2417 | wire [1:1] sout; | |
2418 | ||
2419 | input [1:0] din; | |
2420 | input reset; | |
2421 | input l1clk; | |
2422 | input scan_in; | |
2423 | ||
2424 | ||
2425 | input siclk; | |
2426 | input soclk; | |
2427 | ||
2428 | output [1:0] dout; | |
2429 | output scan_out; | |
2430 | assign fdin[1:0] = din[1:0] & {2 {reset}}; | |
2431 | ||
2432 | ||
2433 | ||
2434 | ||
2435 | ||
2436 | ||
2437 | ||
2438 | ||
2439 | ||
2440 | ||
2441 | ||
2442 | ||
2443 | ||
2444 | ||
2445 | ||
2446 | ||
2447 | ||
2448 | cl_a1_msff_syrst_4x d0_0 ( | |
2449 | .l1clk(l1clk), | |
2450 | .siclk(siclk), | |
2451 | .soclk(soclk), | |
2452 | .d(fdin[0]), | |
2453 | .si(sout[1]), | |
2454 | .so(scan_out), | |
2455 | .reset(reset), | |
2456 | .q(dout[0]) | |
2457 | ); | |
2458 | cl_a1_msff_syrst_4x d0_1 ( | |
2459 | .l1clk(l1clk), | |
2460 | .siclk(siclk), | |
2461 | .soclk(soclk), | |
2462 | .d(fdin[1]), | |
2463 | .si(scan_in), | |
2464 | .so(sout[1]), | |
2465 | .reset(reset), | |
2466 | .q(dout[1]) | |
2467 | ); | |
2468 | ||
2469 | ||
2470 | ||
2471 | ||
2472 | endmodule | |
2473 | ||
2474 | ||
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | ||
2480 |