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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_meta_arb.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_meta_arb.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`include "niu_meta_arb_define.h"
36
37// VPERL: PERL_BEG
38//
39// $VPERL_PORT_COMM = 1;
40// $VPERL_INST_COMM = 2;
41//
42// &MODULE ("niu_meta_arb");
43// &DECLARE ("input", niu_clk);
44//
45// &INSTANCE ("/vobs/neptune/design/niu/niu_meta_arb/rtl/niu_wr_meta_arb.v", "niu_wr_meta_arb");
46// &INSTANCE ("/vobs/neptune/design/niu/niu_meta_arb/rtl/niu_rd_meta_arb.v", "niu_rd_meta_arb");
47// &INSTANCE ("/vobs/neptune/design/niu/niu_meta_arb/rtl/niu_meta_arb_reset.v", "niu_meta_arb_reset");
48// &INSTANCE ("/vobs/neptune/design/niu/niu_meta_arb/rtl/niu_meta_arb_dbg.v", "arb_debug");
49//
50// &FORCE ("wire", "clk");
51//
52//# &FORCE ("wire", "clk_cts");
53//# &CONNECT ("niu_wr_meta_arb.clk" , "clk_cts");
54//# &CONNECT ("niu_rd_meta_arb.clk" , "clk_cts");
55//# &CONNECT ("niu_meta_arb_reset.clk" , "clk_cts");
56//# &CONNECT ("arb_debug.clk" , "clk_cts");
57//
58// VPERL: PERL_END
59// VPERL: GENERATED_BEG
60
61module niu_meta_arb (
62 niu_clk, // input () <= ()
63 niu_reset_l, // input (niu_meta_arb_reset) <= ()
64`ifdef NEPTUNE
65 zcp_arb1_req, // input (niu_rd_meta_arb) <= ()
66 zcp_arb1_req_address, // input (niu_rd_meta_arb) <= ()
67 zcp_arb1_req_cmd, // input (niu_rd_meta_arb) <= ()
68 zcp_arb1_req_dma_num, // input (niu_rd_meta_arb) <= ()
69 zcp_arb1_req_func_num, // input (niu_rd_meta_arb) <= ()
70 zcp_arb1_req_length, // input (niu_rd_meta_arb) <= ()
71 zcp_arb1_req_port_num, // input (niu_rd_meta_arb) <= ()
72 arb1_zcp_req_accept, // output (niu_rd_meta_arb) => ()
73 dmc_meta0_req_func_num, // output (niu_wr_meta_arb) => ()
74 dmc_meta1_req_func_num, // output (niu_rd_meta_arb) => ()
75 dmc_meta_ack_accept, // input (niu_wr_meta_arb) <= ()
76 dmc_meta_resp_accept, // input (niu_rd_meta_arb) <= ()
77`else
78 rdmc_meta_ack_accept, // input (niu_wr_meta_arb) <= ()
79 tdmc_meta_ack_accept, // input (niu_wr_meta_arb) <= ()
80 rdmc_meta_resp_accept, // input (niu_rd_meta_arb) <= ()
81 tdmc_meta_resp_accept, // input (niu_rd_meta_arb) <= ()
82 txc_meta_resp_accept, // input (niu_rd_meta_arb) <= ()
83`endif
84
85 meta_dmc0_data_req, // input (niu_wr_meta_arb) <= ()
86 meta_dmc0_req_accept, // input (niu_wr_meta_arb) <= ()
87 meta_dmc0_req_errors, // input (niu_wr_meta_arb) <= ()
88 meta_dmc1_req_accept, // input (niu_rd_meta_arb) <= ()
89 meta_dmc1_req_errors, // input (niu_rd_meta_arb) <= ()
90 meta_dmc_ack_cmd_status, // input (niu_wr_meta_arb) <= ()
91 meta_dmc_ack_transID, // input (niu_wr_meta_arb) <= ()
92 meta_dmc_ack_transfer_cmpl, // input (niu_wr_meta_arb) <= ()
93 meta_dmc_resp_cmd_status, // input (niu_rd_meta_arb) <= ()
94 meta_dmc_resp_transID, // input (niu_rd_meta_arb) <= ()
95 meta_dmc_resp_transfer_cmpl, // input (niu_rd_meta_arb) <= ()
96 pio_arb_ctrl, // input (arb_debug) <= ()
97 pio_arb_debug_vector, // input (arb_debug) <= ()
98 pio_arb_dirtid_clr, // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
99 pio_arb_dirtid_enable, // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
100 pio_arb_np_threshold, // input (niu_wr_meta_arb) <= ()
101 pio_arb_rd_threshold, // input (niu_rd_meta_arb) <= ()
102 rbr_arb1_req, // input (niu_rd_meta_arb) <= ()
103 rbr_arb1_req_address, // input (niu_rd_meta_arb) <= ()
104 rbr_arb1_req_cmd, // input (niu_rd_meta_arb) <= ()
105 rbr_arb1_req_dma_num, // input (niu_rd_meta_arb) <= ()
106 rbr_arb1_req_func_num, // input (niu_rd_meta_arb) <= ()
107 rbr_arb1_req_length, // input (niu_rd_meta_arb) <= ()
108 rbr_arb1_req_port_num, // input (niu_rd_meta_arb) <= ()
109 rcr_arb0_data, // input (niu_wr_meta_arb) <= ()
110 rcr_arb0_data_valid, // input (niu_wr_meta_arb) <= ()
111 rcr_arb0_req, // input (niu_wr_meta_arb) <= ()
112 rcr_arb0_req_address, // input (niu_wr_meta_arb) <= ()
113 rcr_arb0_req_byteenable, // input (niu_wr_meta_arb) <= ()
114 rcr_arb0_req_cmd, // input (niu_wr_meta_arb) <= ()
115 rcr_arb0_req_dma_num, // input (niu_wr_meta_arb) <= ()
116 rcr_arb0_req_func_num, // input (niu_wr_meta_arb) <= ()
117 rcr_arb0_req_length, // input (niu_wr_meta_arb) <= ()
118 rcr_arb0_req_port_num, // input (niu_wr_meta_arb) <= ()
119 rcr_arb0_status, // input (niu_wr_meta_arb) <= ()
120 rcr_arb0_transfer_complete, // input (niu_wr_meta_arb) <= ()
121 rdc_arb0_data, // input (niu_wr_meta_arb) <= ()
122 rdc_arb0_data_valid, // input (niu_wr_meta_arb) <= ()
123 rdc_arb0_req, // input (niu_wr_meta_arb) <= ()
124 rdc_arb0_req_address, // input (niu_wr_meta_arb) <= ()
125 rdc_arb0_req_byteenable, // input (niu_wr_meta_arb) <= ()
126 rdc_arb0_req_cmd, // input (niu_wr_meta_arb) <= ()
127 rdc_arb0_req_dma_num, // input (niu_wr_meta_arb) <= ()
128 rdc_arb0_req_func_num, // input (niu_wr_meta_arb) <= ()
129 rdc_arb0_req_length, // input (niu_wr_meta_arb) <= ()
130 rdc_arb0_req_port_num, // input (niu_wr_meta_arb) <= ()
131 rdc_arb0_status, // input (niu_wr_meta_arb) <= ()
132 rdc_arb0_transfer_complete, // input (niu_wr_meta_arb) <= ()
133 tdmc_arb0_data, // input (niu_wr_meta_arb) <= ()
134 tdmc_arb0_data_valid, // input (niu_wr_meta_arb) <= ()
135 tdmc_arb0_req, // input (niu_wr_meta_arb) <= ()
136 tdmc_arb0_req_address, // input (niu_wr_meta_arb) <= ()
137 tdmc_arb0_req_byteenable, // input (niu_wr_meta_arb) <= ()
138 tdmc_arb0_req_cmd, // input (niu_wr_meta_arb) <= ()
139 tdmc_arb0_req_dma_num, // input (niu_wr_meta_arb) <= ()
140 tdmc_arb0_req_func_num, // input (niu_wr_meta_arb) <= ()
141 tdmc_arb0_req_length, // input (niu_wr_meta_arb) <= ()
142 tdmc_arb0_req_port_num, // input (niu_wr_meta_arb) <= ()
143 tdmc_arb0_status, // input (niu_wr_meta_arb) <= ()
144 tdmc_arb0_transfer_complete, // input (niu_wr_meta_arb) <= ()
145 tdmc_arb1_req, // input (niu_rd_meta_arb) <= ()
146 tdmc_arb1_req_address, // input (niu_rd_meta_arb) <= ()
147 tdmc_arb1_req_cmd, // input (niu_rd_meta_arb) <= ()
148 tdmc_arb1_req_dma_num, // input (niu_rd_meta_arb) <= ()
149 tdmc_arb1_req_func_num, // input (niu_rd_meta_arb) <= ()
150 tdmc_arb1_req_length, // input (niu_rd_meta_arb) <= ()
151 tdmc_arb1_req_port_num, // input (niu_rd_meta_arb) <= ()
152 txc_arb1_req, // input (niu_rd_meta_arb) <= ()
153 txc_arb1_req_address, // input (niu_rd_meta_arb) <= ()
154 txc_arb1_req_cmd, // input (niu_rd_meta_arb) <= ()
155 txc_arb1_req_dma_num, // input (niu_rd_meta_arb) <= ()
156 txc_arb1_req_func_num, // input (niu_rd_meta_arb) <= ()
157 txc_arb1_req_length, // input (niu_rd_meta_arb) <= ()
158 txc_arb1_req_port_num, // input (niu_rd_meta_arb) <= ()
159 arb0_rcr_data_req, // output (niu_wr_meta_arb) => ()
160 arb0_rcr_req_accept, // output (niu_wr_meta_arb) => ()
161 arb0_rdc_data_req, // output (niu_wr_meta_arb) => ()
162 arb0_rdc_req_accept, // output (niu_wr_meta_arb) => ()
163 arb0_tdmc_data_req, // output (niu_wr_meta_arb) => ()
164 arb0_tdmc_req_accept, // output (niu_wr_meta_arb) => ()
165 arb1_rbr_req_accept, // output (niu_rd_meta_arb) => ()
166 arb1_tdmc_req_accept, // output (niu_rd_meta_arb) => ()
167 arb1_txc_req_accept, // output (niu_rd_meta_arb) => ()
168/*
169 arb0_rcr_req_errors, // output (niu_wr_meta_arb) => ()
170 arb0_rdc_req_errors, // output (niu_wr_meta_arb) => ()
171 arb0_tdmc_req_errors, // output (niu_wr_meta_arb) => ()
172 arb1_tdmc_req_errors, // output (niu_rd_meta_arb) => ()
173 arb1_txc_req_errors, // output (niu_rd_meta_arb) => ()
174 arb1_zcp_req_errors, // output (niu_rd_meta_arb) => ()
175*/
176 arb1_rbr_req_errors, // output (niu_rd_meta_arb) => ()
177
178 arb_pio_all_npwdirty, // output (niu_wr_meta_arb) => ()
179 arb_pio_all_rddirty, // output (niu_rd_meta_arb) => ()
180 arb_pio_dirtid_npwstatus, // output (niu_wr_meta_arb) => ()
181 arb_pio_dirtid_rdstatus, // output (niu_rd_meta_arb) => ()
182 dmc_meta0_data, // output (niu_wr_meta_arb) => ()
183 dmc_meta0_data_valid, // output (niu_wr_meta_arb) => ()
184 dmc_meta0_req, // output (niu_wr_meta_arb) => ()
185 dmc_meta0_req_address, // output (niu_wr_meta_arb) => ()
186 dmc_meta0_req_byteenable, // output (niu_wr_meta_arb) => ()
187 dmc_meta0_req_client, // output (niu_wr_meta_arb) => ()
188 dmc_meta0_req_cmd, // output (niu_wr_meta_arb) => ()
189 dmc_meta0_req_dma_num, // output (niu_wr_meta_arb) => ()
190 dmc_meta0_req_length, // output (niu_wr_meta_arb) => ()
191 dmc_meta0_req_port_num, // output (niu_wr_meta_arb) => ()
192 dmc_meta0_req_transID, // output (niu_wr_meta_arb) => ()
193 dmc_meta0_status, // output (niu_wr_meta_arb) => ()
194 dmc_meta0_transfer_complete, // output (niu_wr_meta_arb) => ()
195 dmc_meta1_req, // output (niu_rd_meta_arb) => ()
196 dmc_meta1_req_address, // output (niu_rd_meta_arb) => ()
197 dmc_meta1_req_client, // output (niu_rd_meta_arb) => ()
198 dmc_meta1_req_cmd, // output (niu_rd_meta_arb) => ()
199 dmc_meta1_req_dma_num, // output (niu_rd_meta_arb) => ()
200 dmc_meta1_req_length, // output (niu_rd_meta_arb) => ()
201 dmc_meta1_req_port_num, // output (niu_rd_meta_arb) => ()
202 dmc_meta1_req_transID, // output (niu_rd_meta_arb) => ()
203 meta_arb_debug_port // output (arb_debug) => ()
204 );
205
206input meta_dmc0_data_req; // Memory line request
207input meta_dmc0_req_accept; // Response to REQ
208input meta_dmc0_req_errors; // Error flag
209input meta_dmc1_req_accept; // Response to REQ
210input meta_dmc1_req_errors; // Error flag
211input [3:0] meta_dmc_ack_cmd_status; // status in command phase
212input [5:0] meta_dmc_ack_transID; // Free TransID
213input [7:0] meta_dmc_ack_transfer_cmpl; // Last trans of TransID
214input [3:0] meta_dmc_resp_cmd_status; // status in command phase
215input [5:0] meta_dmc_resp_transID; // Free TransID
216input [7:0] meta_dmc_resp_transfer_cmpl; // Last trans of TransID
217input [31:0] pio_arb_ctrl;
218input [31:0] pio_arb_debug_vector;
219input pio_arb_dirtid_clr; // Clear all Dirty TID Entries
220input pio_arb_dirtid_enable; // Enable Dirty TID logic
221input [5:0] pio_arb_np_threshold; // np write threshold
222input [5:0] pio_arb_rd_threshold; // read threshold
223input rbr_arb1_req; // Req Command Request
224input [63:0] rbr_arb1_req_address; // Memory Address
225input [7:0] rbr_arb1_req_cmd; // Command Request
226input [4:0] rbr_arb1_req_dma_num; // Channel Number
227input [1:0] rbr_arb1_req_func_num; // Channel Number
228input [13:0] rbr_arb1_req_length; // Packet Length
229input [1:0] rbr_arb1_req_port_num; // Port Number
230input [127:0] rcr_arb0_data; // Transfer Data
231input rcr_arb0_data_valid; // Transfer Data Ack
232input rcr_arb0_req; // Req Command Request
233input [63:0] rcr_arb0_req_address; // Memory Address
234input [15:0] rcr_arb0_req_byteenable; // First/Last BE
235input [7:0] rcr_arb0_req_cmd; // Command Request
236input [4:0] rcr_arb0_req_dma_num; // Channel Number
237input [1:0] rcr_arb0_req_func_num; // Channel Number
238input [13:0] rcr_arb0_req_length; // Packet Length
239input [1:0] rcr_arb0_req_port_num; // Port Number
240input [3:0] rcr_arb0_status; // Transfer Data Status
241input rcr_arb0_transfer_complete; // Transfer Data Complete
242input [127:0] rdc_arb0_data; // Transfer Data
243input rdc_arb0_data_valid; // Transfer Data Ack
244input rdc_arb0_req; // Req Command Request
245input [63:0] rdc_arb0_req_address; // Memory Address
246input [15:0] rdc_arb0_req_byteenable; // First/Last BE
247input [7:0] rdc_arb0_req_cmd; // Command Request
248input [4:0] rdc_arb0_req_dma_num; // Channel Number
249input [1:0] rdc_arb0_req_func_num; // Channel Number
250input [13:0] rdc_arb0_req_length; // Packet Length
251input [1:0] rdc_arb0_req_port_num; // Port Number
252input [3:0] rdc_arb0_status; // Transfer Data Status
253input rdc_arb0_transfer_complete; // Transfer Data Complete
254input [127:0] tdmc_arb0_data; // Transfer Data
255input tdmc_arb0_data_valid; // Transfer Data Ack
256input tdmc_arb0_req; // Req Command Request
257input [63:0] tdmc_arb0_req_address; // Memory Address
258input [15:0] tdmc_arb0_req_byteenable; // First/Last BE
259input [7:0] tdmc_arb0_req_cmd; // Command Request
260input [4:0] tdmc_arb0_req_dma_num; // Channel Number
261input [1:0] tdmc_arb0_req_func_num; // Func Number
262input [13:0] tdmc_arb0_req_length; // Packet Length
263input [1:0] tdmc_arb0_req_port_num; // Port Number
264input [3:0] tdmc_arb0_status; // Transfer Data Status
265input tdmc_arb0_transfer_complete; // Transfer Data Complete
266input tdmc_arb1_req; // Req Command Request
267input [63:0] tdmc_arb1_req_address; // Memory Address
268input [7:0] tdmc_arb1_req_cmd; // Command Request
269input [4:0] tdmc_arb1_req_dma_num; // Channel Number
270input [1:0] tdmc_arb1_req_func_num; // Channel Number
271input [13:0] tdmc_arb1_req_length; // Packet Length
272input [1:0] tdmc_arb1_req_port_num; // Port Number
273input txc_arb1_req; // Req Command Request
274input [63:0] txc_arb1_req_address; // Memory Address
275input [7:0] txc_arb1_req_cmd; // Command Request
276input [4:0] txc_arb1_req_dma_num; // Channel Number
277input [1:0] txc_arb1_req_func_num; // Channel Number
278input [13:0] txc_arb1_req_length; // Packet Length
279input [1:0] txc_arb1_req_port_num; // Port Number
280output arb0_rcr_data_req; // Memory line request
281output arb0_rcr_req_accept; // Response to REQ
282output arb0_rdc_data_req; // Memory line request
283output arb0_rdc_req_accept; // Response to REQ
284output arb0_tdmc_data_req; // Memory line request
285output arb0_tdmc_req_accept; // Response to REQ
286output arb1_rbr_req_accept; // Response to REQ
287output arb1_tdmc_req_accept; // Response to REQ
288output arb1_txc_req_accept; // Response to REQ
289/*
290output arb0_rcr_req_errors; // Error flag
291output arb0_rdc_req_errors; // Error flag
292output arb0_tdmc_req_errors; // Error flag
293output arb1_tdmc_req_errors; // Error flag
294output arb1_txc_req_errors; // Error flag
295output arb1_zcp_req_errors; // Error flag
296*/
297
298output arb1_rbr_req_errors; // Error flag
299
300output arb_pio_all_npwdirty; // all dirty bin entries are dirty
301output arb_pio_all_rddirty; // all dirty bin entries are dirty
302output [5:0] arb_pio_dirtid_npwstatus; // count for number of np write TID's dirty
303output [5:0] arb_pio_dirtid_rdstatus; // count for number of read TID's dirty
304output [127:0] dmc_meta0_data; // Transfer Data
305output dmc_meta0_data_valid; // Transfer Data Ack
306output dmc_meta0_req; // Req Command Request
307output [63:0] dmc_meta0_req_address; // Memory Address
308output [15:0] dmc_meta0_req_byteenable; // First/Last BE
309output [7:0] dmc_meta0_req_client; // Client [vector]
310output [7:0] dmc_meta0_req_cmd; // Command Request
311output [4:0] dmc_meta0_req_dma_num; // Channel Number
312output [13:0] dmc_meta0_req_length; // Packet Length
313output [1:0] dmc_meta0_req_port_num; // Port Number
314output [5:0] dmc_meta0_req_transID; // Transaction ID
315output [3:0] dmc_meta0_status; // Transfer Data Status
316output dmc_meta0_transfer_complete; // Transfer Data Complete
317output dmc_meta1_req; // Req Command Request
318output [63:0] dmc_meta1_req_address; // Memory Address
319output [7:0] dmc_meta1_req_client; // Client [vector]
320output [7:0] dmc_meta1_req_cmd; // Command Request
321output [4:0] dmc_meta1_req_dma_num; // Channel Number
322output [13:0] dmc_meta1_req_length; // Packet Length
323output [1:0] dmc_meta1_req_port_num; // Port Number
324output [5:0] dmc_meta1_req_transID; // Transaction ID
325output [31:0] meta_arb_debug_port;
326
327
328input niu_clk;
329input niu_reset_l;
330
331`ifdef NEPTUNE
332input zcp_arb1_req; // Req Command Request
333input [63:0] zcp_arb1_req_address; // Memory Address
334input [7:0] zcp_arb1_req_cmd; // Command Request
335input [4:0] zcp_arb1_req_dma_num; // Channel Number
336input [1:0] zcp_arb1_req_func_num; // Channel Number
337input [13:0] zcp_arb1_req_length; // Packet Length
338input [1:0] zcp_arb1_req_port_num; // Port Number
339output arb1_zcp_req_accept; // Response to REQ
340output [1:0] dmc_meta0_req_func_num; // Channel Number
341output [1:0] dmc_meta1_req_func_num; // Channel Number
342input [7:0] dmc_meta_ack_accept; // Valid TransID
343input [7:0] dmc_meta_resp_accept; // Valid TransID
344`else
345input rdmc_meta_ack_accept; // Valid TransID
346input tdmc_meta_ack_accept; // Valid TransID
347input rdmc_meta_resp_accept; // Valid TransID
348input tdmc_meta_resp_accept; // Valid TransID
349input txc_meta_resp_accept; // Valid TransID
350wire zcp_arb1_req= 1'b0; // Req Command Request
351wire [63:0] zcp_arb1_req_address= 64'h0; // Memory Address
352wire [7:0] zcp_arb1_req_cmd= 8'h0; // Command Request
353wire [4:0] zcp_arb1_req_dma_num= 5'h0; // Channel Number
354wire [1:0] zcp_arb1_req_func_num= 2'h0; // Channel Number
355wire [13:0] zcp_arb1_req_length= 14'h0; // Packet Length
356wire [1:0] zcp_arb1_req_port_num= 2'h0; // Port Number
357wire arb1_zcp_req_accept; // Response to REQ
358wire [1:0] dmc_meta0_req_func_num; // Channel Number
359wire [1:0] dmc_meta1_req_func_num; // Channel Number
360wire [7:0] dmc_meta_ack_accept= {1'b0, 1'b0, 1'b0,
361 rdmc_meta_ack_accept, 1'b0,
362 tdmc_meta_ack_accept, 1'b0, 1'b0};
363wire [7:0] dmc_meta_resp_accept= {1'b0, 1'b0,
364 rdmc_meta_resp_accept, 1'b0, 1'b0,
365 tdmc_meta_resp_accept,
366 txc_meta_resp_accept, 1'b0};
367`endif
368
369// wire clk;
370wire reset;
371wire arb0_rcr_req_errors; // Error flag
372wire arb0_rdc_req_errors; // Error flag
373wire arb0_tdmc_req_errors; // Error flag
374wire arb1_tdmc_req_errors; // Error flag
375wire arb1_txc_req_errors; // Error flag
376wire arb1_zcp_req_errors; // Error flag
377
378reg pio_arb_dirtid_clr_r; // Clear all Dirty TID Entries
379reg pio_arb_dirtid_enable_r; // Enable Dirty TID logic
380reg [5:0] pio_arb_np_threshold_r; // np write threshold
381reg [5:0] pio_arb_rd_threshold_r; // read threshold
382
383wire [31:0] int_debug_port;
384
385niu_wr_meta_arb niu_wr_meta_arb (
386 .dmc_meta0_req_cmd (dmc_meta0_req_cmd[7:0]), // output (niu_wr_meta_arb) => ()
387 .dmc_meta0_req_address (dmc_meta0_req_address[63:0]), // output (niu_wr_meta_arb) => ()
388 .dmc_meta0_req_length (dmc_meta0_req_length[13:0]), // output (niu_wr_meta_arb) => ()
389 .dmc_meta0_req_transID (dmc_meta0_req_transID[5:0]), // output (niu_wr_meta_arb) => ()
390 .dmc_meta0_req_port_num (dmc_meta0_req_port_num[1:0]), // output (niu_wr_meta_arb) => ()
391 .dmc_meta0_req_dma_num (dmc_meta0_req_dma_num[4:0]), // output (niu_wr_meta_arb) => ()
392 .dmc_meta0_req_func_num (dmc_meta0_req_func_num[1:0]), // output (niu_wr_meta_arb) => ()
393 .dmc_meta0_req_client (dmc_meta0_req_client[7:0]), // output (niu_wr_meta_arb) => ()
394 .dmc_meta0_req (dmc_meta0_req), // output (niu_wr_meta_arb) => ()
395 .dmc_meta0_transfer_complete (dmc_meta0_transfer_complete), // output (niu_wr_meta_arb) => ()
396 .dmc_meta0_data (dmc_meta0_data[127:0]), // output (niu_wr_meta_arb) => ()
397 .dmc_meta0_req_byteenable (dmc_meta0_req_byteenable[15:0]), // output (niu_wr_meta_arb) => ()
398 .dmc_meta0_status (dmc_meta0_status[3:0]), // output (niu_wr_meta_arb) => ()
399 .dmc_meta0_data_valid (dmc_meta0_data_valid), // output (niu_wr_meta_arb) => ()
400 .arb0_tdmc_req_accept (arb0_tdmc_req_accept), // output (niu_wr_meta_arb) => ()
401 .arb0_tdmc_data_req (arb0_tdmc_data_req), // output (niu_wr_meta_arb) => ()
402 .arb0_tdmc_req_errors (arb0_tdmc_req_errors), // output (niu_wr_meta_arb) => ()
403 .arb0_rdc_req_accept (arb0_rdc_req_accept), // output (niu_wr_meta_arb) => ()
404 .arb0_rdc_data_req (arb0_rdc_data_req), // output (niu_wr_meta_arb) => ()
405 .arb0_rdc_req_errors (arb0_rdc_req_errors), // output (niu_wr_meta_arb) => ()
406 .arb0_rcr_req_accept (arb0_rcr_req_accept), // output (niu_wr_meta_arb) => ()
407 .arb0_rcr_data_req (arb0_rcr_data_req), // output (niu_wr_meta_arb) => ()
408 .arb0_rcr_req_errors (arb0_rcr_req_errors), // output (niu_wr_meta_arb) => ()
409 .arb_pio_dirtid_npwstatus (arb_pio_dirtid_npwstatus[5:0]), // output (niu_wr_meta_arb) => ()
410 .arb_pio_all_npwdirty (arb_pio_all_npwdirty), // output (niu_wr_meta_arb) => ()
411 .meta_dmc0_req_accept (meta_dmc0_req_accept), // input (niu_wr_meta_arb) <= ()
412 .meta_dmc0_data_req (meta_dmc0_data_req), // input (niu_wr_meta_arb) <= ()
413 .meta_dmc0_req_errors (meta_dmc0_req_errors), // input (niu_wr_meta_arb) <= ()
414 .tdmc_arb0_req_cmd (tdmc_arb0_req_cmd[7:0]), // input (niu_wr_meta_arb) <= ()
415 .tdmc_arb0_req_address (tdmc_arb0_req_address[63:0]), // input (niu_wr_meta_arb) <= ()
416 .tdmc_arb0_req_length (tdmc_arb0_req_length[13:0]), // input (niu_wr_meta_arb) <= ()
417 .tdmc_arb0_req_port_num (tdmc_arb0_req_port_num[1:0]), // input (niu_wr_meta_arb) <= ()
418 .tdmc_arb0_req_dma_num (tdmc_arb0_req_dma_num[4:0]), // input (niu_wr_meta_arb) <= ()
419 .tdmc_arb0_req_func_num (tdmc_arb0_req_func_num[1:0]), // input (niu_wr_meta_arb) <= ()
420 .tdmc_arb0_req (tdmc_arb0_req), // input (niu_wr_meta_arb) <= ()
421 .tdmc_arb0_transfer_complete (tdmc_arb0_transfer_complete), // input (niu_wr_meta_arb) <= ()
422 .tdmc_arb0_data (tdmc_arb0_data[127:0]), // input (niu_wr_meta_arb) <= ()
423 .tdmc_arb0_req_byteenable (tdmc_arb0_req_byteenable[15:0]), // input (niu_wr_meta_arb) <= ()
424 .tdmc_arb0_status (tdmc_arb0_status[3:0]), // input (niu_wr_meta_arb) <= ()
425 .tdmc_arb0_data_valid (tdmc_arb0_data_valid), // input (niu_wr_meta_arb) <= ()
426 .rdc_arb0_req_cmd (rdc_arb0_req_cmd[7:0]), // input (niu_wr_meta_arb) <= ()
427 .rdc_arb0_req_address (rdc_arb0_req_address[63:0]), // input (niu_wr_meta_arb) <= ()
428 .rdc_arb0_req_length (rdc_arb0_req_length[13:0]), // input (niu_wr_meta_arb) <= ()
429 .rdc_arb0_req_port_num (rdc_arb0_req_port_num[1:0]), // input (niu_wr_meta_arb) <= ()
430 .rdc_arb0_req_dma_num (rdc_arb0_req_dma_num[4:0]), // input (niu_wr_meta_arb) <= ()
431 .rdc_arb0_req_func_num (rdc_arb0_req_func_num[1:0]), // input (niu_wr_meta_arb) <= ()
432 .rdc_arb0_req (rdc_arb0_req), // input (niu_wr_meta_arb) <= ()
433 .rdc_arb0_transfer_complete (rdc_arb0_transfer_complete), // input (niu_wr_meta_arb) <= ()
434 .rdc_arb0_data (rdc_arb0_data[127:0]), // input (niu_wr_meta_arb) <= ()
435 .rdc_arb0_req_byteenable (rdc_arb0_req_byteenable[15:0]), // input (niu_wr_meta_arb) <= ()
436 .rdc_arb0_status (rdc_arb0_status[3:0]), // input (niu_wr_meta_arb) <= ()
437 .rdc_arb0_data_valid (rdc_arb0_data_valid), // input (niu_wr_meta_arb) <= ()
438 .rcr_arb0_req_cmd (rcr_arb0_req_cmd[7:0]), // input (niu_wr_meta_arb) <= ()
439 .rcr_arb0_req_address (rcr_arb0_req_address[63:0]), // input (niu_wr_meta_arb) <= ()
440 .rcr_arb0_req_length (rcr_arb0_req_length[13:0]), // input (niu_wr_meta_arb) <= ()
441 .rcr_arb0_req_port_num (rcr_arb0_req_port_num[1:0]), // input (niu_wr_meta_arb) <= ()
442 .rcr_arb0_req_dma_num (rcr_arb0_req_dma_num[4:0]), // input (niu_wr_meta_arb) <= ()
443 .rcr_arb0_req_func_num (rcr_arb0_req_func_num[1:0]), // input (niu_wr_meta_arb) <= ()
444 .rcr_arb0_req (rcr_arb0_req), // input (niu_wr_meta_arb) <= ()
445 .rcr_arb0_transfer_complete (rcr_arb0_transfer_complete), // input (niu_wr_meta_arb) <= ()
446 .rcr_arb0_data (rcr_arb0_data[127:0]), // input (niu_wr_meta_arb) <= ()
447 .rcr_arb0_req_byteenable (rcr_arb0_req_byteenable[15:0]), // input (niu_wr_meta_arb) <= ()
448 .rcr_arb0_status (rcr_arb0_status[3:0]), // input (niu_wr_meta_arb) <= ()
449 .rcr_arb0_data_valid (rcr_arb0_data_valid), // input (niu_wr_meta_arb) <= ()
450 .meta_dmc_ack_transID (meta_dmc_ack_transID[5:0]), // input (niu_wr_meta_arb) <= ()
451 .dmc_meta_ack_accept (dmc_meta_ack_accept[7:0]), // input (niu_wr_meta_arb) <= ()
452 .meta_dmc_ack_transfer_cmpl (meta_dmc_ack_transfer_cmpl[7:0]), // input (niu_wr_meta_arb) <= ()
453 .meta_dmc_ack_cmd_status (meta_dmc_ack_cmd_status[3:0]), // input (niu_wr_meta_arb) <= ()
454 .pio_arb_dirtid_enable (pio_arb_dirtid_enable_r), // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
455 .pio_arb_dirtid_clr (pio_arb_dirtid_clr_r), // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
456 .pio_arb_np_threshold (pio_arb_np_threshold_r[5:0]), // input (niu_wr_meta_arb) <= ()
457 .clk (niu_clk), // input (arb_debug,niu_meta_arb_reset,niu_rd_meta_arb,niu_wr_meta_arb) <= ()
458 .reset (reset) // input (niu_rd_meta_arb,niu_wr_meta_arb) <= (niu_meta_arb_reset)
459 );
460
461niu_rd_meta_arb niu_rd_meta_arb (
462 .dmc_meta1_req_cmd (dmc_meta1_req_cmd[7:0]), // output (niu_rd_meta_arb) => ()
463 .dmc_meta1_req_address (dmc_meta1_req_address[63:0]), // output (niu_rd_meta_arb) => ()
464 .dmc_meta1_req_length (dmc_meta1_req_length[13:0]), // output (niu_rd_meta_arb) => ()
465 .dmc_meta1_req_transID (dmc_meta1_req_transID[5:0]), // output (niu_rd_meta_arb) => ()
466 .dmc_meta1_req_port_num (dmc_meta1_req_port_num[1:0]), // output (niu_rd_meta_arb) => ()
467 .dmc_meta1_req_dma_num (dmc_meta1_req_dma_num[4:0]), // output (niu_rd_meta_arb) => ()
468 .dmc_meta1_req_func_num (dmc_meta1_req_func_num[1:0]), // output (niu_rd_meta_arb) => ()
469 .dmc_meta1_req_client (dmc_meta1_req_client[7:0]), // output (niu_rd_meta_arb) => ()
470 .dmc_meta1_req (dmc_meta1_req), // output (niu_rd_meta_arb) => ()
471 .arb1_zcp_req_accept (arb1_zcp_req_accept), // output (niu_rd_meta_arb) => ()
472 .arb1_zcp_req_errors (arb1_zcp_req_errors), // output (niu_rd_meta_arb) => ()
473 .arb1_txc_req_accept (arb1_txc_req_accept), // output (niu_rd_meta_arb) => ()
474 .arb1_txc_req_errors (arb1_txc_req_errors), // output (niu_rd_meta_arb) => ()
475 .arb1_tdmc_req_accept (arb1_tdmc_req_accept), // output (niu_rd_meta_arb) => ()
476 .arb1_tdmc_req_errors (arb1_tdmc_req_errors), // output (niu_rd_meta_arb) => ()
477 .arb1_rbr_req_accept (arb1_rbr_req_accept), // output (niu_rd_meta_arb) => ()
478 .arb1_rbr_req_errors (arb1_rbr_req_errors), // output (niu_rd_meta_arb) => ()
479 .arb_pio_dirtid_rdstatus (arb_pio_dirtid_rdstatus[5:0]), // output (niu_rd_meta_arb) => ()
480 .arb_pio_all_rddirty (arb_pio_all_rddirty), // output (niu_rd_meta_arb) => ()
481 .meta_dmc1_req_accept (meta_dmc1_req_accept), // input (niu_rd_meta_arb) <= ()
482 .meta_dmc1_req_errors (meta_dmc1_req_errors), // input (niu_rd_meta_arb) <= ()
483 .zcp_arb1_req_cmd (zcp_arb1_req_cmd[7:0]), // input (niu_rd_meta_arb) <= ()
484 .zcp_arb1_req_address (zcp_arb1_req_address[63:0]), // input (niu_rd_meta_arb) <= ()
485 .zcp_arb1_req_length (zcp_arb1_req_length[13:0]), // input (niu_rd_meta_arb) <= ()
486 .zcp_arb1_req_port_num (zcp_arb1_req_port_num[1:0]), // input (niu_rd_meta_arb) <= ()
487 .zcp_arb1_req_dma_num (zcp_arb1_req_dma_num[4:0]), // input (niu_rd_meta_arb) <= ()
488 .zcp_arb1_req_func_num (zcp_arb1_req_func_num[1:0]), // input (niu_rd_meta_arb) <= ()
489 .zcp_arb1_req (zcp_arb1_req), // input (niu_rd_meta_arb) <= ()
490 .txc_arb1_req_cmd (txc_arb1_req_cmd[7:0]), // input (niu_rd_meta_arb) <= ()
491 .txc_arb1_req_address (txc_arb1_req_address[63:0]), // input (niu_rd_meta_arb) <= ()
492 .txc_arb1_req_length (txc_arb1_req_length[13:0]), // input (niu_rd_meta_arb) <= ()
493 .txc_arb1_req_port_num (txc_arb1_req_port_num[1:0]), // input (niu_rd_meta_arb) <= ()
494 .txc_arb1_req_dma_num (txc_arb1_req_dma_num[4:0]), // input (niu_rd_meta_arb) <= ()
495 .txc_arb1_req_func_num (txc_arb1_req_func_num[1:0]), // input (niu_rd_meta_arb) <= ()
496 .txc_arb1_req (txc_arb1_req), // input (niu_rd_meta_arb) <= ()
497 .tdmc_arb1_req_cmd (tdmc_arb1_req_cmd[7:0]), // input (niu_rd_meta_arb) <= ()
498 .tdmc_arb1_req_address (tdmc_arb1_req_address[63:0]), // input (niu_rd_meta_arb) <= ()
499 .tdmc_arb1_req_length (tdmc_arb1_req_length[13:0]), // input (niu_rd_meta_arb) <= ()
500 .tdmc_arb1_req_port_num (tdmc_arb1_req_port_num[1:0]), // input (niu_rd_meta_arb) <= ()
501 .tdmc_arb1_req_dma_num (tdmc_arb1_req_dma_num[4:0]), // input (niu_rd_meta_arb) <= ()
502 .tdmc_arb1_req_func_num (tdmc_arb1_req_func_num[1:0]), // input (niu_rd_meta_arb) <= ()
503 .tdmc_arb1_req (tdmc_arb1_req), // input (niu_rd_meta_arb) <= ()
504 .rbr_arb1_req_cmd (rbr_arb1_req_cmd[7:0]), // input (niu_rd_meta_arb) <= ()
505 .rbr_arb1_req_address (rbr_arb1_req_address[63:0]), // input (niu_rd_meta_arb) <= ()
506 .rbr_arb1_req_length (rbr_arb1_req_length[13:0]), // input (niu_rd_meta_arb) <= ()
507 .rbr_arb1_req_port_num (rbr_arb1_req_port_num[1:0]), // input (niu_rd_meta_arb) <= ()
508 .rbr_arb1_req_dma_num (rbr_arb1_req_dma_num[4:0]), // input (niu_rd_meta_arb) <= ()
509 .rbr_arb1_req_func_num (rbr_arb1_req_func_num[1:0]), // input (niu_rd_meta_arb) <= ()
510 .rbr_arb1_req (rbr_arb1_req), // input (niu_rd_meta_arb) <= ()
511 .meta_dmc_resp_transID (meta_dmc_resp_transID[5:0]), // input (niu_rd_meta_arb) <= ()
512 .dmc_meta_resp_accept (dmc_meta_resp_accept[7:0]), // input (niu_rd_meta_arb) <= ()
513 .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl[7:0]), // input (niu_rd_meta_arb) <= ()
514 .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status[3:0]), // input (niu_rd_meta_arb) <= ()
515 .pio_arb_dirtid_enable (pio_arb_dirtid_enable_r), // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
516 .pio_arb_dirtid_clr (pio_arb_dirtid_clr_r), // input (niu_rd_meta_arb,niu_wr_meta_arb) <= ()
517 .pio_arb_rd_threshold (pio_arb_rd_threshold_r[5:0]), // input (niu_rd_meta_arb) <= ()
518 .clk (niu_clk), // input (arb_debug,niu_meta_arb_reset,niu_rd_meta_arb,niu_wr_meta_arb) <= ()
519 .reset (reset) // input (niu_rd_meta_arb,niu_wr_meta_arb) <= (niu_meta_arb_reset)
520 );
521
522niu_meta_arb_reset niu_meta_arb_reset (
523 .clk (niu_clk), // input (arb_debug,niu_meta_arb_reset,niu_rd_meta_arb,niu_wr_meta_arb) <= ()
524 .reset_l (niu_reset_l), // input (niu_meta_arb_reset) <= ()
525 .reset (reset) // output (niu_meta_arb_reset) => (niu_rd_meta_arb,niu_wr_meta_arb)
526 );
527
528niu_meta_arb_dbg arb_debug (
529 .clk (niu_clk), // input (arb_debug,niu_meta_arb_reset,niu_rd_meta_arb,niu_wr_meta_arb) <= ()
530 .pio_arb_ctrl (pio_arb_ctrl[31:0]), // input (arb_debug) <= ()
531 .pio_arb_debug_vector (pio_arb_debug_vector[31:0]), // input (arb_debug) <= ()
532 .meta_arb_debug_port (meta_arb_debug_port[31:0]), // output (arb_debug) => ()
533 .int_debug_port (int_debug_port[31:0])
534 );
535// VPERL: GENERATED_END
536
537
538
539// add flop in for pio signals to fix timing
540// do this on top as a kludge :<
541always @(posedge niu_clk) begin
542 if(reset) begin
543 pio_arb_dirtid_clr_r<= 1'b0;
544 pio_arb_dirtid_enable_r<= 1'b0;
545 pio_arb_np_threshold_r<= 6'd31;
546 pio_arb_rd_threshold_r<= 6'd32;
547 end
548 else begin
549 pio_arb_dirtid_clr_r<= pio_arb_dirtid_clr;
550 pio_arb_dirtid_enable_r<= pio_arb_dirtid_enable;
551 pio_arb_np_threshold_r<= pio_arb_np_threshold;
552 pio_arb_rd_threshold_r<= pio_arb_rd_threshold;
553 end
554end
555
556assign int_debug_port= {
557 2'h0,
558 tdmc_arb0_req, // Req Command Request
559 rcr_arb0_req, // Req Command Request
560 rdc_arb0_req, // Req Command Request
561 tdmc_arb1_req, // Req Command Request
562 txc_arb1_req, // Req Command Request
563 rbr_arb1_req, // Req Command Request
564 arb0_tdmc_data_req, // Memory line request
565 arb0_rcr_data_req, // Memory line request
566 arb0_rdc_data_req, // Memory line request
567 dmc_meta0_req, // Req Command Request
568 dmc_meta1_req, // Req Command Request
569 meta_dmc0_data_req, // Memory line request
570 meta_dmc_ack_transfer_cmpl[2], // Last trans of TransID
571 meta_dmc_ack_transfer_cmpl[3], // Last trans of TransID
572 meta_dmc_ack_transfer_cmpl[4], // Last trans of TransID
573 meta_dmc_resp_transfer_cmpl[1], // Last trans of TransID
574 meta_dmc_resp_transfer_cmpl[2], // Last trans of TransID
575 meta_dmc_resp_transfer_cmpl[5], // Last trans of TransID
576 rcr_arb0_data_valid, // Transfer Data Ack
577 rdc_arb0_data_valid, // Transfer Data Ack
578 tdmc_arb0_data_valid, // Transfer Data Ack
579 dmc_meta0_data_valid, // Transfer Data Ack
580 rcr_arb0_transfer_complete, // Transfer Data Complete
581 rdc_arb0_transfer_complete, // Transfer Data Complete
582 tdmc_arb0_transfer_complete, // Transfer Data Complete
583 dmc_meta0_transfer_complete, // Transfer Data Complete
584 meta_dmc_resp_cmd_status[3:2], // status in command phase
585 meta_dmc_ack_cmd_status[3:2] // status in command phase
586 };
587
588
589`ifdef NEPTUNE
590wire [3:0] do_nad;
591wire [3:0] do_nor;
592wire [3:0] do_inv;
593wire [3:0] do_mux;
594wire [3:0] do_q;
595wire so;
596
597 nep_spare_meta_arb spare_0 (
598 .di_nd3 ({1'h1, 1'h1, do_q[3]}),
599 .di_nd2 ({1'h1, 1'h1, do_q[2]}),
600 .di_nd1 ({1'h1, 1'h1, do_q[1]}),
601 .di_nd0 ({1'h1, 1'h1, do_q[0]}),
602 .di_nr3 ({1'h0, 1'h0}),
603 .di_nr2 ({1'h0, 1'h0}),
604 .di_nr1 ({1'h0, 1'h0}),
605 .di_nr0 ({1'h0, 1'h0}),
606 .di_inv (do_nad[3:0]),
607 .di_mx3 ({1'h0, 1'h0}),
608 .di_mx2 ({1'h0, 1'h0}),
609 .di_mx1 ({1'h0, 1'h0}),
610 .di_mx0 ({1'h0, 1'h0}),
611 .mx_sel (do_nor[3:0]),
612 .di_reg (do_inv[3:0]),
613 .wt_ena (do_mux[3:0]),
614 .rst ({reset,reset,reset,reset}),
615 .si (1'h0),
616 .se (1'h0),
617 .clk (niu_clk),
618 .do_nad (do_nad[3:0]),
619 .do_nor (do_nor[3:0]),
620 .do_inv (do_inv[3:0]),
621 .do_mux (do_mux[3:0]),
622 .do_q (do_q[3:0]),
623 .so (so)
624 );
625`endif
626
627endmodule
Full OpenSPARC design & verification tarball including full HDL.