Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_meta_arb_dbg.v

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// OpenSPARC T2 Processor File: niu_meta_arb_dbg.v
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module niu_meta_arb_dbg(
	/*AUTOARG*/
   // Outputs
   meta_arb_debug_port, 
   // Inputs
   clk, pio_arb_ctrl, pio_arb_debug_vector,
   int_debug_port
   );

input clk;

input [31:0] pio_arb_ctrl;
input [31:0] pio_arb_debug_vector;
input [31:0] int_debug_port;

		// output to debug blk
output [31:0]   meta_arb_debug_port;


reg [31:0]  meta_arb_debug_port, meta_arb_debug_port_n;
reg [31:0] pio_arb_debug_vector_r;
reg [2:0] debug_sel;
 
// wire [31:0] int_debug_port= 32'h0;

always @(posedge clk)  begin
  meta_arb_debug_port<= meta_arb_debug_port_n;
  pio_arb_debug_vector_r<=  pio_arb_debug_vector;
  debug_sel<= pio_arb_ctrl[2:0];
end


/*AUTO_CONSTANT (`META_ARB__TRAINING_SET `MEGA_ARB__TRAINING_LOAD)*/

always @ (/*AUTOSENSE*/debug_sel or int_debug_port
	  or meta_arb_debug_port or pio_arb_debug_vector_r) begin
  case(debug_sel) 
    `META_ARB_TRAINING_SET: meta_arb_debug_port_n= ~meta_arb_debug_port;
    `META_ARB_TRAINING_LOAD: meta_arb_debug_port_n= pio_arb_debug_vector_r;
    default: meta_arb_debug_port_n= int_debug_port;
  endcase 
end


endmodule