Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_meta_arb_reset.v

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// OpenSPARC T2 Processor File: niu_meta_arb_reset.v
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/*********************************************************************
 *
 *  niu_meta_arb_reset.v
 *
 *  Reset Block, includes LogicVision Reset Gating
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):        Nimita Taneja
 *  Project(s):          Neptune/Niagara 2
 *
 *  Copyright (c) 2003   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/



module niu_meta_arb_reset ( /*AUTOARG*/
   // Outputs
   reset, 
   // Inputs
   clk, reset_l
   );


// Clock & Reset
input   clk;
input   reset_l;
output  reset;

/*--------------------------------------------------------------*/
// Registers & Wires
/*--------------------------------------------------------------*/
reg     resetDlyOneCycle;

/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign reset = resetDlyOneCycle;


/*--------------------------------------------------------------*/
// Control Logic
/*--------------------------------------------------------------*/
 always @ (posedge clk)
   begin
     resetDlyOneCycle <=  ~reset_l;
   end

endmodule