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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_meta_rd_tagfifo.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * niu_meta_rd_tagfifo.v | |
38 | * | |
39 | * Parameterized synchronous fifo for buffering data and commands | |
40 | * in the gpi data path, this fifo is initialized with default tags | |
41 | * | |
42 | * Original Author(s): Nimita Taneja | |
43 | * Modifier(s): | |
44 | * Project(s): Neptune | |
45 | * | |
46 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
47 | * | |
48 | * Revision History: 03-01-2004 : Initial Release | |
49 | * | |
50 | * All Rights Reserved. | |
51 | * | |
52 | * This verilog model is the confidential and proprietary property of | |
53 | * Sun Microsystems, Inc., and the possession or use of this model | |
54 | * requires a written license from Sun Microsystems, Inc. | |
55 | * | |
56 | **********************************************************************/ | |
57 | ||
58 | module niu_meta_rd_tagfifo (core_clk, reset , inc_rp, inc_wp, fifo_not_empty, | |
59 | fifo_full, din, rdout, dout, count); | |
60 | ||
61 | parameter WIDTH = 5; | |
62 | parameter [31:0] DEPTH = 32; | |
63 | parameter ASIZE = 5; | |
64 | ||
65 | input core_clk, reset , inc_rp, inc_wp; | |
66 | input [WIDTH-1:0] din; | |
67 | ||
68 | output fifo_not_empty, fifo_full; | |
69 | output [WIDTH-1:0] rdout; | |
70 | output [WIDTH-1:0] dout; | |
71 | output [ASIZE:0] count; | |
72 | ||
73 | ||
74 | reg [WIDTH-1:0] fifo[0:DEPTH-1]; | |
75 | reg [ASIZE-1:0] wp; | |
76 | reg [ASIZE-1:0] rp; | |
77 | wire [WIDTH-1:0] dout; | |
78 | reg [WIDTH-1:0] rdout; | |
79 | reg [ASIZE:0] fifosize; | |
80 | wire fifo_not_empty; | |
81 | wire fifo_empty; | |
82 | wire fifo_full; | |
83 | //reg [WIDTH-1:0] i; | |
84 | integer i; | |
85 | wire [ASIZE:0] count; | |
86 | assign count = fifosize; | |
87 | ||
88 | assign fifo_full = (fifosize==DEPTH[ASIZE:0]); | |
89 | ||
90 | // synopsys translate_off | |
91 | `ifdef META_ERR_CHECK | |
92 | reg error; | |
93 | always@(posedge core_clk) begin | |
94 | if (reset) error <= 0; | |
95 | else if (fifo_full & inc_wp) begin | |
96 | error = 1; | |
97 | $display($time, " %m -ERROR: fifo overrun !!!!!!!!!"); | |
98 | repeat(10) @(posedge core_clk); | |
99 | end | |
100 | else if ((fifosize == 0) & inc_rp) begin | |
101 | error = 1; | |
102 | $display($time, " %m -ERROR: fifo underrun !!!!!!!!!"); | |
103 | repeat(10) @(posedge core_clk); | |
104 | end | |
105 | end | |
106 | `endif | |
107 | // synopsys translate_on | |
108 | ||
109 | always@(posedge core_clk) | |
110 | if (reset) fifosize <= 6'd32; | |
111 | else if (inc_wp & !inc_rp) fifosize <= fifosize +1'b1; | |
112 | else if (!inc_wp & inc_rp) fifosize <= fifosize -1'b1; | |
113 | else fifosize <= fifosize; | |
114 | ||
115 | ||
116 | ||
117 | assign fifo_not_empty = fifosize > 0; | |
118 | assign fifo_empty = (fifosize == 0); | |
119 | ||
120 | always@(posedge core_clk ) | |
121 | if (reset) wp <= 0; | |
122 | else if (inc_wp & !fifo_full) wp <= wp + 1'b1; | |
123 | ||
124 | always@(posedge core_clk) | |
125 | if (reset) rp <= 0; | |
126 | else if (inc_rp & !fifo_empty) rp <= rp + 1'b1; | |
127 | ||
128 | always@(posedge core_clk ) | |
129 | if (reset) begin | |
130 | // for (i=0; i<DEPTH; i=i+1) fifo[i] <= i; | |
131 | fifo[0] <= 5'd0; | |
132 | fifo[1] <= 5'd1; | |
133 | fifo[2] <= 5'd2; | |
134 | fifo[3] <= 5'd3; | |
135 | fifo[4] <= 5'd4; | |
136 | fifo[5] <= 5'd5; | |
137 | fifo[6] <= 5'd6; | |
138 | fifo[7] <= 5'd7; | |
139 | fifo[8] <= 5'd8; | |
140 | fifo[9] <= 5'd9; | |
141 | fifo[10] <= 5'd10; | |
142 | fifo[11] <= 5'd11; | |
143 | fifo[12] <= 5'd12; | |
144 | fifo[13] <= 5'd13; | |
145 | fifo[14] <= 5'd14; | |
146 | fifo[15] <= 5'd15; | |
147 | fifo[16] <= 5'd16; | |
148 | fifo[17] <= 5'd17; | |
149 | fifo[18] <= 5'd18; | |
150 | fifo[19] <= 5'd19; | |
151 | fifo[20] <= 5'd20; | |
152 | fifo[21] <= 5'd21; | |
153 | fifo[22] <= 5'd22; | |
154 | fifo[23] <= 5'd23; | |
155 | fifo[24] <= 5'd24; | |
156 | fifo[25] <= 5'd25; | |
157 | fifo[26] <= 5'd26; | |
158 | fifo[27] <= 5'd27; | |
159 | fifo[28] <= 5'd28; | |
160 | fifo[29] <= 5'd29; | |
161 | fifo[30] <= 5'd30; | |
162 | fifo[31] <= 5'd31; | |
163 | end | |
164 | else if (inc_wp) | |
165 | fifo[wp] <= din; | |
166 | else begin | |
167 | for (i=0; i<DEPTH; i=i+1) fifo[i] <= fifo[i]; | |
168 | end | |
169 | /* | |
170 | always@(rp or fifo[0] or fifo[1] or fifo_not_empty) | |
171 | case(rp) // synopsys parallel_case | |
172 | 1'b0: dout = fifo[0] & {WIDTH{fifo_not_empty}}; | |
173 | 1'b1: dout = fifo[1] & {WIDTH{fifo_not_empty}}; | |
174 | default: dout = fifo[0] & {WIDTH{fifo_not_empty}}; | |
175 | endcase | |
176 | */ | |
177 | ||
178 | assign dout = fifo[rp] & {WIDTH{fifo_not_empty}}; | |
179 | ||
180 | always@(posedge core_clk) | |
181 | if (reset) | |
182 | rdout <= 0; | |
183 | else | |
184 | rdout <= dout; | |
185 | ||
186 | endmodule |