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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_pio.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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17//
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21//
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34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : niu_pio.v
40 * Author Name : John Lo
41 * Description : It contains niu pio interface, interrupt controller,
42 * UCB for N2.
43 * Parent Module: niu
44 * Child Module:
45 * Interface Mod: many.
46 * Date Created : 3/08/2004
47 *
48 * Copyright (c) 2020, Sun Microsystems, Inc.
49 * Sun Proprietary and Confidential
50 *
51 * Modification : 4/19/04 : added reset_
52 * 8/25/04 : added pio_peu_32b, pio_peu_afull, pio_ht_32b.
53 * changed niu_reset_ to niu_reset_l.
54 * changed reset_ to reset_l.
55 *
56 * Synthesis Notes:
57 *
58 *************************************************************************/
59`include "niu_pio.h"
60
61module niu_pio (
62`ifdef NEPTUNE
63// peu interface signals
64// ------------------------
65peu_pio_32b,
66pio_peu_32b,
67pio_peu_afull,
68pio_clients_32b,
69int_invld,
70// prom pio signals
71pio_prom_sel,
72prom_pio_ack,
73prom_pio_rdata,
74prom_pio_err,
75// pim pio signals
76pio_pim_sel,
77pim_pio_ack,
78pim_pio_rdata,
79pim_pio_err,
80pim_pio_intr,
81// per port mac reset
82mac_reset2,
83mac_reset3,
84mac_pio_intr2,
85mac_pio_intr3,
86// pio gpio signals
87pio_gpio_data_out,
88pio_gpio_en_out,
89gpio_pio_data_in,
90`else
91// smx Interface
92pio_smx_cfg_data,
93smx_pio_intr,
94smx_pio_status,
95pio_smx_clear_intr,
96pio_smx_ctrl,
97pio_smx_debug_vector,
98// DFT Interface
99`endif
100// global signals
101niu_reset_l,
102niu_clk,
103reset,
104// pio broadcast signals
105pio_clients_addr,
106pio_clients_rd,
107pio_clients_wdata,
108// designated pio signals
109// mac pio signals
110pio_mac_sel,
111mac_pio_ack,
112mac_pio_rdata,
113mac_pio_err,
114mac_pio_intr0,
115mac_pio_intr1,
116mif_pio_intr,
117// ipp pio signals
118pio_ipp_sel,
119ipp_pio_ack,
120ipp_pio_rdata,
121ipp_pio_err,
122ipp_pio_intr,
123// fflp pio signals
124pio_fflp_sel,
125fflp_pio_ack,
126fflp_pio_rdata,
127fflp_pio_err,
128fflp_pio_intr,
129// zcp pio signals
130pio_zcp_sel,
131zcp_pio_ack,
132zcp_pio_rdata,
133zcp_pio_err,
134zcp_pio_intr,
135// dmc pio signals
136pio_tdmc_sel,
137tdmc_pio_ack,
138tdmc_pio_rdata,
139tdmc_pio_err,
140pio_rdmc_sel,
141rdmc_pio_ack,
142rdmc_pio_rdata,
143rdmc_pio_err,
144rdmc_pio_port_int,
145dmc_pio_intri, // level
146dmc_pio_intrj, // level
147// txc pio signals
148pio_txc_sel,
149txc_pio_ack,
150txc_pio_rdata,
151txc_pio_err,
152txc_pio_intr,
153// pio ucb signals
154// read cycle
155rd_req_vld,
156addr_in,
157thr_id_in,
158buf_id_in,
159req_accepted,
160rack_busy,
161rd_ack_vld,
162rd_nack_vld,
163data_out,
164thr_id_out,
165buf_id_out,
166// write cycle
167wr_req_vld,
168data_in,
169// interrupt intf
170int_busy,
171int_vld,
172dev_id,
173// Debug Port
174pio_debug_port,
175// per port mac reset
176mac_reset0,
177mac_reset1,
178// pio meta arb signals
179pio_arb_ctrl,
180pio_arb_debug_vector,
181arb_pio_all_npwdirty,
182arb_pio_all_rddirty,
183pio_arb_dirtid_enable,
184pio_arb_dirtid_clr,
185pio_arb_np_threshold,
186pio_arb_rd_threshold,
187arb_pio_dirtid_rdstatus,
188arb_pio_dirtid_npwstatus
189);
190
191
192`ifdef NEPTUNE
193 // peu interface signals
194 // ------------------------
195 input peu_pio_32b;
196 output pio_peu_32b;
197 output pio_peu_afull;
198 output pio_clients_32b;
199 output int_invld;
200 // prom pio signals
201 output pio_prom_sel;
202 input prom_pio_ack;
203 input [63:0] prom_pio_rdata;
204 input prom_pio_err;
205 // pim pio signals
206 output pio_pim_sel;
207 input pim_pio_ack;
208 input [63:0] pim_pio_rdata;
209 input pim_pio_err;
210 input pim_pio_intr;
211 // per port mac reset
212 output mac_reset2;
213 output mac_reset3;
214 // pio gpio signals
215 output [15:0] pio_gpio_data_out;
216 output [15:0] pio_gpio_en_out;
217 input [15:0] gpio_pio_data_in;
218
219 input mac_pio_intr2;
220 input mac_pio_intr3;
221`else
222 output [31:0] pio_smx_cfg_data ;
223 input smx_pio_intr ;
224 input [31:0] smx_pio_status ;
225 output pio_smx_clear_intr ;
226 output [31:0] pio_smx_ctrl ;
227 output [31:0] pio_smx_debug_vector ;
228`endif // ifdef NEPTUNE
229 // global signals
230 input niu_reset_l;
231 input niu_clk;
232 output reset;
233 // pio broadcast signals
234 output [19:0] pio_clients_addr;
235 output pio_clients_rd;
236 output [63:0] pio_clients_wdata;
237 // designated pio signals
238 // mac pio signals
239 output pio_mac_sel;
240 input mac_pio_ack;
241 input [63:0] mac_pio_rdata;
242 input mac_pio_err;
243 input mac_pio_intr0;
244 input mac_pio_intr1;
245 input mif_pio_intr;
246 // ipp pio signals
247 output pio_ipp_sel;
248 input ipp_pio_ack;
249 input [63:0] ipp_pio_rdata;
250 input ipp_pio_err;
251 input ipp_pio_intr;
252 // fflp pio signals
253 output pio_fflp_sel;
254 input fflp_pio_ack;
255 input [63:0] fflp_pio_rdata;
256 input fflp_pio_err;
257 input fflp_pio_intr;
258 // zcp pio signals
259 output pio_zcp_sel;
260 input zcp_pio_ack;
261 input [63:0] zcp_pio_rdata;
262 input zcp_pio_err;
263 input zcp_pio_intr;
264 // tdmc pio signals
265 output pio_tdmc_sel;
266 input tdmc_pio_ack;
267 input [63:0] tdmc_pio_rdata;
268 input tdmc_pio_err;
269 // rdmc pio signals
270 output pio_rdmc_sel;
271 input rdmc_pio_ack;
272 input [63:0] rdmc_pio_rdata;
273 input rdmc_pio_err;
274 input rdmc_pio_port_int;
275 // dmc interrupt signals
276 input [63:0] dmc_pio_intri; // level
277 input [63:0] dmc_pio_intrj; // level
278 // txc pio signals
279 output pio_txc_sel;
280 input txc_pio_ack;
281 input [63:0] txc_pio_rdata;
282 input txc_pio_err;
283 input txc_pio_intr;
284 // pio-ucb interface signals
285 // ------------------------
286 // read cycle
287 input rd_req_vld;
288 input [`PIO_ADDR_R] addr_in;
289 input [5:0] thr_id_in;
290 input [1:0] buf_id_in;
291 output req_accepted;
292 input rack_busy;
293 output rd_ack_vld;
294 output rd_nack_vld;
295 output [63:0] data_out;
296 output [5:0] thr_id_out;
297 output [1:0] buf_id_out;
298 // write cycle
299 input wr_req_vld;
300 input [63:0] data_in;
301 // interrupt intf
302 input int_busy;
303 output int_vld;
304 output [6:0] dev_id;
305 // per port mac reset
306 output mac_reset0;
307 output mac_reset1;
308
309 // PIO Debug Port
310 output [31:0] pio_debug_port;
311
312 // Meta Arb Ports
313 output pio_arb_dirtid_enable;
314 output pio_arb_dirtid_clr;
315 output [5:0] pio_arb_np_threshold;
316 output [5:0] pio_arb_rd_threshold;
317 input [5:0] arb_pio_dirtid_rdstatus;
318 input [5:0] arb_pio_dirtid_npwstatus;
319 input arb_pio_all_npwdirty;
320 input arb_pio_all_rddirty;
321 output [31:0] pio_arb_ctrl;
322 output [31:0] pio_arb_debug_vector;
323
324// Register and Wire Declaration
325// -----------------------------
326
327 reg pio_ack;
328 reg [63:0] pio_rdata;
329 reg pio_err;
330
331 wire meta_intr1;
332 wire meta_intr2;
333 wire smx_meta_intr_hld;
334
335 wire [31:0] pio_debug_port;
336
337 wire reset;
338 wire [19:0] pio_clients_addr;
339 wire [63:0] pio_clients_wdata;
340 wire [1:0] pio_clients_buf_id;
341 wire pio_clients_rd;
342 wire [19:0] clients_addr;
343 wire [`PIO_ADDR_R] addr;
344 wire [63:0] wdata;
345 wire [1:0] buf_id;
346 wire [5:0] thr_id;
347 wire rd;
348 wire mac_pio_ack;
349 wire [63:0] mac_pio_rdata;
350 wire mac_pio_err;
351 wire ipp_pio_ack;
352 wire [63:0] ipp_pio_rdata;
353 wire ipp_pio_err;
354 wire fflp_pio_ack;
355 wire [63:0] fflp_pio_rdata;
356 wire fflp_pio_err;
357 wire zcp_pio_ack;
358 wire [63:0] zcp_pio_rdata;
359 wire zcp_pio_err;
360 wire dmc_pio_ack;
361 wire [63:0] dmc_pio_rdata;
362 wire dmc_pio_err;
363 wire txc_pio_ack;
364 wire [63:0] txc_pio_rdata;
365 wire txc_pio_err;
366 wire mac_pio_ack_reg;
367 wire [63:0] mac_pio_rdata_reg;
368 wire mac_pio_err_reg;
369 wire ipp_pio_ack_reg;
370 wire [63:0] ipp_pio_rdata_reg;
371 wire ipp_pio_err_reg;
372 wire fflp_pio_ack_reg;
373 wire [63:0] fflp_pio_rdata_reg;
374 wire fflp_pio_err_reg;
375 wire zcp_pio_ack_reg;
376 wire [63:0] zcp_pio_rdata_reg;
377 wire zcp_pio_err_reg;
378 wire dmc_pio_ack_reg;
379 wire [63:0] dmc_pio_rdata_reg;
380 wire dmc_pio_err_reg;
381 wire txc_pio_ack_reg;
382 wire [63:0] txc_pio_rdata_reg;
383 wire txc_pio_err_reg;
384
385 wire prom_pio_ack_reg;
386 wire [63:0] prom_pio_rdata_reg;
387 wire prom_pio_err_reg;
388
389 wire pim_pio_ack_reg;
390 wire [63:0] pim_pio_rdata_reg;
391 wire pim_pio_err_reg;
392
393 wire ucb_ack;
394 wire ucb_nack;
395 wire ucb_rack;
396 wire [2:0] pio_rw_state;
397 wire ucb_rd_req;
398 wire [`PIO_ADDR_R] ucb_addr;
399 wire [5:0] ucb_thr_id;
400 wire [1:0] ucb_buf_id;
401 wire ucb_rack_busy;
402 wire ucb_wr_req;
403 wire [63:0] ucb_wdata;
404 wire full;
405 wire [4:0] wr_ptr;
406 wire [4:0] rd_ptr;
407 wire mode32b;
408 wire [`PIO_FIFO_W_R] fifo_din;
409 wire [`PIO_FIFO_W_R] fifo_dout;
410 wire [`PIO_FIFO_W_R] fifo_dout_reg;
411 wire accepted;
412 wire fc0;
413 wire fc1;
414 wire fc2;
415 wire fc3;
416 wire fc;
417 wire [68:0] ldfi;
418 wire [68:0] ldfj;
419 wire sel1;
420 wire pio_32b ;
421 wire pio_peu_afull ;
422 wire pio_clients_32b ;
423`ifdef NEPTUNE
424`endif
425 wire ibusy ;
426 wire fifo_wr_en ;
427 wire empty ;
428 wire slv_sel_reg ;
429 wire fzc_slv_sel_reg ;
430 wire ldsv_sel_reg ;
431 wire ldgim_sel_reg ;
432 wire imask0_sel_reg ;
433 wire imask1_sel_reg ;
434 wire ipp_intr ;
435 wire fflp_intr ;
436 wire zcp_intr ;
437 wire txc_intr ;
438 wire rdmc_intr ;
439 wire mif_intr ;
440 wire mac_reset2 ;
441 wire mac_reset3 ;
442
443 wire intr_reg_sel;
444
445 reg slv_sel ; // 0
446 reg fzc_slv_sel ; // 1
447 reg fzc_mac_sel ; // 2
448 reg fzc_ipp_sel ; // 3
449 reg fflp_sel ; // 4
450 reg fzc_fflp_sel ; // 5
451 reg zcp_sel ; // 6
452 reg fzc_zcp_sel ; // 8
453 reg dmc_sel ; // 9
454 reg fzc_dmc_sel ; // a
455 reg txc_sel ; // b
456 reg fzc_txc_sel ; // c
457 reg ldsv_sel ; // d
458// reg ldgim_sel ; // e
459 reg imask0_sel ; // f
460 reg imask1_sel ; //10
461 reg fzc_prom_sel ; //11
462 reg fzc_pim_sel ;
463
464// Split the PIO - DMC signals going out to RDMC and TDMC
465wire pio_dmc_sel ;
466assign pio_rdmc_sel = pio_dmc_sel & ~pio_clients_addr[18];
467assign pio_tdmc_sel = pio_dmc_sel & pio_clients_addr[18];
468
469assign dmc_pio_ack = (tdmc_pio_ack | rdmc_pio_ack);
470assign dmc_pio_err = pio_rdmc_sel? rdmc_pio_err : tdmc_pio_err;
471assign dmc_pio_rdata = pio_rdmc_sel? rdmc_pio_rdata : tdmc_pio_rdata;
472
473// End of modification.
474
475/*AUTOWIRE*/
476// Beginning of automatic wires (for undeclared instantiated-module outputs)
477wire [1:0] accepted_state; // From niu_pio_accepted_sm of niu_pio_accepted_sm.v
478wire ack_TO_en; // From niu_pio_regs of niu_pio_regs.v
479wire [9:0] ack_TO_value; // From niu_pio_regs of niu_pio_regs.v
480wire arm0; // From niu_pio_regs of niu_pio_regs.v
481wire arm1; // From niu_pio_regs of niu_pio_regs.v
482wire arm10; // From niu_pio_regs of niu_pio_regs.v
483wire arm11; // From niu_pio_regs of niu_pio_regs.v
484wire arm12; // From niu_pio_regs of niu_pio_regs.v
485wire arm13; // From niu_pio_regs of niu_pio_regs.v
486wire arm14; // From niu_pio_regs of niu_pio_regs.v
487wire arm15; // From niu_pio_regs of niu_pio_regs.v
488wire arm16; // From niu_pio_regs of niu_pio_regs.v
489wire arm17; // From niu_pio_regs of niu_pio_regs.v
490wire arm18; // From niu_pio_regs of niu_pio_regs.v
491wire arm19; // From niu_pio_regs of niu_pio_regs.v
492wire arm2; // From niu_pio_regs of niu_pio_regs.v
493wire arm20; // From niu_pio_regs of niu_pio_regs.v
494wire arm21; // From niu_pio_regs of niu_pio_regs.v
495wire arm22; // From niu_pio_regs of niu_pio_regs.v
496wire arm23; // From niu_pio_regs of niu_pio_regs.v
497wire arm24; // From niu_pio_regs of niu_pio_regs.v
498wire arm25; // From niu_pio_regs of niu_pio_regs.v
499wire arm26; // From niu_pio_regs of niu_pio_regs.v
500wire arm27; // From niu_pio_regs of niu_pio_regs.v
501wire arm28; // From niu_pio_regs of niu_pio_regs.v
502wire arm29; // From niu_pio_regs of niu_pio_regs.v
503wire arm3; // From niu_pio_regs of niu_pio_regs.v
504wire arm30; // From niu_pio_regs of niu_pio_regs.v
505wire arm31; // From niu_pio_regs of niu_pio_regs.v
506wire arm32; // From niu_pio_regs of niu_pio_regs.v
507wire arm33; // From niu_pio_regs of niu_pio_regs.v
508wire arm34; // From niu_pio_regs of niu_pio_regs.v
509wire arm35; // From niu_pio_regs of niu_pio_regs.v
510wire arm36; // From niu_pio_regs of niu_pio_regs.v
511wire arm37; // From niu_pio_regs of niu_pio_regs.v
512wire arm38; // From niu_pio_regs of niu_pio_regs.v
513wire arm39; // From niu_pio_regs of niu_pio_regs.v
514wire arm4; // From niu_pio_regs of niu_pio_regs.v
515wire arm40; // From niu_pio_regs of niu_pio_regs.v
516wire arm41; // From niu_pio_regs of niu_pio_regs.v
517wire arm42; // From niu_pio_regs of niu_pio_regs.v
518wire arm43; // From niu_pio_regs of niu_pio_regs.v
519wire arm44; // From niu_pio_regs of niu_pio_regs.v
520wire arm45; // From niu_pio_regs of niu_pio_regs.v
521wire arm46; // From niu_pio_regs of niu_pio_regs.v
522wire arm47; // From niu_pio_regs of niu_pio_regs.v
523wire arm48; // From niu_pio_regs of niu_pio_regs.v
524wire arm49; // From niu_pio_regs of niu_pio_regs.v
525wire arm5; // From niu_pio_regs of niu_pio_regs.v
526wire arm50; // From niu_pio_regs of niu_pio_regs.v
527wire arm51; // From niu_pio_regs of niu_pio_regs.v
528wire arm52; // From niu_pio_regs of niu_pio_regs.v
529wire arm53; // From niu_pio_regs of niu_pio_regs.v
530wire arm54; // From niu_pio_regs of niu_pio_regs.v
531wire arm55; // From niu_pio_regs of niu_pio_regs.v
532wire arm56; // From niu_pio_regs of niu_pio_regs.v
533wire arm57; // From niu_pio_regs of niu_pio_regs.v
534wire arm58; // From niu_pio_regs of niu_pio_regs.v
535wire arm59; // From niu_pio_regs of niu_pio_regs.v
536wire arm6; // From niu_pio_regs of niu_pio_regs.v
537wire arm60; // From niu_pio_regs of niu_pio_regs.v
538wire arm61; // From niu_pio_regs of niu_pio_regs.v
539wire arm62; // From niu_pio_regs of niu_pio_regs.v
540wire arm63; // From niu_pio_regs of niu_pio_regs.v
541wire arm7; // From niu_pio_regs of niu_pio_regs.v
542wire arm8; // From niu_pio_regs of niu_pio_regs.v
543wire arm9; // From niu_pio_regs of niu_pio_regs.v
544wire fifo_rd_en; // From niu_pio_rw_sm of niu_pio_rw_sm.v
545wire fzc_slv_ack; // From niu_pio_regs of niu_pio_regs.v
546wire fzc_slv_err; // From niu_pio_regs of niu_pio_regs.v
547wire [63:0] fzc_slv_rdata; // From niu_pio_regs of niu_pio_regs.v
548wire [5:0] group; // From niu_pio_ic of niu_pio_ic.v
549wire imask0_ack; // From niu_pio_regs of niu_pio_regs.v
550wire imask0_err; // From niu_pio_regs of niu_pio_regs.v
551wire [63:0] imask0_rdata; // From niu_pio_regs of niu_pio_regs.v
552wire imask1_ack; // From niu_pio_regs of niu_pio_regs.v
553wire imask1_err; // From niu_pio_regs of niu_pio_regs.v
554wire [63:0] imask1_rdata; // From niu_pio_regs of niu_pio_regs.v
555wire intr_valid; // From niu_pio_ic of niu_pio_ic.v
556wire [1:0] ldf_mask0; // From niu_pio_regs of niu_pio_regs.v
557wire [1:0] ldf_mask1; // From niu_pio_regs of niu_pio_regs.v
558wire [1:0] ldf_mask10; // From niu_pio_regs of niu_pio_regs.v
559wire [1:0] ldf_mask11; // From niu_pio_regs of niu_pio_regs.v
560wire [1:0] ldf_mask12; // From niu_pio_regs of niu_pio_regs.v
561wire [1:0] ldf_mask13; // From niu_pio_regs of niu_pio_regs.v
562wire [1:0] ldf_mask14; // From niu_pio_regs of niu_pio_regs.v
563wire [1:0] ldf_mask15; // From niu_pio_regs of niu_pio_regs.v
564wire [1:0] ldf_mask16; // From niu_pio_regs of niu_pio_regs.v
565wire [1:0] ldf_mask17; // From niu_pio_regs of niu_pio_regs.v
566wire [1:0] ldf_mask18; // From niu_pio_regs of niu_pio_regs.v
567wire [1:0] ldf_mask19; // From niu_pio_regs of niu_pio_regs.v
568wire [1:0] ldf_mask2; // From niu_pio_regs of niu_pio_regs.v
569wire [1:0] ldf_mask20; // From niu_pio_regs of niu_pio_regs.v
570wire [1:0] ldf_mask21; // From niu_pio_regs of niu_pio_regs.v
571wire [1:0] ldf_mask22; // From niu_pio_regs of niu_pio_regs.v
572wire [1:0] ldf_mask23; // From niu_pio_regs of niu_pio_regs.v
573wire [1:0] ldf_mask24; // From niu_pio_regs of niu_pio_regs.v
574wire [1:0] ldf_mask25; // From niu_pio_regs of niu_pio_regs.v
575wire [1:0] ldf_mask26; // From niu_pio_regs of niu_pio_regs.v
576wire [1:0] ldf_mask27; // From niu_pio_regs of niu_pio_regs.v
577wire [1:0] ldf_mask28; // From niu_pio_regs of niu_pio_regs.v
578wire [1:0] ldf_mask29; // From niu_pio_regs of niu_pio_regs.v
579wire [1:0] ldf_mask3; // From niu_pio_regs of niu_pio_regs.v
580wire [1:0] ldf_mask30; // From niu_pio_regs of niu_pio_regs.v
581wire [1:0] ldf_mask31; // From niu_pio_regs of niu_pio_regs.v
582wire [1:0] ldf_mask32; // From niu_pio_regs of niu_pio_regs.v
583wire [1:0] ldf_mask33; // From niu_pio_regs of niu_pio_regs.v
584wire [1:0] ldf_mask34; // From niu_pio_regs of niu_pio_regs.v
585wire [1:0] ldf_mask35; // From niu_pio_regs of niu_pio_regs.v
586wire [1:0] ldf_mask36; // From niu_pio_regs of niu_pio_regs.v
587wire [1:0] ldf_mask37; // From niu_pio_regs of niu_pio_regs.v
588wire [1:0] ldf_mask38; // From niu_pio_regs of niu_pio_regs.v
589wire [1:0] ldf_mask39; // From niu_pio_regs of niu_pio_regs.v
590wire [1:0] ldf_mask4; // From niu_pio_regs of niu_pio_regs.v
591wire [1:0] ldf_mask40; // From niu_pio_regs of niu_pio_regs.v
592wire [1:0] ldf_mask41; // From niu_pio_regs of niu_pio_regs.v
593wire [1:0] ldf_mask42; // From niu_pio_regs of niu_pio_regs.v
594wire [1:0] ldf_mask43; // From niu_pio_regs of niu_pio_regs.v
595wire [1:0] ldf_mask44; // From niu_pio_regs of niu_pio_regs.v
596wire [1:0] ldf_mask45; // From niu_pio_regs of niu_pio_regs.v
597wire [1:0] ldf_mask46; // From niu_pio_regs of niu_pio_regs.v
598wire [1:0] ldf_mask47; // From niu_pio_regs of niu_pio_regs.v
599wire [1:0] ldf_mask48; // From niu_pio_regs of niu_pio_regs.v
600wire [1:0] ldf_mask49; // From niu_pio_regs of niu_pio_regs.v
601wire [1:0] ldf_mask5; // From niu_pio_regs of niu_pio_regs.v
602wire [1:0] ldf_mask50; // From niu_pio_regs of niu_pio_regs.v
603wire [1:0] ldf_mask51; // From niu_pio_regs of niu_pio_regs.v
604wire [1:0] ldf_mask52; // From niu_pio_regs of niu_pio_regs.v
605wire [1:0] ldf_mask53; // From niu_pio_regs of niu_pio_regs.v
606wire [1:0] ldf_mask54; // From niu_pio_regs of niu_pio_regs.v
607wire [1:0] ldf_mask55; // From niu_pio_regs of niu_pio_regs.v
608wire [1:0] ldf_mask56; // From niu_pio_regs of niu_pio_regs.v
609wire [1:0] ldf_mask57; // From niu_pio_regs of niu_pio_regs.v
610wire [1:0] ldf_mask58; // From niu_pio_regs of niu_pio_regs.v
611wire [1:0] ldf_mask59; // From niu_pio_regs of niu_pio_regs.v
612wire [1:0] ldf_mask6; // From niu_pio_regs of niu_pio_regs.v
613wire [1:0] ldf_mask60; // From niu_pio_regs of niu_pio_regs.v
614wire [1:0] ldf_mask61; // From niu_pio_regs of niu_pio_regs.v
615wire [1:0] ldf_mask62; // From niu_pio_regs of niu_pio_regs.v
616wire [1:0] ldf_mask63; // From niu_pio_regs of niu_pio_regs.v
617wire [1:0] ldf_mask64; // From niu_pio_regs of niu_pio_regs.v
618wire [1:0] ldf_mask65; // From niu_pio_regs of niu_pio_regs.v
619wire [1:0] ldf_mask66; // From niu_pio_regs of niu_pio_regs.v
620wire [1:0] ldf_mask67; // From niu_pio_regs of niu_pio_regs.v
621wire [1:0] ldf_mask68; // From niu_pio_regs of niu_pio_regs.v
622wire [1:0] ldf_mask7; // From niu_pio_regs of niu_pio_regs.v
623wire [1:0] ldf_mask8; // From niu_pio_regs of niu_pio_regs.v
624wire [1:0] ldf_mask9; // From niu_pio_regs of niu_pio_regs.v
625wire ldgim_ack; // From niu_pio_regs of niu_pio_regs.v
626wire ldgim_err; // From niu_pio_regs of niu_pio_regs.v
627wire [63:0] ldgim_rdata; // From niu_pio_regs of niu_pio_regs.v
628wire [5:0] ldgn0; // From niu_pio_regs of niu_pio_regs.v
629wire [5:0] ldgn1; // From niu_pio_regs of niu_pio_regs.v
630wire [5:0] ldgn10; // From niu_pio_regs of niu_pio_regs.v
631wire [5:0] ldgn11; // From niu_pio_regs of niu_pio_regs.v
632wire [5:0] ldgn12; // From niu_pio_regs of niu_pio_regs.v
633wire [5:0] ldgn13; // From niu_pio_regs of niu_pio_regs.v
634wire [5:0] ldgn14; // From niu_pio_regs of niu_pio_regs.v
635wire [5:0] ldgn15; // From niu_pio_regs of niu_pio_regs.v
636wire [5:0] ldgn16; // From niu_pio_regs of niu_pio_regs.v
637wire [5:0] ldgn17; // From niu_pio_regs of niu_pio_regs.v
638wire [5:0] ldgn18; // From niu_pio_regs of niu_pio_regs.v
639wire [5:0] ldgn19; // From niu_pio_regs of niu_pio_regs.v
640wire [5:0] ldgn2; // From niu_pio_regs of niu_pio_regs.v
641wire [5:0] ldgn20; // From niu_pio_regs of niu_pio_regs.v
642wire [5:0] ldgn21; // From niu_pio_regs of niu_pio_regs.v
643wire [5:0] ldgn22; // From niu_pio_regs of niu_pio_regs.v
644wire [5:0] ldgn23; // From niu_pio_regs of niu_pio_regs.v
645wire [5:0] ldgn24; // From niu_pio_regs of niu_pio_regs.v
646wire [5:0] ldgn25; // From niu_pio_regs of niu_pio_regs.v
647wire [5:0] ldgn26; // From niu_pio_regs of niu_pio_regs.v
648wire [5:0] ldgn27; // From niu_pio_regs of niu_pio_regs.v
649wire [5:0] ldgn28; // From niu_pio_regs of niu_pio_regs.v
650wire [5:0] ldgn29; // From niu_pio_regs of niu_pio_regs.v
651wire [5:0] ldgn3; // From niu_pio_regs of niu_pio_regs.v
652wire [5:0] ldgn30; // From niu_pio_regs of niu_pio_regs.v
653wire [5:0] ldgn31; // From niu_pio_regs of niu_pio_regs.v
654wire [5:0] ldgn32; // From niu_pio_regs of niu_pio_regs.v
655wire [5:0] ldgn33; // From niu_pio_regs of niu_pio_regs.v
656wire [5:0] ldgn34; // From niu_pio_regs of niu_pio_regs.v
657wire [5:0] ldgn35; // From niu_pio_regs of niu_pio_regs.v
658wire [5:0] ldgn36; // From niu_pio_regs of niu_pio_regs.v
659wire [5:0] ldgn37; // From niu_pio_regs of niu_pio_regs.v
660wire [5:0] ldgn38; // From niu_pio_regs of niu_pio_regs.v
661wire [5:0] ldgn39; // From niu_pio_regs of niu_pio_regs.v
662wire [5:0] ldgn4; // From niu_pio_regs of niu_pio_regs.v
663wire [5:0] ldgn40; // From niu_pio_regs of niu_pio_regs.v
664wire [5:0] ldgn41; // From niu_pio_regs of niu_pio_regs.v
665wire [5:0] ldgn42; // From niu_pio_regs of niu_pio_regs.v
666wire [5:0] ldgn43; // From niu_pio_regs of niu_pio_regs.v
667wire [5:0] ldgn44; // From niu_pio_regs of niu_pio_regs.v
668wire [5:0] ldgn45; // From niu_pio_regs of niu_pio_regs.v
669wire [5:0] ldgn46; // From niu_pio_regs of niu_pio_regs.v
670wire [5:0] ldgn47; // From niu_pio_regs of niu_pio_regs.v
671wire [5:0] ldgn48; // From niu_pio_regs of niu_pio_regs.v
672wire [5:0] ldgn49; // From niu_pio_regs of niu_pio_regs.v
673wire [5:0] ldgn5; // From niu_pio_regs of niu_pio_regs.v
674wire [5:0] ldgn50; // From niu_pio_regs of niu_pio_regs.v
675wire [5:0] ldgn51; // From niu_pio_regs of niu_pio_regs.v
676wire [5:0] ldgn52; // From niu_pio_regs of niu_pio_regs.v
677wire [5:0] ldgn53; // From niu_pio_regs of niu_pio_regs.v
678wire [5:0] ldgn54; // From niu_pio_regs of niu_pio_regs.v
679wire [5:0] ldgn55; // From niu_pio_regs of niu_pio_regs.v
680wire [5:0] ldgn56; // From niu_pio_regs of niu_pio_regs.v
681wire [5:0] ldgn57; // From niu_pio_regs of niu_pio_regs.v
682wire [5:0] ldgn58; // From niu_pio_regs of niu_pio_regs.v
683wire [5:0] ldgn59; // From niu_pio_regs of niu_pio_regs.v
684wire [5:0] ldgn6; // From niu_pio_regs of niu_pio_regs.v
685wire [5:0] ldgn60; // From niu_pio_regs of niu_pio_regs.v
686wire [5:0] ldgn61; // From niu_pio_regs of niu_pio_regs.v
687wire [5:0] ldgn62; // From niu_pio_regs of niu_pio_regs.v
688wire [5:0] ldgn63; // From niu_pio_regs of niu_pio_regs.v
689wire [5:0] ldgn64; // From niu_pio_regs of niu_pio_regs.v
690wire [5:0] ldgn65; // From niu_pio_regs of niu_pio_regs.v
691wire [5:0] ldgn66; // From niu_pio_regs of niu_pio_regs.v
692wire [5:0] ldgn67; // From niu_pio_regs of niu_pio_regs.v
693wire [5:0] ldgn68; // From niu_pio_regs of niu_pio_regs.v
694wire [5:0] ldgn7; // From niu_pio_regs of niu_pio_regs.v
695wire [5:0] ldgn8; // From niu_pio_regs of niu_pio_regs.v
696wire [5:0] ldgn9; // From niu_pio_regs of niu_pio_regs.v
697wire ldsv_ack; // From niu_pio_regs of niu_pio_regs.v
698wire ldsv_err; // From niu_pio_regs of niu_pio_regs.v
699wire [63:0] ldsv_rdata; // From niu_pio_regs of niu_pio_regs.v
700wire [68:0] memship_group0; // From niu_pio_ic of niu_pio_ic.v
701wire [68:0] memship_group1; // From niu_pio_ic of niu_pio_ic.v
702wire [68:0] memship_group10; // From niu_pio_ic of niu_pio_ic.v
703wire [68:0] memship_group11; // From niu_pio_ic of niu_pio_ic.v
704wire [68:0] memship_group12; // From niu_pio_ic of niu_pio_ic.v
705wire [68:0] memship_group13; // From niu_pio_ic of niu_pio_ic.v
706wire [68:0] memship_group14; // From niu_pio_ic of niu_pio_ic.v
707wire [68:0] memship_group15; // From niu_pio_ic of niu_pio_ic.v
708wire [68:0] memship_group16; // From niu_pio_ic of niu_pio_ic.v
709wire [68:0] memship_group17; // From niu_pio_ic of niu_pio_ic.v
710wire [68:0] memship_group18; // From niu_pio_ic of niu_pio_ic.v
711wire [68:0] memship_group19; // From niu_pio_ic of niu_pio_ic.v
712wire [68:0] memship_group2; // From niu_pio_ic of niu_pio_ic.v
713wire [68:0] memship_group20; // From niu_pio_ic of niu_pio_ic.v
714wire [68:0] memship_group21; // From niu_pio_ic of niu_pio_ic.v
715wire [68:0] memship_group22; // From niu_pio_ic of niu_pio_ic.v
716wire [68:0] memship_group23; // From niu_pio_ic of niu_pio_ic.v
717wire [68:0] memship_group24; // From niu_pio_ic of niu_pio_ic.v
718wire [68:0] memship_group25; // From niu_pio_ic of niu_pio_ic.v
719wire [68:0] memship_group26; // From niu_pio_ic of niu_pio_ic.v
720wire [68:0] memship_group27; // From niu_pio_ic of niu_pio_ic.v
721wire [68:0] memship_group28; // From niu_pio_ic of niu_pio_ic.v
722wire [68:0] memship_group29; // From niu_pio_ic of niu_pio_ic.v
723wire [68:0] memship_group3; // From niu_pio_ic of niu_pio_ic.v
724wire [68:0] memship_group30; // From niu_pio_ic of niu_pio_ic.v
725wire [68:0] memship_group31; // From niu_pio_ic of niu_pio_ic.v
726wire [68:0] memship_group32; // From niu_pio_ic of niu_pio_ic.v
727wire [68:0] memship_group33; // From niu_pio_ic of niu_pio_ic.v
728wire [68:0] memship_group34; // From niu_pio_ic of niu_pio_ic.v
729wire [68:0] memship_group35; // From niu_pio_ic of niu_pio_ic.v
730wire [68:0] memship_group36; // From niu_pio_ic of niu_pio_ic.v
731wire [68:0] memship_group37; // From niu_pio_ic of niu_pio_ic.v
732wire [68:0] memship_group38; // From niu_pio_ic of niu_pio_ic.v
733wire [68:0] memship_group39; // From niu_pio_ic of niu_pio_ic.v
734wire [68:0] memship_group4; // From niu_pio_ic of niu_pio_ic.v
735wire [68:0] memship_group40; // From niu_pio_ic of niu_pio_ic.v
736wire [68:0] memship_group41; // From niu_pio_ic of niu_pio_ic.v
737wire [68:0] memship_group42; // From niu_pio_ic of niu_pio_ic.v
738wire [68:0] memship_group43; // From niu_pio_ic of niu_pio_ic.v
739wire [68:0] memship_group44; // From niu_pio_ic of niu_pio_ic.v
740wire [68:0] memship_group45; // From niu_pio_ic of niu_pio_ic.v
741wire [68:0] memship_group46; // From niu_pio_ic of niu_pio_ic.v
742wire [68:0] memship_group47; // From niu_pio_ic of niu_pio_ic.v
743wire [68:0] memship_group48; // From niu_pio_ic of niu_pio_ic.v
744wire [68:0] memship_group49; // From niu_pio_ic of niu_pio_ic.v
745wire [68:0] memship_group5; // From niu_pio_ic of niu_pio_ic.v
746wire [68:0] memship_group50; // From niu_pio_ic of niu_pio_ic.v
747wire [68:0] memship_group51; // From niu_pio_ic of niu_pio_ic.v
748wire [68:0] memship_group52; // From niu_pio_ic of niu_pio_ic.v
749wire [68:0] memship_group53; // From niu_pio_ic of niu_pio_ic.v
750wire [68:0] memship_group54; // From niu_pio_ic of niu_pio_ic.v
751wire [68:0] memship_group55; // From niu_pio_ic of niu_pio_ic.v
752wire [68:0] memship_group56; // From niu_pio_ic of niu_pio_ic.v
753wire [68:0] memship_group57; // From niu_pio_ic of niu_pio_ic.v
754wire [68:0] memship_group58; // From niu_pio_ic of niu_pio_ic.v
755wire [68:0] memship_group59; // From niu_pio_ic of niu_pio_ic.v
756wire [68:0] memship_group6; // From niu_pio_ic of niu_pio_ic.v
757wire [68:0] memship_group60; // From niu_pio_ic of niu_pio_ic.v
758wire [68:0] memship_group61; // From niu_pio_ic of niu_pio_ic.v
759wire [68:0] memship_group62; // From niu_pio_ic of niu_pio_ic.v
760wire [68:0] memship_group63; // From niu_pio_ic of niu_pio_ic.v
761wire [68:0] memship_group7; // From niu_pio_ic of niu_pio_ic.v
762wire [68:0] memship_group8; // From niu_pio_ic of niu_pio_ic.v
763wire [68:0] memship_group9; // From niu_pio_ic of niu_pio_ic.v
764wire mpc; // From niu_pio_regs of niu_pio_regs.v
765wire [6:0] msi_data; // From niu_pio_regs of niu_pio_regs.v
766wire pio_sel_state; // From niu_pio_rw_sm of niu_pio_rw_sm.v
767wire rst_at; // From niu_pio_ic of niu_pio_ic.v
768wire slv_ack; // From niu_pio_regs of niu_pio_regs.v
769wire slv_err; // From niu_pio_regs of niu_pio_regs.v
770wire [63:0] slv_rdata; // From niu_pio_regs of niu_pio_regs.v
771wire [5:0] timer0; // From niu_pio_regs of niu_pio_regs.v
772wire [5:0] timer1; // From niu_pio_regs of niu_pio_regs.v
773wire [5:0] timer10; // From niu_pio_regs of niu_pio_regs.v
774wire [5:0] timer11; // From niu_pio_regs of niu_pio_regs.v
775wire [5:0] timer12; // From niu_pio_regs of niu_pio_regs.v
776wire [5:0] timer13; // From niu_pio_regs of niu_pio_regs.v
777wire [5:0] timer14; // From niu_pio_regs of niu_pio_regs.v
778wire [5:0] timer15; // From niu_pio_regs of niu_pio_regs.v
779wire [5:0] timer16; // From niu_pio_regs of niu_pio_regs.v
780wire [5:0] timer17; // From niu_pio_regs of niu_pio_regs.v
781wire [5:0] timer18; // From niu_pio_regs of niu_pio_regs.v
782wire [5:0] timer19; // From niu_pio_regs of niu_pio_regs.v
783wire [5:0] timer2; // From niu_pio_regs of niu_pio_regs.v
784wire [5:0] timer20; // From niu_pio_regs of niu_pio_regs.v
785wire [5:0] timer21; // From niu_pio_regs of niu_pio_regs.v
786wire [5:0] timer22; // From niu_pio_regs of niu_pio_regs.v
787wire [5:0] timer23; // From niu_pio_regs of niu_pio_regs.v
788wire [5:0] timer24; // From niu_pio_regs of niu_pio_regs.v
789wire [5:0] timer25; // From niu_pio_regs of niu_pio_regs.v
790wire [5:0] timer26; // From niu_pio_regs of niu_pio_regs.v
791wire [5:0] timer27; // From niu_pio_regs of niu_pio_regs.v
792wire [5:0] timer28; // From niu_pio_regs of niu_pio_regs.v
793wire [5:0] timer29; // From niu_pio_regs of niu_pio_regs.v
794wire [5:0] timer3; // From niu_pio_regs of niu_pio_regs.v
795wire [5:0] timer30; // From niu_pio_regs of niu_pio_regs.v
796wire [5:0] timer31; // From niu_pio_regs of niu_pio_regs.v
797wire [5:0] timer32; // From niu_pio_regs of niu_pio_regs.v
798wire [5:0] timer33; // From niu_pio_regs of niu_pio_regs.v
799wire [5:0] timer34; // From niu_pio_regs of niu_pio_regs.v
800wire [5:0] timer35; // From niu_pio_regs of niu_pio_regs.v
801wire [5:0] timer36; // From niu_pio_regs of niu_pio_regs.v
802wire [5:0] timer37; // From niu_pio_regs of niu_pio_regs.v
803wire [5:0] timer38; // From niu_pio_regs of niu_pio_regs.v
804wire [5:0] timer39; // From niu_pio_regs of niu_pio_regs.v
805wire [5:0] timer4; // From niu_pio_regs of niu_pio_regs.v
806wire [5:0] timer40; // From niu_pio_regs of niu_pio_regs.v
807wire [5:0] timer41; // From niu_pio_regs of niu_pio_regs.v
808wire [5:0] timer42; // From niu_pio_regs of niu_pio_regs.v
809wire [5:0] timer43; // From niu_pio_regs of niu_pio_regs.v
810wire [5:0] timer44; // From niu_pio_regs of niu_pio_regs.v
811wire [5:0] timer45; // From niu_pio_regs of niu_pio_regs.v
812wire [5:0] timer46; // From niu_pio_regs of niu_pio_regs.v
813wire [5:0] timer47; // From niu_pio_regs of niu_pio_regs.v
814wire [5:0] timer48; // From niu_pio_regs of niu_pio_regs.v
815wire [5:0] timer49; // From niu_pio_regs of niu_pio_regs.v
816wire [5:0] timer5; // From niu_pio_regs of niu_pio_regs.v
817wire [5:0] timer50; // From niu_pio_regs of niu_pio_regs.v
818wire [5:0] timer51; // From niu_pio_regs of niu_pio_regs.v
819wire [5:0] timer52; // From niu_pio_regs of niu_pio_regs.v
820wire [5:0] timer53; // From niu_pio_regs of niu_pio_regs.v
821wire [5:0] timer54; // From niu_pio_regs of niu_pio_regs.v
822wire [5:0] timer55; // From niu_pio_regs of niu_pio_regs.v
823wire [5:0] timer56; // From niu_pio_regs of niu_pio_regs.v
824wire [5:0] timer57; // From niu_pio_regs of niu_pio_regs.v
825wire [5:0] timer58; // From niu_pio_regs of niu_pio_regs.v
826wire [5:0] timer59; // From niu_pio_regs of niu_pio_regs.v
827wire [5:0] timer6; // From niu_pio_regs of niu_pio_regs.v
828wire [5:0] timer60; // From niu_pio_regs of niu_pio_regs.v
829wire [5:0] timer61; // From niu_pio_regs of niu_pio_regs.v
830wire [5:0] timer62; // From niu_pio_regs of niu_pio_regs.v
831wire [5:0] timer63; // From niu_pio_regs of niu_pio_regs.v
832wire [5:0] timer7; // From niu_pio_regs of niu_pio_regs.v
833wire [5:0] timer8; // From niu_pio_regs of niu_pio_regs.v
834wire [5:0] timer9; // From niu_pio_regs of niu_pio_regs.v
835wire [19:0] vdmc_addr; // From niu_pio_regs of niu_pio_regs.v
836wire vdmc_sel_ok; // From niu_pio_regs of niu_pio_regs.v
837wire [2:0] ig_state;
838
839wire [5:0] debug_select ;
840wire arb_dirtid_en ;
841wire arb_dirtid_clr;
842wire [5:0] arb_np_threshold;
843wire [5:0] arb_rd_threshold;
844wire [5:0] arb_rdstat;
845wire [5:0] arb_wrstat;
846
847wire [31:0] TrainingVector;
848
849// End of automatics
850
851`ifdef NEPTUNE // --------------------------------------------
852 wire NEPTUNE_signature = 1;
853 wire peu_pio_32b;
854 // prom
855 wire pio_prom_sel; // O
856 wire prom_pio_ack; // I
857 wire [63:0] prom_pio_rdata; // I
858 wire prom_pio_err; // I
859
860 // pim
861 wire pio_pim_sel; // O
862 wire pim_pio_ack; // I
863 wire [63:0] pim_pio_rdata; // I
864 wire pim_pio_err; // I
865 wire pim_pio_intr; // I
866
867`else // N2 mode ---------------------------------------------
868
869 wire NEPTUNE_signature = 0;
870 wire peu_pio_32b = 0;
871 // prom
872 wire pio_prom_sel; // O
873 wire prom_pio_ack = 0; // I
874 wire [63:0] prom_pio_rdata = 0; // I
875 wire prom_pio_err = 0; // I
876
877 // prom
878 wire pio_pim_sel; // O
879 wire pim_pio_ack = 0; // I
880 wire [63:0] pim_pio_rdata = 0; // I
881 wire pim_pio_err = 0; // I
882// wire pim_pio_intr = 0; // I
883
884`endif // ifdef NEPTUNE
885
886/* --------------------- common rtl -------------------------- */
887 wire niu_reset = ~niu_reset_l;
888 wire [10:0] sys_err_mask ;
889
890df1 # (1) reset_df1 (.clk(niu_clk),.d(niu_reset), .q(reset));
891
892// register inputs from ucb/pci
893// ---------------------------------
894
895df1 # (1) pio_32b_df1 (.clk(niu_clk),.d(peu_pio_32b), .q(pio_32b));
896df1 # (1) ucb_rd_req_df1 (.clk(niu_clk),.d(rd_req_vld), .q(ucb_rd_req));
897df1 # (27) ucb_addr_df1 (.clk(niu_clk),.d(addr_in[`PIO_ADDR_R]),.q(ucb_addr[`PIO_ADDR_R]));
898df1 # (6) ucb_thr_id_df1 (.clk(niu_clk),.d(thr_id_in[5:0]), .q(ucb_thr_id[5:0]));
899df1 # (2) ucb_buf_id_df1 (.clk(niu_clk),.d(buf_id_in[1:0]), .q(ucb_buf_id[1:0]));
900df1 # (1) ucb_rack_busy_df1(.clk(niu_clk),.d(rack_busy), .q(ucb_rack_busy));
901df1 # (1) ucb_wr_req_df1 (.clk(niu_clk),.d(wr_req_vld), .q(ucb_wr_req));
902df1 # (64) ucb_wdata_df1 (.clk(niu_clk),.d(data_in[63:0]), .q(ucb_wdata[63:0]));
903df1 # (1) ibusy_df1 (.clk(niu_clk),.d(int_busy), .q(ibusy));
904// register outputs to ucb/pci
905assign ucb_rack = ucb_ack | ucb_nack;
906df1 # (1) req_accepted_df1(.clk(niu_clk), .d(accepted), .q(req_accepted));
907dffr # (1) rd_ack_vld_dffr (.clk(niu_clk),.reset(reset), .d(ucb_ack), .q(rd_ack_vld));
908dffr # (1) rd_nack_vld_dffr(.clk(niu_clk),.reset(reset), .d(ucb_nack), .q(rd_nack_vld));
909`ifdef NEPTUNE
910dffre # (64) data_out_dffre (.clk(niu_clk),.reset(reset),.en(pio_ack |(ucb_ack & insert_db)),.d(pio_rdata), .q(data_out[63:0]));
911`else
912dffre # (64) data_out_dffre (.clk(niu_clk),.reset(reset),.en(pio_ack),.d(pio_rdata), .q(data_out[63:0]));
913`endif
914dffre # (6) thr_id_out_dffre(.clk(niu_clk),.reset(reset),.en(ucb_rack),.d(thr_id[5:0]),.q(thr_id_out[5:0]));
915dffre # (2) buf_id_out_dffre(.clk(niu_clk),.reset(reset),.en(ucb_rack),.d(buf_id[1:0]),.q(buf_id_out[1:0]));
916df1 # (1) int_vld_df1 (.clk(niu_clk),.d(intr_valid), .q(int_vld));
917df1 # (7) dev_id_df1 (.clk(niu_clk),.d(msi_data), .q(dev_id));
918
919// Registering Meta Arb Signals
920dffr # (1) arb_dirtid_en_dffr (.clk(niu_clk),.reset(reset),.d(arb_dirtid_en),.q(pio_arb_dirtid_enable));
921dffr # (1) arb_dirtid_clr_dffr (.clk(niu_clk),.reset(reset),.d(arb_dirtid_clr),.q(pio_arb_dirtid_clr));
922dffr # (6) arb_dirtid_np_dffr (.clk(niu_clk),.reset(reset),.d(arb_np_threshold[5:0]),.q(pio_arb_np_threshold[5:0]));
923dffr # (6) arb_dirtid_rd_dffr (.clk(niu_clk),.reset(reset),.d(arb_rd_threshold[5:0]),.q(pio_arb_rd_threshold[5:0]));
924df1 # (6) arb_dtid_rdstat_df1 (.clk(niu_clk),.d(arb_pio_dirtid_rdstatus[5:0]),.q(arb_rdstat[5:0]));
925df1 # (6) arb_dtid_npwrstat_df1 (.clk(niu_clk),.d(arb_pio_dirtid_npwstatus[5:0]),.q(arb_wrstat[5:0]));
926// --------------------------------------------------------------------------------------------
927 reg [31:0] pio_arb_ctrl ;
928 reg [31:0] pio_arb_debug_vector ;
929
930 wire [31:0] arb_ctrl ;
931 wire [31:0] arb_debug_vector ;
932
933 always@(posedge niu_clk)
934 begin
935 pio_arb_ctrl[31:0] <= arb_ctrl[31:0];
936 pio_arb_debug_vector[31:0] <= arb_debug_vector[31:0];
937 end
938// --------------------------------------------------------------------------------------------
939 wire pio_peu_32b_int ;
940 wire intr_invalid ;
941
942`ifdef NEPTUNE
943
944 reg pio_peu_32b ;
945 reg int_invld ;
946 reg [15:0] pio_gpio_data_out ;
947 reg [15:0] pio_gpio_en_out ;
948 reg [15:0] gpio_din ;
949
950 wire [15:0] gpio_dout ;
951 wire [15:0] gpio_en ;
952
953 always@(posedge niu_clk)
954 begin
955 pio_peu_32b <= pio_peu_32b_int ;
956 int_invld <= intr_invalid ;
957 pio_gpio_data_out[15:0] <= gpio_dout[15:0] ;
958 pio_gpio_en_out[15:0] <= gpio_en[15:0] ;
959 gpio_din[15:0] <= gpio_pio_data_in[15:0] ;
960 end
961
962`endif
963
964// signals to smx Interface
965// ------------------------
966
967`ifdef NEPTUNE
968 wire smx_pio_intr = 0 ; // I
969 wire [31:0] smx_pio_status = 32'b0 ; // I
970
971 reg pim_intr ;
972
973 always@(posedge niu_clk)
974 begin
975 pim_intr <= pim_pio_intr ;
976 end
977
978`else
979
980 wire [15:0] gpio_pio_data_in = 16'b0 ;
981 wire mac_pio_intr2 = 1'b0 ;
982 wire mac_pio_intr3 = 1'b0 ;
983
984 reg [31:0] pio_smx_cfg_data ;
985 reg pio_smx_clear_intr ;
986 reg [31:0] pio_smx_ctrl ;
987 reg [31:0] pio_smx_debug_vector ;
988 reg [31:0] smx_status ;
989 reg smx_intr ;
990
991 wire [31:0] smx_config_data ;
992 wire clear_intr4smx ;
993 wire [31:0] smx_ctrl ;
994 wire [31:0] smx_debug_vector ;
995
996 always@(posedge niu_clk)
997 begin
998 pio_smx_cfg_data[31:0] <= smx_config_data[31:0];
999 pio_smx_clear_intr <= clear_intr4smx ;
1000 pio_smx_ctrl[31:0] <= smx_ctrl[31:0] ;
1001 pio_smx_debug_vector[31:0] <= smx_debug_vector[31:0] ;
1002 smx_status[31:0] <= smx_pio_status[31:0] ;
1003 smx_intr <= smx_pio_intr ;
1004 end
1005`endif
1006
1007// write to fifo
1008niu_pio_accepted_sm niu_pio_accepted_sm
1009(/*AUTOINST*/
1010 // Outputs
1011 .accepted (accepted),
1012 .accepted_state (accepted_state[1:0]),
1013 // Inputs
1014 .clk (niu_clk),
1015 .reset (reset),
1016 .full (full),
1017 .ucb_rd_req (ucb_rd_req),
1018 .ucb_wr_req (ucb_wr_req));
1019
1020df1 # (1) fifo_wr_en_df1(.d(accepted), .clk(niu_clk), .q(fifo_wr_en));
1021
1022 assign fifo_din[`PIO_ADDR_R] = ucb_addr[`PIO_ADDR_R]; // 27b
1023 assign fifo_din[90:27] = ucb_wdata[63:0]; // 64b
1024 assign fifo_din[92:91] = ucb_buf_id[1:0]; // 2b
1025 assign fifo_din[98:93] = ucb_thr_id[5:0]; // 6b
1026 assign fifo_din[99] = ucb_rd_req; // 1b
1027 assign fifo_din[100] = pio_32b; // 1b
1028 //101b -> 100:0
1029// ------------ start fifo instantiation --------------
1030niu_pio_fifo16d niu_pio_fifo16d(
1031.clk(niu_clk),
1032.reset(reset),
1033.rd(fifo_rd_en),
1034.wr(fifo_wr_en),
1035.din(fifo_din[`PIO_FIFO_W_R]),
1036.dout(fifo_dout[`PIO_FIFO_W_R]),
1037.pio_peu_afull(pio_peu_afull),
1038.full(full),
1039.empty(empty),
1040.rd_ptr(rd_ptr[4:0]),
1041.wr_ptr(wr_ptr[4:0])
1042);
1043
1044// ------------ end of fifo instantiation --------------
1045
1046// output of fifo
1047dffre #(101) dffre(.d(fifo_dout[`PIO_FIFO_W_R]),
1048 .reset(reset),
1049 .en(fifo_rd_en),
1050 .clk(niu_clk),
1051 .q(fifo_dout_reg[`PIO_FIFO_W_R]));
1052
1053 assign addr = fifo_dout_reg[`PIO_ADDR_R];
1054 assign wdata = fifo_dout_reg[90:27];
1055 assign buf_id = fifo_dout_reg[92:91];
1056 assign thr_id = fifo_dout_reg[98:93];
1057 assign rd = fifo_dout_reg[99];
1058 assign mode32b= fifo_dout_reg[100];
1059
1060 wire [26:0] addr_2 ;
1061 wire vdmc_sel ;
1062
1063 wire pio_virt_sel_ok ;
1064 wire fflp_virt_sel_ok ;
1065 wire dma_virt_sel_ok ;
1066 wire [26:0] virt_addr ;
1067
1068 assign clients_addr[19:0] = vdmc_sel ? vdmc_addr[19:0] : addr_2[19:0];
1069 assign vdmc_sel = (dma_virt_sel_ok & vdmc_sel_ok) ? 1'b1 : 1'b0;
1070
1071 df1 # (20) pio_clients_addr_df1 (.clk(niu_clk),.d(clients_addr[19:0]), .q(pio_clients_addr[19:0]));
1072 df1 # (64) pio_clients_wdata_df1 (.clk(niu_clk),.d(wdata[63:0]),.q(pio_clients_wdata[63:0]));
1073 df1 # (2) pio_clients_buf_id_df1 (.clk(niu_clk),.d(buf_id[1:0]),.q(pio_clients_buf_id[1:0]));
1074// df1 # (2) pio_clients_thr_id_df1 (.clk(niu_clk),.d(thr_id[1:0]),.q(pio_clients_thr_id[1:0]));
1075 df1 # (1) pio_clients_rd_df1 (.clk(niu_clk),.d(rd), .q(pio_clients_rd));
1076 df1 # (1) pio_clients_32b_df1 (.clk(niu_clk),.d(mode32b), .q(pio_clients_32b));
1077
1078// ------------ Logic for 32b PIO Access ----------------------
1079 reg pio_32b_rd ;
1080 reg pio_32b_wr ;
1081
1082 always@(posedge niu_clk)
1083 begin
1084 if (pio_clients_32b)
1085 begin
1086 if (pio_clients_addr[2:0] == 3'b100)
1087 if (pio_clients_rd)
1088 begin
1089 pio_32b_rd <= 1'b1 ;
1090 pio_32b_wr <= 1'b0 ;
1091 end
1092 else
1093 begin
1094 pio_32b_rd <= 1'b0 ;
1095 pio_32b_wr <= 1'b1 ;
1096 end
1097 else
1098 begin
1099 pio_32b_rd <= 1'b0 ;
1100 pio_32b_wr <= 1'b0 ;
1101 end
1102 end
1103 else
1104 begin
1105 pio_32b_rd <= 1'b0 ;
1106 pio_32b_wr <= 1'b0 ;
1107 end
1108 end
1109// --------------------------------------------------------------
1110
1111// ------------ start rw_sm instantiation --------------
1112// fifo read write state machine
1113niu_pio_rw_sm niu_pio_rw_sm
1114(/*AUTOINST*/
1115 // Outputs
1116 .ucb_ack (ucb_ack),
1117 .ucb_nack (ucb_nack),
1118 .fifo_rd_en (fifo_rd_en),
1119 .pio_sel_state (pio_sel_state),
1120 .pio_rw_state (pio_rw_state[2:0]),
1121 .pio_peu_32b_int (pio_peu_32b_int),
1122`ifdef NEPTUNE
1123 .insert_db (insert_db),
1124`else
1125`endif
1126 // Inputs
1127 .clk (niu_clk),
1128 .reset (reset),
1129 .empty (empty),
1130 .pio_ack (pio_ack),
1131 .pio_err (pio_err),
1132 .rd (rd),
1133 .ack_TO_en (ack_TO_en),
1134 .ack_TO_value (ack_TO_value[9:0]),
1135 .sel1 (sel1),
1136 .ucb_rack_busy (ucb_rack_busy),
1137 .pio_clients_32b (pio_clients_32b));
1138// ------------ End of rw_sm instantiation ----------------------
1139
1140// address decoder and selection generation
1141// if (mpc == 1) only function 0 has write access.
1142// if (mpc == 0) all functions have write access.
1143
1144// ------------ Original Code (Two Functions) -------------------
1145// `ifdef NEPTUNE
1146// assign fc0 = (addr[25:24] == 2'b00);
1147// assign fc1 = (addr[25:24] != 2'b00) & (~mpc | (mpc & rd));
1148// `else
1149// assign fc0 = ~addr[24];
1150// assign fc1 = addr[24] & (~mpc | (mpc & rd));
1151// `endif
1152//
1153// assign fc = fc0 | fc1;
1154// ------------ End of Original Code (Two Functions) --------------
1155
1156 assign fc0 = (addr[26:24] == 3'b000);
1157 assign fc1 = (addr[26:24] == 3'b010) & (~mpc | (mpc & rd));
1158 assign fc2 = (addr[26:24] == 3'b100) & (~mpc | (mpc & rd));
1159 assign fc3 = (addr[26:24] == 3'b110) & (~mpc | (mpc & rd));
1160 assign fc = (fc0 | fc1 | fc2 | fc3 );
1161
1162 wire fc0_v ;
1163 wire fc1_v ;
1164 wire fc2_v ;
1165 wire fc3_v ;
1166
1167 assign fc0_v = (addr[26:24] == 3'b001 );
1168 assign fc1_v = (addr[26:24] == 3'b011);
1169 assign fc2_v = (addr[26:24] == 3'b101);
1170 assign fc3_v = (addr[26:24] == 3'b111);
1171
1172// -----------------------------------------------------------------
1173
1174always @ (/*AUTOSENSE*/addr or fc)
1175 begin
1176 slv_sel = 0;
1177 fzc_slv_sel = 0;
1178 fzc_mac_sel = 0;
1179 fzc_ipp_sel = 0;
1180 fflp_sel = 0;
1181 fzc_fflp_sel = 0;
1182// vdmc_sel = 0;
1183 zcp_sel = 0;
1184 fzc_zcp_sel = 0;
1185 dmc_sel = 0;
1186 fzc_dmc_sel = 0;
1187 txc_sel = 0;
1188 fzc_txc_sel = 0;
1189 ldsv_sel = 0;
1190// ldgim_sel = 0;
1191 imask0_sel = 0;
1192 imask1_sel = 0;
1193 fzc_prom_sel = 0;
1194 fzc_pim_sel = 0;
1195 casex({addr[23:20],addr[19]}) // block number
1196 5'b0000_0: slv_sel = 1; // 0
1197 5'b0011_0: fflp_sel = 1; // 3
1198// 5'b0100_0: vdmc_sel = vdmc_sel_ok; // 4 // vdmc_sel_ok decodes addr[15:9] plus enable bit (binding bit).
1199// // vdmc_sel_ok decodes addr[26:25],addr[14],addr[12:10]
1200 5'b0101_0: zcp_sel = 1; // 5
1201 5'b0110_0: dmc_sel = 1; // 6
1202 5'b0111_0: txc_sel = 1; // 7
1203 5'b1000_0: ldsv_sel = 1; // 8
1204// 5'b1001_0: ldgim_sel = 1; // 9
1205 5'b1010_0: imask0_sel = 1; // A
1206 5'b1011_0: imask1_sel = 1; // B
1207 // fzc
1208 5'b0000_1: fzc_slv_sel = fc;// 0
1209 5'b0001_1: fzc_mac_sel = fc;// 1
1210 5'b0010_1: fzc_ipp_sel = fc;// 2
1211 5'b0011_1: fzc_fflp_sel = fc;// 3
1212 5'b0101_1: fzc_zcp_sel = fc;// 5
1213 5'b0110_1: fzc_dmc_sel = fc;// 6
1214 5'b0111_1: fzc_txc_sel = fc;// 7
1215 5'b1100_1: fzc_prom_sel = fc;// C
1216 5'b1101_1: fzc_pim_sel = fc;// C
1217 endcase
1218 end // always @ (...
1219
1220 assign addr_2[26:0] = (pio_virt_sel_ok || fflp_virt_sel_ok) ? virt_addr[26:0] : addr[26:0];
1221
1222// total 12 sets of pio acks.
1223df1 # (1) slv_sel_reg_df1 (.clk(niu_clk),
1224 .d((slv_sel & !dma_virt_sel_ok & !fflp_virt_sel_ok & !pio_virt_sel_ok ) & pio_sel_state),
1225 .q(slv_sel_reg));
1226df1 # (1) fzc_slv_sel_reg_df1(.clk(niu_clk),.d(fzc_slv_sel & pio_sel_state),.q(fzc_slv_sel_reg));
1227df1 # (1) pio_mac_sel_df1 (.clk(niu_clk),.d(fzc_mac_sel & pio_sel_state),.q(pio_mac_sel));
1228df1 # (1) pio_ipp_sel_df1 (.clk(niu_clk),.d(fzc_ipp_sel & pio_sel_state),.q(pio_ipp_sel));
1229df1 # (1) pio_fflp_sel_df1 (.clk(niu_clk),.d((fzc_fflp_sel|fflp_sel|fflp_virt_sel_ok) & pio_sel_state),.q(pio_fflp_sel));
1230df1 # (1) pio_zcp_sel_df1 (.clk(niu_clk),.d((fzc_zcp_sel |zcp_sel) & pio_sel_state),.q(pio_zcp_sel));
1231df1 # (1) pio_txc_sel_df1 (.clk(niu_clk),.d((fzc_txc_sel |txc_sel) & pio_sel_state),.q(pio_txc_sel));
1232df1 # (1) ldsv_sel_reg_df1 (.clk(niu_clk),.d((ldsv_sel |pio_virt_sel_ok) & pio_sel_state),.q(ldsv_sel_reg));
1233df1 # (1) ldgin_sel_reg_df1 (.clk(niu_clk),.d(ldsv_sel & pio_sel_state),.q(ldgim_sel_reg));
1234df1 # (1) imask0_sel_reg_df1 (.clk(niu_clk),.d(imask0_sel & pio_sel_state),.q(imask0_sel_reg));
1235df1 # (1) imask1_sel_reg_df1 (.clk(niu_clk),.d(imask1_sel & pio_sel_state),.q(imask1_sel_reg));
1236df1 # (1) pio_dmc_sel_df1 (.clk(niu_clk),.d((fzc_dmc_sel |( dmc_sel & !pio_virt_sel_ok )| vdmc_sel) & pio_sel_state),.q(pio_dmc_sel));
1237// df1 # (1) pio_dmc_sel_df1 (.clk(niu_clk),.d((fzc_dmc_sel |dmc_sel | vdmc_sel) & pio_sel_state),.q(pio_dmc_sel));
1238`ifdef NEPTUNE
1239df1 # (1) pio_prom_sel_reg_df1 (.clk(niu_clk),.d((fzc_prom_sel) & pio_sel_state),.q(pio_prom_sel));
1240df1 # (1) pio_pim_sel_reg_df1 (.clk(niu_clk),.d((fzc_pim_sel) & pio_sel_state),.q(pio_pim_sel));
1241`else
1242 assign pio_prom_sel = ((fzc_pim_sel) & pio_sel_state);
1243 assign pio_pim_sel = ((fzc_pim_sel) & pio_sel_state);
1244`endif
1245
1246 // 16 clients
1247 assign sel1 = (slv_sel & !dma_virt_sel_ok & !fflp_virt_sel_ok & !pio_virt_sel_ok ) |
1248 fzc_slv_sel |
1249 fzc_mac_sel |
1250 fzc_ipp_sel |
1251 fflp_sel |
1252 fzc_fflp_sel |
1253 zcp_sel |
1254 fzc_zcp_sel |
1255 ( dmc_sel &!pio_virt_sel_ok ) |
1256 vdmc_sel |
1257 fzc_dmc_sel |
1258 txc_sel |
1259 fzc_txc_sel |
1260 ldsv_sel |
1261 imask0_sel |
1262 imask1_sel |
1263 fzc_pim_sel |
1264 fzc_prom_sel |
1265 fflp_virt_sel_ok |
1266 pio_virt_sel_ok ;
1267
1268always @ (/*AUTOSENSE*/dmc_pio_ack_reg or dmc_pio_err_reg
1269 or dmc_pio_rdata_reg or fflp_pio_ack_reg or fflp_pio_err_reg
1270 or fflp_pio_rdata_reg or fzc_slv_ack or fzc_slv_err
1271 or fzc_slv_rdata or fzc_slv_sel or imask0_ack or imask0_err
1272 or imask0_rdata or imask0_sel_reg or imask1_ack
1273 or imask1_err or imask1_rdata or imask1_sel_reg
1274 or ipp_pio_ack_reg or ipp_pio_err_reg or ipp_pio_rdata_reg
1275 or ldgim_ack or ldgim_err or ldgim_rdata
1276 or ldsv_ack or ldsv_err or ldsv_rdata or ldsv_sel_reg
1277 or mac_pio_ack_reg or mac_pio_err_reg or mac_pio_rdata_reg
1278 or pio_dmc_sel or pio_fflp_sel or pio_ipp_sel or pio_mac_sel
1279 or pio_prom_sel or pio_pim_sel or pio_txc_sel or pio_zcp_sel
1280 or prom_pio_ack_reg or prom_pio_err_reg
1281 or prom_pio_rdata_reg or slv_ack or slv_err or slv_rdata
1282 or slv_sel_reg or txc_pio_ack_reg or txc_pio_err_reg
1283 or txc_pio_rdata_reg or zcp_pio_ack_reg or zcp_pio_err_reg
1284 or zcp_pio_rdata_reg or intr_reg_sel
1285 or pim_pio_err_reg or pim_pio_ack_reg or pim_pio_rdata_reg
1286 or pio_32b_rd)
1287begin
1288 pio_ack = 1'b0;
1289 pio_rdata = 64'hdead_beef_dead_beef;
1290 pio_err = 1'b0;
1291
1292 case ({pio_prom_sel,imask1_sel_reg,imask0_sel_reg,pio_pim_sel,ldsv_sel_reg,pio_txc_sel,pio_dmc_sel,pio_zcp_sel,pio_fflp_sel,pio_ipp_sel,pio_mac_sel,fzc_slv_sel,slv_sel_reg})
1293 13'b0_0000_0000_0001:begin
1294 pio_ack = slv_ack; // already registered in decoder logic.
1295`ifdef NEPTUNE
1296 pio_err = 1'b0; // already registered in decoder logic.
1297`else
1298 pio_err = slv_err; // already registered in decoder logic.
1299`endif
1300 if(pio_32b_rd)
1301 pio_rdata = ({32'b0,slv_rdata[63:32]}); // already registered in decoder logic.
1302 else
1303 pio_rdata = slv_rdata; // already registered in decoder logic.
1304 end
1305 13'b0_0000_0000_0010:begin
1306 pio_ack = fzc_slv_ack; // already registered in decoder logic.
1307`ifdef NEPTUNE
1308 pio_err = 1'b0; // already registered in decoder logic.
1309`else
1310 pio_err = fzc_slv_err; // already registered in decoder logic.
1311`endif
1312 if(pio_32b_rd)
1313 pio_rdata = ({32'b0,fzc_slv_rdata[63:32]}); // already registered in decoder logic.
1314 else
1315 pio_rdata = fzc_slv_rdata; // already registered in decoder logic.
1316 end
1317 13'b0_0000_0000_0100:begin
1318 pio_ack = mac_pio_ack_reg;
1319 pio_rdata = mac_pio_rdata_reg;
1320`ifdef NEPTUNE
1321 pio_err = 1'b0; // already registered in decoder logic.
1322`else
1323 pio_err = mac_pio_err_reg;
1324`endif
1325 end
1326 13'b0_0000_0000_1000:begin
1327 pio_ack = ipp_pio_ack_reg;
1328 pio_rdata = ipp_pio_rdata_reg;
1329`ifdef NEPTUNE
1330 pio_err = 1'b0; // already registered in decoder logic.
1331`else
1332 pio_err = ipp_pio_err_reg;
1333`endif
1334 end
1335 13'b0_0000_0001_0000:begin
1336 pio_ack = fflp_pio_ack_reg;
1337 pio_rdata = fflp_pio_rdata_reg;
1338`ifdef NEPTUNE
1339 pio_err = 1'b0; // already registered in decoder logic.
1340`else
1341 pio_err = fflp_pio_err_reg;
1342`endif
1343 end
1344 13'b0_0000_0010_0000:begin
1345 pio_ack = zcp_pio_ack_reg;
1346 pio_rdata = zcp_pio_rdata_reg;
1347`ifdef NEPTUNE
1348 pio_err = 1'b0; // already registered in decoder logic.
1349`else
1350 pio_err = zcp_pio_err_reg;
1351`endif
1352 end
1353 13'b0_0000_0100_0000:begin
1354 pio_ack = dmc_pio_ack_reg;
1355 pio_rdata = dmc_pio_rdata_reg;
1356`ifdef NEPTUNE
1357 pio_err = 1'b0; // already registered in decoder logic.
1358`else
1359 pio_err = dmc_pio_err_reg;
1360`endif
1361 end
1362 13'b0_0000_1000_0000:begin
1363 pio_ack = txc_pio_ack_reg;
1364 pio_rdata = txc_pio_rdata_reg;
1365`ifdef NEPTUNE
1366 pio_err = 1'b0; // already registered in decoder logic.
1367`else
1368 pio_err = txc_pio_err_reg;
1369`endif
1370 end
1371 13'b0_0001_0000_0000:
1372 begin
1373 if (!intr_reg_sel)
1374 begin
1375 pio_ack = ldsv_ack; // already registered in decoder logic.
1376`ifdef NEPTUNE
1377 pio_err = 1'b0; // already registered in decoder logic.
1378`else
1379 pio_err = ldsv_err; // already registered in decoder logic.
1380`endif
1381 if(pio_32b_rd)
1382 pio_rdata = ({32'b0,ldsv_rdata[63:32]}); // already registered in decoder logic.
1383 else
1384 pio_rdata = ldsv_rdata; // already registered in decoder logic.
1385 end
1386 else
1387 begin
1388 pio_ack = ldgim_ack; // already registered in decoder logic.
1389`ifdef NEPTUNE
1390 pio_err = 1'b0; // already registered in decoder logic.
1391`else
1392 pio_err = ldgim_err; // already registered in decoder logic.
1393`endif
1394 if(pio_32b_rd)
1395 pio_rdata = ({32'b0,ldgim_rdata[63:32]}); // already registered in decoder logic.
1396 else
1397 pio_rdata = ldgim_rdata; // already registered in decoder logic.
1398 end
1399 end
1400 13'b0_0010_0000_0000:
1401 begin
1402 pio_ack = pim_pio_ack_reg;
1403 pio_rdata = pim_pio_rdata_reg;
1404`ifdef NEPTUNE
1405 pio_err = 1'b0; // already registered in decoder logic.
1406`else
1407 pio_err = pim_pio_err_reg;
1408`endif
1409 end
1410 13'b0_0100_0000_0000:begin
1411 pio_ack = imask0_ack; // already registered in decoder logic.
1412`ifdef NEPTUNE
1413 pio_err = 1'b0; // already registered in decoder logic.
1414`else
1415 pio_err = imask0_err; // already registered in decoder logic.
1416`endif
1417 if(pio_32b_rd)
1418 pio_rdata = ({32'b0,imask0_rdata[63:32]});// already registered in decoder logic.
1419 else
1420 pio_rdata = imask0_rdata; // already registered in decoder logic.
1421 end
1422 13'b0_1000_0000_0000:begin
1423 pio_ack = imask1_ack; // already registered in decoder logic.
1424`ifdef NEPTUNE
1425 pio_err = 1'b0; // already registered in decoder logic.
1426`else
1427 pio_err = imask1_err; // already registered in decoder logic.
1428`endif
1429 if(pio_32b_rd)
1430 pio_rdata = ({32'b0,imask1_rdata[63:32]});// already registered in decoder logic.
1431 else
1432 pio_rdata = imask1_rdata; // already registered in decoder logic.
1433 end
1434 13'b1_0000_0000_0000:begin
1435 pio_ack = prom_pio_ack_reg;
1436`ifdef NEPTUNE
1437 pio_err = 1'b0; // already registered in decoder logic.
1438`else
1439 pio_err = prom_pio_err_reg;
1440`endif
1441 pio_rdata = prom_pio_rdata_reg;
1442 end
1443 default: begin
1444 pio_ack = 1'b0;
1445 pio_rdata = 64'hdead_beef_dead_beef;
1446`ifdef NEPTUNE
1447 pio_err = 1'b0; // already registered in decoder logic.
1448`else
1449 pio_err = 1'b0;
1450`endif
1451 end
1452 endcase
1453end // always @ (...
1454
1455// register external clients input signals
1456
1457df1 # (1) mac_pio_ack_reg_df1 (.d(mac_pio_ack), .clk(niu_clk),.q(mac_pio_ack_reg));
1458dffre # (64) mac_pio_rdata_reg_dffre (.d(mac_pio_rdata), .reset(reset),.en(mac_pio_ack), .clk(niu_clk),.q(mac_pio_rdata_reg));
1459
1460df1 # (1) ipp_pio_ack_reg_df1 (.d(ipp_pio_ack), .clk(niu_clk),.q(ipp_pio_ack_reg));
1461dffre # (64) ipp_pio_rdata_reg_dffre (.d(ipp_pio_rdata), .reset(reset),.en(ipp_pio_ack), .clk(niu_clk),.q(ipp_pio_rdata_reg));
1462
1463df1 # (1) fflp_pio_ack_reg_df1 (.d(fflp_pio_ack), .clk(niu_clk),.q(fflp_pio_ack_reg));
1464dffre # (64) fflp_pio_rdata_reg_dffre(.d(fflp_pio_rdata),.reset(reset),.en(fflp_pio_ack),.clk(niu_clk),.q(fflp_pio_rdata_reg));
1465
1466df1 # (1) zcp_pio_ack_reg_df1 (.d(zcp_pio_ack), .clk(niu_clk),.q(zcp_pio_ack_reg));
1467dffre # (64) zcp_pio_rdata_reg_dffre (.d(zcp_pio_rdata), .reset(reset),.en(zcp_pio_ack), .clk(niu_clk),.q(zcp_pio_rdata_reg));
1468
1469df1 # (1) dmc_pio_ack_reg_df1 (.d(dmc_pio_ack), .clk(niu_clk),.q(dmc_pio_ack_reg));
1470dffre # (64) dmc_pio_rdata_reg_dffre (.d(dmc_pio_rdata), .reset(reset),.en(dmc_pio_ack), .clk(niu_clk),.q(dmc_pio_rdata_reg));
1471
1472df1 # (1) txc_pio_ack_reg_df1 (.d(txc_pio_ack), .clk(niu_clk),.q(txc_pio_ack_reg));
1473dffre # (64) txc_pio_rdata_reg_dffre (.d(txc_pio_rdata), .reset(reset),.en(txc_pio_ack), .clk(niu_clk),.q(txc_pio_rdata_reg));
1474
1475`ifdef NEPTUNE
1476
1477df1 # (1) prom_pio_ack_reg_df1 (.d(prom_pio_ack), .clk(niu_clk),.q(prom_pio_ack_reg));
1478dffre # (64) prom_pio_rdata_reg_dffre(.d(prom_pio_rdata),.reset(reset),.en(prom_pio_ack),.clk(niu_clk),.q(prom_pio_rdata_reg));
1479dffre # (1) prom_pio_err_reg_dffre (.d(prom_pio_err), .reset(reset),.en(prom_pio_ack),.clk(niu_clk),.q(prom_pio_err_reg));
1480
1481df1 # (1) pim_pio_ack_reg_df1 (.d(pim_pio_ack), .clk(niu_clk),.q(pim_pio_ack_reg));
1482dffre # (64) pim_pio_rdata_reg_dffre(.d(pim_pio_rdata),.reset(reset),.en(pim_pio_ack),.clk(niu_clk),.q(pim_pio_rdata_reg));
1483dffre # (1) pim_pio_err_reg_dffre (.d(pim_pio_err), .reset(reset),.en(pim_pio_ack),.clk(niu_clk),.q(pim_pio_err_reg));
1484
1485 assign mac_pio_err_reg = mac_pio_err ;
1486 assign ipp_pio_err_reg = ipp_pio_err ;
1487 assign fflp_pio_err_reg = fflp_pio_err ;
1488 assign zcp_pio_err_reg = zcp_pio_err ;
1489 assign dmc_pio_err_reg = dmc_pio_err ;
1490 assign txc_pio_err_reg = txc_pio_err ;
1491
1492`else
1493dffre # (1) mac_pio_err_reg_dffre (.d(mac_pio_err), .reset(reset),.en(mac_pio_ack), .clk(niu_clk),.q(mac_pio_err_reg));
1494dffre # (1) ipp_pio_err_reg_dffre (.d(ipp_pio_err), .reset(reset),.en(ipp_pio_ack), .clk(niu_clk),.q(ipp_pio_err_reg));
1495dffre # (1) fflp_pio_err_reg_dffre (.d(fflp_pio_err), .reset(reset),.en(fflp_pio_ack),.clk(niu_clk),.q(fflp_pio_err_reg));
1496dffre # (1) zcp_pio_err_reg_dffre (.d(zcp_pio_err), .reset(reset),.en(zcp_pio_ack), .clk(niu_clk),.q(zcp_pio_err_reg));
1497dffre # (1) dmc_pio_err_reg_dffre (.d(dmc_pio_err), .reset(reset),.en(dmc_pio_ack), .clk(niu_clk),.q(dmc_pio_err_reg));
1498dffre # (1) txc_pio_err_reg_dffre (.d(txc_pio_err), .reset(reset),.en(txc_pio_ack), .clk(niu_clk),.q(txc_pio_err_reg));
1499
1500 assign prom_pio_ack_reg = prom_pio_ack ;
1501 assign prom_pio_rdata_reg[63:0] = prom_pio_rdata[63:0] ;
1502 assign prom_pio_err_reg = prom_pio_err ;
1503
1504 assign pim_pio_ack_reg = pim_pio_ack ;
1505 assign pim_pio_rdata_reg[63:0] = pim_pio_rdata[63:0] ;
1506 assign pim_pio_err_reg = pim_pio_err ;
1507`endif
1508
1509// register client interrupts
1510// df1 # (64) dmc_intri_df1 (.d(dmc_pio_intri[63:0]),.clk(niu_clk),.q(ldfi[63:0]));
1511// df1 # (64) dmc_intrj_df1 (.d(dmc_pio_intrj[63:0]),.clk(niu_clk),.q(ldfj[63:0]));
1512
1513`ifdef NEPTUNE
1514wire [31:0] del_pio_clients_wdata ;
1515df1 # (32) del_pio_clients_wdata_df1 (.d(pio_clients_wdata[31:0]),.clk(niu_clk),.q(del_pio_clients_wdata[31:0]));
1516`else
1517`endif
1518
1519`ifdef NEPTUNE
1520
1521 df1 # (16) dmc_intri_df1_0_15 (.d(dmc_pio_intri[15:0]),.clk(niu_clk),.q(ldfj[15:0]));
1522 df1 # (16) dmc_intrj_df1_0_15 (.d(dmc_pio_intrj[15:0]),.clk(niu_clk),.q(ldfi[15:0]));
1523
1524 assign ldfi[31:16] = 16'b0 ;
1525 assign ldfj[31:16] = 16'b0 ;
1526
1527 df1 # (24) dmc_intri_df1_55_32 (.d(dmc_pio_intri[55:32]),.clk(niu_clk),.q(ldfj[55:32]));
1528 df1 # (24) dmc_intrj_df1_55_32 (.d(dmc_pio_intrj[55:32]),.clk(niu_clk),.q(ldfi[55:32]));
1529
1530 assign ldfi[62:56] = 7'b0 ;
1531 assign ldfj[63:56] = 8'b0 ;
1532
1533`else
1534 df1 # (16) dmc_intri_df1_0_15 (.d(dmc_pio_intri[15:0]),.clk(niu_clk),.q(ldfj[15:0]));
1535 df1 # (16) dmc_intrj_df1_0_15 (.d(dmc_pio_intrj[15:0]),.clk(niu_clk),.q(ldfi[15:0]));
1536
1537 assign ldfi[31:16] = 16'b0 ;
1538 assign ldfj[31:16] = 16'b0 ;
1539
1540 df1 # (16) dmc_intri_df1_47_32 (.d(dmc_pio_intri[47:32]),.clk(niu_clk),.q(ldfj[47:32]));
1541 df1 # (16) dmc_intrj_df1_47_32 (.d(dmc_pio_intrj[47:32]),.clk(niu_clk),.q(ldfi[47:32]));
1542
1543 assign ldfi[62:48] = 15'b0 ;
1544 assign ldfj[63:48] = 16'b0 ;
1545
1546`endif
1547
1548// mac
1549df1 # (1) mif_pio_intr_df1 (.d(mif_pio_intr), .clk(niu_clk),.q(ldfi[63]));
1550df1 # (1) mac_intr0_df1 (.d(mac_pio_intr0),.clk(niu_clk),.q(ldfi[64]));
1551df1 # (1) mac_intr1_df1 (.d(mac_pio_intr1), .clk(niu_clk),.q(ldfi[65]));
1552
1553`ifdef NEPTUNE
1554df1 # (1) mac_intr2_df1 (.d(mac_pio_intr2), .clk(niu_clk),.q(ldfi[66]));
1555df1 # (1) mac_intr3_df1 (.d(mac_pio_intr3), .clk(niu_clk),.q(ldfi[67]));
1556`else
1557 assign ldfi[66] = 1'b0 ;
1558 assign ldfi[67] = 1'b0 ;
1559`endif
1560
1561 assign ldfj[65] = 1'b0 ;
1562 assign ldfj[64] = 1'b0 ;
1563 assign ldfj[66] = 1'b0 ;
1564 assign ldfj[67] = 1'b0 ;
1565 assign ldfj[68] = 1'b0 ;
1566
1567// system error
1568df1 # (1) ipp_intr_df1 (.d(ipp_pio_intr), .clk(niu_clk),.q(ipp_intr));
1569df1 # (1) fflp_intr_df1 (.d(fflp_pio_intr), .clk(niu_clk),.q(fflp_intr));
1570df1 # (1) zcp_intr_df1 (.d(zcp_pio_intr), .clk(niu_clk),.q(zcp_intr));
1571df1 # (1) txc_intr_df1 (.d(txc_pio_intr), .clk(niu_clk),.q(txc_intr));
1572df1 # (1) mif_intr_df1 (.d(mif_pio_intr), .clk(niu_clk),.q(mif_intr));
1573df1 # (1) rdmc_intr_df1 (.d(rdmc_pio_port_int), .clk(niu_clk),.q(rdmc_intr));
1574
1575df1 # (1) meta_intr_df1 (.d(arb_pio_all_npwdirty), .clk(niu_clk),.q(meta_intr1));
1576df1 # (1) meta_intr_df2 (.d(arb_pio_all_rddirty), .clk(niu_clk),.q(meta_intr2));
1577
1578`ifdef NEPTUNE
1579 wire other_intr = ((ipp_intr & !sys_err_mask[2]) |
1580 (fflp_intr & !sys_err_mask[3]) |
1581 (zcp_intr & !sys_err_mask[4]) |
1582 (txc_intr & !sys_err_mask[7]) |
1583 (rdmc_intr & !sys_err_mask[6]) |
1584 (mif_intr & !sys_err_mask[1]) |
1585 (smx_meta_intr_hld | meta_intr1 & !sys_err_mask[9]) |
1586 (smx_meta_intr_hld | meta_intr2 & !sys_err_mask[10])|
1587 (pim_intr & !sys_err_mask[8]) );
1588`else
1589 wire other_intr = ((ipp_intr & !sys_err_mask[2]) |
1590 (fflp_intr & !sys_err_mask[3]) |
1591 (zcp_intr & !sys_err_mask[4]) |
1592 (txc_intr & !sys_err_mask[7]) |
1593 (rdmc_intr & !sys_err_mask[6]) |
1594 (mif_intr & !sys_err_mask[1]) |
1595 (smx_meta_intr_hld | meta_intr1 & !sys_err_mask[9]) |
1596 (smx_meta_intr_hld | meta_intr2 & !sys_err_mask[10])|
1597 (smx_meta_intr_hld | smx_intr & !sys_err_mask[0]) );
1598`endif
1599
1600df1 # (1) other_intr_df1 (.d(other_intr), .clk(niu_clk),.q(ldfi[68]));
1601
1602niu_pio_regs niu_pio_regs
1603(/*AUTOINST*/
1604 // Outputs
1605 .slv_ack (slv_ack),
1606 .slv_rdata (slv_rdata[63:0]),
1607 .slv_err (slv_err),
1608 .fzc_slv_ack (fzc_slv_ack),
1609 .fzc_slv_rdata (fzc_slv_rdata[63:0]),
1610 .fzc_slv_err (fzc_slv_err),
1611 .vdmc_addr (vdmc_addr[19:0]),
1612 .vdmc_sel_ok (vdmc_sel_ok),
1613 .ldsv_ack (ldsv_ack),
1614 .ldsv_rdata (ldsv_rdata[63:0]),
1615 .ldsv_err (ldsv_err),
1616 .ldgim_ack (ldgim_ack),
1617 .ldgim_rdata (ldgim_rdata[63:0]),
1618 .ldgim_err (ldgim_err),
1619 .intr_reg_sel (intr_reg_sel),
1620 .imask0_ack (imask0_ack),
1621 .imask0_rdata (imask0_rdata[63:0]),
1622 .imask0_err (imask0_err),
1623 .imask1_ack (imask1_ack),
1624 .imask1_rdata (imask1_rdata[63:0]),
1625 .imask1_err (imask1_err),
1626 .mpc (mpc),
1627 .ack_TO_en (ack_TO_en),
1628 .ack_TO_value (ack_TO_value[9:0]),
1629 .mac_reset0 (mac_reset0),
1630 .mac_reset1 (mac_reset1),
1631 .mac_reset2 (mac_reset2),
1632 .mac_reset3 (mac_reset3),
1633 .msi_data (msi_data[6:0]),
1634 .ldgn0 (ldgn0[5:0]),
1635 .ldgn1 (ldgn1[5:0]),
1636 .ldgn2 (ldgn2[5:0]),
1637 .ldgn3 (ldgn3[5:0]),
1638 .ldgn4 (ldgn4[5:0]),
1639 .ldgn5 (ldgn5[5:0]),
1640 .ldgn6 (ldgn6[5:0]),
1641 .ldgn7 (ldgn7[5:0]),
1642 .ldgn8 (ldgn8[5:0]),
1643 .ldgn9 (ldgn9[5:0]),
1644 .ldgn10 (ldgn10[5:0]),
1645 .ldgn11 (ldgn11[5:0]),
1646 .ldgn12 (ldgn12[5:0]),
1647 .ldgn13 (ldgn13[5:0]),
1648 .ldgn14 (ldgn14[5:0]),
1649 .ldgn15 (ldgn15[5:0]),
1650 .ldgn16 (ldgn16[5:0]),
1651 .ldgn17 (ldgn17[5:0]),
1652 .ldgn18 (ldgn18[5:0]),
1653 .ldgn19 (ldgn19[5:0]),
1654 .ldgn20 (ldgn20[5:0]),
1655 .ldgn21 (ldgn21[5:0]),
1656 .ldgn22 (ldgn22[5:0]),
1657 .ldgn23 (ldgn23[5:0]),
1658 .ldgn24 (ldgn24[5:0]),
1659 .ldgn25 (ldgn25[5:0]),
1660 .ldgn26 (ldgn26[5:0]),
1661 .ldgn27 (ldgn27[5:0]),
1662 .ldgn28 (ldgn28[5:0]),
1663 .ldgn29 (ldgn29[5:0]),
1664 .ldgn30 (ldgn30[5:0]),
1665 .ldgn31 (ldgn31[5:0]),
1666 .ldgn32 (ldgn32[5:0]),
1667 .ldgn33 (ldgn33[5:0]),
1668 .ldgn34 (ldgn34[5:0]),
1669 .ldgn35 (ldgn35[5:0]),
1670 .ldgn36 (ldgn36[5:0]),
1671 .ldgn37 (ldgn37[5:0]),
1672 .ldgn38 (ldgn38[5:0]),
1673 .ldgn39 (ldgn39[5:0]),
1674 .ldgn40 (ldgn40[5:0]),
1675 .ldgn41 (ldgn41[5:0]),
1676 .ldgn42 (ldgn42[5:0]),
1677 .ldgn43 (ldgn43[5:0]),
1678 .ldgn44 (ldgn44[5:0]),
1679 .ldgn45 (ldgn45[5:0]),
1680 .ldgn46 (ldgn46[5:0]),
1681 .ldgn47 (ldgn47[5:0]),
1682 .ldgn48 (ldgn48[5:0]),
1683 .ldgn49 (ldgn49[5:0]),
1684 .ldgn50 (ldgn50[5:0]),
1685 .ldgn51 (ldgn51[5:0]),
1686 .ldgn52 (ldgn52[5:0]),
1687 .ldgn53 (ldgn53[5:0]),
1688 .ldgn54 (ldgn54[5:0]),
1689 .ldgn55 (ldgn55[5:0]),
1690 .ldgn56 (ldgn56[5:0]),
1691 .ldgn57 (ldgn57[5:0]),
1692 .ldgn58 (ldgn58[5:0]),
1693 .ldgn59 (ldgn59[5:0]),
1694 .ldgn60 (ldgn60[5:0]),
1695 .ldgn61 (ldgn61[5:0]),
1696 .ldgn62 (ldgn62[5:0]),
1697 .ldgn63 (ldgn63[5:0]),
1698 .ldgn64 (ldgn64[5:0]),
1699 .ldgn65 (ldgn65[5:0]),
1700 .ldgn66 (ldgn66[5:0]),
1701 .ldgn67 (ldgn67[5:0]),
1702 .ldgn68 (ldgn68[5:0]),
1703 .arm0 (arm0),
1704 .arm1 (arm1),
1705 .arm2 (arm2),
1706 .arm3 (arm3),
1707 .arm4 (arm4),
1708 .arm5 (arm5),
1709 .arm6 (arm6),
1710 .arm7 (arm7),
1711 .arm8 (arm8),
1712 .arm9 (arm9),
1713 .arm10 (arm10),
1714 .arm11 (arm11),
1715 .arm12 (arm12),
1716 .arm13 (arm13),
1717 .arm14 (arm14),
1718 .arm15 (arm15),
1719 .arm16 (arm16),
1720 .arm17 (arm17),
1721 .arm18 (arm18),
1722 .arm19 (arm19),
1723 .arm20 (arm20),
1724 .arm21 (arm21),
1725 .arm22 (arm22),
1726 .arm23 (arm23),
1727 .arm24 (arm24),
1728 .arm25 (arm25),
1729 .arm26 (arm26),
1730 .arm27 (arm27),
1731 .arm28 (arm28),
1732 .arm29 (arm29),
1733 .arm30 (arm30),
1734 .arm31 (arm31),
1735 .arm32 (arm32),
1736 .arm33 (arm33),
1737 .arm34 (arm34),
1738 .arm35 (arm35),
1739 .arm36 (arm36),
1740 .arm37 (arm37),
1741 .arm38 (arm38),
1742 .arm39 (arm39),
1743 .arm40 (arm40),
1744 .arm41 (arm41),
1745 .arm42 (arm42),
1746 .arm43 (arm43),
1747 .arm44 (arm44),
1748 .arm45 (arm45),
1749 .arm46 (arm46),
1750 .arm47 (arm47),
1751 .arm48 (arm48),
1752 .arm49 (arm49),
1753 .arm50 (arm50),
1754 .arm51 (arm51),
1755 .arm52 (arm52),
1756 .arm53 (arm53),
1757 .arm54 (arm54),
1758 .arm55 (arm55),
1759 .arm56 (arm56),
1760 .arm57 (arm57),
1761 .arm58 (arm58),
1762 .arm59 (arm59),
1763 .arm60 (arm60),
1764 .arm61 (arm61),
1765 .arm62 (arm62),
1766 .arm63 (arm63),
1767 .ldf_mask0 (ldf_mask0[1:0]),
1768 .ldf_mask1 (ldf_mask1[1:0]),
1769 .ldf_mask2 (ldf_mask2[1:0]),
1770 .ldf_mask3 (ldf_mask3[1:0]),
1771 .ldf_mask4 (ldf_mask4[1:0]),
1772 .ldf_mask5 (ldf_mask5[1:0]),
1773 .ldf_mask6 (ldf_mask6[1:0]),
1774 .ldf_mask7 (ldf_mask7[1:0]),
1775 .ldf_mask8 (ldf_mask8[1:0]),
1776 .ldf_mask9 (ldf_mask9[1:0]),
1777 .ldf_mask10 (ldf_mask10[1:0]),
1778 .ldf_mask11 (ldf_mask11[1:0]),
1779 .ldf_mask12 (ldf_mask12[1:0]),
1780 .ldf_mask13 (ldf_mask13[1:0]),
1781 .ldf_mask14 (ldf_mask14[1:0]),
1782 .ldf_mask15 (ldf_mask15[1:0]),
1783 .ldf_mask16 (ldf_mask16[1:0]),
1784 .ldf_mask17 (ldf_mask17[1:0]),
1785 .ldf_mask18 (ldf_mask18[1:0]),
1786 .ldf_mask19 (ldf_mask19[1:0]),
1787 .ldf_mask20 (ldf_mask20[1:0]),
1788 .ldf_mask21 (ldf_mask21[1:0]),
1789 .ldf_mask22 (ldf_mask22[1:0]),
1790 .ldf_mask23 (ldf_mask23[1:0]),
1791 .ldf_mask24 (ldf_mask24[1:0]),
1792 .ldf_mask25 (ldf_mask25[1:0]),
1793 .ldf_mask26 (ldf_mask26[1:0]),
1794 .ldf_mask27 (ldf_mask27[1:0]),
1795 .ldf_mask28 (ldf_mask28[1:0]),
1796 .ldf_mask29 (ldf_mask29[1:0]),
1797 .ldf_mask30 (ldf_mask30[1:0]),
1798 .ldf_mask31 (ldf_mask31[1:0]),
1799 .ldf_mask32 (ldf_mask32[1:0]),
1800 .ldf_mask33 (ldf_mask33[1:0]),
1801 .ldf_mask34 (ldf_mask34[1:0]),
1802 .ldf_mask35 (ldf_mask35[1:0]),
1803 .ldf_mask36 (ldf_mask36[1:0]),
1804 .ldf_mask37 (ldf_mask37[1:0]),
1805 .ldf_mask38 (ldf_mask38[1:0]),
1806 .ldf_mask39 (ldf_mask39[1:0]),
1807 .ldf_mask40 (ldf_mask40[1:0]),
1808 .ldf_mask41 (ldf_mask41[1:0]),
1809 .ldf_mask42 (ldf_mask42[1:0]),
1810 .ldf_mask43 (ldf_mask43[1:0]),
1811 .ldf_mask44 (ldf_mask44[1:0]),
1812 .ldf_mask45 (ldf_mask45[1:0]),
1813 .ldf_mask46 (ldf_mask46[1:0]),
1814 .ldf_mask47 (ldf_mask47[1:0]),
1815 .ldf_mask48 (ldf_mask48[1:0]),
1816 .ldf_mask49 (ldf_mask49[1:0]),
1817 .ldf_mask50 (ldf_mask50[1:0]),
1818 .ldf_mask51 (ldf_mask51[1:0]),
1819 .ldf_mask52 (ldf_mask52[1:0]),
1820 .ldf_mask53 (ldf_mask53[1:0]),
1821 .ldf_mask54 (ldf_mask54[1:0]),
1822 .ldf_mask55 (ldf_mask55[1:0]),
1823 .ldf_mask56 (ldf_mask56[1:0]),
1824 .ldf_mask57 (ldf_mask57[1:0]),
1825 .ldf_mask58 (ldf_mask58[1:0]),
1826 .ldf_mask59 (ldf_mask59[1:0]),
1827 .ldf_mask60 (ldf_mask60[1:0]),
1828 .ldf_mask61 (ldf_mask61[1:0]),
1829 .ldf_mask62 (ldf_mask62[1:0]),
1830 .ldf_mask63 (ldf_mask63[1:0]),
1831 .ldf_mask64 (ldf_mask64[1:0]),
1832 .ldf_mask65 (ldf_mask65[1:0]),
1833 .ldf_mask66 (ldf_mask66[1:0]),
1834 .ldf_mask67 (ldf_mask67[1:0]),
1835 .ldf_mask68 (ldf_mask68[1:0]),
1836 .timer0 (timer0[5:0]),
1837 .timer1 (timer1[5:0]),
1838 .timer2 (timer2[5:0]),
1839 .timer3 (timer3[5:0]),
1840 .timer4 (timer4[5:0]),
1841 .timer5 (timer5[5:0]),
1842 .timer6 (timer6[5:0]),
1843 .timer7 (timer7[5:0]),
1844 .timer8 (timer8[5:0]),
1845 .timer9 (timer9[5:0]),
1846 .timer10 (timer10[5:0]),
1847 .timer11 (timer11[5:0]),
1848 .timer12 (timer12[5:0]),
1849 .timer13 (timer13[5:0]),
1850 .timer14 (timer14[5:0]),
1851 .timer15 (timer15[5:0]),
1852 .timer16 (timer16[5:0]),
1853 .timer17 (timer17[5:0]),
1854 .timer18 (timer18[5:0]),
1855 .timer19 (timer19[5:0]),
1856 .timer20 (timer20[5:0]),
1857 .timer21 (timer21[5:0]),
1858 .timer22 (timer22[5:0]),
1859 .timer23 (timer23[5:0]),
1860 .timer24 (timer24[5:0]),
1861 .timer25 (timer25[5:0]),
1862 .timer26 (timer26[5:0]),
1863 .timer27 (timer27[5:0]),
1864 .timer28 (timer28[5:0]),
1865 .timer29 (timer29[5:0]),
1866 .timer30 (timer30[5:0]),
1867 .timer31 (timer31[5:0]),
1868 .timer32 (timer32[5:0]),
1869 .timer33 (timer33[5:0]),
1870 .timer34 (timer34[5:0]),
1871 .timer35 (timer35[5:0]),
1872 .timer36 (timer36[5:0]),
1873 .timer37 (timer37[5:0]),
1874 .timer38 (timer38[5:0]),
1875 .timer39 (timer39[5:0]),
1876 .timer40 (timer40[5:0]),
1877 .timer41 (timer41[5:0]),
1878 .timer42 (timer42[5:0]),
1879 .timer43 (timer43[5:0]),
1880 .timer44 (timer44[5:0]),
1881 .timer45 (timer45[5:0]),
1882 .timer46 (timer46[5:0]),
1883 .timer47 (timer47[5:0]),
1884 .timer48 (timer48[5:0]),
1885 .timer49 (timer49[5:0]),
1886 .timer50 (timer50[5:0]),
1887 .timer51 (timer51[5:0]),
1888 .timer52 (timer52[5:0]),
1889 .timer53 (timer53[5:0]),
1890 .timer54 (timer54[5:0]),
1891 .timer55 (timer55[5:0]),
1892 .timer56 (timer56[5:0]),
1893 .timer57 (timer57[5:0]),
1894 .timer58 (timer58[5:0]),
1895 .timer59 (timer59[5:0]),
1896 .timer60 (timer60[5:0]),
1897 .timer61 (timer61[5:0]),
1898 .timer62 (timer62[5:0]),
1899 .timer63 (timer63[5:0]),
1900 .sys_err_mask (sys_err_mask[10:0]),
1901 .smx_meta_intr_hld (smx_meta_intr_hld),
1902 // Inputs
1903 .clk (niu_clk),
1904 .reset (reset),
1905 .niu_reset (niu_reset),
1906 .addr (addr_2[26:0]),
1907 .rd (rd),
1908 .slv_sel_reg (slv_sel_reg),
1909 .fzc_slv_sel_reg (fzc_slv_sel_reg),
1910 .ldsv_sel_reg (ldsv_sel_reg),
1911 .ldgim_sel_reg (ldgim_sel_reg),
1912 .imask0_sel_reg (imask0_sel_reg),
1913 .imask1_sel_reg (imask1_sel_reg),
1914 .group (group[5:0]),
1915`ifdef NEPTUNE
1916 .wr_data (del_pio_clients_wdata[31:0]),
1917`else
1918 .wr_data (pio_clients_wdata[31:0]),
1919`endif
1920 .pio_32b_wr (pio_32b_wr),
1921 .memship_group0 (memship_group0[68:0]),
1922 .memship_group1 (memship_group1[68:0]),
1923 .memship_group2 (memship_group2[68:0]),
1924 .memship_group3 (memship_group3[68:0]),
1925 .memship_group4 (memship_group4[68:0]),
1926 .memship_group5 (memship_group5[68:0]),
1927 .memship_group6 (memship_group6[68:0]),
1928 .memship_group7 (memship_group7[68:0]),
1929 .memship_group8 (memship_group8[68:0]),
1930 .memship_group9 (memship_group9[68:0]),
1931 .memship_group10 (memship_group10[68:0]),
1932 .memship_group11 (memship_group11[68:0]),
1933 .memship_group12 (memship_group12[68:0]),
1934 .memship_group13 (memship_group13[68:0]),
1935 .memship_group14 (memship_group14[68:0]),
1936 .memship_group15 (memship_group15[68:0]),
1937 .memship_group16 (memship_group16[68:0]),
1938 .memship_group17 (memship_group17[68:0]),
1939 .memship_group18 (memship_group18[68:0]),
1940 .memship_group19 (memship_group19[68:0]),
1941 .memship_group20 (memship_group20[68:0]),
1942 .memship_group21 (memship_group21[68:0]),
1943 .memship_group22 (memship_group22[68:0]),
1944 .memship_group23 (memship_group23[68:0]),
1945 .memship_group24 (memship_group24[68:0]),
1946 .memship_group25 (memship_group25[68:0]),
1947 .memship_group26 (memship_group26[68:0]),
1948 .memship_group27 (memship_group27[68:0]),
1949 .memship_group28 (memship_group28[68:0]),
1950 .memship_group29 (memship_group29[68:0]),
1951 .memship_group30 (memship_group30[68:0]),
1952 .memship_group31 (memship_group31[68:0]),
1953 .memship_group32 (memship_group32[68:0]),
1954 .memship_group33 (memship_group33[68:0]),
1955 .memship_group34 (memship_group34[68:0]),
1956 .memship_group35 (memship_group35[68:0]),
1957 .memship_group36 (memship_group36[68:0]),
1958 .memship_group37 (memship_group37[68:0]),
1959 .memship_group38 (memship_group38[68:0]),
1960 .memship_group39 (memship_group39[68:0]),
1961 .memship_group40 (memship_group40[68:0]),
1962 .memship_group41 (memship_group41[68:0]),
1963 .memship_group42 (memship_group42[68:0]),
1964 .memship_group43 (memship_group43[68:0]),
1965 .memship_group44 (memship_group44[68:0]),
1966 .memship_group45 (memship_group45[68:0]),
1967 .memship_group46 (memship_group46[68:0]),
1968 .memship_group47 (memship_group47[68:0]),
1969 .memship_group48 (memship_group48[68:0]),
1970 .memship_group49 (memship_group49[68:0]),
1971 .memship_group50 (memship_group50[68:0]),
1972 .memship_group51 (memship_group51[68:0]),
1973 .memship_group52 (memship_group52[68:0]),
1974 .memship_group53 (memship_group53[68:0]),
1975 .memship_group54 (memship_group54[68:0]),
1976 .memship_group55 (memship_group55[68:0]),
1977 .memship_group56 (memship_group56[68:0]),
1978 .memship_group57 (memship_group57[68:0]),
1979 .memship_group58 (memship_group58[68:0]),
1980 .memship_group59 (memship_group59[68:0]),
1981 .memship_group60 (memship_group60[68:0]),
1982 .memship_group61 (memship_group61[68:0]),
1983 .memship_group62 (memship_group62[68:0]),
1984 .memship_group63 (memship_group63[68:0]),
1985 .rst_at (rst_at),
1986 .ldfi (ldfi[68:0]),
1987 .ldfj (ldfj[68:0]),
1988 .arb_dirtid_en (arb_dirtid_en),
1989 .arb_dirtid_clr (arb_dirtid_clr),
1990 .arb_np_threshold (arb_np_threshold[5:0]),
1991 .arb_rd_threshold (arb_rd_threshold[5:0]),
1992 .arb_rdstat (arb_rdstat[5:0]),
1993 .arb_wrstat (arb_wrstat[5:0]),
1994 .TrainingVector (TrainingVector[31:0]),
1995 .arb_ctrl (arb_ctrl[31:0]),
1996 .arb_debug_vector (arb_debug_vector[31:0]),
1997 .mif_intr (mif_intr),
1998 .ipp_intr (ipp_intr),
1999 .fflp_intr (fflp_intr),
2000 .zcp_intr (zcp_intr),
2001 .txc_intr (txc_intr),
2002 .rdmc_intr (rdmc_intr),
2003 .meta_intr1 (meta_intr1),
2004 .meta_intr2 (meta_intr2),
2005`ifdef NEPTUNE
2006 .pim_intr (pim_intr),
2007 .gpio_dout (gpio_dout[15:0]),
2008 .gpio_din (gpio_din[15:0]),
2009 .gpio_en (gpio_en[15:0]),
2010 .debug_select (debug_select[5:0]));
2011`else
2012 .debug_select (debug_select[5:0]),
2013 .smx_intr (smx_intr),
2014 .smx_ctrl (smx_ctrl[31:0]),
2015 .smx_debug_vector (smx_debug_vector[31:0]),
2016 .smx_config_data (smx_config_data[31:0]),
2017 .smx_status (smx_status[31:0]),
2018 .smx_intr_clr (clear_intr4smx));
2019`endif
2020
2021niu_pio_ic niu_pio_ic
2022(/*AUTOINST*/
2023 // Outputs
2024 .intr_valid (intr_valid),
2025 .intr_invalid (intr_invalid),
2026 .rst_at (rst_at),
2027 .group (group[5:0]),
2028 .memship_group0 (memship_group0[68:0]),
2029 .memship_group1 (memship_group1[68:0]),
2030 .memship_group2 (memship_group2[68:0]),
2031 .memship_group3 (memship_group3[68:0]),
2032 .memship_group4 (memship_group4[68:0]),
2033 .memship_group5 (memship_group5[68:0]),
2034 .memship_group6 (memship_group6[68:0]),
2035 .memship_group7 (memship_group7[68:0]),
2036 .memship_group8 (memship_group8[68:0]),
2037 .memship_group9 (memship_group9[68:0]),
2038 .memship_group10 (memship_group10[68:0]),
2039 .memship_group11 (memship_group11[68:0]),
2040 .memship_group12 (memship_group12[68:0]),
2041 .memship_group13 (memship_group13[68:0]),
2042 .memship_group14 (memship_group14[68:0]),
2043 .memship_group15 (memship_group15[68:0]),
2044 .memship_group16 (memship_group16[68:0]),
2045 .memship_group17 (memship_group17[68:0]),
2046 .memship_group18 (memship_group18[68:0]),
2047 .memship_group19 (memship_group19[68:0]),
2048 .memship_group20 (memship_group20[68:0]),
2049 .memship_group21 (memship_group21[68:0]),
2050 .memship_group22 (memship_group22[68:0]),
2051 .memship_group23 (memship_group23[68:0]),
2052 .memship_group24 (memship_group24[68:0]),
2053 .memship_group25 (memship_group25[68:0]),
2054 .memship_group26 (memship_group26[68:0]),
2055 .memship_group27 (memship_group27[68:0]),
2056 .memship_group28 (memship_group28[68:0]),
2057 .memship_group29 (memship_group29[68:0]),
2058 .memship_group30 (memship_group30[68:0]),
2059 .memship_group31 (memship_group31[68:0]),
2060 .memship_group32 (memship_group32[68:0]),
2061 .memship_group33 (memship_group33[68:0]),
2062 .memship_group34 (memship_group34[68:0]),
2063 .memship_group35 (memship_group35[68:0]),
2064 .memship_group36 (memship_group36[68:0]),
2065 .memship_group37 (memship_group37[68:0]),
2066 .memship_group38 (memship_group38[68:0]),
2067 .memship_group39 (memship_group39[68:0]),
2068 .memship_group40 (memship_group40[68:0]),
2069 .memship_group41 (memship_group41[68:0]),
2070 .memship_group42 (memship_group42[68:0]),
2071 .memship_group43 (memship_group43[68:0]),
2072 .memship_group44 (memship_group44[68:0]),
2073 .memship_group45 (memship_group45[68:0]),
2074 .memship_group46 (memship_group46[68:0]),
2075 .memship_group47 (memship_group47[68:0]),
2076 .memship_group48 (memship_group48[68:0]),
2077 .memship_group49 (memship_group49[68:0]),
2078 .memship_group50 (memship_group50[68:0]),
2079 .memship_group51 (memship_group51[68:0]),
2080 .memship_group52 (memship_group52[68:0]),
2081 .memship_group53 (memship_group53[68:0]),
2082 .memship_group54 (memship_group54[68:0]),
2083 .memship_group55 (memship_group55[68:0]),
2084 .memship_group56 (memship_group56[68:0]),
2085 .memship_group57 (memship_group57[68:0]),
2086 .memship_group58 (memship_group58[68:0]),
2087 .memship_group59 (memship_group59[68:0]),
2088 .memship_group60 (memship_group60[68:0]),
2089 .memship_group61 (memship_group61[68:0]),
2090 .memship_group62 (memship_group62[68:0]),
2091 .memship_group63 (memship_group63[68:0]),
2092 .ig_state (ig_state[2:0]),
2093 // Inputs
2094 .clk (niu_clk),
2095 .reset (reset),
2096 .ldgn0 (ldgn0[5:0]),
2097 .ldgn1 (ldgn1[5:0]),
2098 .ldgn2 (ldgn2[5:0]),
2099 .ldgn3 (ldgn3[5:0]),
2100 .ldgn4 (ldgn4[5:0]),
2101 .ldgn5 (ldgn5[5:0]),
2102 .ldgn6 (ldgn6[5:0]),
2103 .ldgn7 (ldgn7[5:0]),
2104 .ldgn8 (ldgn8[5:0]),
2105 .ldgn9 (ldgn9[5:0]),
2106 .ldgn10 (ldgn10[5:0]),
2107 .ldgn11 (ldgn11[5:0]),
2108 .ldgn12 (ldgn12[5:0]),
2109 .ldgn13 (ldgn13[5:0]),
2110 .ldgn14 (ldgn14[5:0]),
2111 .ldgn15 (ldgn15[5:0]),
2112 .ldgn16 (ldgn16[5:0]),
2113 .ldgn17 (ldgn17[5:0]),
2114 .ldgn18 (ldgn18[5:0]),
2115 .ldgn19 (ldgn19[5:0]),
2116 .ldgn20 (ldgn20[5:0]),
2117 .ldgn21 (ldgn21[5:0]),
2118 .ldgn22 (ldgn22[5:0]),
2119 .ldgn23 (ldgn23[5:0]),
2120 .ldgn24 (ldgn24[5:0]),
2121 .ldgn25 (ldgn25[5:0]),
2122 .ldgn26 (ldgn26[5:0]),
2123 .ldgn27 (ldgn27[5:0]),
2124 .ldgn28 (ldgn28[5:0]),
2125 .ldgn29 (ldgn29[5:0]),
2126 .ldgn30 (ldgn30[5:0]),
2127 .ldgn31 (ldgn31[5:0]),
2128 .ldgn32 (ldgn32[5:0]),
2129 .ldgn33 (ldgn33[5:0]),
2130 .ldgn34 (ldgn34[5:0]),
2131 .ldgn35 (ldgn35[5:0]),
2132 .ldgn36 (ldgn36[5:0]),
2133 .ldgn37 (ldgn37[5:0]),
2134 .ldgn38 (ldgn38[5:0]),
2135 .ldgn39 (ldgn39[5:0]),
2136 .ldgn40 (ldgn40[5:0]),
2137 .ldgn41 (ldgn41[5:0]),
2138 .ldgn42 (ldgn42[5:0]),
2139 .ldgn43 (ldgn43[5:0]),
2140 .ldgn44 (ldgn44[5:0]),
2141 .ldgn45 (ldgn45[5:0]),
2142 .ldgn46 (ldgn46[5:0]),
2143 .ldgn47 (ldgn47[5:0]),
2144 .ldgn48 (ldgn48[5:0]),
2145 .ldgn49 (ldgn49[5:0]),
2146 .ldgn50 (ldgn50[5:0]),
2147 .ldgn51 (ldgn51[5:0]),
2148 .ldgn52 (ldgn52[5:0]),
2149 .ldgn53 (ldgn53[5:0]),
2150 .ldgn54 (ldgn54[5:0]),
2151 .ldgn55 (ldgn55[5:0]),
2152 .ldgn56 (ldgn56[5:0]),
2153 .ldgn57 (ldgn57[5:0]),
2154 .ldgn58 (ldgn58[5:0]),
2155 .ldgn59 (ldgn59[5:0]),
2156 .ldgn60 (ldgn60[5:0]),
2157 .ldgn61 (ldgn61[5:0]),
2158 .ldgn62 (ldgn62[5:0]),
2159 .ldgn63 (ldgn63[5:0]),
2160 .ldgn64 (ldgn64[5:0]),
2161 .ldgn65 (ldgn65[5:0]),
2162 .ldgn66 (ldgn66[5:0]),
2163 .ldgn67 (ldgn67[5:0]),
2164 .ldgn68 (ldgn68[5:0]),
2165 .ldf_mask0 (ldf_mask0[1:0]),
2166 .ldf_mask1 (ldf_mask1[1:0]),
2167 .ldf_mask2 (ldf_mask2[1:0]),
2168 .ldf_mask3 (ldf_mask3[1:0]),
2169 .ldf_mask4 (ldf_mask4[1:0]),
2170 .ldf_mask5 (ldf_mask5[1:0]),
2171 .ldf_mask6 (ldf_mask6[1:0]),
2172 .ldf_mask7 (ldf_mask7[1:0]),
2173 .ldf_mask8 (ldf_mask8[1:0]),
2174 .ldf_mask9 (ldf_mask9[1:0]),
2175 .ldf_mask10 (ldf_mask10[1:0]),
2176 .ldf_mask11 (ldf_mask11[1:0]),
2177 .ldf_mask12 (ldf_mask12[1:0]),
2178 .ldf_mask13 (ldf_mask13[1:0]),
2179 .ldf_mask14 (ldf_mask14[1:0]),
2180 .ldf_mask15 (ldf_mask15[1:0]),
2181 .ldf_mask16 (ldf_mask16[1:0]),
2182 .ldf_mask17 (ldf_mask17[1:0]),
2183 .ldf_mask18 (ldf_mask18[1:0]),
2184 .ldf_mask19 (ldf_mask19[1:0]),
2185 .ldf_mask20 (ldf_mask20[1:0]),
2186 .ldf_mask21 (ldf_mask21[1:0]),
2187 .ldf_mask22 (ldf_mask22[1:0]),
2188 .ldf_mask23 (ldf_mask23[1:0]),
2189 .ldf_mask24 (ldf_mask24[1:0]),
2190 .ldf_mask25 (ldf_mask25[1:0]),
2191 .ldf_mask26 (ldf_mask26[1:0]),
2192 .ldf_mask27 (ldf_mask27[1:0]),
2193 .ldf_mask28 (ldf_mask28[1:0]),
2194 .ldf_mask29 (ldf_mask29[1:0]),
2195 .ldf_mask30 (ldf_mask30[1:0]),
2196 .ldf_mask31 (ldf_mask31[1:0]),
2197 .ldf_mask32 (ldf_mask32[1:0]),
2198 .ldf_mask33 (ldf_mask33[1:0]),
2199 .ldf_mask34 (ldf_mask34[1:0]),
2200 .ldf_mask35 (ldf_mask35[1:0]),
2201 .ldf_mask36 (ldf_mask36[1:0]),
2202 .ldf_mask37 (ldf_mask37[1:0]),
2203 .ldf_mask38 (ldf_mask38[1:0]),
2204 .ldf_mask39 (ldf_mask39[1:0]),
2205 .ldf_mask40 (ldf_mask40[1:0]),
2206 .ldf_mask41 (ldf_mask41[1:0]),
2207 .ldf_mask42 (ldf_mask42[1:0]),
2208 .ldf_mask43 (ldf_mask43[1:0]),
2209 .ldf_mask44 (ldf_mask44[1:0]),
2210 .ldf_mask45 (ldf_mask45[1:0]),
2211 .ldf_mask46 (ldf_mask46[1:0]),
2212 .ldf_mask47 (ldf_mask47[1:0]),
2213 .ldf_mask48 (ldf_mask48[1:0]),
2214 .ldf_mask49 (ldf_mask49[1:0]),
2215 .ldf_mask50 (ldf_mask50[1:0]),
2216 .ldf_mask51 (ldf_mask51[1:0]),
2217 .ldf_mask52 (ldf_mask52[1:0]),
2218 .ldf_mask53 (ldf_mask53[1:0]),
2219 .ldf_mask54 (ldf_mask54[1:0]),
2220 .ldf_mask55 (ldf_mask55[1:0]),
2221 .ldf_mask56 (ldf_mask56[1:0]),
2222 .ldf_mask57 (ldf_mask57[1:0]),
2223 .ldf_mask58 (ldf_mask58[1:0]),
2224 .ldf_mask59 (ldf_mask59[1:0]),
2225 .ldf_mask60 (ldf_mask60[1:0]),
2226 .ldf_mask61 (ldf_mask61[1:0]),
2227 .ldf_mask62 (ldf_mask62[1:0]),
2228 .ldf_mask63 (ldf_mask63[1:0]),
2229 .ldf_mask64 (ldf_mask64[1:0]),
2230 .ldf_mask65 (ldf_mask65[1:0]),
2231 .ldf_mask66 (ldf_mask66[1:0]),
2232 .ldf_mask67 (ldf_mask67[1:0]),
2233 .ldf_mask68 (ldf_mask68[1:0]),
2234 .ldfi (ldfi[68:0]),
2235 .ldfj (ldfj[68:0]),
2236 .arm0 (arm0),
2237 .arm1 (arm1),
2238 .arm2 (arm2),
2239 .arm3 (arm3),
2240 .arm4 (arm4),
2241 .arm5 (arm5),
2242 .arm6 (arm6),
2243 .arm7 (arm7),
2244 .arm8 (arm8),
2245 .arm9 (arm9),
2246 .arm10 (arm10),
2247 .arm11 (arm11),
2248 .arm12 (arm12),
2249 .arm13 (arm13),
2250 .arm14 (arm14),
2251 .arm15 (arm15),
2252 .arm16 (arm16),
2253 .arm17 (arm17),
2254 .arm18 (arm18),
2255 .arm19 (arm19),
2256 .arm20 (arm20),
2257 .arm21 (arm21),
2258 .arm22 (arm22),
2259 .arm23 (arm23),
2260 .arm24 (arm24),
2261 .arm25 (arm25),
2262 .arm26 (arm26),
2263 .arm27 (arm27),
2264 .arm28 (arm28),
2265 .arm29 (arm29),
2266 .arm30 (arm30),
2267 .arm31 (arm31),
2268 .arm32 (arm32),
2269 .arm33 (arm33),
2270 .arm34 (arm34),
2271 .arm35 (arm35),
2272 .arm36 (arm36),
2273 .arm37 (arm37),
2274 .arm38 (arm38),
2275 .arm39 (arm39),
2276 .arm40 (arm40),
2277 .arm41 (arm41),
2278 .arm42 (arm42),
2279 .arm43 (arm43),
2280 .arm44 (arm44),
2281 .arm45 (arm45),
2282 .arm46 (arm46),
2283 .arm47 (arm47),
2284 .arm48 (arm48),
2285 .arm49 (arm49),
2286 .arm50 (arm50),
2287 .arm51 (arm51),
2288 .arm52 (arm52),
2289 .arm53 (arm53),
2290 .arm54 (arm54),
2291 .arm55 (arm55),
2292 .arm56 (arm56),
2293 .arm57 (arm57),
2294 .arm58 (arm58),
2295 .arm59 (arm59),
2296 .arm60 (arm60),
2297 .arm61 (arm61),
2298 .arm62 (arm62),
2299 .arm63 (arm63),
2300 .timer0 (timer0[5:0]),
2301 .timer1 (timer1[5:0]),
2302 .timer2 (timer2[5:0]),
2303 .timer3 (timer3[5:0]),
2304 .timer4 (timer4[5:0]),
2305 .timer5 (timer5[5:0]),
2306 .timer6 (timer6[5:0]),
2307 .timer7 (timer7[5:0]),
2308 .timer8 (timer8[5:0]),
2309 .timer9 (timer9[5:0]),
2310 .timer10 (timer10[5:0]),
2311 .timer11 (timer11[5:0]),
2312 .timer12 (timer12[5:0]),
2313 .timer13 (timer13[5:0]),
2314 .timer14 (timer14[5:0]),
2315 .timer15 (timer15[5:0]),
2316 .timer16 (timer16[5:0]),
2317 .timer17 (timer17[5:0]),
2318 .timer18 (timer18[5:0]),
2319 .timer19 (timer19[5:0]),
2320 .timer20 (timer20[5:0]),
2321 .timer21 (timer21[5:0]),
2322 .timer22 (timer22[5:0]),
2323 .timer23 (timer23[5:0]),
2324 .timer24 (timer24[5:0]),
2325 .timer25 (timer25[5:0]),
2326 .timer26 (timer26[5:0]),
2327 .timer27 (timer27[5:0]),
2328 .timer28 (timer28[5:0]),
2329 .timer29 (timer29[5:0]),
2330 .timer30 (timer30[5:0]),
2331 .timer31 (timer31[5:0]),
2332 .timer32 (timer32[5:0]),
2333 .timer33 (timer33[5:0]),
2334 .timer34 (timer34[5:0]),
2335 .timer35 (timer35[5:0]),
2336 .timer36 (timer36[5:0]),
2337 .timer37 (timer37[5:0]),
2338 .timer38 (timer38[5:0]),
2339 .timer39 (timer39[5:0]),
2340 .timer40 (timer40[5:0]),
2341 .timer41 (timer41[5:0]),
2342 .timer42 (timer42[5:0]),
2343 .timer43 (timer43[5:0]),
2344 .timer44 (timer44[5:0]),
2345 .timer45 (timer45[5:0]),
2346 .timer46 (timer46[5:0]),
2347 .timer47 (timer47[5:0]),
2348 .timer48 (timer48[5:0]),
2349 .timer49 (timer49[5:0]),
2350 .timer50 (timer50[5:0]),
2351 .timer51 (timer51[5:0]),
2352 .timer52 (timer52[5:0]),
2353 .timer53 (timer53[5:0]),
2354 .timer54 (timer54[5:0]),
2355 .timer55 (timer55[5:0]),
2356 .timer56 (timer56[5:0]),
2357 .timer57 (timer57[5:0]),
2358 .timer58 (timer58[5:0]),
2359 .timer59 (timer59[5:0]),
2360 .timer60 (timer60[5:0]),
2361 .timer61 (timer61[5:0]),
2362 .timer62 (timer62[5:0]),
2363 .timer63 (timer63[5:0]),
2364 .ibusy (ibusy));
2365
2366
2367niu_pio_debug niu_pio_debug ( // Outputs
2368 .pio_debug_port(pio_debug_port[31:0]),
2369 // Inputs
2370 .SysClk(niu_clk),
2371 .Reset_L(niu_reset_l),
2372 .TrainingVector(TrainingVector[31:0]),
2373 .rd_ptr(rd_ptr[4:0]),
2374 .wr_ptr(wr_ptr[4:0]),
2375 .pio_rw_state(pio_rw_state[2:0]),
2376 .accepted_state(accepted_state[1:0]),
2377 .ig_state(ig_state[2:0]),
2378 .debug_select(debug_select[5:0]));
2379
2380niu_pio_virt_decode niu_pio_virt_decode (
2381 .virt_addr(virt_addr[26:0]),
2382 .pio_virt_sel_ok(pio_virt_sel_ok),
2383 .fflp_virt_sel_ok(fflp_virt_sel_ok),
2384 .dma_virt_sel_ok(dma_virt_sel_ok),
2385 .addr(addr[26:0]),
2386 .fc0_v(fc0_v),
2387 .fc1_v(fc1_v),
2388 .fc2_v(fc2_v),
2389 .fc3_v(fc3_v));
2390`ifdef NEPTUNE
2391
2392// instantiate spare here
2393wire [3:0] do_nad_0;
2394wire [3:0] do_nor_0;
2395wire [3:0] do_inv_0;
2396wire [3:0] do_mux_0;
2397wire [3:0] do_q_0;
2398wire so_0;
2399wire [3:0] do_nad_1;
2400wire [3:0] do_nor_1;
2401wire [3:0] do_inv_1;
2402wire [3:0] do_mux_1;
2403wire [3:0] do_q_1;
2404wire so_1;
2405wire [3:0] do_nad_2;
2406wire [3:0] do_nor_2;
2407wire [3:0] do_inv_2;
2408wire [3:0] do_mux_2;
2409wire [3:0] do_q_2;
2410wire so_2;
2411wire [3:0] do_nad_3;
2412wire [3:0] do_nor_3;
2413wire [3:0] do_inv_3;
2414wire [3:0] do_mux_3;
2415wire [3:0] do_q_3;
2416wire so_3;
2417
2418niu_pio_spare niu_pio_spare_0 (
2419 .di_nd3 ({1'h1, 1'h1, do_q_0[3]}),
2420 .di_nd2 ({1'h1, 1'h1, do_q_0[2]}),
2421 .di_nd1 ({1'h1, 1'h1, do_q_0[1]}),
2422 .di_nd0 ({1'h1, 1'h1, do_q_0[0]}),
2423 .di_nr3 ({1'h0, 1'h0}),
2424 .di_nr2 ({1'h0, 1'h0}),
2425 .di_nr1 ({1'h0, 1'h0}),
2426 .di_nr0 ({1'h0, 1'h0}),
2427 .di_inv (do_nad_0[3:0]),
2428 .di_mx3 ({1'h0, 1'h0}),
2429 .di_mx2 ({1'h0, 1'h0}),
2430 .di_mx1 ({1'h0, 1'h0}),
2431 .di_mx0 ({1'h0, 1'h0}),
2432 .mx_sel (do_nor_0[3:0]),
2433 .di_reg (do_inv_0[3:0]),
2434 .wt_ena (do_mux_0[3:0]),
2435 .rst ({niu_reset_l,niu_reset_l,niu_reset_l,niu_reset_l}),
2436 .si (1'h0),
2437 .se (1'h0),
2438 .clk (niu_clk),
2439 .do_nad (do_nad_0[3:0]),
2440 .do_nor (do_nor_0[3:0]),
2441 .do_inv (do_inv_0[3:0]),
2442 .do_mux (do_mux_0[3:0]),
2443 .do_q (do_q_0[3:0]),
2444 .so (so_0)
2445 );
2446
2447niu_pio_spare niu_pio_spare_1 (
2448 .di_nd3 ({1'h1, 1'h1, do_q_1[3]}),
2449 .di_nd2 ({1'h1, 1'h1, do_q_1[2]}),
2450 .di_nd1 ({1'h1, 1'h1, do_q_1[1]}),
2451 .di_nd0 ({1'h1, 1'h1, do_q_1[0]}),
2452 .di_nr3 ({1'h0, 1'h0}),
2453 .di_nr2 ({1'h0, 1'h0}),
2454 .di_nr1 ({1'h0, 1'h0}),
2455 .di_nr0 ({1'h0, 1'h0}),
2456 .di_inv (do_nad_1[3:0]),
2457 .di_mx3 ({1'h0, 1'h0}),
2458 .di_mx2 ({1'h0, 1'h0}),
2459 .di_mx1 ({1'h0, 1'h0}),
2460 .di_mx0 ({1'h0, 1'h0}),
2461 .mx_sel (do_nor_1[3:0]),
2462 .di_reg (do_inv_1[3:0]),
2463 .wt_ena (do_mux_1[3:0]),
2464 .rst ({niu_reset_l,niu_reset_l,niu_reset_l,niu_reset_l}),
2465 .si (1'h0),
2466 .se (1'h0),
2467 .clk (niu_clk),
2468 .do_nad (do_nad_1[3:0]),
2469 .do_nor (do_nor_1[3:0]),
2470 .do_inv (do_inv_1[3:0]),
2471 .do_mux (do_mux_1[3:0]),
2472 .do_q (do_q_1[3:0]),
2473 .so (so_1)
2474 );
2475
2476niu_pio_spare niu_pio_spare_2 (
2477 .di_nd3 ({1'h1, 1'h1, do_q_2[3]}),
2478 .di_nd2 ({1'h1, 1'h1, do_q_2[2]}),
2479 .di_nd1 ({1'h1, 1'h1, do_q_2[1]}),
2480 .di_nd0 ({1'h1, 1'h1, do_q_2[0]}),
2481 .di_nr3 ({1'h0, 1'h0}),
2482 .di_nr2 ({1'h0, 1'h0}),
2483 .di_nr1 ({1'h0, 1'h0}),
2484 .di_nr0 ({1'h0, 1'h0}),
2485 .di_inv (do_nad_2[3:0]),
2486 .di_mx3 ({1'h0, 1'h0}),
2487 .di_mx2 ({1'h0, 1'h0}),
2488 .di_mx1 ({1'h0, 1'h0}),
2489 .di_mx0 ({1'h0, 1'h0}),
2490 .mx_sel (do_nor_2[3:0]),
2491 .di_reg (do_inv_2[3:0]),
2492 .wt_ena (do_mux_2[3:0]),
2493 .rst ({niu_reset_l,niu_reset_l,niu_reset_l,niu_reset_l}),
2494 .si (1'h0),
2495 .se (1'h0),
2496 .clk (niu_clk),
2497 .do_nad (do_nad_2[3:0]),
2498 .do_nor (do_nor_2[3:0]),
2499 .do_inv (do_inv_2[3:0]),
2500 .do_mux (do_mux_2[3:0]),
2501 .do_q (do_q_2[3:0]),
2502 .so (so_2)
2503 );
2504
2505niu_pio_spare niu_pio_spare_3 (
2506 .di_nd3 ({1'h1, 1'h1, do_q_3[3]}),
2507 .di_nd2 ({1'h1, 1'h1, do_q_3[2]}),
2508 .di_nd1 ({1'h1, 1'h1, do_q_3[1]}),
2509 .di_nd0 ({1'h1, 1'h1, do_q_3[0]}),
2510 .di_nr3 ({1'h0, 1'h0}),
2511 .di_nr2 ({1'h0, 1'h0}),
2512 .di_nr1 ({1'h0, 1'h0}),
2513 .di_nr0 ({1'h0, 1'h0}),
2514 .di_inv (do_nad_3[3:0]),
2515 .di_mx3 ({1'h0, 1'h0}),
2516 .di_mx2 ({1'h0, 1'h0}),
2517 .di_mx1 ({1'h0, 1'h0}),
2518 .di_mx0 ({1'h0, 1'h0}),
2519 .mx_sel (do_nor_3[3:0]),
2520 .di_reg (do_inv_3[3:0]),
2521 .wt_ena (do_mux_3[3:0]),
2522 .rst ({niu_reset_l,niu_reset_l,niu_reset_l,niu_reset_l}),
2523 .si (1'h0),
2524 .se (1'h0),
2525 .clk (niu_clk),
2526 .do_nad (do_nad_3[3:0]),
2527 .do_nor (do_nor_3[3:0]),
2528 .do_inv (do_inv_3[3:0]),
2529 .do_mux (do_mux_3[3:0]),
2530 .do_q (do_q_3[3:0]),
2531 .so (so_3)
2532 );
2533
2534
2535`else
2536`endif
2537endmodule // niu_pio
Full OpenSPARC design & verification tarball including full HDL.