projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_fzc_slv_decoder.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_pio_fzc_slv_decoder.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%w% %G%*/
36
37/*****************************************************************
38 *
39 * File Name : niu_pio_fzc_slv_decoder.v
40 * Author Name : John Lo
41 * Description : It contains PIO itslef read/write decoder,
42 *
43 * Parent Module: niu_pio_fzc_slv_decoder.v
44 * Child Module:
45 * Interface Mod: many.
46 * Date Created : 3/30/04
47 *
48 * Copyright (c) 2020, Sun Microsystems, Inc.
49 * Sun Proprietary and Confidential
50 *
51 * Modification :
52 *
53 ****************************************************************/
54
55module niu_pio_fzc_slv_decoder (/*AUTOARG*/
56 // Outputs
57 fzc_slv_ack, fzc_slv_rdata, fzc_slv_err, ld_config1,
58 ld_rst_ctl, ld_sys_err_mask, ld_sys_err_stat, ld_rtimer,
59 ld_dma_bind0, ld_dma_bind1, ld_dma_bind2, ld_dma_bind3,
60 ld_dma_bind4, ld_dma_bind5, ld_dma_bind6, ld_dma_bind7,
61 ld_dma_bind8, ld_dma_bind9, ld_dma_bind10, ld_dma_bind11,
62 ld_dma_bind12, ld_dma_bind13, ld_dma_bind14, ld_dma_bind15,
63 ld_dma_bind16, ld_dma_bind17, ld_dma_bind18, ld_dma_bind19,
64 ld_dma_bind20, ld_dma_bind21, ld_dma_bind22, ld_dma_bind23,
65 ld_dma_bind24, ld_dma_bind25, ld_dma_bind26, ld_dma_bind27,
66 ld_dma_bind28, ld_dma_bind29, ld_dma_bind30, ld_dma_bind31,
67 ld_dma_bind32, ld_dma_bind33, ld_dma_bind34, ld_dma_bind35,
68 ld_dma_bind36, ld_dma_bind37, ld_dma_bind38, ld_dma_bind39,
69 ld_dma_bind40, ld_dma_bind41, ld_dma_bind42, ld_dma_bind43,
70 ld_dma_bind44, ld_dma_bind45, ld_dma_bind46, ld_dma_bind47,
71 ld_dma_bind48, ld_dma_bind49, ld_dma_bind50, ld_dma_bind51,
72 ld_dma_bind52, ld_dma_bind53, ld_dma_bind54, ld_dma_bind55,
73 ld_dma_bind56, ld_dma_bind57, ld_dma_bind58, ld_dma_bind59,
74 ld_dma_bind60, ld_dma_bind61, ld_dma_bind62, ld_dma_bind63,
75 ld_sid0, ld_sid1, ld_sid2, ld_sid3, ld_sid4, ld_sid5, ld_sid6,
76 ld_sid7, ld_sid8, ld_sid9, ld_sid10, ld_sid11, ld_sid12, ld_sid13,
77 ld_sid14, ld_sid15, ld_sid16, ld_sid17, ld_sid18, ld_sid19,
78 ld_sid20, ld_sid21, ld_sid22, ld_sid23, ld_sid24, ld_sid25,
79 ld_sid26, ld_sid27, ld_sid28, ld_sid29, ld_sid30, ld_sid31,
80 ld_sid32, ld_sid33, ld_sid34, ld_sid35, ld_sid36, ld_sid37,
81 ld_sid38, ld_sid39, ld_sid40, ld_sid41, ld_sid42, ld_sid43,
82 ld_sid44, ld_sid45, ld_sid46, ld_sid47, ld_sid48, ld_sid49,
83 ld_sid50, ld_sid51, ld_sid52, ld_sid53, ld_sid54, ld_sid55,
84 ld_sid56, ld_sid57, ld_sid58, ld_sid59, ld_sid60, ld_sid61,
85 ld_sid62, ld_sid63, ld_ldgn0, ld_ldgn1, ld_ldgn2, ld_ldgn3,
86 ld_ldgn4, ld_ldgn5, ld_ldgn6, ld_ldgn7, ld_ldgn8, ld_ldgn9,
87 ld_ldgn10, ld_ldgn11, ld_ldgn12, ld_ldgn13, ld_ldgn14, ld_ldgn15,
88 ld_ldgn16, ld_ldgn17, ld_ldgn18, ld_ldgn19, ld_ldgn20, ld_ldgn21,
89 ld_ldgn22, ld_ldgn23, ld_ldgn24, ld_ldgn25, ld_ldgn26, ld_ldgn27,
90 ld_ldgn28, ld_ldgn29, ld_ldgn30, ld_ldgn31, ld_ldgn32, ld_ldgn33,
91 ld_ldgn34, ld_ldgn35, ld_ldgn36, ld_ldgn37, ld_ldgn38, ld_ldgn39,
92 ld_ldgn40, ld_ldgn41, ld_ldgn42, ld_ldgn43, ld_ldgn44, ld_ldgn45,
93 ld_ldgn46, ld_ldgn47, ld_ldgn48, ld_ldgn49, ld_ldgn50, ld_ldgn51,
94 ld_ldgn52, ld_ldgn53, ld_ldgn54, ld_ldgn55, ld_ldgn56, ld_ldgn57,
95 ld_ldgn58, ld_ldgn59, ld_ldgn60, ld_ldgn61, ld_ldgn62, ld_ldgn63,
96 ld_ldgn64, ld_ldgn65, ld_ldgn66, ld_ldgn67, ld_ldgn68,
97 ld_debug_select, ld_TrainingVector,
98 ld_arb_dout, ld_arb_din, ld_arb_ctrl, ld_arb_debug_vector,
99 ld_smx_meta_intr_hld,
100`ifdef NEPTUNE
101 ld_gpio_dout, ld_gpio_en, ld_gpio_din,
102`else
103 ld_smx_intr_clr, ld_smx_config_data, ld_smx_ctrl, ld_smx_debug_vector,
104 ld_smx_intr_status,
105`endif
106 // Inputs
107 niu_clk, fzc_slv_sel_reg, addr, rd, config1, rst_ctl, sys_err_stat,
108 sys_err_mask, rtimer,
109 dma_bind0, dma_bind1, dma_bind2, dma_bind3, dma_bind4, dma_bind5,
110 dma_bind6, dma_bind7, dma_bind8, dma_bind9, dma_bind10,
111 dma_bind11, dma_bind12, dma_bind13, dma_bind14, dma_bind15,
112 dma_bind16, dma_bind17, dma_bind18, dma_bind19, dma_bind20,
113 dma_bind21, dma_bind22, dma_bind23, dma_bind24, dma_bind25,
114 dma_bind26, dma_bind27, dma_bind28, dma_bind29, dma_bind30,
115 dma_bind31, dma_bind32, dma_bind33, dma_bind34, dma_bind35,
116 dma_bind36, dma_bind37, dma_bind38, dma_bind39, dma_bind40,
117 dma_bind41, dma_bind42, dma_bind43, dma_bind44, dma_bind45,
118 dma_bind46, dma_bind47, dma_bind48, dma_bind49, dma_bind50,
119 dma_bind51, dma_bind52, dma_bind53, dma_bind54, dma_bind55,
120 dma_bind56, dma_bind57, dma_bind58, dma_bind59, dma_bind60,
121 dma_bind61, dma_bind62, dma_bind63, sid0, sid1, sid2, sid3, sid4,
122 sid5, sid6, sid7, sid8, sid9, sid10, sid11, sid12, sid13, sid14,
123 sid15, sid16, sid17, sid18, sid19, sid20, sid21, sid22, sid23,
124 sid24, sid25, sid26, sid27, sid28, sid29, sid30, sid31, sid32,
125 sid33, sid34, sid35, sid36, sid37, sid38, sid39, sid40, sid41,
126 sid42, sid43, sid44, sid45, sid46, sid47, sid48, sid49, sid50,
127 sid51, sid52, sid53, sid54, sid55, sid56, sid57, sid58, sid59,
128 sid60, sid61, sid62, sid63, ldgn0, ldgn1, ldgn2, ldgn3, ldgn4,
129 ldgn5, ldgn6, ldgn7, ldgn8, ldgn9, ldgn10, ldgn11, ldgn12, ldgn13,
130 ldgn14, ldgn15, ldgn16, ldgn17, ldgn18, ldgn19, ldgn20, ldgn21,
131 ldgn22, ldgn23, ldgn24, ldgn25, ldgn26, ldgn27, ldgn28, ldgn29,
132 ldgn30, ldgn31, ldgn32, ldgn33, ldgn34, ldgn35, ldgn36, ldgn37,
133 ldgn38, ldgn39, ldgn40, ldgn41, ldgn42, ldgn43, ldgn44, ldgn45,
134 ldgn46, ldgn47, ldgn48, ldgn49, ldgn50, ldgn51, ldgn52, ldgn53,
135 ldgn54, ldgn55, ldgn56, ldgn57, ldgn58, ldgn59, ldgn60, ldgn61,
136 ldgn62, ldgn63, ldgn64, ldgn65, ldgn66, ldgn67, ldgn68,
137 debug_select, TrainingVector, reset,
138 arb_ctrl, arb_debug_vector, arb_dout, arb_din_int,
139 smx_meta_intr_hld,
140`ifdef NEPTUNE
141 gpio_dout, gpio_en, gpio_din_int
142`else
143 smx_intr_clr, smx_config_data, smx_ctrl, smx_debug_vector,
144 smx_intr_status
145`endif
146 );
147 input niu_clk;
148 input reset;
149
150 input fzc_slv_sel_reg;
151 // pio broadcast signals
152 input [18:0] addr;
153 input rd;
154 input config1;
155 input [22:0] rst_ctl;
156 input [10:0] sys_err_stat;
157 input [10:0] sys_err_mask;
158 input [19:0] rtimer;
159 input [13:0] dma_bind0 ;
160 input [13:0] dma_bind1 ;
161 input [13:0] dma_bind2 ;
162 input [13:0] dma_bind3 ;
163 input [13:0] dma_bind4 ;
164 input [13:0] dma_bind5 ;
165 input [13:0] dma_bind6 ;
166 input [13:0] dma_bind7 ;
167 input [13:0] dma_bind8 ;
168 input [13:0] dma_bind9 ;
169 input [13:0] dma_bind10;
170 input [13:0] dma_bind11;
171 input [13:0] dma_bind12;
172 input [13:0] dma_bind13;
173 input [13:0] dma_bind14;
174 input [13:0] dma_bind15;
175 input [13:0] dma_bind16;
176 input [13:0] dma_bind17;
177 input [13:0] dma_bind18;
178 input [13:0] dma_bind19;
179 input [13:0] dma_bind20;
180 input [13:0] dma_bind21;
181 input [13:0] dma_bind22;
182 input [13:0] dma_bind23;
183 input [13:0] dma_bind24;
184 input [13:0] dma_bind25;
185 input [13:0] dma_bind26;
186 input [13:0] dma_bind27;
187 input [13:0] dma_bind28;
188 input [13:0] dma_bind29;
189 input [13:0] dma_bind30;
190 input [13:0] dma_bind31;
191 input [13:0] dma_bind32;
192 input [13:0] dma_bind33;
193 input [13:0] dma_bind34;
194 input [13:0] dma_bind35;
195 input [13:0] dma_bind36;
196 input [13:0] dma_bind37;
197 input [13:0] dma_bind38;
198 input [13:0] dma_bind39;
199 input [13:0] dma_bind40;
200 input [13:0] dma_bind41;
201 input [13:0] dma_bind42;
202 input [13:0] dma_bind43;
203 input [13:0] dma_bind44;
204 input [13:0] dma_bind45;
205 input [13:0] dma_bind46;
206 input [13:0] dma_bind47;
207 input [13:0] dma_bind48;
208 input [13:0] dma_bind49;
209 input [13:0] dma_bind50;
210 input [13:0] dma_bind51;
211 input [13:0] dma_bind52;
212 input [13:0] dma_bind53;
213 input [13:0] dma_bind54;
214 input [13:0] dma_bind55;
215 input [13:0] dma_bind56;
216 input [13:0] dma_bind57;
217 input [13:0] dma_bind58;
218 input [13:0] dma_bind59;
219 input [13:0] dma_bind60;
220 input [13:0] dma_bind61;
221 input [13:0] dma_bind62;
222 input [13:0] dma_bind63;
223
224 input [6:0] sid0 ;
225 input [6:0] sid1 ;
226 input [6:0] sid2 ;
227 input [6:0] sid3 ;
228 input [6:0] sid4 ;
229 input [6:0] sid5 ;
230 input [6:0] sid6 ;
231 input [6:0] sid7 ;
232 input [6:0] sid8 ;
233 input [6:0] sid9 ;
234 input [6:0] sid10;
235 input [6:0] sid11;
236 input [6:0] sid12;
237 input [6:0] sid13;
238 input [6:0] sid14;
239 input [6:0] sid15;
240 input [6:0] sid16;
241 input [6:0] sid17;
242 input [6:0] sid18;
243 input [6:0] sid19;
244 input [6:0] sid20;
245 input [6:0] sid21;
246 input [6:0] sid22;
247 input [6:0] sid23;
248 input [6:0] sid24;
249 input [6:0] sid25;
250 input [6:0] sid26;
251 input [6:0] sid27;
252 input [6:0] sid28;
253 input [6:0] sid29;
254 input [6:0] sid30;
255 input [6:0] sid31;
256 input [6:0] sid32;
257 input [6:0] sid33;
258 input [6:0] sid34;
259 input [6:0] sid35;
260 input [6:0] sid36;
261 input [6:0] sid37;
262 input [6:0] sid38;
263 input [6:0] sid39;
264 input [6:0] sid40;
265 input [6:0] sid41;
266 input [6:0] sid42;
267 input [6:0] sid43;
268 input [6:0] sid44;
269 input [6:0] sid45;
270 input [6:0] sid46;
271 input [6:0] sid47;
272 input [6:0] sid48;
273 input [6:0] sid49;
274 input [6:0] sid50;
275 input [6:0] sid51;
276 input [6:0] sid52;
277 input [6:0] sid53;
278 input [6:0] sid54;
279 input [6:0] sid55;
280 input [6:0] sid56;
281 input [6:0] sid57;
282 input [6:0] sid58;
283 input [6:0] sid59;
284 input [6:0] sid60;
285 input [6:0] sid61;
286 input [6:0] sid62;
287 input [6:0] sid63;
288
289 input [5:0] ldgn0 ;
290 input [5:0] ldgn1 ;
291 input [5:0] ldgn2 ;
292 input [5:0] ldgn3 ;
293 input [5:0] ldgn4 ;
294 input [5:0] ldgn5 ;
295 input [5:0] ldgn6 ;
296 input [5:0] ldgn7 ;
297 input [5:0] ldgn8 ;
298 input [5:0] ldgn9 ;
299 input [5:0] ldgn10;
300 input [5:0] ldgn11;
301 input [5:0] ldgn12;
302 input [5:0] ldgn13;
303 input [5:0] ldgn14;
304 input [5:0] ldgn15;
305 input [5:0] ldgn16;
306 input [5:0] ldgn17;
307 input [5:0] ldgn18;
308 input [5:0] ldgn19;
309 input [5:0] ldgn20;
310 input [5:0] ldgn21;
311 input [5:0] ldgn22;
312 input [5:0] ldgn23;
313 input [5:0] ldgn24;
314 input [5:0] ldgn25;
315 input [5:0] ldgn26;
316 input [5:0] ldgn27;
317 input [5:0] ldgn28;
318 input [5:0] ldgn29;
319 input [5:0] ldgn30;
320 input [5:0] ldgn31;
321 input [5:0] ldgn32;
322 input [5:0] ldgn33;
323 input [5:0] ldgn34;
324 input [5:0] ldgn35;
325 input [5:0] ldgn36;
326 input [5:0] ldgn37;
327 input [5:0] ldgn38;
328 input [5:0] ldgn39;
329 input [5:0] ldgn40;
330 input [5:0] ldgn41;
331 input [5:0] ldgn42;
332 input [5:0] ldgn43;
333 input [5:0] ldgn44;
334 input [5:0] ldgn45;
335 input [5:0] ldgn46;
336 input [5:0] ldgn47;
337 input [5:0] ldgn48;
338 input [5:0] ldgn49;
339 input [5:0] ldgn50;
340 input [5:0] ldgn51;
341 input [5:0] ldgn52;
342 input [5:0] ldgn53;
343 input [5:0] ldgn54;
344 input [5:0] ldgn55;
345 input [5:0] ldgn56;
346 input [5:0] ldgn57;
347 input [5:0] ldgn58;
348 input [5:0] ldgn59;
349 input [5:0] ldgn60;
350 input [5:0] ldgn61;
351 input [5:0] ldgn62;
352 input [5:0] ldgn63;
353 input [5:0] ldgn64;
354 input [5:0] ldgn65;
355 input [5:0] ldgn66;
356 input [5:0] ldgn67;
357 input [5:0] ldgn68;
358
359 output fzc_slv_ack;
360 output [63:0] fzc_slv_rdata;
361 output fzc_slv_err;
362 //
363 output ld_config1;
364 output ld_sys_err_mask;
365 output ld_sys_err_stat;
366 output ld_rst_ctl;
367 output ld_rtimer;
368
369 output ld_dma_bind0 ;
370 output ld_dma_bind1 ;
371 output ld_dma_bind2 ;
372 output ld_dma_bind3 ;
373 output ld_dma_bind4 ;
374 output ld_dma_bind5 ;
375 output ld_dma_bind6 ;
376 output ld_dma_bind7 ;
377 output ld_dma_bind8 ;
378 output ld_dma_bind9 ;
379 output ld_dma_bind10;
380 output ld_dma_bind11;
381 output ld_dma_bind12;
382 output ld_dma_bind13;
383 output ld_dma_bind14;
384 output ld_dma_bind15;
385 output ld_dma_bind16;
386 output ld_dma_bind17;
387 output ld_dma_bind18;
388 output ld_dma_bind19;
389 output ld_dma_bind20;
390 output ld_dma_bind21;
391 output ld_dma_bind22;
392 output ld_dma_bind23;
393 output ld_dma_bind24;
394 output ld_dma_bind25;
395 output ld_dma_bind26;
396 output ld_dma_bind27;
397 output ld_dma_bind28;
398 output ld_dma_bind29;
399 output ld_dma_bind30;
400 output ld_dma_bind31;
401 output ld_dma_bind32;
402 output ld_dma_bind33;
403 output ld_dma_bind34;
404 output ld_dma_bind35;
405 output ld_dma_bind36;
406 output ld_dma_bind37;
407 output ld_dma_bind38;
408 output ld_dma_bind39;
409 output ld_dma_bind40;
410 output ld_dma_bind41;
411 output ld_dma_bind42;
412 output ld_dma_bind43;
413 output ld_dma_bind44;
414 output ld_dma_bind45;
415 output ld_dma_bind46;
416 output ld_dma_bind47;
417 output ld_dma_bind48;
418 output ld_dma_bind49;
419 output ld_dma_bind50;
420 output ld_dma_bind51;
421 output ld_dma_bind52;
422 output ld_dma_bind53;
423 output ld_dma_bind54;
424 output ld_dma_bind55;
425 output ld_dma_bind56;
426 output ld_dma_bind57;
427 output ld_dma_bind58;
428 output ld_dma_bind59;
429 output ld_dma_bind60;
430 output ld_dma_bind61;
431 output ld_dma_bind62;
432 output ld_dma_bind63;
433
434 output ld_sid0 ;
435 output ld_sid1 ;
436 output ld_sid2 ;
437 output ld_sid3 ;
438 output ld_sid4 ;
439 output ld_sid5 ;
440 output ld_sid6 ;
441 output ld_sid7 ;
442 output ld_sid8 ;
443 output ld_sid9 ;
444 output ld_sid10;
445 output ld_sid11;
446 output ld_sid12;
447 output ld_sid13;
448 output ld_sid14;
449 output ld_sid15;
450 output ld_sid16;
451 output ld_sid17;
452 output ld_sid18;
453 output ld_sid19;
454 output ld_sid20;
455 output ld_sid21;
456 output ld_sid22;
457 output ld_sid23;
458 output ld_sid24;
459 output ld_sid25;
460 output ld_sid26;
461 output ld_sid27;
462 output ld_sid28;
463 output ld_sid29;
464 output ld_sid30;
465 output ld_sid31;
466 output ld_sid32;
467 output ld_sid33;
468 output ld_sid34;
469 output ld_sid35;
470 output ld_sid36;
471 output ld_sid37;
472 output ld_sid38;
473 output ld_sid39;
474 output ld_sid40;
475 output ld_sid41;
476 output ld_sid42;
477 output ld_sid43;
478 output ld_sid44;
479 output ld_sid45;
480 output ld_sid46;
481 output ld_sid47;
482 output ld_sid48;
483 output ld_sid49;
484 output ld_sid50;
485 output ld_sid51;
486 output ld_sid52;
487 output ld_sid53;
488 output ld_sid54;
489 output ld_sid55;
490 output ld_sid56;
491 output ld_sid57;
492 output ld_sid58;
493 output ld_sid59;
494 output ld_sid60;
495 output ld_sid61;
496 output ld_sid62;
497 output ld_sid63;
498
499 output ld_ldgn0 ;
500 output ld_ldgn1 ;
501 output ld_ldgn2 ;
502 output ld_ldgn3 ;
503 output ld_ldgn4 ;
504 output ld_ldgn5 ;
505 output ld_ldgn6 ;
506 output ld_ldgn7 ;
507 output ld_ldgn8 ;
508 output ld_ldgn9 ;
509 output ld_ldgn10;
510 output ld_ldgn11;
511 output ld_ldgn12;
512 output ld_ldgn13;
513 output ld_ldgn14;
514 output ld_ldgn15;
515 output ld_ldgn16;
516 output ld_ldgn17;
517 output ld_ldgn18;
518 output ld_ldgn19;
519 output ld_ldgn20;
520 output ld_ldgn21;
521 output ld_ldgn22;
522 output ld_ldgn23;
523 output ld_ldgn24;
524 output ld_ldgn25;
525 output ld_ldgn26;
526 output ld_ldgn27;
527 output ld_ldgn28;
528 output ld_ldgn29;
529 output ld_ldgn30;
530 output ld_ldgn31;
531 output ld_ldgn32;
532 output ld_ldgn33;
533 output ld_ldgn34;
534 output ld_ldgn35;
535 output ld_ldgn36;
536 output ld_ldgn37;
537 output ld_ldgn38;
538 output ld_ldgn39;
539 output ld_ldgn40;
540 output ld_ldgn41;
541 output ld_ldgn42;
542 output ld_ldgn43;
543 output ld_ldgn44;
544 output ld_ldgn45;
545 output ld_ldgn46;
546 output ld_ldgn47;
547 output ld_ldgn48;
548 output ld_ldgn49;
549 output ld_ldgn50;
550 output ld_ldgn51;
551 output ld_ldgn52;
552 output ld_ldgn53;
553 output ld_ldgn54;
554 output ld_ldgn55;
555 output ld_ldgn56;
556 output ld_ldgn57;
557 output ld_ldgn58;
558 output ld_ldgn59;
559 output ld_ldgn60;
560 output ld_ldgn61;
561 output ld_ldgn62;
562 output ld_ldgn63;
563 output ld_ldgn64;
564 output ld_ldgn65;
565 output ld_ldgn66;
566 output ld_ldgn67;
567 output ld_ldgn68;
568
569 input [5:0] debug_select ;
570 output ld_debug_select ;
571
572 input [31:0] TrainingVector ;
573 output ld_TrainingVector ;
574
575 output ld_arb_dout ;
576 output ld_arb_din ;
577 output ld_arb_ctrl ;
578 output ld_arb_debug_vector ;
579 output ld_smx_meta_intr_hld ;
580 input [31:0] arb_ctrl ;
581 input [31:0] arb_debug_vector ;
582 input [31:0] arb_dout ;
583 input [31:0] arb_din_int ;
584 input smx_meta_intr_hld ;
585
586`ifdef NEPTUNE
587 output ld_gpio_dout ;
588 output ld_gpio_en ;
589 output ld_gpio_din ;
590 input [15:0] gpio_dout ;
591 input [15:0] gpio_en ;
592 input [15:0] gpio_din_int ;
593`else
594 input [31:0] smx_config_data ;
595 input [31:0] smx_intr_status ;
596 input [31:0] smx_ctrl ;
597 input [31:0] smx_debug_vector ;
598 input smx_intr_clr ;
599 output ld_smx_config_data ;
600 output ld_smx_ctrl ;
601 output ld_smx_debug_vector ;
602 output ld_smx_intr_clr ;
603 output ld_smx_intr_status ;
604`endif
605
606// common reg declaration
607 reg [63:0] rd_data;
608 reg non_qualified_addr_err;
609// common wrie declaration
610 wire [63:0] fzc_slv_rdata;
611 wire rd_en;
612 wire wr_en;
613 wire rasr;
614// output reg declaration
615 reg ld_config1;
616 reg ld_sys_err_mask;
617 reg ld_sys_err_stat;
618 reg ld_rst_ctl;
619 reg ld_rtimer;
620 reg ld_dma_bind0 ;
621 reg ld_dma_bind1 ;
622 reg ld_dma_bind2 ;
623 reg ld_dma_bind3 ;
624 reg ld_dma_bind4 ;
625 reg ld_dma_bind5 ;
626 reg ld_dma_bind6 ;
627 reg ld_dma_bind7 ;
628 reg ld_dma_bind8 ;
629 reg ld_dma_bind9 ;
630 reg ld_dma_bind10;
631 reg ld_dma_bind11;
632 reg ld_dma_bind12;
633 reg ld_dma_bind13;
634 reg ld_dma_bind14;
635 reg ld_dma_bind15;
636 reg ld_dma_bind16;
637 reg ld_dma_bind17;
638 reg ld_dma_bind18;
639 reg ld_dma_bind19;
640 reg ld_dma_bind20;
641 reg ld_dma_bind21;
642 reg ld_dma_bind22;
643 reg ld_dma_bind23;
644 reg ld_dma_bind24;
645 reg ld_dma_bind25;
646 reg ld_dma_bind26;
647 reg ld_dma_bind27;
648 reg ld_dma_bind28;
649 reg ld_dma_bind29;
650 reg ld_dma_bind30;
651 reg ld_dma_bind31;
652 reg ld_dma_bind32;
653 reg ld_dma_bind33;
654 reg ld_dma_bind34;
655 reg ld_dma_bind35;
656 reg ld_dma_bind36;
657 reg ld_dma_bind37;
658 reg ld_dma_bind38;
659 reg ld_dma_bind39;
660 reg ld_dma_bind40;
661 reg ld_dma_bind41;
662 reg ld_dma_bind42;
663 reg ld_dma_bind43;
664 reg ld_dma_bind44;
665 reg ld_dma_bind45;
666 reg ld_dma_bind46;
667 reg ld_dma_bind47;
668 reg ld_dma_bind48;
669 reg ld_dma_bind49;
670 reg ld_dma_bind50;
671 reg ld_dma_bind51;
672 reg ld_dma_bind52;
673 reg ld_dma_bind53;
674 reg ld_dma_bind54;
675 reg ld_dma_bind55;
676 reg ld_dma_bind56;
677 reg ld_dma_bind57;
678 reg ld_dma_bind58;
679 reg ld_dma_bind59;
680 reg ld_dma_bind60;
681 reg ld_dma_bind61;
682 reg ld_dma_bind62;
683 reg ld_dma_bind63;
684
685 reg ld_sid0 ;
686 reg ld_sid1 ;
687 reg ld_sid2 ;
688 reg ld_sid3 ;
689 reg ld_sid4 ;
690 reg ld_sid5 ;
691 reg ld_sid6 ;
692 reg ld_sid7 ;
693 reg ld_sid8 ;
694 reg ld_sid9 ;
695 reg ld_sid10;
696 reg ld_sid11;
697 reg ld_sid12;
698 reg ld_sid13;
699 reg ld_sid14;
700 reg ld_sid15;
701 reg ld_sid16;
702 reg ld_sid17;
703 reg ld_sid18;
704 reg ld_sid19;
705 reg ld_sid20;
706 reg ld_sid21;
707 reg ld_sid22;
708 reg ld_sid23;
709 reg ld_sid24;
710 reg ld_sid25;
711 reg ld_sid26;
712 reg ld_sid27;
713 reg ld_sid28;
714 reg ld_sid29;
715 reg ld_sid30;
716 reg ld_sid31;
717 reg ld_sid32;
718 reg ld_sid33;
719 reg ld_sid34;
720 reg ld_sid35;
721 reg ld_sid36;
722 reg ld_sid37;
723 reg ld_sid38;
724 reg ld_sid39;
725 reg ld_sid40;
726 reg ld_sid41;
727 reg ld_sid42;
728 reg ld_sid43;
729 reg ld_sid44;
730 reg ld_sid45;
731 reg ld_sid46;
732 reg ld_sid47;
733 reg ld_sid48;
734 reg ld_sid49;
735 reg ld_sid50;
736 reg ld_sid51;
737 reg ld_sid52;
738 reg ld_sid53;
739 reg ld_sid54;
740 reg ld_sid55;
741 reg ld_sid56;
742 reg ld_sid57;
743 reg ld_sid58;
744 reg ld_sid59;
745 reg ld_sid60;
746 reg ld_sid61;
747 reg ld_sid62;
748 reg ld_sid63;
749
750 reg ld_ldgn0 ;
751 reg ld_ldgn1 ;
752 reg ld_ldgn2 ;
753 reg ld_ldgn3 ;
754 reg ld_ldgn4 ;
755 reg ld_ldgn5 ;
756 reg ld_ldgn6 ;
757 reg ld_ldgn7 ;
758 reg ld_ldgn8 ;
759 reg ld_ldgn9 ;
760 reg ld_ldgn10;
761 reg ld_ldgn11;
762 reg ld_ldgn12;
763 reg ld_ldgn13;
764 reg ld_ldgn14;
765 reg ld_ldgn15;
766 reg ld_ldgn16;
767 reg ld_ldgn17;
768 reg ld_ldgn18;
769 reg ld_ldgn19;
770 reg ld_ldgn20;
771 reg ld_ldgn21;
772 reg ld_ldgn22;
773 reg ld_ldgn23;
774 reg ld_ldgn24;
775 reg ld_ldgn25;
776 reg ld_ldgn26;
777 reg ld_ldgn27;
778 reg ld_ldgn28;
779 reg ld_ldgn29;
780 reg ld_ldgn30;
781 reg ld_ldgn31;
782 reg ld_ldgn32;
783 reg ld_ldgn33;
784 reg ld_ldgn34;
785 reg ld_ldgn35;
786 reg ld_ldgn36;
787 reg ld_ldgn37;
788 reg ld_ldgn38;
789 reg ld_ldgn39;
790 reg ld_ldgn40;
791 reg ld_ldgn41;
792 reg ld_ldgn42;
793 reg ld_ldgn43;
794 reg ld_ldgn44;
795 reg ld_ldgn45;
796 reg ld_ldgn46;
797 reg ld_ldgn47;
798 reg ld_ldgn48;
799 reg ld_ldgn49;
800 reg ld_ldgn50;
801 reg ld_ldgn51;
802 reg ld_ldgn52;
803 reg ld_ldgn53;
804 reg ld_ldgn54;
805 reg ld_ldgn55;
806 reg ld_ldgn56;
807 reg ld_ldgn57;
808 reg ld_ldgn58;
809 reg ld_ldgn59;
810 reg ld_ldgn60;
811 reg ld_ldgn61;
812 reg ld_ldgn62;
813 reg ld_ldgn63;
814 reg ld_ldgn64;
815 reg ld_ldgn65;
816 reg ld_ldgn66;
817 reg ld_ldgn67;
818 reg ld_ldgn68;
819 reg ld_debug_select;
820 reg ld_TrainingVector;
821 reg ld_arb_dout;
822 reg ld_arb_din;
823 reg ld_arb_ctrl;
824 reg ld_arb_debug_vector;
825 reg ld_smx_meta_intr_hld;
826
827`ifdef NEPTUNE
828 reg ld_gpio_dout;
829 reg ld_gpio_din;
830 reg ld_gpio_en;
831`else
832 reg ld_smx_config_data;
833 reg ld_smx_ctrl;
834 reg ld_smx_debug_vector;
835 reg ld_smx_intr_clr;
836 reg ld_smx_intr_status;
837`endif
838
839`ifdef NEPTUNE
840/* ---------------------------------------------------------- */
841 reg fzc_slv_sel_reg_int;
842 reg rd_int;
843 reg [18:0] addr_int;
844
845always @(posedge niu_clk)
846 if (reset)
847 begin
848 fzc_slv_sel_reg_int <= 1'b0;
849 rd_int <= 1'b0;
850 addr_int <= 19'b0;
851 end
852 else
853 begin
854 fzc_slv_sel_reg_int <= fzc_slv_sel_reg ;
855 rd_int <= rd ;
856 addr_int <= addr;
857 end
858
859`else
860/* ---------------------------------------------------------- */
861
862 wire fzc_slv_sel_reg_int;
863 wire rd_int;
864 wire [18:0] addr_int;
865
866 assign fzc_slv_sel_reg_int = fzc_slv_sel_reg ;
867 assign rd_int = rd ;
868 assign addr_int = addr ;
869/* ----------------------------------------------------------- */
870`endif
871
872
873niu_rw_ctl fzc_slv_rw_ctl(
874 // Outputs
875 .wr_en (wr_en),
876 .rd_en (rd_en),
877 .ack (fzc_slv_ack),
878 .rdata (fzc_slv_rdata[63:0]),
879 .err (fzc_slv_err),
880 .rasr (rasr),
881 // Inputs
882 .clk (niu_clk),
883 .sel (fzc_slv_sel_reg_int),
884 .rd (rd_int),
885 .rd_data (rd_data[63:0]),
886 .non_qualified_addr_err(non_qualified_addr_err));
887
888always @ (/*AUTOSENSE*/addr_int or config1
889 or rst_ctl or sys_err_stat or sys_err_mask
890 or dma_bind0 or dma_bind1
891 or dma_bind10 or dma_bind11 or dma_bind12 or dma_bind13
892 or dma_bind14 or dma_bind15 or dma_bind16 or dma_bind17
893 or dma_bind18 or dma_bind19 or dma_bind2 or dma_bind20
894 or dma_bind21 or dma_bind22 or dma_bind23 or dma_bind24
895 or dma_bind25 or dma_bind26 or dma_bind27 or dma_bind28
896 or dma_bind29 or dma_bind3 or dma_bind30 or dma_bind31
897 or dma_bind32 or dma_bind33 or dma_bind34 or dma_bind35
898 or dma_bind36 or dma_bind37 or dma_bind38 or dma_bind39
899 or dma_bind4 or dma_bind40 or dma_bind41 or dma_bind42
900 or dma_bind43 or dma_bind44 or dma_bind45 or dma_bind46
901 or dma_bind47 or dma_bind48 or dma_bind49 or dma_bind5
902 or dma_bind50 or dma_bind51 or dma_bind52 or dma_bind53
903 or dma_bind54 or dma_bind55 or dma_bind56 or dma_bind57
904 or dma_bind58 or dma_bind59 or dma_bind6 or dma_bind60
905 or dma_bind61 or dma_bind62 or dma_bind63 or dma_bind7
906 or dma_bind8 or dma_bind9 or ldgn0 or ldgn1 or ldgn10
907 or ldgn11 or ldgn12 or ldgn13 or ldgn14 or ldgn15 or ldgn16
908 or ldgn17 or ldgn18 or ldgn19 or ldgn2 or ldgn20 or ldgn21
909 or ldgn22 or ldgn23 or ldgn24 or ldgn25 or ldgn26 or ldgn27
910 or ldgn28 or ldgn29 or ldgn3 or ldgn30 or ldgn31 or ldgn32
911 or ldgn33 or ldgn34 or ldgn35 or ldgn36 or ldgn37 or ldgn38
912 or ldgn39 or ldgn4 or ldgn40 or ldgn41 or ldgn42 or ldgn43
913 or ldgn44 or ldgn45 or ldgn46 or ldgn47 or ldgn48 or ldgn49
914 or ldgn5 or ldgn50 or ldgn51 or ldgn52 or ldgn53 or ldgn54
915 or ldgn55 or ldgn56 or ldgn57 or ldgn58 or ldgn59 or ldgn6
916 or ldgn60 or ldgn61 or ldgn62 or ldgn63 or ldgn64 or ldgn65
917 or ldgn66 or ldgn67 or ldgn68 or ldgn7 or ldgn8 or ldgn9
918 or rtimer or sid0 or sid1 or sid10 or sid11 or sid12
919 or sid13 or sid14 or sid15 or sid16 or sid17 or sid18
920 or sid19 or sid2 or sid20 or sid21 or sid22 or sid23
921 or sid24 or sid25 or sid26 or sid27 or sid28 or sid29
922 or sid3 or sid30 or sid31 or sid32 or sid33 or sid34
923 or sid35 or sid36 or sid37 or sid38 or sid39 or sid4
924 or sid40 or sid41 or sid42 or sid43 or sid44 or sid45
925 or sid46 or sid47 or sid48 or sid49 or sid5 or sid50
926 or sid51 or sid52 or sid53 or sid54 or sid55 or sid56
927 or sid57 or sid58 or sid59 or sid6 or sid60 or sid61
928 or sid62 or sid63 or sid7 or sid8 or sid9 or wr_en
929 or debug_select[5:0] or TrainingVector[31:0]
930 or arb_ctrl[31:0] or arb_debug_vector[31:0]
931 or arb_dout[31:0] or arb_din_int[31:0]
932 or smx_meta_intr_hld or rd_int
933`ifdef NEPTUNE
934 or gpio_dout[15:0] or gpio_en[15:0] or gpio_din_int[15:0]
935`else
936 or smx_intr_clr or smx_config_data or smx_intr_status or smx_ctrl or
937 smx_debug_vector
938`endif
939 )
940 begin
941 non_qualified_addr_err = 0;
942 rd_data = 64'hdead_beef_dead_beef;
943 ld_config1 = 0;
944 ld_sys_err_mask = 0;
945 ld_sys_err_stat = 0;
946 ld_rst_ctl = 0;
947 ld_rtimer = 0;
948 ld_dma_bind0 = 0;
949 ld_dma_bind1 = 0;
950 ld_dma_bind2 = 0;
951 ld_dma_bind3 = 0;
952 ld_dma_bind4 = 0;
953 ld_dma_bind5 = 0;
954 ld_dma_bind6 = 0;
955 ld_dma_bind7 = 0;
956 ld_dma_bind8 = 0;
957 ld_dma_bind9 = 0;
958 ld_dma_bind10 = 0;
959 ld_dma_bind11 = 0;
960 ld_dma_bind12 = 0;
961 ld_dma_bind13 = 0;
962 ld_dma_bind14 = 0;
963 ld_dma_bind15 = 0;
964 ld_dma_bind16 = 0;
965 ld_dma_bind17 = 0;
966 ld_dma_bind18 = 0;
967 ld_dma_bind19 = 0;
968 ld_dma_bind20 = 0;
969 ld_dma_bind21 = 0;
970 ld_dma_bind22 = 0;
971 ld_dma_bind23 = 0;
972 ld_dma_bind24 = 0;
973 ld_dma_bind25 = 0;
974 ld_dma_bind26 = 0;
975 ld_dma_bind27 = 0;
976 ld_dma_bind28 = 0;
977 ld_dma_bind29 = 0;
978 ld_dma_bind30 = 0;
979 ld_dma_bind31 = 0;
980 ld_dma_bind32 = 0;
981 ld_dma_bind33 = 0;
982 ld_dma_bind34 = 0;
983 ld_dma_bind35 = 0;
984 ld_dma_bind36 = 0;
985 ld_dma_bind37 = 0;
986 ld_dma_bind38 = 0;
987 ld_dma_bind39 = 0;
988 ld_dma_bind40 = 0;
989 ld_dma_bind41 = 0;
990 ld_dma_bind42 = 0;
991 ld_dma_bind43 = 0;
992 ld_dma_bind44 = 0;
993 ld_dma_bind45 = 0;
994 ld_dma_bind46 = 0;
995 ld_dma_bind47 = 0;
996 ld_dma_bind48 = 0;
997 ld_dma_bind49 = 0;
998 ld_dma_bind50 = 0;
999 ld_dma_bind51 = 0;
1000 ld_dma_bind52 = 0;
1001 ld_dma_bind53 = 0;
1002 ld_dma_bind54 = 0;
1003 ld_dma_bind55 = 0;
1004 ld_dma_bind56 = 0;
1005 ld_dma_bind57 = 0;
1006 ld_dma_bind58 = 0;
1007 ld_dma_bind59 = 0;
1008 ld_dma_bind60 = 0;
1009 ld_dma_bind61 = 0;
1010 ld_dma_bind62 = 0;
1011 ld_dma_bind63 = 0;
1012
1013 ld_sid0 = 0;
1014 ld_sid1 = 0;
1015 ld_sid2 = 0;
1016 ld_sid3 = 0;
1017 ld_sid4 = 0;
1018 ld_sid5 = 0;
1019 ld_sid6 = 0;
1020 ld_sid7 = 0;
1021 ld_sid8 = 0;
1022 ld_sid9 = 0;
1023 ld_sid10 = 0;
1024 ld_sid11 = 0;
1025 ld_sid12 = 0;
1026 ld_sid13 = 0;
1027 ld_sid14 = 0;
1028 ld_sid15 = 0;
1029 ld_sid16 = 0;
1030 ld_sid17 = 0;
1031 ld_sid18 = 0;
1032 ld_sid19 = 0;
1033 ld_sid20 = 0;
1034 ld_sid21 = 0;
1035 ld_sid22 = 0;
1036 ld_sid23 = 0;
1037 ld_sid24 = 0;
1038 ld_sid25 = 0;
1039 ld_sid26 = 0;
1040 ld_sid27 = 0;
1041 ld_sid28 = 0;
1042 ld_sid29 = 0;
1043 ld_sid30 = 0;
1044 ld_sid31 = 0;
1045 ld_sid32 = 0;
1046 ld_sid33 = 0;
1047 ld_sid34 = 0;
1048 ld_sid35 = 0;
1049 ld_sid36 = 0;
1050 ld_sid37 = 0;
1051 ld_sid38 = 0;
1052 ld_sid39 = 0;
1053 ld_sid40 = 0;
1054 ld_sid41 = 0;
1055 ld_sid42 = 0;
1056 ld_sid43 = 0;
1057 ld_sid44 = 0;
1058 ld_sid45 = 0;
1059 ld_sid46 = 0;
1060 ld_sid47 = 0;
1061 ld_sid48 = 0;
1062 ld_sid49 = 0;
1063 ld_sid50 = 0;
1064 ld_sid51 = 0;
1065 ld_sid52 = 0;
1066 ld_sid53 = 0;
1067 ld_sid54 = 0;
1068 ld_sid55 = 0;
1069 ld_sid56 = 0;
1070 ld_sid57 = 0;
1071 ld_sid58 = 0;
1072 ld_sid59 = 0;
1073 ld_sid60 = 0;
1074 ld_sid61 = 0;
1075 ld_sid62 = 0;
1076 ld_sid63 = 0;
1077
1078 ld_ldgn0 = 0;
1079 ld_ldgn1 = 0;
1080 ld_ldgn2 = 0;
1081 ld_ldgn3 = 0;
1082 ld_ldgn4 = 0;
1083 ld_ldgn5 = 0;
1084 ld_ldgn6 = 0;
1085 ld_ldgn7 = 0;
1086 ld_ldgn8 = 0;
1087 ld_ldgn9 = 0;
1088 ld_ldgn10 = 0;
1089 ld_ldgn11 = 0;
1090 ld_ldgn12 = 0;
1091 ld_ldgn13 = 0;
1092 ld_ldgn14 = 0;
1093 ld_ldgn15 = 0;
1094 ld_ldgn16 = 0;
1095 ld_ldgn17 = 0;
1096 ld_ldgn18 = 0;
1097 ld_ldgn19 = 0;
1098 ld_ldgn20 = 0;
1099 ld_ldgn21 = 0;
1100 ld_ldgn22 = 0;
1101 ld_ldgn23 = 0;
1102 ld_ldgn24 = 0;
1103 ld_ldgn25 = 0;
1104 ld_ldgn26 = 0;
1105 ld_ldgn27 = 0;
1106 ld_ldgn28 = 0;
1107 ld_ldgn29 = 0;
1108 ld_ldgn30 = 0;
1109 ld_ldgn31 = 0;
1110 ld_ldgn32 = 0;
1111 ld_ldgn33 = 0;
1112 ld_ldgn34 = 0;
1113 ld_ldgn35 = 0;
1114 ld_ldgn36 = 0;
1115 ld_ldgn37 = 0;
1116 ld_ldgn38 = 0;
1117 ld_ldgn39 = 0;
1118 ld_ldgn40 = 0;
1119 ld_ldgn41 = 0;
1120 ld_ldgn42 = 0;
1121 ld_ldgn43 = 0;
1122 ld_ldgn44 = 0;
1123 ld_ldgn45 = 0;
1124 ld_ldgn46 = 0;
1125 ld_ldgn47 = 0;
1126 ld_ldgn48 = 0;
1127 ld_ldgn49 = 0;
1128 ld_ldgn50 = 0;
1129 ld_ldgn51 = 0;
1130 ld_ldgn52 = 0;
1131 ld_ldgn53 = 0;
1132 ld_ldgn54 = 0;
1133 ld_ldgn55 = 0;
1134 ld_ldgn56 = 0;
1135 ld_ldgn57 = 0;
1136 ld_ldgn58 = 0;
1137 ld_ldgn59 = 0;
1138 ld_ldgn60 = 0;
1139 ld_ldgn61 = 0;
1140 ld_ldgn62 = 0;
1141 ld_ldgn63 = 0;
1142 ld_ldgn64 = 0;
1143 ld_ldgn65 = 0;
1144 ld_ldgn66 = 0;
1145 ld_ldgn67 = 0;
1146 ld_ldgn68 = 0;
1147 ld_arb_dout = 0;
1148 ld_arb_din = 0;
1149 ld_smx_meta_intr_hld = 0;
1150
1151`ifdef NEPTUNE
1152 ld_gpio_dout = 0;
1153 ld_gpio_en = 0;
1154 ld_gpio_din = 0;
1155`else
1156 ld_smx_config_data = 0;
1157 ld_smx_ctrl = 0;
1158 ld_smx_debug_vector= 0;
1159 ld_smx_intr_clr = 0;
1160 ld_smx_intr_status = 0;
1161`endif
1162 ld_debug_select = 0;
1163 ld_TrainingVector = 0;
1164 ld_arb_ctrl = 0;
1165 ld_arb_debug_vector= 0;
1166
1167
1168 // case({addr_int[18:3],3'b0}) //synopsys parallel_case full_case
1169 case({addr_int[18:3],3'b0}) //synopsys parallel_case full_case infer_mux
1170
1171 19'h0_0000: begin
1172 ld_config1 = wr_en;
1173 rd_data = {63'b0,config1};
1174 end
1175
1176 19'h0_0038: begin
1177 ld_rst_ctl = wr_en;
1178 rd_data = {41'b0,rst_ctl};
1179 end
1180
1181 19'h0_0090: begin
1182 ld_sys_err_mask = wr_en;
1183 rd_data = {53'b0,sys_err_mask[10:0]};
1184 end
1185
1186 19'h0_0098: begin
1187 ld_sys_err_stat = rd_int;
1188 rd_data = {53'b0,sys_err_stat[10:0]};
1189 end
1190 // resolution timer
1191 19'h0_0008: begin
1192 ld_rtimer = wr_en;
1193 rd_data = {44'b0,rtimer};
1194 end
1195// *****************************************************************
1196
1197 // Meta Arb Data Out Register
1198 19'h0_0010: begin
1199 ld_arb_dout = wr_en;
1200 rd_data = {32'b0,arb_dout[31:0]};
1201 end
1202
1203 // Meta Arb Data In Register
1204 19'h0_0018: begin
1205 ld_arb_din = 1'b1;
1206 rd_data = {32'b0,arb_din_int[31:0]};
1207 end
1208
1209`ifdef NEPTUNE
1210// *****************************************************************
1211 // GPIO Data Out Register
1212 19'h0_0020: begin
1213 ld_gpio_dout = wr_en;
1214 rd_data = {48'b0,gpio_dout[15:0]};
1215 end
1216
1217 // GPIO Enable Register
1218 19'h0_0028: begin
1219 ld_gpio_en = wr_en;
1220 rd_data = {48'b0,gpio_en[15:0]};
1221 end
1222
1223 // GPIO Data In Register
1224 19'h0_0030: begin
1225 ld_gpio_din = 1'b1;
1226 rd_data = {48'b0,gpio_din_int[15:0]};
1227 end
1228
1229`else
1230// *****************************************************************
1231 // SMx Register
1232 19'h0_0040: begin
1233 ld_smx_config_data = wr_en;
1234 rd_data = {32'b0,smx_config_data};
1235 end
1236
1237 19'h0_0048: begin
1238 ld_smx_intr_status = rd_int ;
1239 rd_data = {32'b0,smx_intr_status};
1240 end
1241
1242 19'h0_0050: begin
1243 ld_smx_ctrl = wr_en ;
1244 rd_data = {32'b0,smx_ctrl};
1245 end
1246
1247 19'h0_0058: begin
1248 ld_smx_debug_vector= wr_en ;
1249 rd_data = {32'b0,smx_debug_vector};
1250 end
1251
1252 19'h0_00a0: begin
1253 ld_smx_intr_clr = wr_en;
1254 rd_data = {63'b0, smx_intr_clr};
1255 end
1256
1257`endif
1258
1259// *****************************************************************
1260
1261 19'h0_0060: begin
1262 ld_debug_select = wr_en;
1263 rd_data = {58'b0,debug_select[5:0]};
1264 end
1265
1266 19'h0_0068: begin
1267 ld_TrainingVector = wr_en;
1268 rd_data = {32'b0,TrainingVector[31:0]};
1269 end
1270
1271 19'h0_0070: begin
1272 ld_arb_ctrl = wr_en;
1273 rd_data = {32'b0,arb_ctrl[31:0]};
1274 end
1275
1276 19'h0_0078: begin
1277 ld_arb_debug_vector = wr_en;
1278 rd_data = {32'b0,arb_debug_vector[31:0]};
1279 end
1280// *****************************************************************
1281
1282 19'h0_00a8: begin
1283 ld_smx_meta_intr_hld = wr_en;
1284 rd_data = {32'b0,31'b0,smx_meta_intr_hld};
1285 end
1286
1287// *****************************************************************
1288// 19'h0_0010: begin
1289// end
1290// *****************************************************************
1291
1292 // DMA binding registers
1293 19'h1_0000: begin
1294 ld_dma_bind0 = wr_en;
1295 rd_data = {50'b0,dma_bind0};
1296 end
1297 19'h1_0008: begin
1298 ld_dma_bind1 = wr_en;
1299 rd_data = {50'b0,dma_bind1};
1300 end
1301 19'h1_0010: begin
1302 ld_dma_bind2 = wr_en;
1303 rd_data = {50'b0,dma_bind2};
1304 end
1305 19'h1_0018: begin
1306 ld_dma_bind3 = wr_en;
1307 rd_data = {50'b0,dma_bind3};
1308 end
1309 19'h1_0020: begin
1310 ld_dma_bind4 = wr_en;
1311 rd_data = {50'b0,dma_bind4};
1312 end
1313 19'h1_0028: begin
1314 ld_dma_bind5 = wr_en;
1315 rd_data = {50'b0,dma_bind5};
1316 end
1317 19'h1_0030: begin
1318 ld_dma_bind6 = wr_en;
1319 rd_data = {50'b0,dma_bind6};
1320 end
1321 19'h1_0038: begin
1322 ld_dma_bind7 = wr_en;
1323 rd_data = {50'b0,dma_bind7};
1324 end
1325 19'h1_0040: begin
1326 ld_dma_bind8 = wr_en;
1327 rd_data = {50'b0,dma_bind8};
1328 end
1329 19'h1_0048: begin
1330 ld_dma_bind9 = wr_en;
1331 rd_data = {50'b0,dma_bind9};
1332 end
1333 19'h1_0050: begin
1334 ld_dma_bind10 = wr_en;
1335 rd_data = {50'b0,dma_bind10};
1336 end
1337 19'h1_0058: begin
1338 ld_dma_bind11 = wr_en;
1339 rd_data = {50'b0,dma_bind11};
1340 end
1341 19'h1_0060: begin
1342 ld_dma_bind12 = wr_en;
1343 rd_data = {50'b0,dma_bind12};
1344 end
1345 19'h1_0068: begin
1346 ld_dma_bind13 = wr_en;
1347 rd_data = {50'b0,dma_bind13};
1348 end
1349 19'h1_0070: begin
1350 ld_dma_bind14 = wr_en;
1351 rd_data = {50'b0,dma_bind14};
1352 end
1353 19'h1_0078: begin
1354 ld_dma_bind15 = wr_en;
1355 rd_data = {50'b0,dma_bind15};
1356 end
1357 19'h1_0080: begin
1358 ld_dma_bind16 = wr_en;
1359 rd_data = {50'b0,dma_bind16};
1360 end
1361 19'h1_0088: begin
1362 ld_dma_bind17 = wr_en;
1363 rd_data = {50'b0,dma_bind17};
1364 end
1365 19'h1_0090: begin
1366 ld_dma_bind18 = wr_en;
1367 rd_data = {50'b0,dma_bind18};
1368 end
1369 19'h1_0098: begin
1370 ld_dma_bind19 = wr_en;
1371 rd_data = {50'b0,dma_bind19};
1372 end
1373 19'h1_00A0: begin
1374 ld_dma_bind20 = wr_en;
1375 rd_data = {50'b0,dma_bind20};
1376 end
1377 19'h1_00A8: begin
1378 ld_dma_bind21 = wr_en;
1379 rd_data = {50'b0,dma_bind21};
1380 end
1381 19'h1_00B0: begin
1382 ld_dma_bind22 = wr_en;
1383 rd_data = {50'b0,dma_bind22};
1384 end
1385 19'h1_00B8: begin
1386 ld_dma_bind23 = wr_en;
1387 rd_data = {50'b0,dma_bind23};
1388 end
1389 19'h1_00C0: begin
1390 ld_dma_bind24 = wr_en;
1391 rd_data = {50'b0,dma_bind24};
1392 end
1393 19'h1_00C8: begin
1394 ld_dma_bind25 = wr_en;
1395 rd_data = {50'b0,dma_bind25};
1396 end
1397 19'h1_00D0: begin
1398 ld_dma_bind26 = wr_en;
1399 rd_data = {50'b0,dma_bind26};
1400 end
1401 19'h1_00D8: begin
1402 ld_dma_bind27 = wr_en;
1403 rd_data = {50'b0,dma_bind27};
1404 end
1405 19'h1_00E0: begin
1406 ld_dma_bind28 = wr_en;
1407 rd_data = {50'b0,dma_bind28};
1408 end
1409 19'h1_00E8: begin
1410 ld_dma_bind29 = wr_en;
1411 rd_data = {50'b0,dma_bind29};
1412 end
1413 19'h1_00F0: begin
1414 ld_dma_bind30 = wr_en;
1415 rd_data = {50'b0,dma_bind30};
1416 end
1417 19'h1_00F8: begin
1418 ld_dma_bind31 = wr_en;
1419 rd_data = {50'b0,dma_bind31};
1420 end
1421 19'h1_0100: begin
1422 ld_dma_bind32 = wr_en;
1423 rd_data = {50'b0,dma_bind32};
1424 end
1425 19'h1_0108: begin
1426 ld_dma_bind33 = wr_en;
1427 rd_data = {50'b0,dma_bind33};
1428 end
1429 19'h1_0110: begin
1430 ld_dma_bind34 = wr_en;
1431 rd_data = {50'b0,dma_bind34};
1432 end
1433 19'h1_0118: begin
1434 ld_dma_bind35 = wr_en;
1435 rd_data = {50'b0,dma_bind35};
1436 end
1437 19'h1_0120: begin
1438 ld_dma_bind36 = wr_en;
1439 rd_data = {50'b0,dma_bind36};
1440 end
1441 19'h1_0128: begin
1442 ld_dma_bind37 = wr_en;
1443 rd_data = {50'b0,dma_bind37};
1444 end
1445 19'h1_0130: begin
1446 ld_dma_bind38 = wr_en;
1447 rd_data = {50'b0,dma_bind38};
1448 end
1449 19'h1_0138: begin
1450 ld_dma_bind39 = wr_en;
1451 rd_data = {50'b0,dma_bind39};
1452 end
1453 19'h1_0140: begin
1454 ld_dma_bind40 = wr_en;
1455 rd_data = {50'b0,dma_bind40};
1456 end
1457 19'h1_0148: begin
1458 ld_dma_bind41 = wr_en;
1459 rd_data = {50'b0,dma_bind41};
1460 end
1461 19'h1_0150: begin
1462 ld_dma_bind42 = wr_en;
1463 rd_data = {50'b0,dma_bind42};
1464 end
1465 19'h1_0158: begin
1466 ld_dma_bind43 = wr_en;
1467 rd_data = {50'b0,dma_bind43};
1468 end
1469 19'h1_0160: begin
1470 ld_dma_bind44 = wr_en;
1471 rd_data = {50'b0,dma_bind44};
1472 end
1473 19'h1_0168: begin
1474 ld_dma_bind45 = wr_en;
1475 rd_data = {50'b0,dma_bind45};
1476 end
1477 19'h1_0170: begin
1478 ld_dma_bind46 = wr_en;
1479 rd_data = {50'b0,dma_bind46};
1480 end
1481 19'h1_0178: begin
1482 ld_dma_bind47 = wr_en;
1483 rd_data = {50'b0,dma_bind47};
1484 end
1485 19'h1_0180: begin
1486 ld_dma_bind48 = wr_en;
1487 rd_data = {50'b0,dma_bind48};
1488 end
1489 19'h1_0188: begin
1490 ld_dma_bind49 = wr_en;
1491 rd_data = {50'b0,dma_bind49};
1492 end
1493 19'h1_0190: begin
1494 ld_dma_bind50 = wr_en;
1495 rd_data = {50'b0,dma_bind50};
1496 end
1497 19'h1_0198: begin
1498 ld_dma_bind51 = wr_en;
1499 rd_data = {50'b0,dma_bind51};
1500 end
1501 19'h1_01A0: begin
1502 ld_dma_bind52 = wr_en;
1503 rd_data = {50'b0,dma_bind52};
1504 end
1505 19'h1_01A8: begin
1506 ld_dma_bind53 = wr_en;
1507 rd_data = {50'b0,dma_bind53};
1508 end
1509 19'h1_01B0: begin
1510 ld_dma_bind54 = wr_en;
1511 rd_data = {50'b0,dma_bind54};
1512 end
1513 19'h1_01B8: begin
1514 ld_dma_bind55 = wr_en;
1515 rd_data = {50'b0,dma_bind55};
1516 end
1517 19'h1_01C0: begin
1518 ld_dma_bind56 = wr_en;
1519 rd_data = {50'b0,dma_bind56};
1520 end
1521 19'h1_01C8: begin
1522 ld_dma_bind57 = wr_en;
1523 rd_data = {50'b0,dma_bind57};
1524 end
1525 19'h1_01D0: begin
1526 ld_dma_bind58 = wr_en;
1527 rd_data = {50'b0,dma_bind58};
1528 end
1529 19'h1_01D8: begin
1530 ld_dma_bind59 = wr_en;
1531 rd_data = {50'b0,dma_bind59};
1532 end
1533 19'h1_01E0: begin
1534 ld_dma_bind60 = wr_en;
1535 rd_data = {50'b0,dma_bind60};
1536 end
1537 19'h1_01E8: begin
1538 ld_dma_bind61 = wr_en;
1539 rd_data = {50'b0,dma_bind61};
1540 end
1541 19'h1_01F0: begin
1542 ld_dma_bind62 = wr_en;
1543 rd_data = {50'b0,dma_bind62};
1544 end
1545 19'h1_01F8: begin
1546 ld_dma_bind63 = wr_en;
1547 rd_data = {50'b0,dma_bind63};
1548 end
1549
1550 // System Interrupt Data (sid)
1551 19'h1_0200: begin
1552 ld_sid0 = wr_en;
1553 rd_data = {57'b0,sid0};
1554 end
1555 19'h1_0208: begin
1556 ld_sid1 = wr_en;
1557 rd_data = {57'b0,sid1};
1558 end
1559 19'h1_0210: begin
1560 ld_sid2 = wr_en;
1561 rd_data = {57'b0,sid2};
1562 end
1563 19'h1_0218: begin
1564 ld_sid3 = wr_en;
1565 rd_data = {57'b0,sid3};
1566 end
1567 19'h1_0220: begin
1568 ld_sid4 = wr_en;
1569 rd_data = {57'b0,sid4};
1570 end
1571 19'h1_0228: begin
1572 ld_sid5 = wr_en;
1573 rd_data = {57'b0,sid5};
1574 end
1575 19'h1_0230: begin
1576 ld_sid6 = wr_en;
1577 rd_data = {57'b0,sid6};
1578 end
1579 19'h1_0238: begin
1580 ld_sid7 = wr_en;
1581 rd_data = {57'b0,sid7};
1582 end
1583 19'h1_0240: begin
1584 ld_sid8 = wr_en;
1585 rd_data = {57'b0,sid8};
1586 end
1587 19'h1_0248: begin
1588 ld_sid9 = wr_en;
1589 rd_data = {57'b0,sid9};
1590 end
1591 19'h1_0250: begin
1592 ld_sid10 = wr_en;
1593 rd_data = {57'b0,sid10};
1594 end
1595 19'h1_0258: begin
1596 ld_sid11 = wr_en;
1597 rd_data = {57'b0,sid11};
1598 end
1599 19'h1_0260: begin
1600 ld_sid12 = wr_en;
1601 rd_data = {57'b0,sid12};
1602 end
1603 19'h1_0268: begin
1604 ld_sid13 = wr_en;
1605 rd_data = {57'b0,sid13};
1606 end
1607 19'h1_0270: begin
1608 ld_sid14 = wr_en;
1609 rd_data = {57'b0,sid14};
1610 end
1611 19'h1_0278: begin
1612 ld_sid15 = wr_en;
1613 rd_data = {57'b0,sid15};
1614 end
1615 19'h1_0280: begin
1616 ld_sid16 = wr_en;
1617 rd_data = {57'b0,sid16};
1618 end
1619 19'h1_0288: begin
1620 ld_sid17 = wr_en;
1621 rd_data = {57'b0,sid17};
1622 end
1623 19'h1_0290: begin
1624 ld_sid18 = wr_en;
1625 rd_data = {57'b0,sid18};
1626 end
1627 19'h1_0298: begin
1628 ld_sid19 = wr_en;
1629 rd_data = {57'b0,sid19};
1630 end
1631 19'h1_02A0: begin
1632 ld_sid20 = wr_en;
1633 rd_data = {57'b0,sid20};
1634 end
1635 19'h1_02A8: begin
1636 ld_sid21 = wr_en;
1637 rd_data = {57'b0,sid21};
1638 end
1639 19'h1_02B0: begin
1640 ld_sid22 = wr_en;
1641 rd_data = {57'b0,sid22};
1642 end
1643 19'h1_02B8: begin
1644 ld_sid23 = wr_en;
1645 rd_data = {57'b0,sid23};
1646 end
1647 19'h1_02C0: begin
1648 ld_sid24 = wr_en;
1649 rd_data = {57'b0,sid24};
1650 end
1651 19'h1_02C8: begin
1652 ld_sid25 = wr_en;
1653 rd_data = {57'b0,sid25};
1654 end
1655 19'h1_02D0: begin
1656 ld_sid26 = wr_en;
1657 rd_data = {57'b0,sid26};
1658 end
1659 19'h1_02D8: begin
1660 ld_sid27 = wr_en;
1661 rd_data = {57'b0,sid27};
1662 end
1663 19'h1_02E0: begin
1664 ld_sid28 = wr_en;
1665 rd_data = {57'b0,sid28};
1666 end
1667 19'h1_02E8: begin
1668 ld_sid29 = wr_en;
1669 rd_data = {57'b0,sid29};
1670 end
1671 19'h1_02F0: begin
1672 ld_sid30 = wr_en;
1673 rd_data = {57'b0,sid30};
1674 end
1675 19'h1_02F8: begin
1676 ld_sid31 = wr_en;
1677 rd_data = {57'b0,sid31};
1678 end
1679 19'h1_0300: begin
1680 ld_sid32 = wr_en;
1681 rd_data = {57'b0,sid32};
1682 end
1683 19'h1_0308: begin
1684 ld_sid33 = wr_en;
1685 rd_data = {57'b0,sid33};
1686 end
1687 19'h1_0310: begin
1688 ld_sid34 = wr_en;
1689 rd_data = {57'b0,sid34};
1690 end
1691 19'h1_0318: begin
1692 ld_sid35 = wr_en;
1693 rd_data = {57'b0,sid35};
1694 end
1695 19'h1_0320: begin
1696 ld_sid36 = wr_en;
1697 rd_data = {57'b0,sid36};
1698 end
1699 19'h1_0328: begin
1700 ld_sid37 = wr_en;
1701 rd_data = {57'b0,sid37};
1702 end
1703 19'h1_0330: begin
1704 ld_sid38 = wr_en;
1705 rd_data = {57'b0,sid38};
1706 end
1707 19'h1_0338: begin
1708 ld_sid39 = wr_en;
1709 rd_data = {57'b0,sid39};
1710 end
1711 19'h1_0340: begin
1712 ld_sid40 = wr_en;
1713 rd_data = {57'b0,sid40};
1714 end
1715 19'h1_0348: begin
1716 ld_sid41 = wr_en;
1717 rd_data = {57'b0,sid41};
1718 end
1719 19'h1_0350: begin
1720 ld_sid42 = wr_en;
1721 rd_data = {57'b0,sid42};
1722 end
1723 19'h1_0358: begin
1724 ld_sid43 = wr_en;
1725 rd_data = {57'b0,sid43};
1726 end
1727 19'h1_0360: begin
1728 ld_sid44 = wr_en;
1729 rd_data = {57'b0,sid44};
1730 end
1731 19'h1_0368: begin
1732 ld_sid45 = wr_en;
1733 rd_data = {57'b0,sid45};
1734 end
1735 19'h1_0370: begin
1736 ld_sid46 = wr_en;
1737 rd_data = {57'b0,sid46};
1738 end
1739 19'h1_0378: begin
1740 ld_sid47 = wr_en;
1741 rd_data = {57'b0,sid47};
1742 end
1743 19'h1_0380: begin
1744 ld_sid48 = wr_en;
1745 rd_data = {57'b0,sid48};
1746 end
1747 19'h1_0388: begin
1748 ld_sid49 = wr_en;
1749 rd_data = {57'b0,sid49};
1750 end
1751 19'h1_0390: begin
1752 ld_sid50 = wr_en;
1753 rd_data = {57'b0,sid50};
1754 end
1755 19'h1_0398: begin
1756 ld_sid51 = wr_en;
1757 rd_data = {57'b0,sid51};
1758 end
1759 19'h1_03A0: begin
1760 ld_sid52 = wr_en;
1761 rd_data = {57'b0,sid52};
1762 end
1763 19'h1_03A8: begin
1764 ld_sid53 = wr_en;
1765 rd_data = {57'b0,sid53};
1766 end
1767 19'h1_03B0: begin
1768 ld_sid54 = wr_en;
1769 rd_data = {57'b0,sid54};
1770 end
1771 19'h1_03B8: begin
1772 ld_sid55 = wr_en;
1773 rd_data = {57'b0,sid55};
1774 end
1775 19'h1_03C0: begin
1776 ld_sid56 = wr_en;
1777 rd_data = {57'b0,sid56};
1778 end
1779 19'h1_03C8: begin
1780 ld_sid57 = wr_en;
1781 rd_data = {57'b0,sid57};
1782 end
1783 19'h1_03D0: begin
1784 ld_sid58 = wr_en;
1785 rd_data = {57'b0,sid58};
1786 end
1787 19'h1_03D8: begin
1788 ld_sid59 = wr_en;
1789 rd_data = {57'b0,sid59};
1790 end
1791 19'h1_03E0: begin
1792 ld_sid60 = wr_en;
1793 rd_data = {57'b0,sid60};
1794 end
1795 19'h1_03E8: begin
1796 ld_sid61 = wr_en;
1797 rd_data = {57'b0,sid61};
1798 end
1799 19'h1_03F0: begin
1800 ld_sid62 = wr_en;
1801 rd_data = {57'b0,sid62};
1802 end
1803 19'h1_03F8: begin
1804 ld_sid63 = wr_en;
1805 rd_data = {57'b0,sid63};
1806 end
1807
1808 // Logical Device Group Number
1809 19'h2_0000: begin
1810 ld_ldgn0 = wr_en;
1811 rd_data = {58'b0,ldgn0};
1812 end
1813 19'h2_0008: begin
1814 ld_ldgn1 = wr_en;
1815 rd_data = {58'b0,ldgn1};
1816 end
1817 19'h2_0010: begin
1818 ld_ldgn2 = wr_en;
1819 rd_data = {58'b0,ldgn2};
1820 end
1821 19'h2_0018: begin
1822 ld_ldgn3 = wr_en;
1823 rd_data = {58'b0,ldgn3};
1824 end
1825 19'h2_0020: begin
1826 ld_ldgn4 = wr_en;
1827 rd_data = {58'b0,ldgn4};
1828 end
1829 19'h2_0028: begin
1830 ld_ldgn5 = wr_en;
1831 rd_data = {58'b0,ldgn5};
1832 end
1833 19'h2_0030: begin
1834 ld_ldgn6 = wr_en;
1835 rd_data = {58'b0,ldgn6};
1836 end
1837 19'h2_0038: begin
1838 ld_ldgn7 = wr_en;
1839 rd_data = {58'b0,ldgn7};
1840 end
1841 19'h2_0040: begin
1842 ld_ldgn8 = wr_en;
1843 rd_data = {58'b0,ldgn8};
1844 end
1845 19'h2_0048: begin
1846 ld_ldgn9 = wr_en;
1847 rd_data = {58'b0,ldgn9};
1848 end
1849 19'h2_0050: begin
1850 ld_ldgn10 = wr_en;
1851 rd_data = {58'b0,ldgn10};
1852 end
1853 19'h2_0058: begin
1854 ld_ldgn11 = wr_en;
1855 rd_data = {58'b0,ldgn11};
1856 end
1857 19'h2_0060: begin
1858 ld_ldgn12 = wr_en;
1859 rd_data = {58'b0,ldgn12};
1860 end
1861 19'h2_0068: begin
1862 ld_ldgn13 = wr_en;
1863 rd_data = {58'b0,ldgn13};
1864 end
1865 19'h2_0070: begin
1866 ld_ldgn14 = wr_en;
1867 rd_data = {58'b0,ldgn14};
1868 end
1869 19'h2_0078: begin
1870 ld_ldgn15 = wr_en;
1871 rd_data = {58'b0,ldgn15};
1872 end
1873 19'h2_0080: begin
1874 ld_ldgn16 = wr_en;
1875 rd_data = {58'b0,ldgn16};
1876 end
1877 19'h2_0088: begin
1878 ld_ldgn17 = wr_en;
1879 rd_data = {58'b0,ldgn17};
1880 end
1881 19'h2_0090: begin
1882 ld_ldgn18 = wr_en;
1883 rd_data = {58'b0,ldgn18};
1884 end
1885 19'h2_0098: begin
1886 ld_ldgn19 = wr_en;
1887 rd_data = {58'b0,ldgn19};
1888 end
1889 19'h2_00A0: begin
1890 ld_ldgn20 = wr_en;
1891 rd_data = {58'b0,ldgn20};
1892 end
1893 19'h2_00A8: begin
1894 ld_ldgn21 = wr_en;
1895 rd_data = {58'b0,ldgn21};
1896 end
1897 19'h2_00B0: begin
1898 ld_ldgn22 = wr_en;
1899 rd_data = {58'b0,ldgn22};
1900 end
1901 19'h2_00B8: begin
1902 ld_ldgn23 = wr_en;
1903 rd_data = {58'b0,ldgn23};
1904 end
1905 19'h2_00C0: begin
1906 ld_ldgn24 = wr_en;
1907 rd_data = {58'b0,ldgn24};
1908 end
1909 19'h2_00C8: begin
1910 ld_ldgn25 = wr_en;
1911 rd_data = {58'b0,ldgn25};
1912 end
1913 19'h2_00D0: begin
1914 ld_ldgn26 = wr_en;
1915 rd_data = {58'b0,ldgn26};
1916 end
1917 19'h2_00D8: begin
1918 ld_ldgn27 = wr_en;
1919 rd_data = {58'b0,ldgn27};
1920 end
1921 19'h2_00E0: begin
1922 ld_ldgn28 = wr_en;
1923 rd_data = {58'b0,ldgn28};
1924 end
1925 19'h2_00E8: begin
1926 ld_ldgn29 = wr_en;
1927 rd_data = {58'b0,ldgn29};
1928 end
1929 19'h2_00F0: begin
1930 ld_ldgn30 = wr_en;
1931 rd_data = {58'b0,ldgn30};
1932 end
1933 19'h2_00F8: begin
1934 ld_ldgn31 = wr_en;
1935 rd_data = {58'b0,ldgn31};
1936 end
1937 19'h2_0100: begin
1938 ld_ldgn32 = wr_en;
1939 rd_data = {58'b0,ldgn32};
1940 end
1941 19'h2_0108: begin
1942 ld_ldgn33 = wr_en;
1943 rd_data = {58'b0,ldgn33};
1944 end
1945 19'h2_0110: begin
1946 ld_ldgn34 = wr_en;
1947 rd_data = {58'b0,ldgn34};
1948 end
1949 19'h2_0118: begin
1950 ld_ldgn35 = wr_en;
1951 rd_data = {58'b0,ldgn35};
1952 end
1953 19'h2_0120: begin
1954 ld_ldgn36 = wr_en;
1955 rd_data = {58'b0,ldgn36};
1956 end
1957 19'h2_0128: begin
1958 ld_ldgn37 = wr_en;
1959 rd_data = {58'b0,ldgn37};
1960 end
1961 19'h2_0130: begin
1962 ld_ldgn38 = wr_en;
1963 rd_data = {58'b0,ldgn38};
1964 end
1965 19'h2_0138: begin
1966 ld_ldgn39 = wr_en;
1967 rd_data = {58'b0,ldgn39};
1968 end
1969 19'h2_0140: begin
1970 ld_ldgn40 = wr_en;
1971 rd_data = {58'b0,ldgn40};
1972 end
1973 19'h2_0148: begin
1974 ld_ldgn41 = wr_en;
1975 rd_data = {58'b0,ldgn41};
1976 end
1977 19'h2_0150: begin
1978 ld_ldgn42 = wr_en;
1979 rd_data = {58'b0,ldgn42};
1980 end
1981 19'h2_0158: begin
1982 ld_ldgn43 = wr_en;
1983 rd_data = {58'b0,ldgn43};
1984 end
1985 19'h2_0160: begin
1986 ld_ldgn44 = wr_en;
1987 rd_data = {58'b0,ldgn44};
1988 end
1989 19'h2_0168: begin
1990 ld_ldgn45 = wr_en;
1991 rd_data = {58'b0,ldgn45};
1992 end
1993 19'h2_0170: begin
1994 ld_ldgn46 = wr_en;
1995 rd_data = {58'b0,ldgn46};
1996 end
1997 19'h2_0178: begin
1998 ld_ldgn47 = wr_en;
1999 rd_data = {58'b0,ldgn47};
2000 end
2001 19'h2_0180: begin
2002 ld_ldgn48 = wr_en;
2003 rd_data = {58'b0,ldgn48};
2004 end
2005 19'h2_0188: begin
2006 ld_ldgn49 = wr_en;
2007 rd_data = {58'b0,ldgn49};
2008 end
2009 19'h2_0190: begin
2010 ld_ldgn50 = wr_en;
2011 rd_data = {58'b0,ldgn50};
2012 end
2013 19'h2_0198: begin
2014 ld_ldgn51 = wr_en;
2015 rd_data = {58'b0,ldgn51};
2016 end
2017 19'h2_01A0: begin
2018 ld_ldgn52 = wr_en;
2019 rd_data = {58'b0,ldgn52};
2020 end
2021 19'h2_01A8: begin
2022 ld_ldgn53 = wr_en;
2023 rd_data = {58'b0,ldgn53};
2024 end
2025 19'h2_01B0: begin
2026 ld_ldgn54 = wr_en;
2027 rd_data = {58'b0,ldgn54};
2028 end
2029 19'h2_01B8: begin
2030 ld_ldgn55 = wr_en;
2031 rd_data = {58'b0,ldgn55};
2032 end
2033 19'h2_01C0: begin
2034 ld_ldgn56 = wr_en;
2035 rd_data = {58'b0,ldgn56};
2036 end
2037 19'h2_01C8: begin
2038 ld_ldgn57 = wr_en;
2039 rd_data = {58'b0,ldgn57};
2040 end
2041 19'h2_01D0: begin
2042 ld_ldgn58 = wr_en;
2043 rd_data = {58'b0,ldgn58};
2044 end
2045 19'h2_01D8: begin
2046 ld_ldgn59 = wr_en;
2047 rd_data = {58'b0,ldgn59};
2048 end
2049 19'h2_01E0: begin
2050 ld_ldgn60 = wr_en;
2051 rd_data = {58'b0,ldgn60};
2052 end
2053 19'h2_01E8: begin
2054 ld_ldgn61 = wr_en;
2055 rd_data = {58'b0,ldgn61};
2056 end
2057 19'h2_01F0: begin
2058 ld_ldgn62 = wr_en;
2059 rd_data = {58'b0,ldgn62};
2060 end
2061 19'h2_01F8: begin
2062 ld_ldgn63 = wr_en;
2063 rd_data = {58'b0,ldgn63};
2064 end
2065 19'h2_0200: begin
2066 ld_ldgn64 = wr_en;
2067 rd_data = {58'b0,ldgn64};
2068 end
2069 19'h2_0208: begin
2070 ld_ldgn65 = wr_en;
2071 rd_data = {58'b0,ldgn65};
2072 end
2073 19'h2_0210: begin
2074 ld_ldgn66 = wr_en;
2075 rd_data = {58'b0,ldgn66};
2076 end
2077 19'h2_0218: begin
2078 ld_ldgn67 = wr_en;
2079 rd_data = {58'b0,ldgn67};
2080 end
2081 19'h2_0220: begin
2082 ld_ldgn68 = wr_en;
2083 rd_data = {58'b0,ldgn68};
2084 end
2085
2086 default: begin
2087 rd_data = 64'hdead_beef_dead_beef;
2088 non_qualified_addr_err = 1;
2089 end // case: default
2090 endcase // case({addr[18:3],3'b0})
2091 end // always @ (...
2092
2093endmodule // niu_pio_fzc_slv_decoder
2094
Full OpenSPARC design & verification tarball including full HDL.