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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_pio_ig_sm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
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8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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23 | // choice is available it will apply instead, Sun elects to use only | |
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33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /************************************************************************* | |
38 | * | |
39 | * File Name : niu_pio_ig_sm.v | |
40 | * Author Name : John Lo | |
41 | * Description : Interrupt Generator. | |
42 | * This state machine check the group number to generate | |
43 | * interrupt. | |
44 | * It then reset the arm bit and timer. | |
45 | * | |
46 | * Parent Module: niu_pio_ic | |
47 | * Child Module: | |
48 | * Interface Mod: many. | |
49 | * Date Created : 3/19/2004 | |
50 | * | |
51 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
52 | * Sun Proprietary and Confidential | |
53 | * | |
54 | * Modification : | |
55 | * | |
56 | * Synthesis Notes: | |
57 | * | |
58 | *************************************************************************/ | |
59 | ||
60 | module niu_pio_ig_sm (/*AUTOARG*/ | |
61 | // Outputs | |
62 | latch_req_mux_out, latch_result_group, latch_nx_pri_group, | |
63 | intr_valid, intr_invalid, rst_at, ig_state, | |
64 | activate_ig_sm_rel_latched, | |
65 | // Inputs | |
66 | clk, reset, ibusy, activate_ig_sm, activate_ig_sm_rel | |
67 | ); | |
68 | input clk; | |
69 | input reset; | |
70 | input ibusy; | |
71 | input activate_ig_sm; | |
72 | input activate_ig_sm_rel; | |
73 | // outputs | |
74 | output latch_req_mux_out; | |
75 | output latch_result_group; | |
76 | output latch_nx_pri_group; | |
77 | output intr_valid; | |
78 | output intr_invalid; | |
79 | output rst_at; | |
80 | output [2:0] ig_state; | |
81 | output activate_ig_sm_rel_latched ; | |
82 | ||
83 | wire [2:0] ig_state; | |
84 | reg intr_vld_ip; // (ip - in progress) | |
85 | reg intr_invld_ip; // (ip - in progress) | |
86 | reg intr_vld_ip_del ; | |
87 | reg intr_invld_ip_del ; | |
88 | ||
89 | reg [2:0] nx_ig_state; | |
90 | reg latch_req_mux_out; | |
91 | reg latch_result_group; | |
92 | reg latch_nx_pri_group; | |
93 | reg intr_valid; | |
94 | reg intr_invalid; | |
95 | ||
96 | parameter IDLE = 3'h0; | |
97 | parameter LCH_REQ_MUX = 3'h1; | |
98 | parameter LCH_RESULT_GROUP = 3'h2; | |
99 | parameter LCH_NX_PRI = 3'h3; | |
100 | parameter WAIT4BUSY = 3'h4; | |
101 | parameter DLY1 = 3'h5; | |
102 | ||
103 | reg activate_ig_sm_rel_latched ; | |
104 | ||
105 | always @(posedge clk) | |
106 | begin | |
107 | if (reset) | |
108 | activate_ig_sm_rel_latched <= 1'b0 ; | |
109 | else | |
110 | begin | |
111 | if (activate_ig_sm_rel) | |
112 | activate_ig_sm_rel_latched <= 1'b1 ; | |
113 | else | |
114 | if (intr_invalid) | |
115 | activate_ig_sm_rel_latched <= 1'b0 ; | |
116 | end | |
117 | end | |
118 | ||
119 | // comb part | |
120 | always @ (/*AUTOSENSE*/activate_ig_sm or ibusy or ig_state | |
121 | or activate_ig_sm_rel or activate_ig_sm_rel_latched | |
122 | or intr_invld_ip_del or intr_vld_ip_del) | |
123 | begin | |
124 | nx_ig_state = IDLE; | |
125 | latch_req_mux_out = 0; | |
126 | latch_result_group = 0; | |
127 | latch_nx_pri_group = 0; | |
128 | intr_valid = 0; | |
129 | intr_invalid = 0; | |
130 | intr_vld_ip = 0 ; | |
131 | intr_invld_ip = 0 ; | |
132 | case (ig_state) // synopsys parallel_case full_case | |
133 | IDLE: | |
134 | if (activate_ig_sm || activate_ig_sm_rel || activate_ig_sm_rel_latched) | |
135 | begin | |
136 | nx_ig_state = LCH_REQ_MUX; | |
137 | if (activate_ig_sm) | |
138 | intr_vld_ip = 1 ; | |
139 | else | |
140 | if (activate_ig_sm_rel_latched || activate_ig_sm_rel) | |
141 | intr_invld_ip = 1 ; | |
142 | end | |
143 | else | |
144 | begin | |
145 | nx_ig_state = ig_state;// stay&wait | |
146 | end | |
147 | ||
148 | LCH_REQ_MUX: | |
149 | begin | |
150 | nx_ig_state = LCH_RESULT_GROUP; | |
151 | latch_req_mux_out = 1; | |
152 | end | |
153 | ||
154 | LCH_RESULT_GROUP: | |
155 | begin | |
156 | nx_ig_state = LCH_NX_PRI; | |
157 | latch_result_group = 1; | |
158 | end | |
159 | ||
160 | LCH_NX_PRI: | |
161 | begin | |
162 | nx_ig_state = WAIT4BUSY; | |
163 | latch_nx_pri_group = 1; | |
164 | end | |
165 | ||
166 | WAIT4BUSY: | |
167 | if (ibusy) | |
168 | nx_ig_state = ig_state;// stay&wait | |
169 | ||
170 | else | |
171 | begin | |
172 | // geo: if (activate_ig_sm && !intr_invld_ip_del) | |
173 | if ( !intr_invld_ip_del) | |
174 | begin | |
175 | intr_valid = 1; | |
176 | nx_ig_state = DLY1; | |
177 | end | |
178 | else | |
179 | if (activate_ig_sm_rel_latched && !intr_vld_ip_del) | |
180 | begin | |
181 | intr_invalid = 1; | |
182 | nx_ig_state = DLY1; | |
183 | end | |
184 | end | |
185 | ||
186 | DLY1: | |
187 | begin | |
188 | nx_ig_state = IDLE; | |
189 | end | |
190 | ||
191 | default: | |
192 | begin | |
193 | nx_ig_state = IDLE; | |
194 | end | |
195 | endcase // casex(ig_state) | |
196 | end | |
197 | ||
198 | // synopsys translate_off | |
199 | always @(posedge clk) begin | |
200 | if ( (ig_state==WAIT4BUSY) && !ibusy && !activate_ig_sm && !intr_invld_ip_del ) | |
201 | $display ("Warning @time=%d_ns, hit niu_pio_ig_sm looping condition, bugID_119020, ig_state=%h,ibusy=%h,activate_ig_sm=%h,intr_invld_ip_del=%h \n", | |
202 | $stime, ig_state, ibusy, activate_ig_sm, intr_invld_ip_del); | |
203 | end | |
204 | // synopsys translate_on | |
205 | ||
206 | ||
207 | // seq part | |
208 | dffr #(3) ig_state_dffr(.clk(clk), | |
209 | .reset(reset), | |
210 | .d(nx_ig_state), | |
211 | .q(ig_state)); | |
212 | ||
213 | df1 #(1) rst_at_dffr(.clk(clk), | |
214 | .d(intr_valid), | |
215 | .q(rst_at)); | |
216 | ||
217 | ||
218 | always @(posedge clk) | |
219 | begin | |
220 | if (reset) | |
221 | begin | |
222 | intr_vld_ip_del <= 1'b0 ; | |
223 | intr_invld_ip_del <= 1'b0 ; | |
224 | end | |
225 | else | |
226 | begin | |
227 | if(intr_vld_ip) | |
228 | intr_vld_ip_del <= 1'b1 ; | |
229 | else | |
230 | if(intr_valid) | |
231 | intr_vld_ip_del <= 1'b0 ; | |
232 | ||
233 | if(intr_invld_ip) | |
234 | intr_invld_ip_del <= 1'b1 ; | |
235 | else | |
236 | if(intr_invalid) | |
237 | intr_invld_ip_del <= 1'b0 ; | |
238 | end | |
239 | end | |
240 | ||
241 | ||
242 | endmodule // niu_pio_ig_sm |