projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_rw_sm.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_pio_rw_sm.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*************************************************************************
38 *
39 * File Name : niu_pio_rw_sm.v
40 * Author Name : John Lo
41 * Description : It contains niu pio interface, interrupt controller,
42 * UCB for N2.
43 * Parent Module: niu
44 * Child Module:
45 * Interface Mod: many.
46 * Date Created : 3/08/2004
47 *
48 * Copyright (c) 2020, Sun Microsystems, Inc.
49 * Sun Proprietary and Confidential
50 *
51 * Modification :
52 *
53 * Synthesis Notes:
54 *
55 *************************************************************************/
56
57module niu_pio_rw_sm (/*AUTOARG*/
58 // Outputs
59 ucb_ack,
60 ucb_nack,
61 fifo_rd_en,
62 pio_sel_state,
63 pio_rw_state,
64 pio_peu_32b_int,
65`ifdef NEPTUNE
66 insert_db,
67`else
68`endif
69 // Inputs
70 clk,
71 reset,
72 empty,
73 pio_ack,
74 pio_err,
75 rd,
76 ack_TO_en,
77 ack_TO_value,
78 pio_clients_32b,
79 sel1,
80 ucb_rack_busy
81 );
82
83 input clk;
84 input reset;
85 input empty;
86 input pio_ack;
87 input pio_err;
88 input rd;
89 input ack_TO_en;
90 input [9:0] ack_TO_value;
91 input sel1;
92 input ucb_rack_busy;
93 input pio_clients_32b;
94
95 output ucb_ack;
96 output ucb_nack;
97 output fifo_rd_en;
98 output pio_sel_state;
99 output [2:0] pio_rw_state;
100 output pio_peu_32b_int;
101
102 reg [2:0] nx_pio_rw_state;
103 reg fifo_rd_en;
104 reg ucb_ack;
105 reg ucb_nack;
106 reg pio_peu_32b_int_mod;
107 reg [9:0] nx_ack_TO_cnt;
108 wire [9:0] ack_TO_cnt;
109 wire [2:0] pio_rw_state;
110 wire pio_sel_state;
111 wire TO_cnt_state;
112 wire TO;
113 wire goto_idle;
114
115`ifdef NEPTUNE
116 output insert_db ;
117 reg insert_db ;
118`else
119`endif
120
121 parameter IDLE = 3'd0;
122 parameter CHK_SEL= 3'd1;
123 parameter CHK_TO = 3'd2;
124 parameter R_NACK = 3'd3; // ucb err
125 parameter R_ACK = 3'd4; // ucb
126
127`ifdef NEPTUNE
128 parameter R_NACK_noerr = 3'd5; // ucb
129
130 wire detect_rnack_state ;
131 wire assert_pio_peu_32b_int ;
132
133 assign detect_rnack_state = ( pio_rw_state[2] &
134 ! pio_rw_state[1] &
135 pio_rw_state[0] ) ;
136
137 assign assert_pio_peu_32b_int = (detect_rnack_state & pio_clients_32b) ;
138
139 assign pio_peu_32b_int = (pio_peu_32b_int_mod || assert_pio_peu_32b_int) ;
140
141`else
142 assign pio_peu_32b_int = pio_peu_32b_int_mod ;
143`endif
144
145// combination logic
146always @ (/*AUTOSENSE*/TO or empty or pio_ack or pio_err
147 or pio_rw_state or rd or sel1 or ucb_rack_busy
148 or pio_clients_32b )
149 begin
150 fifo_rd_en = 0;
151 ucb_ack = 0;
152 ucb_nack = 0;
153 pio_peu_32b_int_mod = 0;
154 `ifdef NEPTUNE
155 insert_db = 0;
156 `else
157 `endif
158 case (pio_rw_state) // synopsys full_case parallel_case
159 IDLE: begin
160 if (empty)
161 nx_pio_rw_state = pio_rw_state;
162 else
163 begin
164 nx_pio_rw_state = CHK_SEL;
165 fifo_rd_en = 1;
166 end
167 end
168
169 CHK_SEL:casex({sel1,rd}) // synopsys full_case parallel_case
170 2'b00: nx_pio_rw_state = IDLE; // no sel1 and write
171 2'b01:
172 `ifdef NEPTUNE
173 nx_pio_rw_state = R_NACK_noerr; // no sel1 and write
174 `else
175 nx_pio_rw_state = R_NACK; // no sel1 and write
176 `endif
177 2'b1x: nx_pio_rw_state = CHK_TO; // sel1 and write
178 default:nx_pio_rw_state = IDLE;
179 endcase
180
181 CHK_TO: casex({pio_err,rd,TO,pio_ack}) // synopsys full_case parallel_case
182 4'bxx00:nx_pio_rw_state = pio_rw_state; //~TO &~pio_ack
183 4'bx0x1:nx_pio_rw_state = IDLE; // pio_ack & wr
184 4'b01x1:nx_pio_rw_state = R_ACK; // pio_ack & rd & ~err
185 4'b11x1:nx_pio_rw_state = R_NACK; // pio_ack & rd & err
186 4'bx010:nx_pio_rw_state = IDLE; // TO &~pio_ack & wr
187 4'bx110:nx_pio_rw_state = R_NACK; // TO &~pio_ack & rd & err
188 default:nx_pio_rw_state = IDLE;
189 endcase
190
191 R_NACK: if (ucb_rack_busy)
192 nx_pio_rw_state = pio_rw_state;
193 else begin
194 nx_pio_rw_state = IDLE;
195 ucb_nack = 1;
196 if (pio_clients_32b)
197 pio_peu_32b_int_mod = 1;
198 else
199 pio_peu_32b_int_mod = 0;
200
201 end
202
203 R_ACK: if (ucb_rack_busy)
204 nx_pio_rw_state = pio_rw_state;
205 else begin
206 nx_pio_rw_state = IDLE;
207 ucb_ack = 1;
208 if (pio_clients_32b)
209 pio_peu_32b_int_mod = 1;
210 else
211 pio_peu_32b_int_mod = 0;
212 end
213
214`ifdef NEPTUNE
215 R_NACK_noerr: if (ucb_rack_busy)
216 nx_pio_rw_state = pio_rw_state;
217 else begin
218 nx_pio_rw_state = IDLE;
219 ucb_ack = 1;
220 insert_db = 1;
221
222 end
223`else
224`endif
225
226 default: nx_pio_rw_state = IDLE;
227 endcase
228 end
229
230// seq part
231dffr #(3) pio_rw_state_dffr(.d(nx_pio_rw_state[2:0]),.reset(reset),.clk(clk),.q(pio_rw_state[2:0]));
232
233// important equations:
234 assign pio_sel_state =(pio_rw_state == CHK_SEL) | (pio_rw_state == CHK_TO);
235 assign TO_cnt_state = pio_rw_state == CHK_TO;
236 assign TO =(ack_TO_cnt == ack_TO_value) & ack_TO_en;
237 assign goto_idle = nx_pio_rw_state == IDLE;
238
239// TO count up counter
240always @ (/*AUTOSENSE*/TO or TO_cnt_state or ack_TO_cnt or ack_TO_en
241 or ack_TO_value or fifo_rd_en or goto_idle)
242 begin
243 if (goto_idle | fifo_rd_en)
244 nx_ack_TO_cnt = 0;
245 else if ((ack_TO_cnt != ack_TO_value) & TO_cnt_state & ack_TO_en)
246 nx_ack_TO_cnt = ack_TO_cnt + 10'b1;
247 else if (TO)
248 nx_ack_TO_cnt = ack_TO_cnt; // hold
249 else nx_ack_TO_cnt = ack_TO_cnt; // hold
250 end // always @ (...
251
252
253dffr # (10) ack_TO_cnt_dffre(.reset(reset),.clk(clk),.d(nx_ack_TO_cnt[9:0]),.q(ack_TO_cnt[9:0]));
254
255endmodule // niu_pio_rw_sm
256
257
Full OpenSPARC design & verification tarball including full HDL.