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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_vdmc_decoder.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_pio_vdmc_decoder.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*****************************************************************
38 *
39 * File Name : niu_pio_vdmc_decoder.v
40 * Author Name : John Lo
41 * Description :
42 *
43 * Parent Module: niu_pio_regs.v
44 * Child Module:
45 * Interface Mod: many.
46 * Date Created : 3/30/04
47 *
48 * Copyright (c) 2020, Sun Microsystems, Inc.
49 * Sun Proprietary and Confidential
50 *
51 * Modification :
52 *
53 ****************************************************************/
54
55`define VDMA_TX_BASE_ADDR 6'b0100_00
56`define VDMA_RX_BASE_ADDR 6'b0000_00
57
58module niu_pio_vdmc_decoder (/*AUTOARG*/
59 // Outputs
60 vdmc_addr, vdmc_sel_ok,
61 // Inputs
62 addr, dma_bind0, dma_bind1, dma_bind2, dma_bind3, dma_bind4,
63 dma_bind5, dma_bind6, dma_bind7, dma_bind8, dma_bind9, dma_bind10,
64 dma_bind11, dma_bind12, dma_bind13, dma_bind14, dma_bind15,
65 dma_bind16, dma_bind17, dma_bind18, dma_bind19, dma_bind20,
66 dma_bind21, dma_bind22, dma_bind23, dma_bind24, dma_bind25,
67 dma_bind26, dma_bind27, dma_bind28, dma_bind29, dma_bind30,
68 dma_bind31, dma_bind32, dma_bind33, dma_bind34, dma_bind35,
69 dma_bind36, dma_bind37, dma_bind38, dma_bind39, dma_bind40,
70 dma_bind41, dma_bind42, dma_bind43, dma_bind44, dma_bind45,
71 dma_bind46, dma_bind47, dma_bind48, dma_bind49, dma_bind50,
72 dma_bind51, dma_bind52, dma_bind53, dma_bind54, dma_bind55,
73 dma_bind56, dma_bind57, dma_bind58, dma_bind59, dma_bind60,
74 dma_bind61, dma_bind62, dma_bind63
75 );
76 // pio broadcast signals
77 input [26:0] addr;
78 //
79 input [13:0] dma_bind0 ;
80 input [13:0] dma_bind1 ;
81 input [13:0] dma_bind2 ;
82 input [13:0] dma_bind3 ;
83 input [13:0] dma_bind4 ;
84 input [13:0] dma_bind5 ;
85 input [13:0] dma_bind6 ;
86 input [13:0] dma_bind7 ;
87 input [13:0] dma_bind8 ;
88 input [13:0] dma_bind9 ;
89 input [13:0] dma_bind10;
90 input [13:0] dma_bind11;
91 input [13:0] dma_bind12;
92 input [13:0] dma_bind13;
93 input [13:0] dma_bind14;
94 input [13:0] dma_bind15;
95 input [13:0] dma_bind16;
96 input [13:0] dma_bind17;
97 input [13:0] dma_bind18;
98 input [13:0] dma_bind19;
99 input [13:0] dma_bind20;
100 input [13:0] dma_bind21;
101 input [13:0] dma_bind22;
102 input [13:0] dma_bind23;
103 input [13:0] dma_bind24;
104 input [13:0] dma_bind25;
105 input [13:0] dma_bind26;
106 input [13:0] dma_bind27;
107 input [13:0] dma_bind28;
108 input [13:0] dma_bind29;
109 input [13:0] dma_bind30;
110 input [13:0] dma_bind31;
111 input [13:0] dma_bind32;
112 input [13:0] dma_bind33;
113 input [13:0] dma_bind34;
114 input [13:0] dma_bind35;
115 input [13:0] dma_bind36;
116 input [13:0] dma_bind37;
117 input [13:0] dma_bind38;
118 input [13:0] dma_bind39;
119 input [13:0] dma_bind40;
120 input [13:0] dma_bind41;
121 input [13:0] dma_bind42;
122 input [13:0] dma_bind43;
123 input [13:0] dma_bind44;
124 input [13:0] dma_bind45;
125 input [13:0] dma_bind46;
126 input [13:0] dma_bind47;
127 input [13:0] dma_bind48;
128 input [13:0] dma_bind49;
129 input [13:0] dma_bind50;
130 input [13:0] dma_bind51;
131 input [13:0] dma_bind52;
132 input [13:0] dma_bind53;
133 input [13:0] dma_bind54;
134 input [13:0] dma_bind55;
135 input [13:0] dma_bind56;
136 input [13:0] dma_bind57;
137 input [13:0] dma_bind58;
138 input [13:0] dma_bind59;
139 input [13:0] dma_bind60;
140 input [13:0] dma_bind61;
141 input [13:0] dma_bind62;
142 input [13:0] dma_bind63;
143 output [19:0] vdmc_addr;
144 output vdmc_sel_ok;
145
146// common reg declaration
147 reg [19:0] vdmc_addr;
148 reg vdmc_sel_ok;
149// common wrie declaration
150// output reg declaration
151
152
153always @ (/*AUTOSENSE*/`VDMA_RX_BASE_ADDR or `VDMA_TX_BASE_ADDR
154 or addr or dma_bind0 or dma_bind1 or dma_bind10
155 or dma_bind11 or dma_bind12 or dma_bind13 or dma_bind14
156 or dma_bind15 or dma_bind16 or dma_bind17 or dma_bind18
157 or dma_bind19 or dma_bind2 or dma_bind20 or dma_bind21
158 or dma_bind22 or dma_bind23 or dma_bind24 or dma_bind25
159 or dma_bind26 or dma_bind27 or dma_bind28 or dma_bind29
160 or dma_bind3 or dma_bind30 or dma_bind31 or dma_bind32
161 or dma_bind33 or dma_bind34 or dma_bind35 or dma_bind36
162 or dma_bind37 or dma_bind38 or dma_bind39 or dma_bind4
163 or dma_bind40 or dma_bind41 or dma_bind42 or dma_bind43
164 or dma_bind44 or dma_bind45 or dma_bind46 or dma_bind47
165 or dma_bind48 or dma_bind49 or dma_bind5 or dma_bind50
166 or dma_bind51 or dma_bind52 or dma_bind53 or dma_bind54
167 or dma_bind55 or dma_bind56 or dma_bind57 or dma_bind58
168 or dma_bind59 or dma_bind6 or dma_bind60 or dma_bind61
169 or dma_bind62 or dma_bind63 or dma_bind7 or dma_bind8
170 or dma_bind9)
171 begin
172 vdmc_addr[19:0] = addr[19:0];
173 if (addr[9]) // rx dma
174// case({addr[15:10]}) //synopsys parallel_case full_case
175 case({addr[26:25],addr[14],addr[12:10]}) //synopsys parallel_case full_case
176 6'd0 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind0 [4:0],addr[8:0]};
177 6'd1 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind1 [4:0],addr[8:0]};
178 6'd2 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind2 [4:0],addr[8:0]};
179 6'd3 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind3 [4:0],addr[8:0]};
180 6'd4 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind4 [4:0],addr[8:0]};
181 6'd5 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind5 [4:0],addr[8:0]};
182 6'd6 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind6 [4:0],addr[8:0]};
183 6'd7 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind7 [4:0],addr[8:0]};
184 6'd8 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind8 [4:0],addr[8:0]};
185 6'd9 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind9 [4:0],addr[8:0]};
186 6'd10 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind10[4:0],addr[8:0]};
187 6'd11 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind11[4:0],addr[8:0]};
188 6'd12 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind12[4:0],addr[8:0]};
189 6'd13 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind13[4:0],addr[8:0]};
190 6'd14 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind14[4:0],addr[8:0]};
191 6'd15 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind15[4:0],addr[8:0]};
192 6'd16 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind16[4:0],addr[8:0]};
193 6'd17 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind17[4:0],addr[8:0]};
194 6'd18 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind18[4:0],addr[8:0]};
195 6'd19 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind19[4:0],addr[8:0]};
196 6'd20 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind20[4:0],addr[8:0]};
197 6'd21 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind21[4:0],addr[8:0]};
198 6'd22 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind22[4:0],addr[8:0]};
199 6'd23 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind23[4:0],addr[8:0]};
200 6'd24 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind24[4:0],addr[8:0]};
201 6'd25 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind25[4:0],addr[8:0]};
202 6'd26 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind26[4:0],addr[8:0]};
203 6'd27 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind27[4:0],addr[8:0]};
204 6'd28 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind28[4:0],addr[8:0]};
205 6'd29 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind29[4:0],addr[8:0]};
206 6'd30 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind30[4:0],addr[8:0]};
207 6'd31 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind31[4:0],addr[8:0]};
208 6'd32 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind32[4:0],addr[8:0]};
209 6'd33 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind33[4:0],addr[8:0]};
210 6'd34 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind34[4:0],addr[8:0]};
211 6'd35 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind35[4:0],addr[8:0]};
212 6'd36 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind36[4:0],addr[8:0]};
213 6'd37 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind37[4:0],addr[8:0]};
214 6'd38 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind38[4:0],addr[8:0]};
215 6'd39 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind39[4:0],addr[8:0]};
216 6'd40 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind40[4:0],addr[8:0]};
217 6'd41 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind41[4:0],addr[8:0]};
218 6'd42 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind42[4:0],addr[8:0]};
219 6'd43 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind43[4:0],addr[8:0]};
220 6'd44 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind44[4:0],addr[8:0]};
221 6'd45 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind45[4:0],addr[8:0]};
222 6'd46 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind46[4:0],addr[8:0]};
223 6'd47 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind47[4:0],addr[8:0]};
224 6'd48 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind48[4:0],addr[8:0]};
225 6'd49 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind49[4:0],addr[8:0]};
226 6'd50 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind50[4:0],addr[8:0]};
227 6'd51 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind51[4:0],addr[8:0]};
228 6'd52 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind52[4:0],addr[8:0]};
229 6'd53 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind53[4:0],addr[8:0]};
230 6'd54 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind54[4:0],addr[8:0]};
231 6'd55 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind55[4:0],addr[8:0]};
232 6'd56 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind56[4:0],addr[8:0]};
233 6'd57 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind57[4:0],addr[8:0]};
234 6'd58 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind58[4:0],addr[8:0]};
235 6'd59 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind59[4:0],addr[8:0]};
236 6'd60 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind60[4:0],addr[8:0]};
237 6'd61 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind61[4:0],addr[8:0]};
238 6'd62 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind62[4:0],addr[8:0]};
239 6'd63 : vdmc_addr[19:0] = {`VDMA_RX_BASE_ADDR,dma_bind63[4:0],addr[8:0]};
240 default:vdmc_addr[19:0] = 20'hdead;
241 endcase
242 else // tx dma
243// case({addr[15:10]}) //synopsys parallel_case full_case
244 case({addr[26:25],addr[14],addr[12:10]}) //synopsys parallel_case full_case
245 6'd0 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind0 [12:8],addr[8:0]};
246 6'd1 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind1 [12:8],addr[8:0]};
247 6'd2 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind2 [12:8],addr[8:0]};
248 6'd3 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind3 [12:8],addr[8:0]};
249 6'd4 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind4 [12:8],addr[8:0]};
250 6'd5 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind5 [12:8],addr[8:0]};
251 6'd6 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind6 [12:8],addr[8:0]};
252 6'd7 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind7 [12:8],addr[8:0]};
253 6'd8 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind8 [12:8],addr[8:0]};
254 6'd9 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind9 [12:8],addr[8:0]};
255 6'd10 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind10[12:8],addr[8:0]};
256 6'd11 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind11[12:8],addr[8:0]};
257 6'd12 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind12[12:8],addr[8:0]};
258 6'd13 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind13[12:8],addr[8:0]};
259 6'd14 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind14[12:8],addr[8:0]};
260 6'd15 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind15[12:8],addr[8:0]};
261 6'd16 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind16[12:8],addr[8:0]};
262 6'd17 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind17[12:8],addr[8:0]};
263 6'd18 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind18[12:8],addr[8:0]};
264 6'd19 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind19[12:8],addr[8:0]};
265 6'd20 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind20[12:8],addr[8:0]};
266 6'd21 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind21[12:8],addr[8:0]};
267 6'd22 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind22[12:8],addr[8:0]};
268 6'd23 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind23[12:8],addr[8:0]};
269 6'd24 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind24[12:8],addr[8:0]};
270 6'd25 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind25[12:8],addr[8:0]};
271 6'd26 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind26[12:8],addr[8:0]};
272 6'd27 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind27[12:8],addr[8:0]};
273 6'd28 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind28[12:8],addr[8:0]};
274 6'd29 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind29[12:8],addr[8:0]};
275 6'd30 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind30[12:8],addr[8:0]};
276 6'd31 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind31[12:8],addr[8:0]};
277 6'd32 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind32[12:8],addr[8:0]};
278 6'd33 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind33[12:8],addr[8:0]};
279 6'd34 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind34[12:8],addr[8:0]};
280 6'd35 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind35[12:8],addr[8:0]};
281 6'd36 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind36[12:8],addr[8:0]};
282 6'd37 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind37[12:8],addr[8:0]};
283 6'd38 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind38[12:8],addr[8:0]};
284 6'd39 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind39[12:8],addr[8:0]};
285 6'd40 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind40[12:8],addr[8:0]};
286 6'd41 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind41[12:8],addr[8:0]};
287 6'd42 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind42[12:8],addr[8:0]};
288 6'd43 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind43[12:8],addr[8:0]};
289 6'd44 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind44[12:8],addr[8:0]};
290 6'd45 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind45[12:8],addr[8:0]};
291 6'd46 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind46[12:8],addr[8:0]};
292 6'd47 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind47[12:8],addr[8:0]};
293 6'd48 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind48[12:8],addr[8:0]};
294 6'd49 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind49[12:8],addr[8:0]};
295 6'd50 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind50[12:8],addr[8:0]};
296 6'd51 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind51[12:8],addr[8:0]};
297 6'd52 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind52[12:8],addr[8:0]};
298 6'd53 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind53[12:8],addr[8:0]};
299 6'd54 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind54[12:8],addr[8:0]};
300 6'd55 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind55[12:8],addr[8:0]};
301 6'd56 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind56[12:8],addr[8:0]};
302 6'd57 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind57[12:8],addr[8:0]};
303 6'd58 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind58[12:8],addr[8:0]};
304 6'd59 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind59[12:8],addr[8:0]};
305 6'd60 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind60[12:8],addr[8:0]};
306 6'd61 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind61[12:8],addr[8:0]};
307 6'd62 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind62[12:8],addr[8:0]};
308 6'd63 : vdmc_addr[19:0] = {`VDMA_TX_BASE_ADDR,dma_bind63[12:8],addr[8:0]};
309 default:vdmc_addr[19:0] = 20'hdead;
310 endcase
311 end
312
313
314always @ (/*AUTOSENSE*/addr or dma_bind0 or dma_bind1 or dma_bind10
315 or dma_bind11 or dma_bind12 or dma_bind13 or dma_bind14
316 or dma_bind15 or dma_bind16 or dma_bind17 or dma_bind18
317 or dma_bind19 or dma_bind2 or dma_bind20 or dma_bind21
318 or dma_bind22 or dma_bind23 or dma_bind24 or dma_bind25
319 or dma_bind26 or dma_bind27 or dma_bind28 or dma_bind29
320 or dma_bind3 or dma_bind30 or dma_bind31 or dma_bind32
321 or dma_bind33 or dma_bind34 or dma_bind35 or dma_bind36
322 or dma_bind37 or dma_bind38 or dma_bind39 or dma_bind4
323 or dma_bind40 or dma_bind41 or dma_bind42 or dma_bind43
324 or dma_bind44 or dma_bind45 or dma_bind46 or dma_bind47
325 or dma_bind48 or dma_bind49 or dma_bind5 or dma_bind50
326 or dma_bind51 or dma_bind52 or dma_bind53 or dma_bind54
327 or dma_bind55 or dma_bind56 or dma_bind57 or dma_bind58
328 or dma_bind59 or dma_bind6 or dma_bind60 or dma_bind61
329 or dma_bind62 or dma_bind63 or dma_bind7 or dma_bind8
330 or dma_bind9)
331 begin
332 vdmc_sel_ok = 0;
333 if (addr[9]) // rx dma
334// case({addr[15:10]}) //synopsys parallel_case full_case
335 case({addr[26:25],addr[14],addr[12:10]}) //synopsys parallel_case full_case
336 6'd0 : vdmc_sel_ok = dma_bind0 [5];
337 6'd1 : vdmc_sel_ok = dma_bind1 [5];
338 6'd2 : vdmc_sel_ok = dma_bind2 [5];
339 6'd3 : vdmc_sel_ok = dma_bind3 [5];
340 6'd4 : vdmc_sel_ok = dma_bind4 [5];
341 6'd5 : vdmc_sel_ok = dma_bind5 [5];
342 6'd6 : vdmc_sel_ok = dma_bind6 [5];
343 6'd7 : vdmc_sel_ok = dma_bind7 [5];
344 6'd8 : vdmc_sel_ok = dma_bind8 [5];
345 6'd9 : vdmc_sel_ok = dma_bind9 [5];
346 6'd10 : vdmc_sel_ok = dma_bind10[5];
347 6'd11 : vdmc_sel_ok = dma_bind11[5];
348 6'd12 : vdmc_sel_ok = dma_bind12[5];
349 6'd13 : vdmc_sel_ok = dma_bind13[5];
350 6'd14 : vdmc_sel_ok = dma_bind14[5];
351 6'd15 : vdmc_sel_ok = dma_bind15[5];
352 6'd16 : vdmc_sel_ok = dma_bind16[5];
353 6'd17 : vdmc_sel_ok = dma_bind17[5];
354 6'd18 : vdmc_sel_ok = dma_bind18[5];
355 6'd19 : vdmc_sel_ok = dma_bind19[5];
356 6'd20 : vdmc_sel_ok = dma_bind20[5];
357 6'd21 : vdmc_sel_ok = dma_bind21[5];
358 6'd22 : vdmc_sel_ok = dma_bind22[5];
359 6'd23 : vdmc_sel_ok = dma_bind23[5];
360 6'd24 : vdmc_sel_ok = dma_bind24[5];
361 6'd25 : vdmc_sel_ok = dma_bind25[5];
362 6'd26 : vdmc_sel_ok = dma_bind26[5];
363 6'd27 : vdmc_sel_ok = dma_bind27[5];
364 6'd28 : vdmc_sel_ok = dma_bind28[5];
365 6'd29 : vdmc_sel_ok = dma_bind29[5];
366 6'd30 : vdmc_sel_ok = dma_bind30[5];
367 6'd31 : vdmc_sel_ok = dma_bind31[5];
368 6'd32 : vdmc_sel_ok = dma_bind32[5];
369 6'd33 : vdmc_sel_ok = dma_bind33[5];
370 6'd34 : vdmc_sel_ok = dma_bind34[5];
371 6'd35 : vdmc_sel_ok = dma_bind35[5];
372 6'd36 : vdmc_sel_ok = dma_bind36[5];
373 6'd37 : vdmc_sel_ok = dma_bind37[5];
374 6'd38 : vdmc_sel_ok = dma_bind38[5];
375 6'd39 : vdmc_sel_ok = dma_bind39[5];
376 6'd40 : vdmc_sel_ok = dma_bind40[5];
377 6'd41 : vdmc_sel_ok = dma_bind41[5];
378 6'd42 : vdmc_sel_ok = dma_bind42[5];
379 6'd43 : vdmc_sel_ok = dma_bind43[5];
380 6'd44 : vdmc_sel_ok = dma_bind44[5];
381 6'd45 : vdmc_sel_ok = dma_bind45[5];
382 6'd46 : vdmc_sel_ok = dma_bind46[5];
383 6'd47 : vdmc_sel_ok = dma_bind47[5];
384 6'd48 : vdmc_sel_ok = dma_bind48[5];
385 6'd49 : vdmc_sel_ok = dma_bind49[5];
386 6'd50 : vdmc_sel_ok = dma_bind50[5];
387 6'd51 : vdmc_sel_ok = dma_bind51[5];
388 6'd52 : vdmc_sel_ok = dma_bind52[5];
389 6'd53 : vdmc_sel_ok = dma_bind53[5];
390 6'd54 : vdmc_sel_ok = dma_bind54[5];
391 6'd55 : vdmc_sel_ok = dma_bind55[5];
392 6'd56 : vdmc_sel_ok = dma_bind56[5];
393 6'd57 : vdmc_sel_ok = dma_bind57[5];
394 6'd58 : vdmc_sel_ok = dma_bind58[5];
395 6'd59 : vdmc_sel_ok = dma_bind59[5];
396 6'd60 : vdmc_sel_ok = dma_bind60[5];
397 6'd61 : vdmc_sel_ok = dma_bind61[5];
398 6'd62 : vdmc_sel_ok = dma_bind62[5];
399 6'd63 : vdmc_sel_ok = dma_bind63[5];
400 default:vdmc_sel_ok = 0;
401 endcase
402 else // tx dma
403// case({addr[15:10]}) //synopsys parallel_case full_case
404 case({addr[26:25],addr[14],addr[12:10]}) //synopsys parallel_case full_case
405 6'd0 : vdmc_sel_ok = dma_bind0 [13];
406 6'd1 : vdmc_sel_ok = dma_bind1 [13];
407 6'd2 : vdmc_sel_ok = dma_bind2 [13];
408 6'd3 : vdmc_sel_ok = dma_bind3 [13];
409 6'd4 : vdmc_sel_ok = dma_bind4 [13];
410 6'd5 : vdmc_sel_ok = dma_bind5 [13];
411 6'd6 : vdmc_sel_ok = dma_bind6 [13];
412 6'd7 : vdmc_sel_ok = dma_bind7 [13];
413 6'd8 : vdmc_sel_ok = dma_bind8 [13];
414 6'd9 : vdmc_sel_ok = dma_bind9 [13];
415 6'd10 : vdmc_sel_ok = dma_bind10[13];
416 6'd11 : vdmc_sel_ok = dma_bind11[13];
417 6'd12 : vdmc_sel_ok = dma_bind12[13];
418 6'd13 : vdmc_sel_ok = dma_bind13[13];
419 6'd14 : vdmc_sel_ok = dma_bind14[13];
420 6'd15 : vdmc_sel_ok = dma_bind15[13];
421 6'd16 : vdmc_sel_ok = dma_bind16[13];
422 6'd17 : vdmc_sel_ok = dma_bind17[13];
423 6'd18 : vdmc_sel_ok = dma_bind18[13];
424 6'd19 : vdmc_sel_ok = dma_bind19[13];
425 6'd20 : vdmc_sel_ok = dma_bind20[13];
426 6'd21 : vdmc_sel_ok = dma_bind21[13];
427 6'd22 : vdmc_sel_ok = dma_bind22[13];
428 6'd23 : vdmc_sel_ok = dma_bind23[13];
429 6'd24 : vdmc_sel_ok = dma_bind24[13];
430 6'd25 : vdmc_sel_ok = dma_bind25[13];
431 6'd26 : vdmc_sel_ok = dma_bind26[13];
432 6'd27 : vdmc_sel_ok = dma_bind27[13];
433 6'd28 : vdmc_sel_ok = dma_bind28[13];
434 6'd29 : vdmc_sel_ok = dma_bind29[13];
435 6'd30 : vdmc_sel_ok = dma_bind30[13];
436 6'd31 : vdmc_sel_ok = dma_bind31[13];
437 6'd32 : vdmc_sel_ok = dma_bind32[13];
438 6'd33 : vdmc_sel_ok = dma_bind33[13];
439 6'd34 : vdmc_sel_ok = dma_bind34[13];
440 6'd35 : vdmc_sel_ok = dma_bind35[13];
441 6'd36 : vdmc_sel_ok = dma_bind36[13];
442 6'd37 : vdmc_sel_ok = dma_bind37[13];
443 6'd38 : vdmc_sel_ok = dma_bind38[13];
444 6'd39 : vdmc_sel_ok = dma_bind39[13];
445 6'd40 : vdmc_sel_ok = dma_bind40[13];
446 6'd41 : vdmc_sel_ok = dma_bind41[13];
447 6'd42 : vdmc_sel_ok = dma_bind42[13];
448 6'd43 : vdmc_sel_ok = dma_bind43[13];
449 6'd44 : vdmc_sel_ok = dma_bind44[13];
450 6'd45 : vdmc_sel_ok = dma_bind45[13];
451 6'd46 : vdmc_sel_ok = dma_bind46[13];
452 6'd47 : vdmc_sel_ok = dma_bind47[13];
453 6'd48 : vdmc_sel_ok = dma_bind48[13];
454 6'd49 : vdmc_sel_ok = dma_bind49[13];
455 6'd50 : vdmc_sel_ok = dma_bind50[13];
456 6'd51 : vdmc_sel_ok = dma_bind51[13];
457 6'd52 : vdmc_sel_ok = dma_bind52[13];
458 6'd53 : vdmc_sel_ok = dma_bind53[13];
459 6'd54 : vdmc_sel_ok = dma_bind54[13];
460 6'd55 : vdmc_sel_ok = dma_bind55[13];
461 6'd56 : vdmc_sel_ok = dma_bind56[13];
462 6'd57 : vdmc_sel_ok = dma_bind57[13];
463 6'd58 : vdmc_sel_ok = dma_bind58[13];
464 6'd59 : vdmc_sel_ok = dma_bind59[13];
465 6'd60 : vdmc_sel_ok = dma_bind60[13];
466 6'd61 : vdmc_sel_ok = dma_bind61[13];
467 6'd62 : vdmc_sel_ok = dma_bind62[13];
468 6'd63 : vdmc_sel_ok = dma_bind63[13];
469 default:vdmc_sel_ok = 0;
470 endcase
471 end
472
473endmodule // niu_pio_vdmc_decoder
Full OpenSPARC design & verification tarball including full HDL.