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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_ram_256_148.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_ram_256_148.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36/**********************************************************
37***********************************************************
38
39 Project : Niu
40
41 File name : niu_ram_256_148.v
42
43 Module(s) name : niu_ram_256_148
44
45 Parent modules :
46
47 Child modules :
48
49 Author's name : George Chu
50
51 Date : April. 2004
52
53 Description :
54
55 Synthesis Notes:
56
57 Modification History:
58 Date Description
59 ---- -----------
60
61************************************************************
62***********************************************************/
63
64`timescale 1ns/10ps
65
66module niu_ram_256_148 (
67`ifdef NEPTUNE
68`else reset,
69 tcu_aclk,
70 tcu_bclk,
71 tcu_scan_en,
72 tcu_se_scancollar_in,
73 tcu_se_scancollar_out,
74 tcu_array_wr_inhibit,
75 scan_in,
76 scan_out,
77 hdr_sram_rvalue,
78 hdr_sram_rid,
79 hdr_sram_wr_en,
80 hdr_sram_red_clr,
81 sram_hdr_read_data,
82 l2clk_2x,
83 mbi_wdata,
84 mbi_rd_adr,
85 mbi_wr_adr,
86 mbi_wr_en,
87 mbi_rd_en,
88 mbi_run,
89`endif data_inp,
90 addr_rd,
91 addr_wt,
92 wt_enable,
93 cs_rd,
94 clk,
95 data_out
96 );
97
98parameter DATA_WIDTH_MINUS1 = 147;
99parameter ADDR_WIDTH_MINUS1 = 7;
100
101`ifdef NEPTUNE
102`else
103input reset;
104input tcu_aclk;
105input tcu_bclk;
106input tcu_scan_en;
107input tcu_se_scancollar_in;
108input tcu_se_scancollar_out;
109input tcu_array_wr_inhibit;
110input scan_in;
111output scan_out;
112
113input [6:0] hdr_sram_rvalue;
114input [1:0] hdr_sram_rid;
115input hdr_sram_wr_en;
116input hdr_sram_red_clr;
117output [6:0] sram_hdr_read_data;
118
119input l2clk_2x;
120
121input [DATA_WIDTH_MINUS1:0] mbi_wdata;
122input [ADDR_WIDTH_MINUS1:0] mbi_rd_adr;
123input [ADDR_WIDTH_MINUS1:0] mbi_wr_adr;
124input mbi_wr_en;
125input mbi_rd_en;
126input mbi_run;
127`endif
128
129input [DATA_WIDTH_MINUS1:0] data_inp; // data_input, via port_B
130input [ADDR_WIDTH_MINUS1:0] addr_rd; // read_address, via port_A
131input [ADDR_WIDTH_MINUS1:0] addr_wt; // write_address, via port_B
132input wt_enable; // write_enable, via port_B
133input cs_rd; // chip_selet_rd_port, i.e., port_A
134input clk;
135output [DATA_WIDTH_MINUS1:0] data_out; // data read out, via port_A
136
137wire [DATA_WIDTH_MINUS1:0] data_out;
138
139`ifdef NEPTUNE
140 niu_ram_256i148 ram_256i148_0 (
141 .data_inp (data_inp),
142 .addr_rd (addr_rd[7:0]),
143 .addr_wt (addr_wt[7:0]),
144 .wt_enable (wt_enable),
145 .cs_rd (cs_rd),
146 .clk (clk),
147 .data_out (data_out)
148 );
149
150`else
151wire scan_out;
152wire [6:0] sram_hdr_read_data;
153
154 niu_ram_256x148 ram_256x148_0 (
155 .reset (reset),
156 .tcu_aclk (tcu_aclk),
157 .tcu_bclk (tcu_bclk),
158 .tcu_scan_en (tcu_scan_en),
159 .tcu_se_scancollar_in (tcu_se_scancollar_in),
160 .tcu_se_scancollar_out (tcu_se_scancollar_out),
161 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
162 .scan_in (scan_in),
163 .scan_out (scan_out),
164 .hdr_sram_rvalue (hdr_sram_rvalue[6:0]),
165 .hdr_sram_rid (hdr_sram_rid[1:0]),
166 .hdr_sram_wr_en (hdr_sram_wr_en),
167 .hdr_sram_red_clr (hdr_sram_red_clr),
168 .sram_hdr_read_data (sram_hdr_read_data[6:0]),
169 .l2clk_2x (l2clk_2x),
170 .mbi_wdata (mbi_wdata),
171 .mbi_rd_adr (mbi_rd_adr),
172 .mbi_wr_adr (mbi_wr_adr),
173 .mbi_wr_en (mbi_wr_en),
174 .mbi_rd_en (mbi_rd_en),
175 .mbi_run (mbi_run),
176 .data_inp (data_inp[147:0]),
177 .addr_rd (addr_rd[7:0]),
178 .addr_wt (addr_wt[7:0]),
179 .wt_enable (wt_enable),
180 .cs_rd (cs_rd),
181 .clk (clk),
182 .data_out (data_out[147:0])
183 );
184`endif
185
186endmodule
Full OpenSPARC design & verification tarball including full HDL.