Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_ram_640_146.v

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// OpenSPARC T2 Processor File: niu_ram_640_146.v
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/**********************************************************
***********************************************************

    Project         : Niu

    File name       : niu_ram_640_146.v

    Module(s) name  : niu_ram_640_146

    Parent modules  :            

    Child modules   :           

    Author's name   : George Chu

    Date            : April. 2004

    Description     :

    Synthesis Notes:

    Modification History:
    Date       Description
    ----       -----------

************************************************************
***********************************************************/

`timescale 1ns/10ps

module niu_ram_640_146 (
                        data_inp,
                        addr_rd,
                        addr_wt,
                        wt_enable,
                        cs_rd,
                        clk,
                        data_out 
                      );

input  [145:0] data_inp;      // data_input,               via port_B
input    [9:0] addr_rd;       //  read_address,            via port_A
input    [9:0] addr_wt;       // write_address,            via port_B
input          wt_enable;     // write_enable,             via port_B
input          cs_rd;         // chip_selet_rd_port,     i.e., port_A
input          clk;           // clock 
output [145:0] data_out;      // data read out, via port_A

/** temperarily forcing *** TI_scan ******************************************/
// inputs of TI_scan
wire           scan_in      = 1'h0;
wire           se           = 1'h0;
wire           tcu_pce_ov   = 1'h0;
wire           tcu_clk_stop = 1'h0;
wire           tcu_aclk     = clk;
wire           tcu_bclk     = clk;

wire   [145:0] data_out;
wire           scan_out;

  n2_niu_dp_640x146s_cust ram_640_146_0 (
                                           .wr_adr         (addr_wt[9:0]),
                                           .wr_en          (wt_enable),
                                           .rd_adr         (addr_rd[9:0]),
                                           .rd_en          (cs_rd),
                                           .din            (data_inp[145:0]),
                                           .dout           (data_out[145:0]),
                                           .rdclk          (clk),
                                           .wrclk          (clk),
                                           .scan_in        (scan_in),
                                           .se             (se),
                                           .tcu_pce_ov     (tcu_pce_ov),
                                           .tcu_clk_stop   (tcu_aclk),
                                           .tcu_aclk       (tcu_bclk),
                                           .tcu_bclk       (tcu_bclk),
                                           .scan_out       (scan_out)
                                          );

endmodule