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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_rdmc.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niu_rdmc.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`define CACHE_LEN 8'd8
39`define CACHE_LEN_SUB1 `CACHE_LEN - 8'd1
40`define CACHE_LEN_SUB4 `CACHE_LEN - 8'd4
41
42`define SHADW_LEN 8'd16
43`define SHADW_LEN_SUB1 `SHADW_LEN - 8'd1
44`define SHADW_LEN_SUB4 `SHADW_LEN - 8'd4
45
46
47`define CHNL0 5'd0
48`define CHNL1 5'd1
49`define CHNL2 5'd2
50`define CHNL3 5'd3
51`define CHNL4 5'd4
52`define CHNL5 5'd5
53`define CHNL6 5'd6
54`define CHNL7 5'd7
55`define CHNL8 5'd8
56`define CHNL9 5'd9
57`define CHNL10 5'd10
58`define CHNL11 5'd11
59`define CHNL12 5'd12
60`define CHNL13 5'd13
61`define CHNL14 5'd14
62`define CHNL15 5'd15
63
64`define CHNL0_CACHE_START_ADDR 8'h00
65`define CHNL1_CACHE_START_ADDR 8'h08
66`define CHNL2_CACHE_START_ADDR 8'h10
67`define CHNL3_CACHE_START_ADDR 8'h18
68`define CHNL4_CACHE_START_ADDR 8'h20
69`define CHNL5_CACHE_START_ADDR 8'h28
70`define CHNL6_CACHE_START_ADDR 8'h30
71`define CHNL7_CACHE_START_ADDR 8'h38
72`define CHNL8_CACHE_START_ADDR 8'h40
73`define CHNL9_CACHE_START_ADDR 8'h48
74`define CHNL10_CACHE_START_ADDR 8'h50
75`define CHNL11_CACHE_START_ADDR 8'h58
76`define CHNL12_CACHE_START_ADDR 8'h60
77`define CHNL13_CACHE_START_ADDR 8'h68
78`define CHNL14_CACHE_START_ADDR 8'h70
79`define CHNL15_CACHE_START_ADDR 8'h78
80
81`define CHNL0_CACHE_END_ADDR `CHNL0_CACHE_START_ADDR + `CACHE_LEN_SUB1
82`define CHNL1_CACHE_END_ADDR `CHNL1_CACHE_START_ADDR + `CACHE_LEN_SUB1
83`define CHNL2_CACHE_END_ADDR `CHNL2_CACHE_START_ADDR + `CACHE_LEN_SUB1
84`define CHNL3_CACHE_END_ADDR `CHNL3_CACHE_START_ADDR + `CACHE_LEN_SUB1
85`define CHNL4_CACHE_END_ADDR `CHNL4_CACHE_START_ADDR + `CACHE_LEN_SUB1
86`define CHNL5_CACHE_END_ADDR `CHNL5_CACHE_START_ADDR + `CACHE_LEN_SUB1
87`define CHNL6_CACHE_END_ADDR `CHNL6_CACHE_START_ADDR + `CACHE_LEN_SUB1
88`define CHNL7_CACHE_END_ADDR `CHNL7_CACHE_START_ADDR + `CACHE_LEN_SUB1
89`define CHNL8_CACHE_END_ADDR `CHNL8_CACHE_START_ADDR + `CACHE_LEN_SUB1
90`define CHNL9_CACHE_END_ADDR `CHNL9_CACHE_START_ADDR + `CACHE_LEN_SUB1
91`define CHNL10_CACHE_END_ADDR `CHNL10_CACHE_START_ADDR + `CACHE_LEN_SUB1
92`define CHNL11_CACHE_END_ADDR `CHNL11_CACHE_START_ADDR + `CACHE_LEN_SUB1
93`define CHNL12_CACHE_END_ADDR `CHNL12_CACHE_START_ADDR + `CACHE_LEN_SUB1
94`define CHNL13_CACHE_END_ADDR `CHNL13_CACHE_START_ADDR + `CACHE_LEN_SUB1
95`define CHNL14_CACHE_END_ADDR `CHNL14_CACHE_START_ADDR + `CACHE_LEN_SUB1
96`define CHNL15_CACHE_END_ADDR `CHNL15_CACHE_START_ADDR + `CACHE_LEN_SUB1
97
98`define SHADW_MAX_ADDR_CNT 8'd32
99
100`define CHNL0_SHADW_START_ADDR 8'h00
101`define CHNL1_SHADW_START_ADDR 8'h10
102`define CHNL2_SHADW_START_ADDR 8'h20
103`define CHNL3_SHADW_START_ADDR 8'h30
104`define CHNL4_SHADW_START_ADDR 8'h40
105`define CHNL5_SHADW_START_ADDR 8'h50
106`define CHNL6_SHADW_START_ADDR 8'h60
107`define CHNL7_SHADW_START_ADDR 8'h70
108`define CHNL8_SHADW_START_ADDR 8'h80
109`define CHNL9_SHADW_START_ADDR 8'h90
110`define CHNL10_SHADW_START_ADDR 8'ha0
111`define CHNL11_SHADW_START_ADDR 8'hb0
112`define CHNL12_SHADW_START_ADDR 8'hc0
113`define CHNL13_SHADW_START_ADDR 8'hd0
114`define CHNL14_SHADW_START_ADDR 8'he0
115`define CHNL15_SHADW_START_ADDR 8'hf0
116
117`define CHNL0_SHADW_WR_END_ADDR `CHNL0_SHADW_START_ADDR + `SHADW_LEN_SUB1
118`define CHNL1_SHADW_WR_END_ADDR `CHNL1_SHADW_START_ADDR + `SHADW_LEN_SUB1
119`define CHNL2_SHADW_WR_END_ADDR `CHNL2_SHADW_START_ADDR + `SHADW_LEN_SUB1
120`define CHNL3_SHADW_WR_END_ADDR `CHNL3_SHADW_START_ADDR + `SHADW_LEN_SUB1
121`define CHNL4_SHADW_WR_END_ADDR `CHNL4_SHADW_START_ADDR + `SHADW_LEN_SUB1
122`define CHNL5_SHADW_WR_END_ADDR `CHNL5_SHADW_START_ADDR + `SHADW_LEN_SUB1
123`define CHNL6_SHADW_WR_END_ADDR `CHNL6_SHADW_START_ADDR + `SHADW_LEN_SUB1
124`define CHNL7_SHADW_WR_END_ADDR `CHNL7_SHADW_START_ADDR + `SHADW_LEN_SUB1
125`define CHNL8_SHADW_WR_END_ADDR `CHNL8_SHADW_START_ADDR + `SHADW_LEN_SUB1
126`define CHNL9_SHADW_WR_END_ADDR `CHNL9_SHADW_START_ADDR + `SHADW_LEN_SUB1
127`define CHNL10_SHADW_WR_END_ADDR `CHNL10_SHADW_START_ADDR + `SHADW_LEN_SUB1
128`define CHNL11_SHADW_WR_END_ADDR `CHNL11_SHADW_START_ADDR + `SHADW_LEN_SUB1
129`define CHNL12_SHADW_WR_END_ADDR `CHNL12_SHADW_START_ADDR + `SHADW_LEN_SUB1
130`define CHNL13_SHADW_WR_END_ADDR `CHNL13_SHADW_START_ADDR + `SHADW_LEN_SUB1
131`define CHNL14_SHADW_WR_END_ADDR `CHNL14_SHADW_START_ADDR + `SHADW_LEN_SUB1
132`define CHNL15_SHADW_WR_END_ADDR `CHNL15_SHADW_START_ADDR + `SHADW_LEN_SUB1
133
134`define CHNL0_SHADW_RD_END_ADDR `CHNL0_SHADW_START_ADDR + `SHADW_LEN_SUB4
135`define CHNL1_SHADW_RD_END_ADDR `CHNL1_SHADW_START_ADDR + `SHADW_LEN_SUB4
136`define CHNL2_SHADW_RD_END_ADDR `CHNL2_SHADW_START_ADDR + `SHADW_LEN_SUB4
137`define CHNL3_SHADW_RD_END_ADDR `CHNL3_SHADW_START_ADDR + `SHADW_LEN_SUB4
138`define CHNL4_SHADW_RD_END_ADDR `CHNL4_SHADW_START_ADDR + `SHADW_LEN_SUB4
139`define CHNL5_SHADW_RD_END_ADDR `CHNL5_SHADW_START_ADDR + `SHADW_LEN_SUB4
140`define CHNL6_SHADW_RD_END_ADDR `CHNL6_SHADW_START_ADDR + `SHADW_LEN_SUB4
141`define CHNL7_SHADW_RD_END_ADDR `CHNL7_SHADW_START_ADDR + `SHADW_LEN_SUB4
142`define CHNL8_SHADW_RD_END_ADDR `CHNL8_SHADW_START_ADDR + `SHADW_LEN_SUB4
143`define CHNL9_SHADW_RD_END_ADDR `CHNL9_SHADW_START_ADDR + `SHADW_LEN_SUB4
144`define CHNL10_SHADW_RD_END_ADDR `CHNL10_SHADW_START_ADDR + `SHADW_LEN_SUB4
145`define CHNL11_SHADW_RD_END_ADDR `CHNL11_SHADW_START_ADDR + `SHADW_LEN_SUB4
146`define CHNL12_SHADW_RD_END_ADDR `CHNL12_SHADW_START_ADDR + `SHADW_LEN_SUB4
147`define CHNL13_SHADW_RD_END_ADDR `CHNL13_SHADW_START_ADDR + `SHADW_LEN_SUB4
148`define CHNL14_SHADW_RD_END_ADDR `CHNL14_SHADW_START_ADDR + `SHADW_LEN_SUB4
149`define CHNL15_SHADW_RD_END_ADDR `CHNL15_SHADW_START_ADDR + `SHADW_LEN_SUB4
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Full OpenSPARC design & verification tarball including full HDL.