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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rdmc_chnl_pio_if.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module niu_rdmc_chnl_pio_if ( | |
36 | clk, | |
37 | reset, | |
38 | dma_chnl_grp_id, | |
39 | pio_32b_mode, | |
40 | pio_wen, | |
41 | pio_addr, | |
42 | pio_wdata, | |
43 | reset_rcr_flush, | |
44 | m_bit_en, | |
45 | rcr_ctl_stat_word, | |
46 | desp_curr_addr, | |
47 | desp_curr_cnt, | |
48 | desp_addr_not_valid, | |
49 | buf_addr_not_valid, | |
50 | rbr_addr_overflow, | |
51 | desp_curr_cnt_overflow, | |
52 | rbr_empty, | |
53 | muxed_drop_pkt_r, | |
54 | wred_drop_pkt, | |
55 | rcr_drop_pkt, | |
56 | rbr_drop_pkt, | |
57 | chnl_sel_buf_en, | |
58 | rcr_curr_addr, | |
59 | rcr_status_a, | |
60 | rcr_addr_not_valid, | |
61 | mbox_addr_not_valid, | |
62 | rcr_addr_overflow, | |
63 | rcr_curr_cnt_overflow, | |
64 | rcr_curr_cnt_underflow, | |
65 | rcr_pkt_cnt_underflow, | |
66 | rcr_idle_cycle, | |
67 | chnl_has_pkt, | |
68 | chnl_shadw_parity_err, | |
69 | rbr_idle_cycle, | |
70 | chnl_cache_parity_err, | |
71 | resp_bus_err, | |
72 | resp_bus_err_type, | |
73 | rcr_ack_err, | |
74 | data_err_event, | |
75 | rdmc_wr_data_dma_num, | |
76 | ||
77 | dma_reset, | |
78 | dma_en, | |
79 | dma_data_offset, | |
80 | full_header, | |
81 | page_valid0, | |
82 | addr_mask0, | |
83 | comp_value0, | |
84 | relo_value0, | |
85 | page_valid1, | |
86 | addr_mask1, | |
87 | comp_value1, | |
88 | relo_value1, | |
89 | dma_fatal_err, | |
90 | rx_log_page_hdl_reg, | |
91 | dma_func_num, | |
92 | rdc_red_param_reg, | |
93 | rbr_cfig_a_reg, | |
94 | rbr_cfig_b_reg, | |
95 | rbr_kick_reg, | |
96 | rcr_cfig_a_reg, | |
97 | rcr_cfig_b_reg, | |
98 | rx_dma_ctl_stat_reg_s, | |
99 | rx_dma_ctl_stat_reg_bit47, | |
100 | rcr_flush_reg, | |
101 | mbox_addr, | |
102 | mailbox_data, | |
103 | ldf_a, | |
104 | ldf_b, | |
105 | rbr_cfig_a_reg_wenu, | |
106 | rbr_cfig_a_reg_wenl, | |
107 | rbr_kick_reg_wen, | |
108 | rcr_cfig_a_reg_wenu, | |
109 | rcr_cfig_a_reg_wenl, | |
110 | rx_dma_ctl_stat_reg_wenu, | |
111 | rx_dma_ctl_stat_reg_wenl, | |
112 | pio_rd_gnt, | |
113 | chnl_pio_rd_data | |
114 | ||
115 | ); | |
116 | input clk; | |
117 | input reset; | |
118 | input[4:0] dma_chnl_grp_id; | |
119 | input pio_32b_mode; | |
120 | input pio_wen; | |
121 | input[19:0] pio_addr; | |
122 | input[63:0] pio_wdata; | |
123 | input reset_rcr_flush; | |
124 | input m_bit_en; | |
125 | input[2:0] rcr_ctl_stat_word; | |
126 | input[15:0] desp_curr_addr; | |
127 | input[16:0] desp_curr_cnt; | |
128 | input desp_addr_not_valid; | |
129 | input buf_addr_not_valid; | |
130 | input rbr_addr_overflow; | |
131 | input desp_curr_cnt_overflow; | |
132 | input rbr_empty; | |
133 | input muxed_drop_pkt_r; | |
134 | input wred_drop_pkt; | |
135 | input rcr_drop_pkt; | |
136 | input rbr_drop_pkt; | |
137 | input chnl_sel_buf_en; | |
138 | input[15:0] rcr_curr_addr; | |
139 | input[15:0] rcr_status_a; | |
140 | input rcr_addr_not_valid; | |
141 | input mbox_addr_not_valid; | |
142 | input rcr_addr_overflow; | |
143 | input rcr_curr_cnt_overflow; | |
144 | input rcr_curr_cnt_underflow; | |
145 | input rcr_pkt_cnt_underflow; | |
146 | input rcr_idle_cycle; | |
147 | input rbr_idle_cycle; | |
148 | input chnl_has_pkt; | |
149 | input chnl_shadw_parity_err; | |
150 | input chnl_cache_parity_err; | |
151 | input resp_bus_err; | |
152 | input[3:0] resp_bus_err_type; | |
153 | input rcr_ack_err; | |
154 | input data_err_event; | |
155 | input[4:0] rdmc_wr_data_dma_num; | |
156 | ||
157 | output dma_reset; | |
158 | output dma_en; | |
159 | output[1:0] dma_data_offset; | |
160 | output full_header; | |
161 | output page_valid0; | |
162 | output[31:0] addr_mask0; | |
163 | output[31:0] comp_value0; | |
164 | output[31:0] relo_value0; | |
165 | output page_valid1; | |
166 | output[31:0] addr_mask1; | |
167 | output[31:0] comp_value1; | |
168 | output[31:0] relo_value1; | |
169 | output dma_fatal_err; | |
170 | output[19:0] rx_log_page_hdl_reg; | |
171 | output[1:0] dma_func_num; | |
172 | output[31:0] rdc_red_param_reg; | |
173 | output[53:0] rbr_cfig_a_reg; | |
174 | output[10:0] rbr_cfig_b_reg; | |
175 | output[15:0] rbr_kick_reg; | |
176 | output[53:0] rcr_cfig_a_reg; | |
177 | output[22:0] rcr_cfig_b_reg; | |
178 | output[31:0] rx_dma_ctl_stat_reg_s; | |
179 | output rx_dma_ctl_stat_reg_bit47; | |
180 | output rcr_flush_reg; | |
181 | output[43:0] mbox_addr; | |
182 | output[168:0] mailbox_data; | |
183 | output ldf_a; | |
184 | output ldf_b; | |
185 | output rbr_cfig_a_reg_wenu; | |
186 | output rbr_cfig_a_reg_wenl; | |
187 | output rbr_kick_reg_wen; | |
188 | output rcr_cfig_a_reg_wenu; | |
189 | output rcr_cfig_a_reg_wenl; | |
190 | output rx_dma_ctl_stat_reg_wenu; | |
191 | output rx_dma_ctl_stat_reg_wenl; | |
192 | output pio_rd_gnt; | |
193 | output[63:0] chnl_pio_rd_data; | |
194 | ||
195 | reg dma_reset; | |
196 | reg[1:0] dma_reset_cnt; | |
197 | ||
198 | reg[3:0] rx_log_page_vld_reg; | |
199 | reg[31:0] rx_log_mask1_reg; | |
200 | reg[31:0] rx_log_val1_reg; | |
201 | reg[31:0] rx_log_mask2_reg; | |
202 | reg[31:0] rx_log_val2_reg; | |
203 | reg[31:0] rx_log_page_relo1_reg; | |
204 | reg[31:0] rx_log_page_relo2_reg; | |
205 | reg[19:0] rx_log_page_hdl_reg; | |
206 | reg[31:0] rdc_red_param_reg; | |
207 | ||
208 | reg[14:0] rxdma_cfig1_reg; | |
209 | reg[28:0] rxdma_cfig2_reg; | |
210 | reg[53:0] rbr_cfig_a_reg; | |
211 | reg[10:0] rbr_cfig_b_reg; | |
212 | reg[15:0] rbr_kick_reg; | |
213 | reg[53:0] rcr_cfig_a_reg; | |
214 | reg[22:0] rcr_cfig_b_reg; | |
215 | reg[20:0] rx_dma_ent_mask_reg; | |
216 | reg[53:0] rx_dma_ctl_stat_reg; | |
217 | reg rcr_flush_reg; | |
218 | reg[16:0] rx_dma_pkt_drop_cnt_reg; | |
219 | reg[16:0] rx_dma_wred_drop_cnt_reg; | |
220 | reg[10:0] fatal_err_reg; | |
221 | reg fatal_err_all_d; | |
222 | reg pio_disable_dma; | |
223 | ||
224 | reg fzc_pio_rd_err_tmp; | |
225 | reg[63:0] fzc_pio_rd_data_tmp; | |
226 | reg pio_rd_err_tmp; | |
227 | reg[63:0] pio_rd_data_tmp; | |
228 | reg pio_rd_err_tmp_32b; | |
229 | reg[63:0] pio_rd_data_tmp_32b; | |
230 | ||
231 | reg pio_rd_gnt; | |
232 | reg[63:0] chnl_pio_rd_data; | |
233 | ||
234 | reg rbr_empty_r; | |
235 | ||
236 | reg ldf_a; | |
237 | reg ldf_b; | |
238 | ||
239 | wire fatal_err_all_p; | |
240 | wire dma_fatal_err; | |
241 | ||
242 | wire addr_match1 = (pio_addr[10:6] == dma_chnl_grp_id); | |
243 | wire[19:0] pio_addr1 = {pio_addr[19:11], 5'b0, pio_addr[5:0]}; | |
244 | ||
245 | wire rx_log_page_vld_reg_wen = pio_wen & (pio_addr1 == 20'ha0000) & addr_match1; | |
246 | wire rx_log_mask1_reg_wen = pio_wen & (pio_addr1 == 20'ha0008) & addr_match1; | |
247 | wire rx_log_val1_reg_wen = pio_wen & (pio_addr1 == 20'ha0010) & addr_match1; | |
248 | wire rx_log_mask2_reg_wen = pio_wen & (pio_addr1 == 20'ha0018) & addr_match1; | |
249 | wire rx_log_val2_reg_wen = pio_wen & (pio_addr1 == 20'ha0020) & addr_match1; | |
250 | wire rx_log_page_relo1_reg_wen = pio_wen & (pio_addr1 == 20'ha0028) & addr_match1; | |
251 | wire rx_log_page_relo2_reg_wen = pio_wen & (pio_addr1 == 20'ha0030) & addr_match1; | |
252 | wire rx_log_page_hdl_reg_wen = pio_wen & (pio_addr1 == 20'ha0038) & addr_match1; | |
253 | wire rdc_red_param_reg_wen = pio_wen & (pio_addr1 == 20'hb0000) & addr_match1; | |
254 | wire rx_dma_wred_drop_cnt_reg_wen = pio_wen & (pio_addr1 == 20'hb0008) & addr_match1; | |
255 | ||
256 | wire addr_match2 = (pio_addr[13:9] == dma_chnl_grp_id); | |
257 | wire[19:0] pio_addr2 = {pio_addr[19:14], 5'b0, pio_addr[8:0]}; | |
258 | ||
259 | wire rxdma_cfig1_reg_wen = pio_wen & (pio_addr2 == 20'h00000) & addr_match2; | |
260 | wire rxdma_cfig2_reg_wen = pio_wen & (pio_addr2 == 20'h00008) & addr_match2; | |
261 | wire rbr_cfig_a_reg_wen = pio_wen & (pio_addr2 == 20'h00010) & addr_match2; | |
262 | wire rbr_cfig_a_reg_wen_32b = pio_wen & (pio_addr2 == 20'h00014) & addr_match2; | |
263 | ||
264 | wire rbr_cfig_b_reg_wen = pio_wen & (pio_addr2 == 20'h00018) & addr_match2; | |
265 | wire rbr_kick_reg_wen = pio_wen & (pio_addr2 == 20'h00020) & addr_match2; | |
266 | //wire rbr_stat_reg_wen = pio_wen & (pio_addr2 == 20'h00028) & addr_match2;RO reg | |
267 | //wire rbr_head_h_reg_wen = pio_wen & (pio_addr2 == 20'h00030) & addr_match2;RO reg | |
268 | //wire rbr_head_l_reg_wen = pio_wen & (pio_addr2 == 20'h00038) & addr_match2;RO reg | |
269 | ||
270 | wire rcr_cfig_a_reg_wen = pio_wen & (pio_addr2 == 20'h00040) & addr_match2; | |
271 | wire rcr_cfig_a_reg_wen_32b = pio_wen & (pio_addr2 == 20'h00044) & addr_match2; | |
272 | ||
273 | wire rcr_cfig_b_reg_wen = pio_wen & (pio_addr2 == 20'h00048) & addr_match2; | |
274 | ||
275 | wire rx_dma_ent_mask_reg_wen = pio_wen & (pio_addr2 == 20'h00068) & addr_match2; | |
276 | wire rx_dma_ctl_stat_reg_wen = pio_wen & (pio_addr2 == 20'h00070) & addr_match2; | |
277 | wire rx_dma_ctl_stat_reg_wen_32b = pio_wen & (pio_addr2 == 20'h00074) & addr_match2; | |
278 | ||
279 | wire rcr_flush_reg_wen = pio_wen & (pio_addr2 == 20'h00078) & addr_match2; | |
280 | wire rx_dma_pkt_drop_cnt_reg_wen = pio_wen & (pio_addr2 == 20'h00090) & addr_match2; | |
281 | ||
282 | wire rx_dma_ctl_stat_reg_wr = pio_wen & (pio_addr2 == 20'h00098) & addr_match2; | |
283 | wire rx_dma_ctl_stat_reg_wr_32b = pio_wen & (pio_addr2 == 20'h0009c) & addr_match2; | |
284 | ||
285 | wire dma_en = rxdma_cfig1_reg[14]; | |
286 | wire pio_dma_rst = rxdma_cfig1_reg[13]; | |
287 | //wire dma_idle_cycle = rxdma_cfig1_reg[12]; | |
288 | wire full_header = rxdma_cfig2_reg[0]; | |
289 | wire[1:0] dma_data_offset = rxdma_cfig2_reg[2:1]; | |
290 | wire[43:0] mbox_addr = {rxdma_cfig1_reg[11:0], rxdma_cfig2_reg[28:3], 6'b0}; | |
291 | ||
292 | wire[31:0] addr_mask0 = rx_log_mask1_reg[31:0]; | |
293 | wire[31:0] addr_mask1 = rx_log_mask2_reg[31:0]; | |
294 | wire[31:0] comp_value0 = rx_log_val1_reg[31:0]; | |
295 | wire[31:0] comp_value1 = rx_log_val2_reg[31:0]; | |
296 | wire[31:0] relo_value0 = rx_log_page_relo1_reg[31:0]; | |
297 | wire[31:0] relo_value1 = rx_log_page_relo2_reg[31:0]; | |
298 | ||
299 | wire page_valid0 = rx_log_page_vld_reg[0] & dma_en; | |
300 | wire page_valid1 = rx_log_page_vld_reg[1] & dma_en; | |
301 | wire[1:0] dma_func_num = rx_log_page_vld_reg[3:2]; | |
302 | wire page_not_valid = !(page_valid0 | page_valid1) & dma_en; | |
303 | ||
304 | wire idle_cycle; | |
305 | ||
306 | wire rx_dma_ctl_stat_reg_wenl = rx_dma_ctl_stat_reg_wen; | |
307 | wire rx_dma_ctl_stat_reg_wenu = rx_dma_ctl_stat_reg_wen & !pio_32b_mode | rx_dma_ctl_stat_reg_wen_32b & pio_32b_mode; | |
308 | ||
309 | wire rbr_cfig_a_reg_wenl = rbr_cfig_a_reg_wen; | |
310 | wire rbr_cfig_a_reg_wenu = rbr_cfig_a_reg_wen & !pio_32b_mode | rbr_cfig_a_reg_wen_32b & pio_32b_mode; | |
311 | ||
312 | wire rcr_cfig_a_reg_wenl = rcr_cfig_a_reg_wen; | |
313 | wire rcr_cfig_a_reg_wenu = rcr_cfig_a_reg_wen & !pio_32b_mode | rcr_cfig_a_reg_wen_32b & pio_32b_mode; | |
314 | ||
315 | /*************************/ | |
316 | //Status from RBR, RCR | |
317 | /*************************/ | |
318 | wire[25:0] rbr_base_addr = rbr_cfig_a_reg[37:12]; | |
319 | wire[41:0] desp_full_addr = {rbr_base_addr[25:0], desp_curr_addr[15:0]}; | |
320 | ||
321 | wire[24:0] rcr_base_addr = rcr_cfig_a_reg[37:13]; | |
322 | wire[40:0] rcr_full_addr = {rcr_base_addr[24:0], rcr_curr_addr[15:0]}; | |
323 | ||
324 | wire[168:0] mailbox_data = {rcr_status_a[15:0], | |
325 | rcr_full_addr[40:0], | |
326 | desp_full_addr[41:0], | |
327 | desp_curr_cnt[15:0], | |
328 | rx_dma_ctl_stat_reg[53:0]}; | |
329 | ||
330 | always @ (posedge clk) | |
331 | if (reset) | |
332 | rx_log_page_vld_reg <= 4'b0; | |
333 | else if (dma_reset) | |
334 | rx_log_page_vld_reg <= 4'b0; | |
335 | else if (rx_log_page_vld_reg_wen) | |
336 | rx_log_page_vld_reg <= pio_wdata[3:0]; | |
337 | else | |
338 | rx_log_page_vld_reg <= rx_log_page_vld_reg; | |
339 | ||
340 | always @ (posedge clk) | |
341 | if (reset) | |
342 | rx_log_mask1_reg <= 32'b0; | |
343 | else if (dma_reset) | |
344 | rx_log_mask1_reg <= 32'b0; | |
345 | else if (rx_log_mask1_reg_wen) | |
346 | rx_log_mask1_reg <= pio_wdata[31:0]; | |
347 | else | |
348 | rx_log_mask1_reg <= rx_log_mask1_reg; | |
349 | ||
350 | always @ (posedge clk) | |
351 | if (reset) | |
352 | rx_log_val1_reg <= 32'b0; | |
353 | else if (dma_reset) | |
354 | rx_log_val1_reg <= 32'b0; | |
355 | else if (rx_log_val1_reg_wen) | |
356 | rx_log_val1_reg <= pio_wdata[31:0]; | |
357 | else | |
358 | rx_log_val1_reg <= rx_log_val1_reg; | |
359 | ||
360 | always @ (posedge clk) | |
361 | if (reset) | |
362 | rx_log_mask2_reg <= 32'b0; | |
363 | else if (dma_reset) | |
364 | rx_log_mask2_reg <= 32'b0; | |
365 | else if (rx_log_mask2_reg_wen) | |
366 | rx_log_mask2_reg <= pio_wdata[31:0]; | |
367 | else | |
368 | rx_log_mask2_reg <= rx_log_mask2_reg; | |
369 | ||
370 | always @ (posedge clk) | |
371 | if (reset) | |
372 | rx_log_val2_reg <= 32'b0; | |
373 | else if (dma_reset) | |
374 | rx_log_val2_reg <= 32'b0; | |
375 | else if (rx_log_val2_reg_wen) | |
376 | rx_log_val2_reg <= pio_wdata[31:0]; | |
377 | else | |
378 | rx_log_val2_reg <= rx_log_val2_reg; | |
379 | ||
380 | always @ (posedge clk) | |
381 | if (reset) | |
382 | rx_log_page_relo1_reg <= 32'b0; | |
383 | else if (dma_reset) | |
384 | rx_log_page_relo1_reg <= 32'b0; | |
385 | else if (rx_log_page_relo1_reg_wen) | |
386 | rx_log_page_relo1_reg <= pio_wdata[31:0]; | |
387 | else | |
388 | rx_log_page_relo1_reg <= rx_log_page_relo1_reg; | |
389 | ||
390 | ||
391 | always @ (posedge clk) | |
392 | if (reset) | |
393 | rx_log_page_relo2_reg <= 32'b0; | |
394 | else if (dma_reset) | |
395 | rx_log_page_relo2_reg <= 32'b0; | |
396 | else if (rx_log_page_relo2_reg_wen) | |
397 | rx_log_page_relo2_reg <= pio_wdata[31:0]; | |
398 | else | |
399 | rx_log_page_relo2_reg <= rx_log_page_relo2_reg; | |
400 | ||
401 | ||
402 | always @ (posedge clk) | |
403 | if (reset) | |
404 | rx_log_page_hdl_reg <= 20'b0; | |
405 | else if (dma_reset) | |
406 | rx_log_page_hdl_reg <= 20'b0; | |
407 | else if (rx_log_page_hdl_reg_wen) | |
408 | rx_log_page_hdl_reg <= pio_wdata[19:0]; | |
409 | else | |
410 | rx_log_page_hdl_reg <= rx_log_page_hdl_reg; | |
411 | ||
412 | always @ (posedge clk) | |
413 | if (reset) | |
414 | rdc_red_param_reg <= 32'b0; | |
415 | else if (dma_reset) | |
416 | rdc_red_param_reg <= 32'b0; | |
417 | else if (rdc_red_param_reg_wen) | |
418 | rdc_red_param_reg <= pio_wdata[31:0]; | |
419 | else | |
420 | rdc_red_param_reg <= rdc_red_param_reg; | |
421 | ||
422 | wire disable_dma_ture = dma_en & !pio_wdata[31]; | |
423 | wire dam_en_bit = disable_dma_ture ? 1'b1 : pio_wdata[31]; | |
424 | ||
425 | always @ (posedge clk) | |
426 | if (reset) | |
427 | rxdma_cfig1_reg <= 15'b0; | |
428 | else if (dma_reset) | |
429 | rxdma_cfig1_reg <= 15'b0; | |
430 | else if (rxdma_cfig1_reg_wen) | |
431 | rxdma_cfig1_reg <= {dam_en_bit, pio_wdata[30:29], pio_wdata[11:0]}; | |
432 | else if (fatal_err_all_p | idle_cycle & pio_disable_dma) | |
433 | rxdma_cfig1_reg <= {1'b0, rxdma_cfig1_reg[13:0]}; | |
434 | else | |
435 | rxdma_cfig1_reg <= {rxdma_cfig1_reg[14:13], idle_cycle, rxdma_cfig1_reg[11:0]}; | |
436 | ||
437 | always @ (posedge clk) | |
438 | if (reset) | |
439 | rxdma_cfig2_reg <= 29'b0; | |
440 | else if (dma_reset) | |
441 | rxdma_cfig2_reg <= 29'b0; | |
442 | else if (rxdma_cfig2_reg_wen) | |
443 | rxdma_cfig2_reg <= {pio_wdata[31:6], pio_wdata[2:0]}; | |
444 | else | |
445 | rxdma_cfig2_reg <= rxdma_cfig2_reg; | |
446 | ||
447 | ||
448 | always @ (posedge clk) | |
449 | if (reset) | |
450 | rbr_cfig_a_reg <= 54'b0; | |
451 | else if (dma_reset) | |
452 | rbr_cfig_a_reg <= 54'b0; | |
453 | else if (pio_32b_mode & rbr_cfig_a_reg_wen) | |
454 | rbr_cfig_a_reg <= {rbr_cfig_a_reg[53:26], pio_wdata[31:6]}; | |
455 | else if (pio_32b_mode & rbr_cfig_a_reg_wen_32b) | |
456 | rbr_cfig_a_reg <= {pio_wdata[31:16], pio_wdata[11:0], rbr_cfig_a_reg[25:0]}; | |
457 | else if (rbr_cfig_a_reg_wen) | |
458 | rbr_cfig_a_reg <= {pio_wdata[63:48], pio_wdata[43:6]}; | |
459 | else | |
460 | rbr_cfig_a_reg <= rbr_cfig_a_reg; | |
461 | ||
462 | ||
463 | always @ (posedge clk) | |
464 | if (reset) | |
465 | rbr_cfig_b_reg <= 11'b0; | |
466 | else if (dma_reset) | |
467 | rbr_cfig_b_reg <= 11'b0; | |
468 | else if (rbr_cfig_b_reg_wen) | |
469 | rbr_cfig_b_reg <= {pio_wdata[25:24], | |
470 | pio_wdata[23], pio_wdata[17:16], | |
471 | pio_wdata[15], pio_wdata[9:8], | |
472 | pio_wdata[7], pio_wdata[1:0]}; | |
473 | else | |
474 | rbr_cfig_b_reg <= rbr_cfig_b_reg; | |
475 | ||
476 | always @ (posedge clk) | |
477 | if (reset) | |
478 | rbr_kick_reg <= 16'b0; | |
479 | else if (dma_reset) | |
480 | rbr_kick_reg <= 16'b0; | |
481 | else if (rbr_kick_reg_wen) | |
482 | rbr_kick_reg <= pio_wdata[15:0]; | |
483 | else | |
484 | rbr_kick_reg <= rbr_kick_reg; | |
485 | ||
486 | ||
487 | always @ (posedge clk) | |
488 | if (reset) | |
489 | rcr_cfig_a_reg <= 54'b0; | |
490 | else if (dma_reset) | |
491 | rcr_cfig_a_reg <= 54'b0; | |
492 | else if (pio_32b_mode & rcr_cfig_a_reg_wen) | |
493 | rcr_cfig_a_reg <= {rcr_cfig_a_reg[53:26], pio_wdata[31:6]}; | |
494 | else if (pio_32b_mode & rcr_cfig_a_reg_wen_32b) | |
495 | rcr_cfig_a_reg <= {pio_wdata[31:16], pio_wdata[11:0], rcr_cfig_a_reg[25:0]}; | |
496 | else if (rcr_cfig_a_reg_wen) | |
497 | rcr_cfig_a_reg <= {pio_wdata[63:48], pio_wdata[43:6]}; | |
498 | else | |
499 | rcr_cfig_a_reg <= rcr_cfig_a_reg; | |
500 | ||
501 | ||
502 | always @ (posedge clk) | |
503 | if (reset) | |
504 | rcr_cfig_b_reg <= 23'b0; | |
505 | else if (dma_reset) | |
506 | rcr_cfig_b_reg <= 23'b0; | |
507 | else if (rcr_cfig_b_reg_wen) | |
508 | rcr_cfig_b_reg <= {pio_wdata[31:16], pio_wdata[15], pio_wdata[5:0]}; | |
509 | else | |
510 | rcr_cfig_b_reg <= rcr_cfig_b_reg; | |
511 | ||
512 | always @ (posedge clk) | |
513 | if (reset) | |
514 | rx_dma_ent_mask_reg <= 21'h1f_ffff; | |
515 | else if (dma_reset) | |
516 | rx_dma_ent_mask_reg <= 21'h1f_ffff; | |
517 | else if (rx_dma_ent_mask_reg_wen) | |
518 | rx_dma_ent_mask_reg <= {pio_wdata[21:16], pio_wdata[14:0]}; | |
519 | else | |
520 | rx_dma_ent_mask_reg <= rx_dma_ent_mask_reg; | |
521 | ||
522 | ||
523 | always @ (posedge clk) | |
524 | if (reset) | |
525 | rcr_flush_reg <= 1'b0; | |
526 | else if (dma_reset) | |
527 | rcr_flush_reg <= 1'b0; | |
528 | else if (rcr_flush_reg_wen) | |
529 | rcr_flush_reg <= pio_wdata[0]; | |
530 | else if (reset_rcr_flush & rcr_flush_reg) | |
531 | rcr_flush_reg <= 1'b0; | |
532 | else | |
533 | rcr_flush_reg <= rcr_flush_reg; | |
534 | ||
535 | ||
536 | /**********************************/ | |
537 | //Status Reg and Interrupt | |
538 | /**********************************/ | |
539 | wire[31:0] rx_dma_ctl_stat_reg_s = rx_dma_ctl_stat_reg[31:0]; | |
540 | wire rx_dma_ctl_stat_reg_bit47 = rx_dma_ctl_stat_reg[47]; | |
541 | ||
542 | wire rbr_empty_p = rbr_empty & !rbr_empty_r; | |
543 | wire[20:0] rx_dma_ctl_stat_reg_tmp = {rx_dma_ctl_stat_reg[53:48], rx_dma_ctl_stat_reg[46:32]}; | |
544 | wire[20:0] intr_trig = (~rx_dma_ent_mask_reg) & rx_dma_ctl_stat_reg_tmp; | |
545 | wire ldf_a_tmp = (|intr_trig[14:13]); | |
546 | wire ldf_b_tmp = ((|intr_trig[12:0]) | (|intr_trig[20:15])); | |
547 | ||
548 | ||
549 | wire is_port_drop_pkt = chnl_sel_buf_en & muxed_drop_pkt_r; | |
550 | wire is_wred_drop_pkt = chnl_sel_buf_en & wred_drop_pkt; | |
551 | wire is_rbr_drop_pkt = chnl_sel_buf_en & rbr_drop_pkt; | |
552 | wire is_rcr_drop_pkt = chnl_sel_buf_en & rcr_drop_pkt; | |
553 | wire is_drop_pkt = (muxed_drop_pkt_r | rbr_drop_pkt | rcr_drop_pkt) & chnl_sel_buf_en; | |
554 | wire chnl_data_err_event= data_err_event & (rdmc_wr_data_dma_num == dma_chnl_grp_id); | |
555 | ||
556 | //wire[16:0] pio_wdata_h= pio_32b_mode ? pio_wdata[16:0] : pio_wdata[48:32]; | |
557 | ||
558 | wire pio_wdata_h_16 = pio_32b_mode ? pio_wdata[16] : pio_wdata[48]; | |
559 | wire pio_wdata_h_15 = pio_32b_mode ? pio_wdata[15] : pio_wdata[47]; | |
560 | wire pio_wdata_h_14 = pio_32b_mode ? pio_wdata[14] : pio_wdata[46]; | |
561 | wire pio_wdata_h_13 = pio_32b_mode ? pio_wdata[13] : pio_wdata[45]; | |
562 | wire pio_wdata_h_3 = pio_32b_mode ? pio_wdata[3] : pio_wdata[35]; | |
563 | wire pio_wdata_h_10 = pio_32b_mode ? pio_wdata[10] : pio_wdata[42]; | |
564 | wire pio_wdata_h_9 = pio_32b_mode ? pio_wdata[9] : pio_wdata[41]; | |
565 | wire pio_wdata_h_8 = pio_32b_mode ? pio_wdata[8] : pio_wdata[40]; | |
566 | wire pio_wdata_h_7 = pio_32b_mode ? pio_wdata[7] : pio_wdata[39]; | |
567 | ||
568 | wire pio_data_err_bit = pio_wdata_h_16 ? 1'b0 : rx_dma_ctl_stat_reg[48]; | |
569 | wire pio_thresh_bit = pio_wdata_h_14 ? 1'b0 : rx_dma_ctl_stat_reg[46]; | |
570 | wire pio_rcrto_bit = pio_wdata_h_13 ? 1'b0 : rx_dma_ctl_stat_reg[45]; | |
571 | wire pio_rbr_empty_bit = pio_wdata_h_3 ? 1'b0 : rx_dma_ctl_stat_reg[35]; | |
572 | ||
573 | wire pio_port_drop_bit = pio_wdata_h_10 ? 1'b0 : rx_dma_ctl_stat_reg[42]; | |
574 | wire pio_wred_drop_bit = pio_wdata_h_9 ? 1'b0 : rx_dma_ctl_stat_reg[41]; | |
575 | wire pio_rbr_drop_bit = pio_wdata_h_8 ? 1'b0 : rx_dma_ctl_stat_reg[40]; | |
576 | wire pio_rcr_drop_bit = pio_wdata_h_7 ? 1'b0 : rx_dma_ctl_stat_reg[39]; | |
577 | ||
578 | ||
579 | wire[53:0] pio_rx_dma_ctl_stat_word = {rx_dma_ctl_stat_reg[53:49], pio_data_err_bit, | |
580 | pio_wdata_h_15, pio_thresh_bit, pio_rcrto_bit, rx_dma_ctl_stat_reg[44:43], | |
581 | pio_port_drop_bit, pio_wred_drop_bit, pio_rbr_drop_bit, pio_rcr_drop_bit, | |
582 | rx_dma_ctl_stat_reg[38:36], pio_rbr_empty_bit, rx_dma_ctl_stat_reg[34:32], | |
583 | pio_wdata[31:0]}; | |
584 | ||
585 | wire config_not_valid = (page_not_valid | desp_addr_not_valid | rcr_addr_not_valid | mbox_addr_not_valid); | |
586 | wire rbr_rcr_addr_overflow = (rbr_addr_overflow | rcr_addr_overflow); | |
587 | wire rcr_cnt_underflow = (rcr_curr_cnt_underflow | rcr_pkt_cnt_underflow); | |
588 | ||
589 | assign idle_cycle = rcr_idle_cycle & rbr_idle_cycle & !chnl_has_pkt; | |
590 | wire[3:0] resp_err = {4{resp_bus_err}} & resp_bus_err_type; | |
591 | wire[4:0] meta_bus_err = {resp_err, rcr_ack_err}; | |
592 | wire[10:0] fatal_err_event = {meta_bus_err, chnl_shadw_parity_err, chnl_cache_parity_err, | |
593 | rcr_cnt_underflow, rcr_curr_cnt_overflow, desp_curr_cnt_overflow, buf_addr_not_valid}; | |
594 | wire[10:0] fatal_err_bit_in = {11{idle_cycle}} & fatal_err_reg; | |
595 | ||
596 | wire[53:0] rx_dma_ctl_stat_word = {fatal_err_bit_in[10:6], chnl_data_err_event, | |
597 | rx_dma_ctl_stat_reg[47:45], fatal_err_bit_in[5], fatal_err_bit_in[4], | |
598 | is_port_drop_pkt, is_wred_drop_pkt, is_rbr_drop_pkt, is_rcr_drop_pkt, | |
599 | rbr_rcr_addr_overflow, fatal_err_bit_in[3], fatal_err_bit_in[2], | |
600 | rbr_empty_p, fatal_err_bit_in[1], fatal_err_bit_in[0], config_not_valid, | |
601 | rx_dma_ctl_stat_reg[31:0]}; | |
602 | ||
603 | wire[12:0] fatal_err = {rx_dma_ctl_stat_reg[53:49], | |
604 | rx_dma_ctl_stat_reg[44:43], rx_dma_ctl_stat_reg[38:36], rx_dma_ctl_stat_reg[34:32]}; | |
605 | wire fatal_err_all = |fatal_err; | |
606 | assign fatal_err_all_p = fatal_err_all & !fatal_err_all_d; | |
607 | assign dma_fatal_err = |fatal_err_reg | pio_disable_dma; | |
608 | ||
609 | always @ (posedge clk) | |
610 | if (reset) | |
611 | begin | |
612 | ldf_a <= 1'b0; | |
613 | ldf_b <= 1'b0; | |
614 | end | |
615 | else | |
616 | begin | |
617 | ldf_a <= ldf_a_tmp; | |
618 | ldf_b <= ldf_b_tmp; | |
619 | end | |
620 | ||
621 | ||
622 | always @ (posedge clk) | |
623 | if (reset) | |
624 | rbr_empty_r <= 1'b0; | |
625 | else if (dma_reset) | |
626 | rbr_empty_r <= 1'b0; | |
627 | else | |
628 | rbr_empty_r <= rbr_empty; | |
629 | ||
630 | ||
631 | always @ (posedge clk) | |
632 | if (reset) | |
633 | fatal_err_reg <= 11'b0; | |
634 | else if (dma_reset) | |
635 | fatal_err_reg <= 11'b0; | |
636 | else | |
637 | fatal_err_reg <= fatal_err_event | fatal_err_reg; | |
638 | ||
639 | ||
640 | wire[53:0] rx_dma_ctl_stat_reg_mex = {(rx_dma_ctl_stat_reg[53:48] | rx_dma_ctl_stat_word[53:48]), rcr_ctl_stat_word[2:0], | |
641 | (rx_dma_ctl_stat_reg[44:0] | rx_dma_ctl_stat_word[44:0])}; | |
642 | ||
643 | always @ (posedge clk) | |
644 | if (reset) | |
645 | rx_dma_ctl_stat_reg <= 54'b0; | |
646 | else if (dma_reset) | |
647 | rx_dma_ctl_stat_reg <= 54'b0; | |
648 | else if (pio_32b_mode & rx_dma_ctl_stat_reg_wen) | |
649 | rx_dma_ctl_stat_reg <= {rx_dma_ctl_stat_reg[53:32], pio_rx_dma_ctl_stat_word[31:0]}; | |
650 | else if (pio_32b_mode & rx_dma_ctl_stat_reg_wen_32b) | |
651 | rx_dma_ctl_stat_reg <= {pio_rx_dma_ctl_stat_word[53:32], rx_dma_ctl_stat_reg[31:0]}; | |
652 | else if (rx_dma_ctl_stat_reg_wen) | |
653 | rx_dma_ctl_stat_reg <= pio_rx_dma_ctl_stat_word[53:0]; | |
654 | else if (pio_32b_mode & rx_dma_ctl_stat_reg_wr) | |
655 | rx_dma_ctl_stat_reg <= {rx_dma_ctl_stat_reg[53:32], pio_wdata[31:0]}; | |
656 | else if (pio_32b_mode & rx_dma_ctl_stat_reg_wr_32b) | |
657 | rx_dma_ctl_stat_reg <= {pio_wdata[21:0], rx_dma_ctl_stat_reg[31:0]}; | |
658 | else if (rx_dma_ctl_stat_reg_wr) | |
659 | rx_dma_ctl_stat_reg <= pio_wdata[53:0]; | |
660 | else if (m_bit_en & !rcr_ctl_stat_word[2]) | |
661 | rx_dma_ctl_stat_reg <= rx_dma_ctl_stat_reg_mex; | |
662 | else | |
663 | rx_dma_ctl_stat_reg <= rx_dma_ctl_stat_reg | rx_dma_ctl_stat_word; | |
664 | ||
665 | always @ (posedge clk) | |
666 | if (reset) | |
667 | fatal_err_all_d <= 1'b0; | |
668 | else | |
669 | fatal_err_all_d <= fatal_err_all; | |
670 | ||
671 | wire[15:0] rx_dma_pkt_drop_cnt = rx_dma_pkt_drop_cnt_reg[15:0] + 16'd1; | |
672 | wire drop_cnt_overflow = (rx_dma_pkt_drop_cnt_reg[15:0] == 16'hffff); | |
673 | ||
674 | always @ (posedge clk) | |
675 | if (reset) | |
676 | rx_dma_pkt_drop_cnt_reg <= 17'b0; | |
677 | else if (dma_reset) | |
678 | rx_dma_pkt_drop_cnt_reg <= 17'b0; | |
679 | else if (rx_dma_pkt_drop_cnt_reg_wen) | |
680 | rx_dma_pkt_drop_cnt_reg <= pio_wdata[16:0]; | |
681 | else if (is_drop_pkt & drop_cnt_overflow) | |
682 | rx_dma_pkt_drop_cnt_reg <= {1'b1, rx_dma_pkt_drop_cnt_reg[15:0]}; | |
683 | else if (is_drop_pkt) | |
684 | rx_dma_pkt_drop_cnt_reg <= {1'b0, rx_dma_pkt_drop_cnt[15:0]}; | |
685 | else | |
686 | rx_dma_pkt_drop_cnt_reg <= rx_dma_pkt_drop_cnt_reg; | |
687 | ||
688 | wire[15:0] rx_dma_wred_drop_cnt = rx_dma_wred_drop_cnt_reg[15:0] + 16'd1; | |
689 | wire wred_drop_cnt_overflow = (rx_dma_wred_drop_cnt_reg[15:0] == 16'hffff); | |
690 | ||
691 | always @ (posedge clk) | |
692 | if (reset) | |
693 | rx_dma_wred_drop_cnt_reg <= 17'b0; | |
694 | else if (dma_reset) | |
695 | rx_dma_wred_drop_cnt_reg <= 17'b0; | |
696 | else if (rx_dma_wred_drop_cnt_reg_wen) | |
697 | rx_dma_wred_drop_cnt_reg <= pio_wdata[16:0]; | |
698 | else if (is_wred_drop_pkt & wred_drop_cnt_overflow) | |
699 | rx_dma_wred_drop_cnt_reg <= {1'b1, rx_dma_wred_drop_cnt_reg[15:0]}; | |
700 | else if (is_wred_drop_pkt) | |
701 | rx_dma_wred_drop_cnt_reg <= {1'b0, rx_dma_wred_drop_cnt[15:0]}; | |
702 | else | |
703 | rx_dma_wred_drop_cnt_reg <= rx_dma_wred_drop_cnt_reg; | |
704 | ||
705 | ||
706 | always @ (posedge clk) | |
707 | if (reset) | |
708 | pio_disable_dma <= 1'b0; | |
709 | else if (rxdma_cfig1_reg_wen) | |
710 | pio_disable_dma <= disable_dma_ture; | |
711 | else if (idle_cycle) | |
712 | pio_disable_dma <= 1'b0; | |
713 | else | |
714 | pio_disable_dma <= pio_disable_dma; | |
715 | ||
716 | ||
717 | /***************/ | |
718 | //PIO Read | |
719 | /***************/ | |
720 | /* | |
721 | always @ (pio_addr1 or | |
722 | rx_log_page_vld_reg or rx_log_mask1_reg or | |
723 | rx_log_val1_reg or rx_log_mask2_reg or | |
724 | rx_log_val2_reg or rx_log_page_relo1_reg or | |
725 | rx_log_page_relo2_reg or rx_log_page_hdl_reg or | |
726 | rdc_red_param_reg or rx_dma_wred_drop_cnt_reg) | |
727 | begin | |
728 | ||
729 | fzc_pio_rd_err_tmp = 1'b0; | |
730 | case (pio_addr1) //synopsys parallel_case full_case | |
731 | ||
732 | 20'ha0000: fzc_pio_rd_data_tmp = {60'b0, rx_log_page_vld_reg[3:0]}; | |
733 | 20'ha0008: fzc_pio_rd_data_tmp = {32'b0, rx_log_mask1_reg}; | |
734 | 20'ha0010: fzc_pio_rd_data_tmp = {32'b0, rx_log_val1_reg}; | |
735 | 20'ha0018: fzc_pio_rd_data_tmp = {32'b0, rx_log_mask2_reg}; | |
736 | 20'ha0020: fzc_pio_rd_data_tmp = {32'b0, rx_log_val2_reg}; | |
737 | 20'ha0028: fzc_pio_rd_data_tmp = {32'b0, rx_log_page_relo1_reg}; | |
738 | 20'ha0030: fzc_pio_rd_data_tmp = {32'b0, rx_log_page_relo2_reg}; | |
739 | 20'ha0038: fzc_pio_rd_data_tmp = {44'b0, rx_log_page_hdl_reg[19:0]}; | |
740 | 20'hb0000: fzc_pio_rd_data_tmp = {32'b0, rdc_red_param_reg}; | |
741 | 20'hb0008: fzc_pio_rd_data_tmp = {47'b0, rx_dma_wred_drop_cnt_reg[16:0]}; | |
742 | default: begin | |
743 | fzc_pio_rd_err_tmp = 1'b1; | |
744 | fzc_pio_rd_data_tmp = 64'b0; | |
745 | end | |
746 | ||
747 | endcase | |
748 | end | |
749 | */ | |
750 | ||
751 | always @ (pio_addr1 or | |
752 | rx_log_page_vld_reg or rx_log_mask1_reg or | |
753 | rx_log_val1_reg or rx_log_mask2_reg or | |
754 | rx_log_val2_reg or rx_log_page_relo1_reg or | |
755 | rx_log_page_relo2_reg or rx_log_page_hdl_reg or | |
756 | rdc_red_param_reg or rx_dma_wred_drop_cnt_reg) | |
757 | begin | |
758 | ||
759 | fzc_pio_rd_err_tmp = 1'b0; | |
760 | case (pio_addr1[19:2]) //synopsys parallel_case full_case | |
761 | ||
762 | 18'h28000: fzc_pio_rd_data_tmp = {60'b0, rx_log_page_vld_reg[3:0]}; | |
763 | 18'h28001: fzc_pio_rd_data_tmp = 64'b0; | |
764 | 18'h28002: fzc_pio_rd_data_tmp = {32'b0, rx_log_mask1_reg}; | |
765 | 18'h28003: fzc_pio_rd_data_tmp = 64'b0; | |
766 | 18'h28004: fzc_pio_rd_data_tmp = {32'b0, rx_log_val1_reg}; | |
767 | 18'h28005: fzc_pio_rd_data_tmp = 64'b0; | |
768 | 18'h28006: fzc_pio_rd_data_tmp = {32'b0, rx_log_mask2_reg}; | |
769 | 18'h28007: fzc_pio_rd_data_tmp = 64'b0; | |
770 | 18'h28008: fzc_pio_rd_data_tmp = {32'b0, rx_log_val2_reg}; | |
771 | 18'h28009: fzc_pio_rd_data_tmp = 64'b0; | |
772 | 18'h2800a: fzc_pio_rd_data_tmp = {32'b0, rx_log_page_relo1_reg}; | |
773 | 18'h2800b: fzc_pio_rd_data_tmp = 64'b0; | |
774 | 18'h2800c: fzc_pio_rd_data_tmp = {32'b0, rx_log_page_relo2_reg}; | |
775 | 18'h2800d: fzc_pio_rd_data_tmp = 64'b0; | |
776 | 18'h2800e: fzc_pio_rd_data_tmp = {44'b0, rx_log_page_hdl_reg[19:0]}; | |
777 | 18'h2800f: fzc_pio_rd_data_tmp = 64'b0; | |
778 | 18'h2c000: fzc_pio_rd_data_tmp = {32'b0, rdc_red_param_reg}; | |
779 | 18'h2c001: fzc_pio_rd_data_tmp = 64'b0; | |
780 | 18'h2c002: fzc_pio_rd_data_tmp = {47'b0, rx_dma_wred_drop_cnt_reg[16:0]}; | |
781 | 18'h2c003: fzc_pio_rd_data_tmp = 64'b0; | |
782 | default: begin | |
783 | fzc_pio_rd_err_tmp = 1'b1; | |
784 | fzc_pio_rd_data_tmp = 64'hdeadbeefdeadbeef; | |
785 | end | |
786 | ||
787 | endcase | |
788 | end | |
789 | ||
790 | ||
791 | /* | |
792 | always @ (pio_addr2 or | |
793 | rxdma_cfig1_reg or rxdma_cfig2_reg or | |
794 | rbr_cfig_a_reg or rbr_cfig_b_reg or | |
795 | rbr_kick_reg or desp_curr_cnt or | |
796 | desp_full_addr or | |
797 | rcr_cfig_a_reg or rcr_cfig_b_reg or | |
798 | rcr_status_a or rcr_full_addr or | |
799 | rx_dma_ent_mask_reg or rx_dma_ctl_stat_reg or | |
800 | rcr_flush_reg or rx_dma_pkt_drop_cnt_reg) | |
801 | begin | |
802 | ||
803 | pio_rd_err_tmp = 1'b0; | |
804 | case (pio_addr2) //synopsys parallel_case full_case | |
805 | ||
806 | 20'h00000: pio_rd_data_tmp = {32'b0, rxdma_cfig1_reg[14:12], 17'b0, rxdma_cfig1_reg[11:0]}; | |
807 | 20'h00008: pio_rd_data_tmp = {32'b0, rxdma_cfig2_reg[28:3], 3'b0, rxdma_cfig2_reg[2:0]}; | |
808 | 20'h00010: pio_rd_data_tmp = {rbr_cfig_a_reg[53:38], 4'b0, rbr_cfig_a_reg[37:0], 6'b0}; | |
809 | 20'h00018: pio_rd_data_tmp = {38'b0, rbr_cfig_b_reg[10:8], 5'b0, rbr_cfig_b_reg[7:5], 5'b0, rbr_cfig_b_reg[4:2], 5'b0, rbr_cfig_b_reg[1:0]}; | |
810 | 20'h00020: pio_rd_data_tmp = {48'b0, rbr_kick_reg[15:0]}; | |
811 | 20'h00028: pio_rd_data_tmp = {48'b0, desp_curr_cnt[15:0]}; | |
812 | 20'h00030: pio_rd_data_tmp = {52'b0, desp_full_addr[41:30]}; | |
813 | 20'h00038: pio_rd_data_tmp = {32'b0, desp_full_addr[29:0], 2'b0}; | |
814 | 20'h00040: pio_rd_data_tmp = {rcr_cfig_a_reg[53:38], 4'b0, rcr_cfig_a_reg[37:0], 6'b0}; | |
815 | 20'h00048: pio_rd_data_tmp = {32'b0, rcr_cfig_b_reg[22:6], 9'b0, rcr_cfig_b_reg[5:0]}; | |
816 | 20'h00050: pio_rd_data_tmp = {48'b0, rcr_status_a[15:0]}; | |
817 | 20'h00058: pio_rd_data_tmp = {52'b0, rcr_full_addr[40:29]}; | |
818 | 20'h00060: pio_rd_data_tmp = {32'b0, rcr_full_addr[28:0], 3'b0}; | |
819 | 20'h00068: pio_rd_data_tmp = {42'b0, rx_dma_ent_mask_reg[20:15], 1'b0, rx_dma_ent_mask_reg[14:0]}; | |
820 | 20'h00070: pio_rd_data_tmp = {10'b0, rx_dma_ctl_stat_reg[53:0]}; | |
821 | 20'h00078: pio_rd_data_tmp = {63'b0, rcr_flush_reg}; | |
822 | 20'h00090: pio_rd_data_tmp = {47'b0, rx_dma_pkt_drop_cnt_reg[16:0]}; | |
823 | 20'h00098: pio_rd_data_tmp = {10'b0, rx_dma_ctl_stat_reg[53:0]}; | |
824 | default: begin | |
825 | pio_rd_err_tmp = 1'b1; | |
826 | pio_rd_data_tmp = 64'b0; | |
827 | end | |
828 | ||
829 | endcase | |
830 | end | |
831 | */ | |
832 | ||
833 | always @ (pio_addr2 or | |
834 | rxdma_cfig1_reg or rxdma_cfig2_reg or | |
835 | rbr_cfig_a_reg or rbr_cfig_b_reg or | |
836 | rbr_kick_reg or desp_curr_cnt or | |
837 | desp_full_addr or | |
838 | rcr_cfig_a_reg or rcr_cfig_b_reg or | |
839 | rcr_status_a or rcr_full_addr or | |
840 | rx_dma_ent_mask_reg or rx_dma_ctl_stat_reg or | |
841 | rcr_flush_reg or rx_dma_pkt_drop_cnt_reg) | |
842 | begin | |
843 | ||
844 | pio_rd_err_tmp = 1'b0; | |
845 | case (pio_addr2[19:2]) //synopsys parallel_case full_case | |
846 | ||
847 | 18'h00000: pio_rd_data_tmp = {32'b0, rxdma_cfig1_reg[14:12], 17'b0, rxdma_cfig1_reg[11:0]}; | |
848 | 18'h00001: pio_rd_data_tmp = 64'b0; | |
849 | 18'h00002: pio_rd_data_tmp = {32'b0, rxdma_cfig2_reg[28:3], 3'b0, rxdma_cfig2_reg[2:0]}; | |
850 | 18'h00003: pio_rd_data_tmp = 64'b0; | |
851 | 18'h00004: pio_rd_data_tmp = {rbr_cfig_a_reg[53:38], 4'b0, rbr_cfig_a_reg[37:0], 6'b0}; | |
852 | 18'h00005: pio_rd_data_tmp = 64'b0; | |
853 | 18'h00006: pio_rd_data_tmp = {38'b0, rbr_cfig_b_reg[10:8], 5'b0, rbr_cfig_b_reg[7:5], 5'b0, rbr_cfig_b_reg[4:2], 5'b0, rbr_cfig_b_reg[1:0]}; | |
854 | 18'h00007: pio_rd_data_tmp = 64'b0; | |
855 | 18'h00008: pio_rd_data_tmp = {48'b0, rbr_kick_reg[15:0]}; | |
856 | 18'h00009: pio_rd_data_tmp = 64'b0; | |
857 | 18'h0000a: pio_rd_data_tmp = {48'b0, desp_curr_cnt[15:0]}; | |
858 | 18'h0000b: pio_rd_data_tmp = 64'b0; | |
859 | 18'h0000c: pio_rd_data_tmp = {52'b0, desp_full_addr[41:30]}; | |
860 | 18'h0000d: pio_rd_data_tmp = 64'b0; | |
861 | 18'h0000e: pio_rd_data_tmp = {32'b0, desp_full_addr[29:0], 2'b0}; | |
862 | 18'h0000f: pio_rd_data_tmp = 64'b0; | |
863 | 18'h00010: pio_rd_data_tmp = {rcr_cfig_a_reg[53:38], 4'b0, rcr_cfig_a_reg[37:0], 6'b0}; | |
864 | 18'h00011: pio_rd_data_tmp = 64'b0; | |
865 | 18'h00012: pio_rd_data_tmp = {32'b0, rcr_cfig_b_reg[22:6], 9'b0, rcr_cfig_b_reg[5:0]}; | |
866 | 18'h00013: pio_rd_data_tmp = 64'b0; | |
867 | 18'h00014: pio_rd_data_tmp = {48'b0, rcr_status_a[15:0]}; | |
868 | 18'h00015: pio_rd_data_tmp = 64'b0; | |
869 | 18'h00016: pio_rd_data_tmp = {52'b0, rcr_full_addr[40:29]}; | |
870 | 18'h00017: pio_rd_data_tmp = 64'b0; | |
871 | 18'h00018: pio_rd_data_tmp = {32'b0, rcr_full_addr[28:0], 3'b0}; | |
872 | 18'h00019: pio_rd_data_tmp = 64'b0; | |
873 | 18'h0001a: pio_rd_data_tmp = {42'b0, rx_dma_ent_mask_reg[20:15], 1'b0, rx_dma_ent_mask_reg[14:0]}; | |
874 | 18'h0001b: pio_rd_data_tmp = 64'b0; | |
875 | 18'h0001c: pio_rd_data_tmp = {10'b0, rx_dma_ctl_stat_reg[53:0]}; | |
876 | 18'h0001d: pio_rd_data_tmp = 64'b0; | |
877 | 18'h0001e: pio_rd_data_tmp = {63'b0, rcr_flush_reg}; | |
878 | 18'h0001f: pio_rd_data_tmp = 64'b0; | |
879 | 18'h00024: pio_rd_data_tmp = {47'b0, rx_dma_pkt_drop_cnt_reg[16:0]}; | |
880 | 18'h00025: pio_rd_data_tmp = 64'b0; | |
881 | 18'h00026: pio_rd_data_tmp = {10'b0, rx_dma_ctl_stat_reg[53:0]}; | |
882 | 18'h00027: pio_rd_data_tmp = 64'b0; | |
883 | default: begin | |
884 | pio_rd_err_tmp = 1'b1; | |
885 | pio_rd_data_tmp = 64'hdeadbeefdeadbeef; | |
886 | end | |
887 | ||
888 | endcase | |
889 | end | |
890 | ||
891 | ||
892 | ||
893 | /* | |
894 | always @ (pio_addr2 or | |
895 | rxdma_cfig1_reg or rxdma_cfig2_reg or | |
896 | rbr_cfig_a_reg or rbr_cfig_b_reg or | |
897 | rbr_kick_reg or desp_curr_cnt or | |
898 | desp_full_addr or | |
899 | rcr_cfig_a_reg or rcr_cfig_b_reg or | |
900 | rcr_status_a or rcr_full_addr or | |
901 | rx_dma_ent_mask_reg or rx_dma_ctl_stat_reg or | |
902 | rcr_flush_reg or rx_dma_pkt_drop_cnt_reg) | |
903 | begin | |
904 | ||
905 | pio_rd_err_tmp_32b = 1'b0; | |
906 | case (pio_addr2) //synopsys parallel_case full_case | |
907 | ||
908 | 20'h00000: pio_rd_data_tmp_32b = {32'b0, rxdma_cfig1_reg[14:12], 17'b0, rxdma_cfig1_reg[11:0]}; | |
909 | 20'h00008: pio_rd_data_tmp_32b = {32'b0, rxdma_cfig2_reg[28:3], 3'b0, rxdma_cfig2_reg[2:0]}; | |
910 | 20'h00010: pio_rd_data_tmp_32b = {32'b0, rbr_cfig_a_reg[25:0], 6'b0}; | |
911 | 20'h00014: pio_rd_data_tmp_32b = {32'b0, rbr_cfig_a_reg[53:38], 4'b0, rbr_cfig_a_reg[37:26]}; | |
912 | 20'h00018: pio_rd_data_tmp_32b = {38'b0, rbr_cfig_b_reg[10:8], 5'b0, rbr_cfig_b_reg[7:5], 5'b0, rbr_cfig_b_reg[4:2], 5'b0, rbr_cfig_b_reg[1:0]}; | |
913 | 20'h00020: pio_rd_data_tmp_32b = {48'b0, rbr_kick_reg[15:0]}; | |
914 | 20'h00028: pio_rd_data_tmp_32b = {48'b0, desp_curr_cnt[15:0]}; | |
915 | 20'h00030: pio_rd_data_tmp_32b = {52'b0, desp_full_addr[41:30]}; | |
916 | 20'h00038: pio_rd_data_tmp_32b = {32'b0, desp_full_addr[29:0], 2'b0}; | |
917 | 20'h00040: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_a_reg[25:0], 6'b0}; | |
918 | 20'h00044: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_a_reg[53:38], 4'b0, rcr_cfig_a_reg[37:26]}; | |
919 | 20'h00048: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_b_reg[22:6], 9'b0, rcr_cfig_b_reg[5:0]}; | |
920 | 20'h00050: pio_rd_data_tmp_32b = {48'b0, rcr_status_a[15:0]}; | |
921 | 20'h00058: pio_rd_data_tmp_32b = {52'b0, rcr_full_addr[40:29]}; | |
922 | 20'h00060: pio_rd_data_tmp_32b = {32'b0, rcr_full_addr[28:0], 3'b0}; | |
923 | 20'h00068: pio_rd_data_tmp_32b = {42'b0, rx_dma_ent_mask_reg[20:15], 1'b0, rx_dma_ent_mask_reg[14:0]}; | |
924 | 20'h00070: pio_rd_data_tmp_32b = {32'b0, rx_dma_ctl_stat_reg[31:0]}; | |
925 | 20'h00074: pio_rd_data_tmp_32b = {32'b0, 10'b0, rx_dma_ctl_stat_reg[53:32]}; | |
926 | 20'h00078: pio_rd_data_tmp_32b = {63'b0, rcr_flush_reg}; | |
927 | 20'h00090: pio_rd_data_tmp_32b = {47'b0, rx_dma_pkt_drop_cnt_reg[16:0]}; | |
928 | 20'h00098: pio_rd_data_tmp_32b = {32'b0, rx_dma_ctl_stat_reg[31:0]}; | |
929 | 20'h0009c: pio_rd_data_tmp_32b = {32'b0, 10'b0, rx_dma_ctl_stat_reg[53:32]}; | |
930 | default: begin | |
931 | pio_rd_err_tmp_32b = 1'b1; | |
932 | pio_rd_data_tmp_32b = 64'b0; | |
933 | end | |
934 | ||
935 | endcase | |
936 | end | |
937 | */ | |
938 | ||
939 | always @ (pio_addr2 or | |
940 | rxdma_cfig1_reg or rxdma_cfig2_reg or | |
941 | rbr_cfig_a_reg or rbr_cfig_b_reg or | |
942 | rbr_kick_reg or desp_curr_cnt or | |
943 | desp_full_addr or | |
944 | rcr_cfig_a_reg or rcr_cfig_b_reg or | |
945 | rcr_status_a or rcr_full_addr or | |
946 | rx_dma_ent_mask_reg or rx_dma_ctl_stat_reg or | |
947 | rcr_flush_reg or rx_dma_pkt_drop_cnt_reg) | |
948 | begin | |
949 | ||
950 | pio_rd_err_tmp_32b = 1'b0; | |
951 | case (pio_addr2[19:2]) //synopsys parallel_case full_case | |
952 | ||
953 | 18'h00000: pio_rd_data_tmp_32b = {32'b0, rxdma_cfig1_reg[14:12], 17'b0, rxdma_cfig1_reg[11:0]}; | |
954 | 18'h00001: pio_rd_data_tmp_32b = 64'b0; | |
955 | 18'h00002: pio_rd_data_tmp_32b = {32'b0, rxdma_cfig2_reg[28:3], 3'b0, rxdma_cfig2_reg[2:0]}; | |
956 | 18'h00003: pio_rd_data_tmp_32b = 64'b0; | |
957 | 18'h00004: pio_rd_data_tmp_32b = {32'b0, rbr_cfig_a_reg[25:0], 6'b0}; | |
958 | 18'h00005: pio_rd_data_tmp_32b = {32'b0, rbr_cfig_a_reg[53:38], 4'b0, rbr_cfig_a_reg[37:26]}; | |
959 | 18'h00006: pio_rd_data_tmp_32b = {38'b0, rbr_cfig_b_reg[10:8], 5'b0, rbr_cfig_b_reg[7:5], 5'b0, rbr_cfig_b_reg[4:2], 5'b0, rbr_cfig_b_reg[1:0]}; | |
960 | 18'h00007: pio_rd_data_tmp_32b = 64'b0; | |
961 | 18'h00008: pio_rd_data_tmp_32b = {48'b0, rbr_kick_reg[15:0]}; | |
962 | 18'h00009: pio_rd_data_tmp_32b = 64'b0; | |
963 | 18'h0000a: pio_rd_data_tmp_32b = {48'b0, desp_curr_cnt[15:0]}; | |
964 | 18'h0000b: pio_rd_data_tmp_32b = 64'b0; | |
965 | 18'h0000c: pio_rd_data_tmp_32b = {52'b0, desp_full_addr[41:30]}; | |
966 | 18'h0000d: pio_rd_data_tmp_32b = 64'b0; | |
967 | 18'h0000e: pio_rd_data_tmp_32b = {32'b0, desp_full_addr[29:0], 2'b0}; | |
968 | 18'h0000f: pio_rd_data_tmp_32b = 64'b0; | |
969 | 18'h00010: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_a_reg[25:0], 6'b0}; | |
970 | 18'h00011: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_a_reg[53:38], 4'b0, rcr_cfig_a_reg[37:26]}; | |
971 | 18'h00012: pio_rd_data_tmp_32b = {32'b0, rcr_cfig_b_reg[22:6], 9'b0, rcr_cfig_b_reg[5:0]}; | |
972 | 18'h00013: pio_rd_data_tmp_32b = 64'b0; | |
973 | 18'h00014: pio_rd_data_tmp_32b = {48'b0, rcr_status_a[15:0]}; | |
974 | 18'h00015: pio_rd_data_tmp_32b = 64'b0; | |
975 | 18'h00016: pio_rd_data_tmp_32b = {52'b0, rcr_full_addr[40:29]}; | |
976 | 18'h00017: pio_rd_data_tmp_32b = 64'b0; | |
977 | 18'h00018: pio_rd_data_tmp_32b = {32'b0, rcr_full_addr[28:0], 3'b0}; | |
978 | 18'h00019: pio_rd_data_tmp_32b = 64'b0; | |
979 | 18'h0001a: pio_rd_data_tmp_32b = {42'b0, rx_dma_ent_mask_reg[20:15], 1'b0, rx_dma_ent_mask_reg[14:0]}; | |
980 | 18'h0001b: pio_rd_data_tmp_32b = 64'b0; | |
981 | 18'h0001c: pio_rd_data_tmp_32b = {32'b0, rx_dma_ctl_stat_reg[31:0]}; | |
982 | 18'h0001d: pio_rd_data_tmp_32b = {32'b0, 10'b0, rx_dma_ctl_stat_reg[53:32]}; | |
983 | 18'h0001e: pio_rd_data_tmp_32b = {63'b0, rcr_flush_reg}; | |
984 | 18'h0001f: pio_rd_data_tmp_32b = 64'b0; | |
985 | 18'h00024: pio_rd_data_tmp_32b = {47'b0, rx_dma_pkt_drop_cnt_reg[16:0]}; | |
986 | 18'h00025: pio_rd_data_tmp_32b = 64'b0; | |
987 | 18'h00026: pio_rd_data_tmp_32b = {32'b0, rx_dma_ctl_stat_reg[31:0]}; | |
988 | 18'h00027: pio_rd_data_tmp_32b = {32'b0, 10'b0, rx_dma_ctl_stat_reg[53:32]}; | |
989 | default: begin | |
990 | pio_rd_err_tmp_32b = 1'b1; | |
991 | pio_rd_data_tmp_32b = 64'hdeadbeefdeadbeef; | |
992 | end | |
993 | ||
994 | endcase | |
995 | end | |
996 | ||
997 | ||
998 | wire fzc_pio_rd_sel = addr_match1 & ((pio_addr[19:16] == 4'ha) | (pio_addr[19:16] == 4'hb)); | |
999 | wire nom_pio_rd_sel = addr_match2 & (pio_addr[19:16] == 4'h0); | |
1000 | wire[63:0] chnl_pio_rd_data_tmp = fzc_pio_rd_sel ? fzc_pio_rd_data_tmp : | |
1001 | pio_32b_mode ? pio_rd_data_tmp_32b : | |
1002 | pio_rd_data_tmp; | |
1003 | ||
1004 | wire pio_rd_gnt_tmp = fzc_pio_rd_sel & !fzc_pio_rd_err_tmp | | |
1005 | nom_pio_rd_sel & pio_32b_mode & !pio_rd_err_tmp_32b | | |
1006 | nom_pio_rd_sel & !pio_32b_mode & !pio_rd_err_tmp; | |
1007 | ||
1008 | always @ (posedge clk) | |
1009 | if (reset) | |
1010 | pio_rd_gnt <= 1'b0; | |
1011 | else | |
1012 | pio_rd_gnt <= pio_rd_gnt_tmp; | |
1013 | ||
1014 | always @ (posedge clk) | |
1015 | if (reset) | |
1016 | chnl_pio_rd_data <= 64'b0; | |
1017 | else | |
1018 | chnl_pio_rd_data <= chnl_pio_rd_data_tmp; | |
1019 | ||
1020 | ||
1021 | /*********Reset Logic ************/ | |
1022 | /*********************************/ | |
1023 | always @(posedge clk) | |
1024 | if (reset) | |
1025 | dma_reset <= 1'b0; | |
1026 | else if (dma_reset_cnt == 2'b11) | |
1027 | dma_reset <= 1'b0; | |
1028 | else if (pio_dma_rst & idle_cycle) | |
1029 | dma_reset <= 1'b1; | |
1030 | else | |
1031 | dma_reset <= dma_reset; | |
1032 | ||
1033 | always @(posedge clk) | |
1034 | if (reset) | |
1035 | dma_reset_cnt <= 2'b0; | |
1036 | else if (dma_reset) | |
1037 | dma_reset_cnt <= dma_reset_cnt + 2'd1; | |
1038 | else | |
1039 | dma_reset_cnt <= 2'b0; | |
1040 | ||
1041 | ||
1042 | ||
1043 | endmodule | |
1044 | ||
1045 |