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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rdmc_rcr_manager.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /************************************************************************* | |
36 | * | |
37 | * File Name : niu_rdmc_rcr_manager.v | |
38 | * Author Name : Jeanne Cai | |
39 | * Description : | |
40 | * Date Created : 07/18/2004 | |
41 | * | |
42 | * Copyright (c) 2001, Sun Microsystems, Inc. | |
43 | * Sun Proprietary and Confidential | |
44 | * | |
45 | * | |
46 | *************************************************************************/ | |
47 | ||
48 | `include "niu_rdmc.h" | |
49 | module niu_rdmc_rcr_manager ( | |
50 | clk, | |
51 | reset, | |
52 | clk_div_value, | |
53 | dma_chnl_grp_id, | |
54 | shadw_start_addr, | |
55 | shadw_rd_end_addr, | |
56 | shadw_wr_end_addr, | |
57 | dma_en, | |
58 | dma_reset, | |
59 | page_valid0, | |
60 | addr_mask0, | |
61 | comp_value0, | |
62 | relo_value0, | |
63 | page_valid1, | |
64 | addr_mask1, | |
65 | comp_value1, | |
66 | relo_value1, | |
67 | dma_fatal_err, | |
68 | rx_log_page_hdl_reg, | |
69 | rcr_cfig_a_reg, | |
70 | rcr_cfig_b_reg, | |
71 | rx_dma_ctl_stat_reg, | |
72 | rx_dma_ctl_stat_reg_bit47, | |
73 | rcr_flush_reg, | |
74 | mbox_addr, | |
75 | rcr_cfig_a_reg_wenu, | |
76 | rcr_cfig_a_reg_wenl, | |
77 | rx_dma_ctl_stat_reg_wenu, | |
78 | rx_dma_ctl_stat_reg_wenl, | |
79 | chnl_sel_buf_en_r, //from niu_rdmc_buf_manager.v | |
80 | pref_buf_used_num, //up to three for jumbo packets | |
81 | wr_transfer_comp_int, | |
82 | wr_last_pkt_data, | |
83 | update_rcr_shadw, //from niu_rdmc_wr_sched.v, need chnl id | |
84 | rdmc_wr_data_dma_num, | |
85 | rcr_wrbk_gnt, | |
86 | rcr_wrbk_done, | |
87 | rcr_wrbk_pkt_num, | |
88 | rdmc_rcr_ack_valid, | |
89 | rdmc_rcr_ack_err, | |
90 | rdmc_rcr_ack_dma_num, | |
91 | shadw_parity_err, | |
92 | ||
93 | shadw_wr_en, | |
94 | shadw_wr_even, | |
95 | shadw_wr_ptr, | |
96 | shadw_rd_ptr, | |
97 | rcr_wrbk_sched, | |
98 | rcr_wrbk_req, | |
99 | rcr_wrbk_addr, | |
100 | rcr_wrbk_numb, | |
101 | rcr_wrbk_data_type, | |
102 | rcr_ack_accept, | |
103 | rcr_curr_qlen, | |
104 | shadw_curr_space_cnt, | |
105 | reset_rcr_flush, | |
106 | m_bit_en, | |
107 | rcr_ctl_stat_word, | |
108 | rcr_curr_addr, | |
109 | rcr_status_a, | |
110 | rcr_addr_not_valid, | |
111 | mbox_addr_not_valid, | |
112 | rcr_addr_overflow, | |
113 | rcr_curr_cnt_overflow, | |
114 | rcr_curr_cnt_underflow, | |
115 | rcr_pkt_cnt_underflow, | |
116 | rcr_idle_cycle, | |
117 | rcr_ack_err, | |
118 | chnl_has_pkt, | |
119 | chnl_shadw_parity_err | |
120 | ||
121 | ); | |
122 | ||
123 | input clk; | |
124 | input reset; | |
125 | input[15:0] clk_div_value; | |
126 | input[4:0] dma_chnl_grp_id; | |
127 | input[7:0] shadw_start_addr; | |
128 | input[7:0] shadw_rd_end_addr; | |
129 | input[7:0] shadw_wr_end_addr; | |
130 | input dma_en; | |
131 | input dma_reset; | |
132 | input page_valid0; | |
133 | input[31:0] addr_mask0; | |
134 | input[31:0] comp_value0; | |
135 | input[31:0] relo_value0; | |
136 | input page_valid1; | |
137 | input[31:0] addr_mask1; | |
138 | input[31:0] comp_value1; | |
139 | input[31:0] relo_value1; | |
140 | input dma_fatal_err; | |
141 | input[19:0] rx_log_page_hdl_reg; | |
142 | input[53:0] rcr_cfig_a_reg; | |
143 | input[22:0] rcr_cfig_b_reg; | |
144 | input[31:0] rx_dma_ctl_stat_reg; | |
145 | input rx_dma_ctl_stat_reg_bit47; | |
146 | input rcr_flush_reg; | |
147 | input[43:0] mbox_addr; | |
148 | input rcr_cfig_a_reg_wenu; | |
149 | input rcr_cfig_a_reg_wenl; | |
150 | input rx_dma_ctl_stat_reg_wenu; | |
151 | input rx_dma_ctl_stat_reg_wenl; | |
152 | input chnl_sel_buf_en_r; | |
153 | input[1:0] pref_buf_used_num; | |
154 | input wr_transfer_comp_int; | |
155 | input wr_last_pkt_data; | |
156 | input update_rcr_shadw; | |
157 | input[4:0] rdmc_wr_data_dma_num; | |
158 | input rcr_wrbk_gnt; | |
159 | input rcr_wrbk_done; | |
160 | input[3:0] rcr_wrbk_pkt_num; | |
161 | input rdmc_rcr_ack_valid; | |
162 | input rdmc_rcr_ack_err; | |
163 | input[4:0] rdmc_rcr_ack_dma_num; | |
164 | input shadw_parity_err; | |
165 | ||
166 | output shadw_wr_en; | |
167 | output shadw_wr_even; | |
168 | output[7:0] shadw_wr_ptr; | |
169 | output[7:0] shadw_rd_ptr; | |
170 | output rcr_wrbk_sched; | |
171 | output rcr_wrbk_req; | |
172 | output[63:0] rcr_wrbk_addr; | |
173 | output[3:0] rcr_wrbk_numb; | |
174 | output rcr_wrbk_data_type; | |
175 | output rcr_ack_accept; | |
176 | output[15:0] rcr_curr_qlen; | |
177 | output[7:0] shadw_curr_space_cnt; | |
178 | output reset_rcr_flush; | |
179 | output m_bit_en; | |
180 | output[2:0] rcr_ctl_stat_word; | |
181 | output[15:0] rcr_curr_addr; | |
182 | output[15:0] rcr_status_a; | |
183 | output rcr_addr_not_valid; | |
184 | output mbox_addr_not_valid; | |
185 | output rcr_addr_overflow; | |
186 | output rcr_curr_cnt_overflow; | |
187 | output rcr_curr_cnt_underflow; | |
188 | output rcr_pkt_cnt_underflow; | |
189 | output rcr_idle_cycle; | |
190 | output rcr_ack_err; | |
191 | output chnl_has_pkt; | |
192 | output chnl_shadw_parity_err; | |
193 | ||
194 | reg rcr_cfig_a_reg_wenu_dly2; | |
195 | reg rcr_cfig_a_reg_wenu_dly; | |
196 | reg rcr_cfig_a_reg_wenl_dly2; | |
197 | reg rcr_cfig_a_reg_wenl_dly; | |
198 | ||
199 | reg rx_dma_ctl_stat_reg_wenu_dly; | |
200 | reg rx_dma_ctl_stat_reg_wenl_dly; | |
201 | ||
202 | reg[3:0] addr_cnt; | |
203 | reg cal_addr_en; | |
204 | ||
205 | reg[15:0] rcr_curr_addr_tmp; | |
206 | reg[15:0] rcr_curr_addr; | |
207 | reg dec_rcr_curr_cnt; | |
208 | reg dec_rcr_curr_cnt_r; | |
209 | reg[16:0] rcr_curr_cnt; //bit[16] is overflow bit | |
210 | reg[3:0] rcr_wrbk_act_num; | |
211 | reg[3:0] rcr_wrbk_numb; | |
212 | reg[16:0] rcr_curr_pkt_cnt; | |
213 | reg[3:0] rcr_wrbk_pkt_num_sav; | |
214 | reg[3:0] rcr_wrbk_pkt_act_num; | |
215 | reg[3:0] rcr_wrbk_pkt_num_r; | |
216 | reg not_in_cacheline; | |
217 | reg[43:0] rcr_relo_addr_r; | |
218 | ||
219 | reg rcr_curr_cnt_overflow_r; | |
220 | reg shadw_parity_err_r; | |
221 | ||
222 | reg rcr_wrbk_data_type; | |
223 | reg rcr_wrbk_req; | |
224 | reg rcr_wrbk_sched; | |
225 | reg rcr_wrbk_done_r; | |
226 | reg rcr_wrbk_done_r1; | |
227 | reg rcr_wrbk_ack_done; | |
228 | reg rcr_wrbk_ack_done_r; | |
229 | reg mbox_update_done; | |
230 | reg rcr_ack_accept; | |
231 | ||
232 | reg rcr_idle_cycle; | |
233 | reg rcr_wrbk_req_sm; | |
234 | reg mbox_req_sm; | |
235 | reg rcr_wrbk_ack_done_sm; | |
236 | reg mbox_update_done_sm; | |
237 | reg rcr_ack_accept_sm; | |
238 | reg reset_rcr_timer; | |
239 | reg reset_m_bit; | |
240 | reg[3:0] state; | |
241 | reg[3:0] next_state; | |
242 | ||
243 | reg shadw_wr_en; | |
244 | reg[7:0] shadw_wr_ptr; | |
245 | reg[7:0] shadw_rd_ptr; | |
246 | reg inc_shadw_curr_cnt; | |
247 | reg[7:0] shadw_curr_cnt; | |
248 | reg[5:0] shadw_act_curr_cnt; | |
249 | reg dec_shadw_space_cnt; | |
250 | reg[7:0] shadw_curr_space_cnt; | |
251 | reg chnl_has_pkt_s1; | |
252 | reg chnl_has_pkt_s2; | |
253 | ||
254 | reg timer_m_bit; | |
255 | reg[15:0] clk_cnt; | |
256 | reg[5:0] timeout_cnt; | |
257 | reg rcr_timer_done_r; | |
258 | reg rcr_timer_done_r_dly; | |
259 | reg mbox_update_done_dly; | |
260 | reg rcr_flush_reg_dly; | |
261 | reg rcr_thresh_reg; | |
262 | reg thresh_m_bit; | |
263 | ||
264 | ||
265 | wire[2:0] rcr_ctl_stat_word; | |
266 | wire[15:0] rcr_curr_qlen = rcr_curr_cnt[15:0]; | |
267 | //wire[17:0] rcr_status_a = {rcr_curr_cnt[16], rcr_curr_pkt_cnt[16:0]}; | |
268 | wire[15:0] rcr_status_a = rcr_curr_pkt_cnt[15:0]; | |
269 | ||
270 | wire rcr_ack_err = rdmc_rcr_ack_valid & rdmc_rcr_ack_err; | |
271 | ||
272 | ||
273 | /**********************************************/ | |
274 | //PIO programmed parameters | |
275 | /**********************************************/ | |
276 | reg[16:0] rcr_end_addr_r; | |
277 | ||
278 | wire[15:0] rcr_max_len = rcr_cfig_a_reg[53:38]; | |
279 | wire[24:0] rcr_base_addr = rcr_cfig_a_reg[37:13]; | |
280 | wire[15:0] rcr_start_addr = {rcr_cfig_a_reg[12:0], 3'b0}; | |
281 | wire[15:0] rcr_end_addr = rcr_end_addr_r[15:0]; | |
282 | wire rcr_addr_overflow = rcr_end_addr_r[16] & dma_en; | |
283 | ||
284 | wire[15:0] pkt_thresh = rcr_cfig_b_reg[22:7]; | |
285 | wire timeout_en = rcr_cfig_b_reg[6]; | |
286 | wire[5:0] timeout_value = rcr_cfig_b_reg[5:0]; | |
287 | ||
288 | wire[19:0] page_handle = rx_log_page_hdl_reg; | |
289 | ||
290 | wire m_bit = rx_dma_ctl_stat_reg_bit47; | |
291 | //wire rcr_thresh_bit = rx_dma_ctl_stat_reg[46]; | |
292 | //wire rcrto_bit = rx_dma_ctl_stat_reg[45]; | |
293 | wire[15:0] cpu_ptr_rd_num = rx_dma_ctl_stat_reg[31:16]; | |
294 | wire[15:0] cpu_pkt_rd_num = rx_dma_ctl_stat_reg[15:0]; | |
295 | ||
296 | /****************************/ | |
297 | //RCR Manager | |
298 | /****************************/ | |
299 | always @ (posedge clk) | |
300 | if (reset) | |
301 | rcr_cfig_a_reg_wenu_dly <= 1'b0; | |
302 | else if (dma_reset) | |
303 | rcr_cfig_a_reg_wenu_dly <= 1'b0; | |
304 | else if (rcr_cfig_a_reg_wenu) | |
305 | rcr_cfig_a_reg_wenu_dly <= 1'b1; | |
306 | else | |
307 | rcr_cfig_a_reg_wenu_dly <= 1'b0; | |
308 | ||
309 | always @ (posedge clk) | |
310 | if (reset) | |
311 | rcr_cfig_a_reg_wenu_dly2 <= 1'b0; | |
312 | else | |
313 | rcr_cfig_a_reg_wenu_dly2 <= rcr_cfig_a_reg_wenu_dly; | |
314 | ||
315 | always @ (posedge clk) | |
316 | if (reset) | |
317 | rcr_cfig_a_reg_wenl_dly <= 1'b0; | |
318 | else if (dma_reset) | |
319 | rcr_cfig_a_reg_wenl_dly <= 1'b0; | |
320 | else if (rcr_cfig_a_reg_wenl) | |
321 | rcr_cfig_a_reg_wenl_dly <= 1'b1; | |
322 | else | |
323 | rcr_cfig_a_reg_wenl_dly <= 1'b0; | |
324 | ||
325 | always @ (posedge clk) | |
326 | if (reset) | |
327 | rcr_cfig_a_reg_wenl_dly2 <= 1'b0; | |
328 | else | |
329 | rcr_cfig_a_reg_wenl_dly2 <= rcr_cfig_a_reg_wenl_dly; | |
330 | ||
331 | ||
332 | always @ (posedge clk) | |
333 | if (reset) | |
334 | rx_dma_ctl_stat_reg_wenu_dly <= 1'b0; | |
335 | else if (dma_reset) | |
336 | rx_dma_ctl_stat_reg_wenu_dly <= 1'b0; | |
337 | else | |
338 | rx_dma_ctl_stat_reg_wenu_dly <= rx_dma_ctl_stat_reg_wenu; | |
339 | ||
340 | always @ (posedge clk) | |
341 | if (reset) | |
342 | rx_dma_ctl_stat_reg_wenl_dly <= 1'b0; | |
343 | else if (dma_reset) | |
344 | rx_dma_ctl_stat_reg_wenl_dly <= 1'b0; | |
345 | else | |
346 | rx_dma_ctl_stat_reg_wenl_dly <= rx_dma_ctl_stat_reg_wenl; | |
347 | ||
348 | ||
349 | wire[15:0] rcr_end_addr_sub = rcr_max_len[15:0] - 16'd1; | |
350 | ||
351 | always @ (posedge clk) | |
352 | if (reset) | |
353 | rcr_end_addr_r <= 17'b0; | |
354 | else if (dma_reset) | |
355 | rcr_end_addr_r <= 17'b0; | |
356 | else if (rcr_cfig_a_reg_wenu_dly & (|rcr_max_len)) | |
357 | rcr_end_addr_r <= {1'b0, rcr_end_addr_sub}; | |
358 | else if (rcr_cfig_a_reg_wenl_dly2 | rcr_cfig_a_reg_wenu_dly2) | |
359 | rcr_end_addr_r <= {1'b0, rcr_start_addr[15:0]} + rcr_end_addr_r; | |
360 | else | |
361 | rcr_end_addr_r <= rcr_end_addr_r; | |
362 | ||
363 | ||
364 | always @ (posedge clk) | |
365 | if (reset) | |
366 | addr_cnt <= 4'b0; | |
367 | else if (dma_reset) | |
368 | addr_cnt <= 4'b0; | |
369 | else if (cal_addr_en) | |
370 | addr_cnt <= rcr_wrbk_act_num; //each write back is one cache line for 8 addresses | |
371 | else if (addr_cnt != 4'b0) | |
372 | addr_cnt <= addr_cnt - 4'd1; | |
373 | else | |
374 | addr_cnt <= addr_cnt; | |
375 | ||
376 | always @ (posedge clk) | |
377 | if (reset) | |
378 | rcr_curr_addr_tmp <= 16'b0; | |
379 | else if ((addr_cnt != 4'b0) & (rcr_curr_addr_tmp == rcr_end_addr)) | |
380 | rcr_curr_addr_tmp <= rcr_start_addr; | |
381 | else if (addr_cnt != 4'b0) | |
382 | rcr_curr_addr_tmp <= rcr_curr_addr_tmp + 16'd1; | |
383 | else if (cal_addr_en) | |
384 | rcr_curr_addr_tmp <= rcr_curr_addr[15:0]; | |
385 | else | |
386 | rcr_curr_addr_tmp <= rcr_curr_addr_tmp; | |
387 | ||
388 | always @ (posedge clk) | |
389 | if (reset) | |
390 | rcr_curr_addr <= 16'b0; | |
391 | else if (rcr_cfig_a_reg_wenl_dly) | |
392 | rcr_curr_addr <= rcr_start_addr; | |
393 | else if (rcr_wrbk_ack_done & !shadw_parity_err_r) | |
394 | rcr_curr_addr <= rcr_curr_addr_tmp; | |
395 | else | |
396 | rcr_curr_addr <= rcr_curr_addr; | |
397 | ||
398 | always @ (posedge clk) | |
399 | if (reset) | |
400 | dec_rcr_curr_cnt <= 1'b0; | |
401 | else if (rx_dma_ctl_stat_reg_wenl & !rcr_wrbk_ack_done_sm | rx_dma_ctl_stat_reg_wenl_dly & !dec_rcr_curr_cnt) | |
402 | dec_rcr_curr_cnt <= 1'b1; | |
403 | else | |
404 | dec_rcr_curr_cnt <= 1'b0; | |
405 | ||
406 | ||
407 | always @ (posedge clk) | |
408 | if (reset) | |
409 | rcr_curr_cnt <= 17'b0; //pio read only, this is rcr addr cnt | |
410 | else if (dma_reset) | |
411 | rcr_curr_cnt <= 17'b0; | |
412 | else if (rcr_curr_cnt[16] | rcr_curr_cnt_overflow_r) | |
413 | rcr_curr_cnt <= rcr_curr_cnt; | |
414 | else if (dec_rcr_curr_cnt) | |
415 | rcr_curr_cnt <= rcr_curr_cnt - {1'b0, cpu_ptr_rd_num[15:0]}; // bit[16] is overflow bit | |
416 | else if (rcr_wrbk_ack_done & !shadw_parity_err_r) | |
417 | rcr_curr_cnt <= rcr_curr_cnt + {13'b0, rcr_wrbk_act_num[3:0]}; | |
418 | else | |
419 | rcr_curr_cnt <= rcr_curr_cnt; | |
420 | ||
421 | always @ (posedge clk) | |
422 | if (reset) | |
423 | rcr_wrbk_pkt_num_sav <= 4'b0; | |
424 | else if (dma_reset) | |
425 | rcr_wrbk_pkt_num_sav <= 4'b0; | |
426 | else if (rcr_wrbk_ack_done & not_in_cacheline & !shadw_parity_err_r) | |
427 | rcr_wrbk_pkt_num_sav <= rcr_wrbk_pkt_num_r; | |
428 | else if (rcr_wrbk_ack_done & !shadw_parity_err_r) | |
429 | rcr_wrbk_pkt_num_sav <= 4'b0; | |
430 | else | |
431 | rcr_wrbk_pkt_num_sav <= rcr_wrbk_pkt_num_sav; | |
432 | ||
433 | always @ (posedge clk) | |
434 | if (reset) | |
435 | rcr_wrbk_pkt_act_num <= 4'b0; | |
436 | else if (dma_reset) | |
437 | rcr_wrbk_pkt_act_num <= 4'b0; | |
438 | else if (rcr_wrbk_ack_done_sm & !shadw_parity_err_r) | |
439 | rcr_wrbk_pkt_act_num <= (rcr_wrbk_pkt_num_r - rcr_wrbk_pkt_num_sav); | |
440 | else | |
441 | rcr_wrbk_pkt_act_num <= rcr_wrbk_pkt_act_num; | |
442 | ||
443 | always @ (posedge clk) | |
444 | if (reset) | |
445 | rcr_curr_pkt_cnt <= 17'b0; | |
446 | else if (dma_reset) | |
447 | rcr_curr_pkt_cnt <= 17'b0; | |
448 | else if (rcr_curr_pkt_cnt[16] | rcr_curr_cnt_overflow_r) | |
449 | rcr_curr_pkt_cnt <= rcr_curr_pkt_cnt; | |
450 | else if (dec_rcr_curr_cnt) | |
451 | rcr_curr_pkt_cnt <= rcr_curr_pkt_cnt - {1'b0, cpu_pkt_rd_num[15:0]}; | |
452 | else if (rcr_wrbk_ack_done & !shadw_parity_err_r) | |
453 | rcr_curr_pkt_cnt <= rcr_curr_pkt_cnt + {13'b0, rcr_wrbk_pkt_act_num[3:0]}; | |
454 | else | |
455 | rcr_curr_pkt_cnt <= rcr_curr_pkt_cnt; | |
456 | ||
457 | /******************************/ | |
458 | //RCR overflow/underflow | |
459 | /******************************/ | |
460 | //can not detect real packet count overflow | |
461 | wire rcr_curr_cnt_overflow = rcr_wrbk_ack_done_r & (rcr_curr_cnt > {1'b0, rcr_max_len[15:0]}) & dma_en; | |
462 | wire rcr_curr_cnt_underflow = dec_rcr_curr_cnt_r & rcr_curr_cnt[16]; | |
463 | wire rcr_pkt_cnt_underflow = dec_rcr_curr_cnt_r & rcr_curr_pkt_cnt[16]; | |
464 | ||
465 | always @ (posedge clk) | |
466 | if (reset) | |
467 | dec_rcr_curr_cnt_r <= 1'b0; | |
468 | else | |
469 | dec_rcr_curr_cnt_r <= dec_rcr_curr_cnt; | |
470 | ||
471 | always @ (posedge clk) | |
472 | if (reset) | |
473 | rcr_curr_cnt_overflow_r <= 1'b0; | |
474 | else if (dma_reset) | |
475 | rcr_curr_cnt_overflow_r <= 1'b0; | |
476 | else if (rcr_curr_cnt_overflow) | |
477 | rcr_curr_cnt_overflow_r <= 1'b1; | |
478 | else | |
479 | rcr_curr_cnt_overflow_r <= rcr_curr_cnt_overflow_r; | |
480 | ||
481 | ||
482 | wire chnl_shadw_parity_err = shadw_parity_err & rcr_wrbk_sched; | |
483 | ||
484 | always @ (posedge clk) | |
485 | if (reset) | |
486 | shadw_parity_err_r <= 1'b0; | |
487 | else if (rcr_wrbk_ack_done) | |
488 | shadw_parity_err_r <= 1'b0; | |
489 | else if (chnl_shadw_parity_err | rcr_ack_err) | |
490 | shadw_parity_err_r <= 1'b1; | |
491 | else | |
492 | shadw_parity_err_r <= shadw_parity_err_r; | |
493 | ||
494 | /*********************************/ | |
495 | //request completion write back | |
496 | /*********************************/ | |
497 | wire shadw_buf_not_empty = (|shadw_act_curr_cnt); | |
498 | wire shadw_buf_empty = !shadw_buf_not_empty; | |
499 | //wire mbox_update_true = (rcrto_bit | rcr_thresh_bit) & m_bit; | |
500 | wire timer_mbox_update = timer_m_bit & (|rcr_curr_pkt_cnt); | |
501 | wire thresh_mbox_update = thresh_m_bit & rcr_thresh_reg; | |
502 | wire mbox_update_true = timer_mbox_update | thresh_mbox_update; | |
503 | wire rcr_wrbk_trig = (|shadw_curr_cnt[7:3]) | | |
504 | (rcr_timer_done_r | rcr_flush_reg | thresh_mbox_update) & shadw_buf_not_empty; | |
505 | ||
506 | wire[3:0] rcr_wrbk_min_num = (|shadw_curr_cnt[7:3]) ? 4'd8 : shadw_curr_cnt[3:0]; | |
507 | wire[3:0] rcr_wrbk_act_num_tmp = not_in_cacheline ? (rcr_wrbk_min_num - {1'b0, rcr_curr_addr[2:0]}) : rcr_wrbk_min_num; | |
508 | ||
509 | wire[43:0] rcr_full_addr = {rcr_base_addr[24:0], rcr_curr_addr[15:3], 6'b0}; //always start in cacheline | |
510 | ||
511 | wire rcr_addr_valid0 = ((rcr_full_addr[43:12] & addr_mask0) == (comp_value0 & addr_mask0)) & page_valid0; | |
512 | wire rcr_addr_valid1 = ((rcr_full_addr[43:12] & addr_mask1) == (comp_value1 & addr_mask1)) & page_valid1; | |
513 | ||
514 | wire rcr_addr_valid = rcr_addr_valid0 | rcr_addr_valid1; | |
515 | ||
516 | wire[31:0] rcr_relo_addr0 = (rcr_full_addr[43:12] & ~addr_mask0) | (relo_value0 & addr_mask0); | |
517 | wire[31:0] rcr_relo_addr1 = (rcr_full_addr[43:12] & ~addr_mask1) | (relo_value1 & addr_mask1); | |
518 | ||
519 | wire[31:0] rcr_relo_addr = rcr_addr_valid0 ? rcr_relo_addr0 : rcr_relo_addr1; | |
520 | ||
521 | wire mbox_addr_valid0= ((mbox_addr[43:12] & addr_mask0) == (comp_value0 & addr_mask0)) & page_valid0; | |
522 | wire mbox_addr_valid1= ((mbox_addr[43:12] & addr_mask1) == (comp_value1 & addr_mask1)) & page_valid1; | |
523 | ||
524 | wire mbox_addr_valid = mbox_addr_valid0 | mbox_addr_valid1; | |
525 | ||
526 | wire[31:0] mbox_relo_addr0 = (mbox_addr[43:12] & ~addr_mask0) | (relo_value0 & addr_mask0); | |
527 | wire[31:0] mbox_relo_addr1 = (mbox_addr[43:12] & ~addr_mask1) | (relo_value1 & addr_mask1); | |
528 | ||
529 | wire[31:0] mbox_relo_addr = mbox_addr_valid0 ? mbox_relo_addr0 : mbox_relo_addr1; | |
530 | ||
531 | wire[43:0] relo_addr_tmp = mbox_req_sm ? {mbox_relo_addr, mbox_addr[11:0]} : | |
532 | {rcr_relo_addr, rcr_full_addr[11:0]}; | |
533 | wire[63:0] rcr_wrbk_addr = {page_handle[19:0], rcr_relo_addr_r[43:0]}; | |
534 | ||
535 | wire rcr_addr_not_valid = !rcr_addr_valid & dma_en; | |
536 | wire mbox_addr_not_valid = !mbox_addr_valid & dma_en; | |
537 | ||
538 | always @ (posedge clk) | |
539 | if (reset) | |
540 | cal_addr_en <= 1'b0; | |
541 | else | |
542 | cal_addr_en <= rcr_wrbk_req_sm; | |
543 | ||
544 | always @ (posedge clk) | |
545 | if (reset) | |
546 | rcr_relo_addr_r <= 44'b0; | |
547 | else if (rcr_wrbk_req_sm | mbox_req_sm) | |
548 | rcr_relo_addr_r <= relo_addr_tmp; | |
549 | else | |
550 | rcr_relo_addr_r <= rcr_relo_addr_r; | |
551 | ||
552 | always @ (posedge clk) | |
553 | if (reset) | |
554 | rcr_wrbk_act_num <= 4'b0; | |
555 | else if (dma_reset) | |
556 | rcr_wrbk_act_num <= 4'b0; | |
557 | else if (rcr_wrbk_req_sm) | |
558 | rcr_wrbk_act_num <= rcr_wrbk_act_num_tmp; | |
559 | else | |
560 | rcr_wrbk_act_num <= rcr_wrbk_act_num; | |
561 | ||
562 | always @ (posedge clk) | |
563 | if (reset) | |
564 | rcr_wrbk_numb <= 4'b0; | |
565 | else if (dma_reset) | |
566 | rcr_wrbk_numb <= 4'b0; | |
567 | else if (rcr_wrbk_req_sm) | |
568 | rcr_wrbk_numb <= rcr_wrbk_min_num; | |
569 | else | |
570 | rcr_wrbk_numb <= rcr_wrbk_numb; | |
571 | ||
572 | ||
573 | always @ (posedge clk) | |
574 | if (reset) | |
575 | not_in_cacheline <= 1'b0; | |
576 | else if (dma_reset) | |
577 | not_in_cacheline <= 1'b0; | |
578 | else if (rcr_wrbk_req_sm) | |
579 | not_in_cacheline <= !rcr_wrbk_min_num[3]; | |
580 | else | |
581 | not_in_cacheline <= not_in_cacheline; | |
582 | ||
583 | ||
584 | always @ (posedge clk) | |
585 | if (reset) | |
586 | rcr_wrbk_data_type <= 1'b0; | |
587 | else if (dma_reset) | |
588 | rcr_wrbk_data_type <= 1'b0; | |
589 | else if (rcr_wrbk_req_sm) | |
590 | rcr_wrbk_data_type <= 1'b1; | |
591 | else if (mbox_req_sm) | |
592 | rcr_wrbk_data_type <= 1'b0; | |
593 | else | |
594 | rcr_wrbk_data_type <= rcr_wrbk_data_type; | |
595 | ||
596 | always @ (posedge clk) | |
597 | if (reset) | |
598 | rcr_wrbk_req <= 1'b0; | |
599 | else if (dma_reset) | |
600 | rcr_wrbk_req <= 1'b0; | |
601 | else if (rcr_wrbk_gnt) | |
602 | rcr_wrbk_req <= 1'b0; | |
603 | else if (rcr_wrbk_req_sm | mbox_req_sm) | |
604 | rcr_wrbk_req <= 1'b1; | |
605 | else | |
606 | rcr_wrbk_req <= rcr_wrbk_req; | |
607 | ||
608 | always @ (posedge clk) | |
609 | if (reset) | |
610 | rcr_wrbk_sched <= 1'b0; | |
611 | else if (dma_reset) | |
612 | rcr_wrbk_sched <= 1'b0; | |
613 | else if (rcr_wrbk_gnt) | |
614 | rcr_wrbk_sched <= 1'b1; | |
615 | else if (rcr_wrbk_done_r) | |
616 | rcr_wrbk_sched <= 1'b0; | |
617 | else | |
618 | rcr_wrbk_sched <= rcr_wrbk_sched; | |
619 | ||
620 | always @ (posedge clk) | |
621 | if (reset) | |
622 | begin | |
623 | rcr_wrbk_done_r <= 1'b0; | |
624 | rcr_wrbk_done_r1 <= 1'b0; | |
625 | end | |
626 | else | |
627 | begin | |
628 | rcr_wrbk_done_r <= rcr_wrbk_sched & rcr_wrbk_done; | |
629 | rcr_wrbk_done_r1 <= rcr_wrbk_done_r; | |
630 | end | |
631 | ||
632 | always @ (posedge clk) | |
633 | if (reset) | |
634 | rcr_wrbk_pkt_num_r <= 4'b0; | |
635 | else if (dma_reset) | |
636 | rcr_wrbk_pkt_num_r <= 4'b0; | |
637 | else if (rcr_wrbk_done_r1) | |
638 | rcr_wrbk_pkt_num_r <= rcr_wrbk_pkt_num; | |
639 | else | |
640 | rcr_wrbk_pkt_num_r <= rcr_wrbk_pkt_num_r; | |
641 | ||
642 | always @ (posedge clk) | |
643 | if (reset) | |
644 | begin | |
645 | rcr_wrbk_ack_done <= 1'b0; | |
646 | rcr_wrbk_ack_done_r <= 1'b0; | |
647 | mbox_update_done <= 1'b0; | |
648 | end | |
649 | else | |
650 | begin | |
651 | rcr_wrbk_ack_done <= rcr_wrbk_ack_done_sm; | |
652 | rcr_wrbk_ack_done_r <= rcr_wrbk_ack_done; | |
653 | mbox_update_done <= mbox_update_done_sm; | |
654 | end | |
655 | ||
656 | ||
657 | always @ (posedge clk) | |
658 | if (reset) | |
659 | rcr_ack_accept <= 1'b0; | |
660 | else | |
661 | rcr_ack_accept <= rcr_ack_accept_sm; | |
662 | ||
663 | ||
664 | ||
665 | /************************************/ | |
666 | //Completion write back FSM | |
667 | /************************************/ | |
668 | wire rdmc_rcr_ack = rdmc_rcr_ack_valid & (rdmc_rcr_ack_dma_num == dma_chnl_grp_id); | |
669 | ||
670 | parameter | |
671 | ||
672 | IDLE = 4'd0, | |
673 | WRBK_REQ = 4'd1, | |
674 | WAIT_WRBK_DONE = 4'd2, | |
675 | WAIT_WRBK_ACK = 4'd3, | |
676 | WRBK_ACK_DONE_WAIT1 = 4'd4, | |
677 | WRBK_ACK_DONE_WAIT2 = 4'd5, | |
678 | WRBK_ACK_DONE = 4'd6, | |
679 | MBOX_REQ = 4'd7, | |
680 | WAIT_MBOX_WR_DONE = 4'd8, | |
681 | WAIT_MBOX_ACK = 4'd9, | |
682 | COMP_S1 = 4'd10, | |
683 | COMP_S2 = 4'd11; | |
684 | ||
685 | always @ (state or rcr_addr_valid or mbox_addr_valid or | |
686 | rcr_wrbk_trig or mbox_update_true or | |
687 | rcr_wrbk_sched or rcr_wrbk_done_r or | |
688 | rdmc_rcr_ack or rdmc_rcr_ack_err or | |
689 | dma_fatal_err or shadw_parity_err_r or | |
690 | rcr_timer_done_r) | |
691 | begin | |
692 | rcr_idle_cycle = 1'b0; | |
693 | rcr_wrbk_req_sm = 1'b0; | |
694 | mbox_req_sm = 1'b0; | |
695 | rcr_wrbk_ack_done_sm = 1'b0; | |
696 | mbox_update_done_sm = 1'b0; | |
697 | rcr_ack_accept_sm = 1'b0; | |
698 | reset_rcr_timer = 1'b0; | |
699 | reset_m_bit = 1'b0; | |
700 | next_state = 4'b0; | |
701 | ||
702 | case (state) //synopsys parallel_case full_case | |
703 | ||
704 | IDLE: | |
705 | begin | |
706 | rcr_idle_cycle = 1'b1; | |
707 | if ((rcr_addr_valid | mbox_addr_valid) & !dma_fatal_err) | |
708 | begin | |
709 | if (rcr_wrbk_trig) | |
710 | begin | |
711 | rcr_wrbk_req_sm = 1'b1; | |
712 | next_state = WRBK_REQ; | |
713 | end | |
714 | else if (mbox_update_true) | |
715 | begin | |
716 | mbox_req_sm = 1'b1; | |
717 | next_state = MBOX_REQ; | |
718 | end | |
719 | else if (rcr_timer_done_r) | |
720 | begin | |
721 | reset_rcr_timer = 1'b1; | |
722 | next_state = state; | |
723 | end | |
724 | else | |
725 | next_state = state; | |
726 | end | |
727 | else | |
728 | next_state = state; | |
729 | end | |
730 | ||
731 | WRBK_REQ: | |
732 | begin | |
733 | if (rcr_wrbk_sched) | |
734 | next_state = WAIT_WRBK_DONE; | |
735 | else | |
736 | next_state = state; | |
737 | end | |
738 | ||
739 | WAIT_WRBK_DONE: | |
740 | begin | |
741 | if (rcr_wrbk_done_r) | |
742 | next_state = WAIT_WRBK_ACK; | |
743 | else | |
744 | next_state = state; | |
745 | end | |
746 | ||
747 | WAIT_WRBK_ACK: | |
748 | begin | |
749 | if (rdmc_rcr_ack) | |
750 | begin | |
751 | rcr_wrbk_ack_done_sm = 1'b1; | |
752 | rcr_ack_accept_sm = 1'b1; | |
753 | if (shadw_parity_err_r | rdmc_rcr_ack_err) | |
754 | next_state = IDLE; | |
755 | else | |
756 | next_state = WRBK_ACK_DONE_WAIT1; | |
757 | end | |
758 | else | |
759 | next_state = state; | |
760 | end | |
761 | ||
762 | WRBK_ACK_DONE_WAIT1: | |
763 | ||
764 | next_state = WRBK_ACK_DONE_WAIT2; | |
765 | ||
766 | WRBK_ACK_DONE_WAIT2: | |
767 | ||
768 | next_state = WRBK_ACK_DONE; | |
769 | ||
770 | ||
771 | WRBK_ACK_DONE: | |
772 | begin | |
773 | if (mbox_update_true) | |
774 | begin | |
775 | mbox_req_sm = 1'b1; | |
776 | next_state = MBOX_REQ; | |
777 | end | |
778 | else if (rcr_timer_done_r) | |
779 | begin | |
780 | reset_m_bit = 1'b1; | |
781 | reset_rcr_timer = 1'b1; | |
782 | next_state = COMP_S2; | |
783 | end | |
784 | else | |
785 | begin | |
786 | reset_m_bit = 1'b1; | |
787 | next_state = COMP_S2; | |
788 | end | |
789 | end | |
790 | ||
791 | MBOX_REQ: | |
792 | begin | |
793 | if (rcr_wrbk_sched) | |
794 | next_state = WAIT_MBOX_WR_DONE; | |
795 | else | |
796 | next_state = state; | |
797 | end | |
798 | ||
799 | WAIT_MBOX_WR_DONE: | |
800 | begin | |
801 | if (rcr_wrbk_done_r) | |
802 | next_state = WAIT_MBOX_ACK; | |
803 | else | |
804 | next_state = state; | |
805 | end | |
806 | ||
807 | WAIT_MBOX_ACK: | |
808 | begin | |
809 | if (rdmc_rcr_ack) | |
810 | begin | |
811 | mbox_update_done_sm = 1'b1; | |
812 | rcr_ack_accept_sm = 1'b1; | |
813 | next_state = COMP_S1; | |
814 | end | |
815 | else | |
816 | next_state = state; | |
817 | end | |
818 | ||
819 | COMP_S1: | |
820 | begin | |
821 | if (rcr_timer_done_r) | |
822 | reset_rcr_timer = 1'b1; | |
823 | else | |
824 | reset_rcr_timer = 1'b0; | |
825 | ||
826 | reset_m_bit = 1'b1; | |
827 | next_state = COMP_S2; | |
828 | end | |
829 | ||
830 | COMP_S2: | |
831 | next_state = IDLE; | |
832 | ||
833 | default: | |
834 | next_state = IDLE; | |
835 | ||
836 | endcase | |
837 | end | |
838 | ||
839 | always @ (posedge clk) | |
840 | if (reset) | |
841 | state <= 4'b0; | |
842 | else if (dma_reset) | |
843 | state <= 4'b0; | |
844 | else | |
845 | state <= next_state; | |
846 | ||
847 | ||
848 | ||
849 | /*********************************/ | |
850 | // shadwow memory manager | |
851 | /*********************************/ | |
852 | wire shadw_wr_even = shadw_curr_cnt[0]; | |
853 | wire last_rd_addr = (shadw_rd_ptr == shadw_rd_end_addr); | |
854 | wire last_wr_addr = (shadw_wr_ptr == shadw_wr_end_addr); | |
855 | ||
856 | always @ (posedge clk) | |
857 | if (reset) | |
858 | shadw_wr_en <= 1'b0; | |
859 | else if (dma_reset) | |
860 | shadw_wr_en <= 1'b0; | |
861 | else | |
862 | shadw_wr_en <= update_rcr_shadw & (rdmc_wr_data_dma_num == dma_chnl_grp_id); | |
863 | ||
864 | always @ (posedge clk) | |
865 | if (reset) | |
866 | shadw_wr_ptr <= shadw_start_addr; | |
867 | else if (dma_reset) | |
868 | shadw_wr_ptr <= shadw_start_addr; | |
869 | else if (shadw_wr_en & shadw_curr_cnt[0] & last_wr_addr) | |
870 | shadw_wr_ptr <= shadw_start_addr; | |
871 | else if (shadw_wr_en & shadw_curr_cnt[0]) | |
872 | shadw_wr_ptr <= shadw_wr_ptr + 8'd1; | |
873 | else | |
874 | shadw_wr_ptr <= shadw_wr_ptr; | |
875 | ||
876 | ||
877 | always @ (posedge clk) | |
878 | if (reset) | |
879 | shadw_rd_ptr <= shadw_start_addr; | |
880 | else if (dma_reset) | |
881 | shadw_rd_ptr <= shadw_start_addr; | |
882 | else if (rcr_wrbk_ack_done & rcr_wrbk_numb[3] & last_rd_addr) | |
883 | shadw_rd_ptr <= shadw_start_addr; | |
884 | else if (rcr_wrbk_ack_done & rcr_wrbk_numb[3]) | |
885 | shadw_rd_ptr <= shadw_rd_ptr + 8'd4; | |
886 | else | |
887 | shadw_rd_ptr <= shadw_rd_ptr; | |
888 | ||
889 | ||
890 | always @ (posedge clk) | |
891 | if (reset) | |
892 | inc_shadw_curr_cnt <= 1'b0; | |
893 | else if (dma_reset) | |
894 | inc_shadw_curr_cnt <= 1'b0; | |
895 | else if (shadw_wr_en & rcr_wrbk_ack_done) | |
896 | inc_shadw_curr_cnt <= 1'b1; | |
897 | else | |
898 | inc_shadw_curr_cnt <= 1'b0; | |
899 | ||
900 | ||
901 | always @ (posedge clk) | |
902 | if (reset) | |
903 | shadw_curr_cnt <= 8'b0; | |
904 | else if (dma_reset) | |
905 | shadw_curr_cnt <= 8'b0; | |
906 | else if (shadw_wr_en & !rcr_wrbk_ack_done | inc_shadw_curr_cnt) | |
907 | shadw_curr_cnt <= shadw_curr_cnt + 8'd1; | |
908 | else if (rcr_wrbk_ack_done & rcr_wrbk_numb[3]) | |
909 | shadw_curr_cnt <= shadw_curr_cnt - 8'd8; | |
910 | else | |
911 | shadw_curr_cnt <= shadw_curr_cnt; | |
912 | ||
913 | always @ (posedge clk) | |
914 | if (reset) | |
915 | shadw_act_curr_cnt <= 6'b0; //support 4 cache line only | |
916 | else if (dma_reset) | |
917 | shadw_act_curr_cnt <= 6'b0; | |
918 | else if (shadw_wr_en & !rcr_wrbk_ack_done | inc_shadw_curr_cnt) | |
919 | shadw_act_curr_cnt <= shadw_act_curr_cnt + 6'd1; | |
920 | else if (rcr_wrbk_ack_done) | |
921 | shadw_act_curr_cnt <= shadw_act_curr_cnt - {2'b0, rcr_wrbk_act_num[3:0]}; | |
922 | else | |
923 | shadw_act_curr_cnt <= shadw_act_curr_cnt; | |
924 | ||
925 | ||
926 | always @ (posedge clk) | |
927 | if (reset) | |
928 | dec_shadw_space_cnt <= 1'b0; | |
929 | else if (chnl_sel_buf_en_r & rcr_wrbk_ack_done) | |
930 | dec_shadw_space_cnt <= 1'b1; | |
931 | else | |
932 | dec_shadw_space_cnt <= 1'b0; | |
933 | ||
934 | ||
935 | always @ (posedge clk) | |
936 | if (reset) | |
937 | shadw_curr_space_cnt <= `SHADW_MAX_ADDR_CNT; | |
938 | else if (dma_reset) | |
939 | shadw_curr_space_cnt <= `SHADW_MAX_ADDR_CNT; | |
940 | else if (chnl_sel_buf_en_r & !rcr_wrbk_ack_done | dec_shadw_space_cnt) | |
941 | shadw_curr_space_cnt <= shadw_curr_space_cnt - {6'b0, pref_buf_used_num[1:0]}; | |
942 | else if (rcr_wrbk_ack_done & rcr_wrbk_numb[3]) | |
943 | shadw_curr_space_cnt <= shadw_curr_space_cnt + 8'd8; | |
944 | else | |
945 | shadw_curr_space_cnt <= shadw_curr_space_cnt; | |
946 | ||
947 | always @ (posedge clk) | |
948 | if (reset) | |
949 | chnl_has_pkt_s1 <= 1'b0; | |
950 | else if (chnl_sel_buf_en_r) | |
951 | chnl_has_pkt_s1 <= 1'b1; | |
952 | else if (wr_last_pkt_data & shadw_wr_en) | |
953 | chnl_has_pkt_s1 <= 1'b0; | |
954 | else | |
955 | chnl_has_pkt_s1 <= chnl_has_pkt_s1; | |
956 | ||
957 | always @ (posedge clk) | |
958 | if (reset) | |
959 | chnl_has_pkt_s2 <= 1'b0; | |
960 | else if (wr_last_pkt_data & shadw_wr_en) | |
961 | chnl_has_pkt_s2 <= 1'b1; | |
962 | else if (wr_transfer_comp_int) | |
963 | chnl_has_pkt_s2 <= 1'b0; | |
964 | else | |
965 | chnl_has_pkt_s2 <= chnl_has_pkt_s2; | |
966 | ||
967 | wire chnl_has_pkt = chnl_has_pkt_s1 | chnl_has_pkt_s2; | |
968 | ||
969 | ||
970 | /********************************/ | |
971 | //Mailbox operations | |
972 | /********************************/ | |
973 | wire m_bit_en = mbox_update_done & !rx_dma_ctl_stat_reg_wenu | mbox_update_done_dly; | |
974 | wire set_rcrto_bit = mbox_update_done ? rcr_timer_done_r : rcr_timer_done_r_dly; | |
975 | wire m_bit_in = !(rcr_thresh_reg | set_rcrto_bit); | |
976 | ||
977 | assign rcr_ctl_stat_word= {m_bit_in, rcr_thresh_reg, set_rcrto_bit}; | |
978 | ||
979 | always @ (posedge clk) | |
980 | if (reset) | |
981 | rcr_thresh_reg <= 1'b0; | |
982 | else | |
983 | rcr_thresh_reg <= (rcr_curr_pkt_cnt[15:0] > pkt_thresh); | |
984 | ||
985 | always @ (posedge clk) | |
986 | if (reset) | |
987 | thresh_m_bit <= 1'b0; | |
988 | else if (reset_m_bit) | |
989 | thresh_m_bit <= 1'b0; | |
990 | else if (rcr_idle_cycle & !rx_dma_ctl_stat_reg_wenu_dly) | |
991 | thresh_m_bit <= m_bit; | |
992 | else | |
993 | thresh_m_bit <= thresh_m_bit; | |
994 | ||
995 | always @ (posedge clk) | |
996 | if (reset) | |
997 | begin | |
998 | rcr_timer_done_r_dly <= 1'b0; | |
999 | mbox_update_done_dly <= 1'b0; | |
1000 | end | |
1001 | else | |
1002 | begin | |
1003 | rcr_timer_done_r_dly <= mbox_update_done & rcr_timer_done_r; | |
1004 | mbox_update_done_dly <= mbox_update_done & rx_dma_ctl_stat_reg_wenu; | |
1005 | end | |
1006 | ||
1007 | /********************************/ | |
1008 | //RCR Timeout counter | |
1009 | /********************************/ | |
1010 | wire clk_cnt_done = (clk_cnt == clk_div_value); | |
1011 | wire rcr_timer_done = (timeout_cnt == timeout_value) & timeout_en; | |
1012 | wire pio_wr_reset = rx_dma_ctl_stat_reg_wenu_dly & m_bit & !rcr_timer_done_r; | |
1013 | ||
1014 | always @ (posedge clk) | |
1015 | if (reset) | |
1016 | timer_m_bit <= 1'b0; | |
1017 | else if (pio_wr_reset | reset_rcr_timer | m_bit_en) | |
1018 | timer_m_bit <= 1'b0; | |
1019 | else if (rcr_timer_done) | |
1020 | timer_m_bit <= m_bit; | |
1021 | else | |
1022 | timer_m_bit <= timer_m_bit; | |
1023 | ||
1024 | ||
1025 | always @ (posedge clk) | |
1026 | if (reset) | |
1027 | clk_cnt <= 16'b0; | |
1028 | else if (dma_reset) | |
1029 | clk_cnt <= 16'b0; | |
1030 | else if (clk_cnt_done) | |
1031 | clk_cnt <= 16'b0; | |
1032 | else | |
1033 | clk_cnt <= clk_cnt + 16'd1; | |
1034 | ||
1035 | always @ (posedge clk) | |
1036 | if (reset) | |
1037 | timeout_cnt <= 6'b0; | |
1038 | else if (dma_reset) | |
1039 | timeout_cnt <= 6'b0; | |
1040 | else if (pio_wr_reset | reset_rcr_timer) | |
1041 | timeout_cnt <= 6'b0; | |
1042 | else if (rcr_timer_done) | |
1043 | timeout_cnt <= timeout_cnt; | |
1044 | else if (clk_cnt_done & timeout_en) | |
1045 | timeout_cnt <= timeout_cnt + 6'd1; | |
1046 | else | |
1047 | timeout_cnt <= timeout_cnt; | |
1048 | ||
1049 | always @ (posedge clk) | |
1050 | if (reset) | |
1051 | rcr_timer_done_r <= 1'b0; | |
1052 | else if (pio_wr_reset | reset_rcr_timer) | |
1053 | rcr_timer_done_r <= 1'b0; | |
1054 | else if (rcr_timer_done) | |
1055 | rcr_timer_done_r <= 1'b1; | |
1056 | else | |
1057 | rcr_timer_done_r <= rcr_timer_done_r; | |
1058 | ||
1059 | ||
1060 | ||
1061 | /********************************/ | |
1062 | //RCR Flush | |
1063 | /********************************/ | |
1064 | always @ (posedge clk) | |
1065 | if (reset) | |
1066 | rcr_flush_reg_dly <= 1'b0; | |
1067 | else | |
1068 | rcr_flush_reg_dly <= rcr_flush_reg; | |
1069 | ||
1070 | wire rcr_flush_pulse = rcr_flush_reg & !rcr_flush_reg_dly; | |
1071 | wire reset_rcr_flush = rcr_flush_pulse & shadw_buf_empty | rcr_wrbk_ack_done; | |
1072 | ||
1073 | ||
1074 | endmodule | |
1075 | ||
1076 | ||
1077 | ||
1078 |